gdb/ppc-tdep.h

   1 /* Target-dependent code for GDB, the GNU debugger.
   2
   3    Copyright (C) 2000-2018 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef PPC_TDEP_H
  21 #define PPC_TDEP_H
  22
  23 struct gdbarch;
  24 struct frame_info;
  25 struct value;
  26 struct regcache;
  27 struct type;
  28
  29 /* From ppc-sysv-tdep.c ...  */
  30 enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
  31                                                         struct value *function,
  32                                                         struct type *valtype,
  33                                                         struct regcache *regcache,
  34                                                         gdb_byte *readbuf,
  35                                                         const gdb_byte *writebuf);
  36 enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
  37                                                                struct value *function,
  38                                                                struct type *valtype,
  39                                                                struct regcache *regcache,
  40                                                                gdb_byte *readbuf,
  41                                                                const gdb_byte *writebuf);
  42
  43 CORE_ADDR ppc_sysv_abi_push_dummy_call
  44   (struct gdbarch *gdbarch, struct value *function, struct regcache *regcache,
  45    CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp,
  46    function_call_return_method return_method, CORE_ADDR struct_addr);
  47
  48 CORE_ADDR ppc64_sysv_abi_push_dummy_call
  49   (struct gdbarch *gdbarch, struct value *function, struct regcache *regcache,
  50    CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp,
  51    function_call_return_method return_method, CORE_ADDR struct_addr);
  52
  53 enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
  54                                                           struct value *function,
  55                                                           struct type *valtype,
  56                                                           struct regcache *regcache,
  57                                                           gdb_byte *readbuf,
  58                                                           const gdb_byte *writebuf);
  59
  60 /* From rs6000-tdep.c...  */
  61 int altivec_register_p (struct gdbarch *gdbarch, int regno);
  62 int vsx_register_p (struct gdbarch *gdbarch, int regno);
  63 int spe_register_p (struct gdbarch *gdbarch, int regno);
  64
  65 /* Return non-zero if the architecture described by GDBARCH has
  66    floating-point registers (f0 --- f31 and fpscr).  */
  67 int ppc_floating_point_unit_p (struct gdbarch *gdbarch);
  68
  69 /* Return non-zero if the architecture described by GDBARCH has
  70    Altivec registers (vr0 --- vr31, vrsave and vscr).  */
  71 int ppc_altivec_support_p (struct gdbarch *gdbarch);
  72
  73 /* Return non-zero if the architecture described by GDBARCH has
  74    VSX registers (vsr0 --- vsr63).  */
  75 int vsx_support_p (struct gdbarch *gdbarch);
  76 std::vector<CORE_ADDR> ppc_deal_with_atomic_sequence
  77   (struct regcache *regcache);
  78
  79
  80 /* Register set description.  */
  81
  82 struct ppc_reg_offsets
  83 {
  84   /* General-purpose registers.  */
  85   int r0_offset;
  86   int gpr_size; /* size for r0-31, pc, ps, lr, ctr.  */
  87   int xr_size;  /* size for cr, xer, mq.  */
  88   int pc_offset;
  89   int ps_offset;
  90   int cr_offset;
  91   int lr_offset;
  92   int ctr_offset;
  93   int xer_offset;
  94   int mq_offset;
  95
  96   /* Floating-point registers.  */
  97   int f0_offset;
  98   int fpscr_offset;
  99   int fpscr_size;
 100 };
 101
 102 extern void ppc_supply_reg (struct regcache *regcache, int regnum,
 103                             const gdb_byte *regs, size_t offset, int regsize);
 104
 105 extern void ppc_collect_reg (const struct regcache *regcache, int regnum,
 106                              gdb_byte *regs, size_t offset, int regsize);
 107
 108 /* Supply register REGNUM in the general-purpose register set REGSET
 109    from the buffer specified by GREGS and LEN to register cache
 110    REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */
 111
 112 extern void ppc_supply_gregset (const struct regset *regset,
 113                                 struct regcache *regcache,
 114                                 int regnum, const void *gregs, size_t len);
 115
 116 /* Supply register REGNUM in the floating-point register set REGSET
 117    from the buffer specified by FPREGS and LEN to register cache
 118    REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */
 119
 120 extern void ppc_supply_fpregset (const struct regset *regset,
 121                                  struct regcache *regcache,
 122                                  int regnum, const void *fpregs, size_t len);
 123
 124 /* Supply register REGNUM in the Altivec register set REGSET
 125    from the buffer specified by VRREGS and LEN to register cache
 126    REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */
 127
 128 extern void ppc_supply_vrregset (const struct regset *regset,
 129                                  struct regcache *regcache,
 130                                  int regnum, const void *vrregs, size_t len);
 131
 132 /* Supply register REGNUM in the VSX register set REGSET
 133    from the buffer specified by VSXREGS and LEN to register cache
 134    REGCACHE.  If REGNUM is -1, do this for all registers in REGSET.  */
 135
 136 extern void ppc_supply_vsxregset (const struct regset *regset,
 137                                  struct regcache *regcache,
 138                                  int regnum, const void *vsxregs, size_t len);
 139
 140 /* Collect register REGNUM in the general-purpose register set
 141    REGSET, from register cache REGCACHE into the buffer specified by
 142    GREGS and LEN.  If REGNUM is -1, do this for all registers in
 143    REGSET.  */
 144
 145 extern void ppc_collect_gregset (const struct regset *regset,
 146                                  const struct regcache *regcache,
 147                                  int regnum, void *gregs, size_t len);
 148
 149 /* Collect register REGNUM in the floating-point register set
 150    REGSET, from register cache REGCACHE into the buffer specified by
 151    FPREGS and LEN.  If REGNUM is -1, do this for all registers in
 152    REGSET.  */
 153
 154 extern void ppc_collect_fpregset (const struct regset *regset,
 155                                   const struct regcache *regcache,
 156                                   int regnum, void *fpregs, size_t len);
 157
 158 /* Collect register REGNUM in the Altivec register set
 159    REGSET from register cache REGCACHE into the buffer specified by
 160    VRREGS and LEN.  If REGNUM is -1, do this for all registers in
 161    REGSET.  */
 162
 163 extern void ppc_collect_vrregset (const struct regset *regset,
 164                                   const struct regcache *regcache,
 165                                   int regnum, void *vrregs, size_t len);
 166
 167 /* Collect register REGNUM in the VSX register set
 168    REGSET from register cache REGCACHE into the buffer specified by
 169    VSXREGS and LEN.  If REGNUM is -1, do this for all registers in
 170    REGSET.  */
 171
 172 extern void ppc_collect_vsxregset (const struct regset *regset,
 173                                   const struct regcache *regcache,
 174                                   int regnum, void *vsxregs, size_t len);
 175
 176 /* Private data that this module attaches to struct gdbarch.  */
 177
 178 /* ELF ABI version used by the inferior.  */
 179 enum powerpc_elf_abi
 180 {
 181   POWERPC_ELF_AUTO,
 182   POWERPC_ELF_V1,
 183   POWERPC_ELF_V2,
 184   POWERPC_ELF_LAST
 185 };
 186
 187 /* Vector ABI used by the inferior.  */
 188 enum powerpc_vector_abi
 189 {
 190   POWERPC_VEC_AUTO,
 191   POWERPC_VEC_GENERIC,
 192   POWERPC_VEC_ALTIVEC,
 193   POWERPC_VEC_SPE,
 194   POWERPC_VEC_LAST
 195 };
 196
 197 /* long double ABI version used by the inferior.  */
 198 enum powerpc_long_double_abi
 199 {
 200   POWERPC_LONG_DOUBLE_AUTO,
 201   POWERPC_LONG_DOUBLE_IBM128,
 202   POWERPC_LONG_DOUBLE_IEEE128,
 203   POWERPC_LONG_DOUBLE_LAST
 204 };
 205
 206 struct gdbarch_tdep
 207   {
 208     int wordsize;               /* Size in bytes of fixed-point word.  */
 209     int soft_float;             /* Avoid FP registers for arguments?  */
 210
 211     enum powerpc_elf_abi elf_abi;       /* ELF ABI version.  */
 212
 213     /* Format to use for the "long double" data type.  */
 214     enum powerpc_long_double_abi long_double_abi;
 215
 216     /* How to pass vector arguments.  Never set to AUTO or LAST.  */
 217     enum powerpc_vector_abi vector_abi;
 218
 219     int ppc_gp0_regnum;         /* GPR register 0 */
 220     int ppc_toc_regnum;         /* TOC register */
 221     int ppc_ps_regnum;          /* Processor (or machine) status (%msr) */
 222     int ppc_cr_regnum;          /* Condition register */
 223     int ppc_lr_regnum;          /* Link register */
 224     int ppc_ctr_regnum;         /* Count register */
 225     int ppc_xer_regnum;         /* Integer exception register */
 226
 227     /* Not all PPC and RS6000 variants will have the registers
 228        represented below.  A -1 is used to indicate that the register
 229        is not present in this variant.  */
 230
 231     /* Floating-point registers.  */
 232     int ppc_fp0_regnum;         /* Floating-point register 0.  */
 233     int ppc_fpscr_regnum;       /* fp status and condition register.  */
 234
 235     /* Multiplier-Quotient Register (older POWER architectures only).  */
 236     int ppc_mq_regnum;
 237
 238     /* POWER7 VSX registers.  */
 239     int ppc_vsr0_regnum;        /* First VSX register.  */
 240     int ppc_vsr0_upper_regnum;  /* First right most dword vsx register.  */
 241     int ppc_efpr0_regnum;       /* First Extended FP register.  */
 242
 243     /* Altivec registers.  */
 244     int ppc_vr0_regnum;         /* First AltiVec register.  */
 245     int ppc_vrsave_regnum;      /* Last AltiVec register.  */
 246
 247     /* SPE registers.  */
 248     int ppc_ev0_upper_regnum;   /* First GPR upper half register.  */
 249     int ppc_ev0_regnum;         /* First ev register.  */
 250     int ppc_acc_regnum;         /* SPE 'acc' register.  */
 251     int ppc_spefscr_regnum;     /* SPE 'spefscr' register.  */
 252
 253     /* Program Priority Register.  */
 254     int ppc_ppr_regnum;
 255
 256     /* Data Stream Control Register.  */
 257     int ppc_dscr_regnum;
 258
 259     /* Target Address Register.  */
 260     int ppc_tar_regnum;
 261
 262     /* Decimal 128 registers.  */
 263     int ppc_dl0_regnum;         /* First Decimal128 argument register pair.  */
 264
 265     int have_ebb;
 266
 267     /* PMU registers.  */
 268     int ppc_mmcr0_regnum;
 269     int ppc_mmcr2_regnum;
 270     int ppc_siar_regnum;
 271     int ppc_sdar_regnum;
 272     int ppc_sier_regnum;
 273
 274     /* Hardware Transactional Memory registers.  */
 275     int have_htm_spr;
 276     int have_htm_core;
 277     int have_htm_fpu;
 278     int have_htm_altivec;
 279     int have_htm_vsx;
 280     int ppc_cppr_regnum;
 281     int ppc_cdscr_regnum;
 282     int ppc_ctar_regnum;
 283
 284     /* HTM pseudo registers.  */
 285     int ppc_cdl0_regnum;
 286     int ppc_cvsr0_regnum;
 287     int ppc_cefpr0_regnum;
 288
 289     /* Offset to ABI specific location where link register is saved.  */
 290     int lr_frame_offset;
 291
 292     /* An array of integers, such that sim_regno[I] is the simulator
 293        register number for GDB register number I, or -1 if the
 294        simulator does not implement that register.  */
 295     int *sim_regno;
 296
 297     /* ISA-specific types.  */
 298     struct type *ppc_builtin_type_vec64;
 299     struct type *ppc_builtin_type_vec128;
 300
 301     int (*ppc_syscall_record) (struct regcache *regcache);
 302 };
 303
 304
 305 /* Constants for register set sizes.  */
 306 enum
 307   {
 308     ppc_num_gprs = 32,          /* 32 general-purpose registers.  */
 309     ppc_num_fprs = 32,          /* 32 floating-point registers.  */
 310     ppc_num_srs = 16,           /* 16 segment registers.  */
 311     ppc_num_vrs = 32,           /* 32 Altivec vector registers.  */
 312     ppc_num_vshrs = 32,         /* 32 doublewords (dword 1 of vs0~vs31).  */
 313     ppc_num_vsrs = 64,          /* 64 VSX vector registers.  */
 314     ppc_num_efprs = 32          /* 32 Extended FP registers.  */
 315   };
 316
 317
 318 /* Register number constants.  These are GDB internal register
 319    numbers; they are not used for the simulator or remote targets.
 320    Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given
 321    numbers above PPC_NUM_REGS.  So are segment registers and other
 322    target-defined registers.  */
 323 enum {
 324   PPC_R0_REGNUM = 0,
 325   PPC_F0_REGNUM = 32,
 326   PPC_PC_REGNUM = 64,
 327   PPC_MSR_REGNUM = 65,
 328   PPC_CR_REGNUM = 66,
 329   PPC_LR_REGNUM = 67,
 330   PPC_CTR_REGNUM = 68,
 331   PPC_XER_REGNUM = 69,
 332   PPC_FPSCR_REGNUM = 70,
 333   PPC_MQ_REGNUM = 71,
 334   PPC_SPE_UPPER_GP0_REGNUM = 72,
 335   PPC_SPE_ACC_REGNUM = 104,
 336   PPC_SPE_FSCR_REGNUM = 105,
 337   PPC_VR0_REGNUM = 106,
 338   PPC_VSCR_REGNUM = 138,
 339   PPC_VRSAVE_REGNUM = 139,
 340   PPC_VSR0_UPPER_REGNUM = 140,
 341   PPC_VSR31_UPPER_REGNUM = 171,
 342   PPC_PPR_REGNUM = 172,
 343   PPC_DSCR_REGNUM = 173,
 344   PPC_TAR_REGNUM = 174,
 345
 346   /* EBB registers.  */
 347   PPC_BESCR_REGNUM = 175,
 348   PPC_EBBHR_REGNUM = 176,
 349   PPC_EBBRR_REGNUM = 177,
 350
 351   /* PMU registers.  */
 352   PPC_MMCR0_REGNUM = 178,
 353   PPC_MMCR2_REGNUM = 179,
 354   PPC_SIAR_REGNUM = 180,
 355   PPC_SDAR_REGNUM = 181,
 356   PPC_SIER_REGNUM = 182,
 357
 358   /* Hardware transactional memory registers.  */
 359   PPC_TFHAR_REGNUM = 183,
 360   PPC_TEXASR_REGNUM = 184,
 361   PPC_TFIAR_REGNUM = 185,
 362
 363   PPC_CR0_REGNUM = 186,
 364   PPC_CCR_REGNUM = 218,
 365   PPC_CXER_REGNUM = 219,
 366   PPC_CLR_REGNUM = 220,
 367   PPC_CCTR_REGNUM = 221,
 368
 369   PPC_CF0_REGNUM = 222,
 370   PPC_CFPSCR_REGNUM = 254,
 371
 372   PPC_CVR0_REGNUM = 255,
 373   PPC_CVSCR_REGNUM = 287,
 374   PPC_CVRSAVE_REGNUM = 288,
 375
 376   PPC_CVSR0_UPPER_REGNUM = 289,
 377
 378   PPC_CPPR_REGNUM = 321,
 379   PPC_CDSCR_REGNUM = 322,
 380   PPC_CTAR_REGNUM = 323,
 381   PPC_NUM_REGS
 382 };
 383
 384 /* Big enough to hold the size of the largest register in bytes.  */
 385 #define PPC_MAX_REGISTER_SIZE   64
 386
 387 #define PPC_IS_EBB_REGNUM(i) \
 388         ((i) >= PPC_BESCR_REGNUM && (i) <= PPC_EBBRR_REGNUM)
 389
 390 #define PPC_IS_PMU_REGNUM(i) \
 391         ((i) >= PPC_MMCR0_REGNUM && (i) <= PPC_SIER_REGNUM)
 392
 393 #define PPC_IS_TMSPR_REGNUM(i) \
 394   ((i) >= PPC_TFHAR_REGNUM && (i) <= PPC_TFIAR_REGNUM)
 395
 396 #define PPC_IS_CKPTGP_REGNUM(i) \
 397   ((i) >= PPC_CR0_REGNUM && (i) <= PPC_CCTR_REGNUM)
 398
 399 #define PPC_IS_CKPTFP_REGNUM(i) \
 400   ((i) >= PPC_CF0_REGNUM && (i) <= PPC_CFPSCR_REGNUM)
 401
 402 #define PPC_IS_CKPTVMX_REGNUM(i) \
 403   ((i) >= PPC_CVR0_REGNUM && (i) <= PPC_CVRSAVE_REGNUM)
 404
 405 #define PPC_IS_CKPTVSX_REGNUM(i) \
 406   ((i) >= PPC_CVSR0_UPPER_REGNUM && (i) < (PPC_CVSR0_UPPER_REGNUM + 32))
 407
 408 /* An instruction to match.  */
 409
 410 struct ppc_insn_pattern
 411 {
 412   unsigned int mask;            /* mask the insn with this...  */
 413   unsigned int data;            /* ...and see if it matches this.  */
 414   int optional;                 /* If non-zero, this insn may be absent.  */
 415 };
 416
 417 extern int ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc,
 418                                     const struct ppc_insn_pattern *pattern,
 419                                     unsigned int *insns);
 420 extern CORE_ADDR ppc_insn_d_field (unsigned int insn);
 421
 422 extern CORE_ADDR ppc_insn_ds_field (unsigned int insn);
 423
 424 extern int ppc_process_record (struct gdbarch *gdbarch,
 425                                struct regcache *regcache, CORE_ADDR addr);
 426
 427 /* Instruction size.  */
 428 #define PPC_INSN_SIZE 4
 429
 430 /* Estimate for the maximum number of instrctions in a function epilogue.  */
 431 #define PPC_MAX_EPILOGUE_INSTRUCTIONS  52
 432
 433 #endif /* ppc-tdep.h */