gdb/riscv-tdep.h

   1 /* Target-dependent header for the RISC-V architecture, for GDB, the
   2    GNU Debugger.
   3
   4    Copyright (C) 2018-2020 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef RISCV_TDEP_H
  22 #define RISCV_TDEP_H
  23
  24 #include "arch/riscv.h"
  25
  26 /* RiscV register numbers.  */
  27 enum
  28 {
  29   RISCV_ZERO_REGNUM = 0,        /* Read-only register, always 0.  */
  30   RISCV_RA_REGNUM = 1,          /* Return Address.  */
  31   RISCV_SP_REGNUM = 2,          /* Stack Pointer.  */
  32   RISCV_GP_REGNUM = 3,          /* Global Pointer.  */
  33   RISCV_TP_REGNUM = 4,          /* Thread Pointer.  */
  34   RISCV_FP_REGNUM = 8,          /* Frame Pointer.  */
  35   RISCV_A0_REGNUM = 10,         /* First argument.  */
  36   RISCV_A1_REGNUM = 11,         /* Second argument.  */
  37   RISCV_PC_REGNUM = 32,         /* Program Counter.  */
  38
  39   RISCV_NUM_INTEGER_REGS = 32,
  40
  41   RISCV_FIRST_FP_REGNUM = 33,   /* First Floating Point Register */
  42   RISCV_FA0_REGNUM = 43,
  43   RISCV_FA1_REGNUM = RISCV_FA0_REGNUM + 1,
  44   RISCV_LAST_FP_REGNUM = 64,    /* Last Floating Point Register */
  45
  46   RISCV_FIRST_CSR_REGNUM = 65,  /* First CSR */
  47 #define DECLARE_CSR(name, num, class, define_version, abort_version) \
  48   RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
  49 #include "opcode/riscv-opc.h"
  50 #undef DECLARE_CSR
  51   RISCV_LAST_CSR_REGNUM = 4160,
  52   RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10 + RISCV_FIRST_CSR_REGNUM,
  53
  54   RISCV_PRIV_REGNUM = 4161,
  55
  56   RISCV_LAST_REGNUM = RISCV_PRIV_REGNUM
  57 };
  58
  59 /* RiscV DWARF register numbers.  */
  60 enum
  61 {
  62   RISCV_DWARF_REGNUM_X0 = 0,
  63   RISCV_DWARF_REGNUM_X31 = 31,
  64   RISCV_DWARF_REGNUM_F0 = 32,
  65   RISCV_DWARF_REGNUM_F31 = 63,
  66 };
  67
  68 /* RISC-V specific per-architecture information.  */
  69 struct gdbarch_tdep
  70 {
  71   /* Features about the target hardware that impact how the gdbarch is
  72      configured.  Two gdbarch instances are compatible only if this field
  73      matches.  */
  74   struct riscv_gdbarch_features isa_features;
  75
  76   /* Features about the abi that impact how the gdbarch is configured.  Two
  77      gdbarch instances are compatible only if this field matches.  */
  78   struct riscv_gdbarch_features abi_features;
  79
  80   /* ISA-specific data types.  */
  81   struct type *riscv_fpreg_d_type = nullptr;
  82
  83   /* Use for tracking unknown CSRs in the target description.
  84      UNKNOWN_CSRS_FIRST_REGNUM is the number assigned to the first unknown
  85      CSR.  All other unknown CSRs will be assigned sequential numbers after
  86      this, with UNKNOWN_CSRS_COUNT being the total number of unknown CSRs.  */
  87   int unknown_csrs_first_regnum = -1;
  88   int unknown_csrs_count = 0;
  89
  90   /* Some targets (QEMU) are reporting three registers twice in the target
  91      description they send.  These three register numbers, when not set to
  92      -1, are for the duplicate copies of these registers.  */
  93   int duplicate_fflags_regnum = -1;
  94   int duplicate_frm_regnum = -1;
  95   int duplicate_fcsr_regnum = -1;
  96
  97 };
  98
  99
 100 /* Return the width in bytes  of the general purpose registers for GDBARCH.
 101    Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
 102    RV128.  */
 103 extern int riscv_isa_xlen (struct gdbarch *gdbarch);
 104
 105 /* Return the width in bytes of the hardware floating point registers for
 106    GDBARCH.  If this architecture has no floating point registers, then
 107    return 0.  Possible values are 4, 8, or 16 for depending on which of
 108    single, double or quad floating point support is available.  */
 109 extern int riscv_isa_flen (struct gdbarch *gdbarch);
 110
 111 /* Return the width in bytes of the general purpose register abi for
 112    GDBARCH.  This can be equal to, or less than RISCV_ISA_XLEN and reflects
 113    how the binary was compiled rather than the hardware that is available.
 114    It is possible that a binary compiled for RV32 is being run on an RV64
 115    target, in which case the isa xlen is 8-bytes, and the abi xlen is
 116    4-bytes.  This will impact how inferior functions are called.  */
 117 extern int riscv_abi_xlen (struct gdbarch *gdbarch);
 118
 119 /* Return the width in bytes of the floating point register abi for
 120    GDBARCH.  This reflects how the binary was compiled rather than the
 121    hardware that is available.  It is possible that a binary is compiled
 122    for single precision floating point, and then run on a target with
 123    double precision floating point.  A return value of 0 indicates that no
 124    floating point abi is in use (floating point arguments will be passed
 125    in integer registers) other possible return value are 4, 8, or 16 as
 126    with RISCV_ISA_FLEN.  */
 127 extern int riscv_abi_flen (struct gdbarch *gdbarch);
 128
 129 /* Single step based on where the current instruction will take us.  */
 130 extern std::vector<CORE_ADDR> riscv_software_single_step
 131   (struct regcache *regcache);
 132
 133 #endif /* RISCV_TDEP_H */