gdb/s12z-tdep.c

   1 /* Target-dependent code for the S12Z, for the GDB.
   2    Copyright (C) 2018-2019 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 /* Much of this file is shamelessly copied from or1k-tdep.c and others.  */
  20
  21 #include "defs.h"
  22
  23 #include "arch-utils.h"
  24 #include "dwarf2-frame.h"
  25 #include "common/errors.h"
  26 #include "frame-unwind.h"
  27 #include "gdbcore.h"
  28 #include "gdbcmd.h"
  29 #include "inferior.h"
  30 #include "opcode/s12z.h"
  31 #include "trad-frame.h"
  32 #include "remote.h"
  33
  34 /* Two of the registers included in S12Z_N_REGISTERS are
  35    the CCH and CCL "registers" which are just views into
  36    the CCW register.  */
  37 #define N_PHYSICAL_REGISTERS (S12Z_N_REGISTERS - 2)
  38
  39
  40 /*  A permutation of all the physical registers.   Indexing this array
  41     with an integer from gdb's internal representation will return the
  42     register enum.  */
  43 static const int reg_perm[N_PHYSICAL_REGISTERS] =
  44   {
  45    REG_D0,
  46    REG_D1,
  47    REG_D2,
  48    REG_D3,
  49    REG_D4,
  50    REG_D5,
  51    REG_D6,
  52    REG_D7,
  53    REG_X,
  54    REG_Y,
  55    REG_S,
  56    REG_P,
  57    REG_CCW
  58   };
  59
  60 /*  The inverse of the above permutation.  Indexing this
  61     array with a register enum (e.g. REG_D2) will return the register
  62     number in gdb's internal representation.  */
  63 static const int inv_reg_perm[N_PHYSICAL_REGISTERS] =
  64   {
  65    2, 3, 4, 5,      /* d2, d3, d4, d5 */
  66    0, 1,            /* d0, d1 */
  67    6, 7,            /* d6, d7 */
  68    8, 9, 10, 11, 12 /* x, y, s, p, ccw */
  69   };
  70
  71 /*  Return the name of the register REGNUM.  */
  72 static const char *
  73 s12z_register_name (struct gdbarch *gdbarch, int regnum)
  74 {
  75   /*  Registers is declared in opcodes/s12z.h.   */
  76   return registers[reg_perm[regnum]].name;
  77 }
  78
  79 static CORE_ADDR
  80 s12z_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
  81 {
  82   CORE_ADDR start_pc = 0;
  83
  84   if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
  85     {
  86       CORE_ADDR prologue_end = skip_prologue_using_sal (gdbarch, pc);
  87
  88       if (prologue_end != 0)
  89         return prologue_end;
  90     }
  91
  92   warning (_("%s Failed to find end of prologue PC = %08x\n"),
  93                       __FUNCTION__, (unsigned int) pc);
  94
  95   return pc;
  96 }
  97
  98 static struct type *
  99 s12z_register_type (struct gdbarch *gdbarch, int reg_nr)
 100 {
 101   switch (registers[reg_perm[reg_nr]].bytes)
 102     {
 103     case 1:
 104       return builtin_type (gdbarch)->builtin_uint8;
 105     case 2:
 106       return builtin_type (gdbarch)->builtin_uint16;
 107     case 3:
 108       return builtin_type (gdbarch)->builtin_uint24;
 109     case 4:
 110       return builtin_type (gdbarch)->builtin_uint32;
 111     default:
 112       return builtin_type (gdbarch)->builtin_uint32;
 113     }
 114   return builtin_type (gdbarch)->builtin_int0;
 115 }
 116
 117
 118 static int
 119 s12z_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int num)
 120 {
 121   switch (num)
 122     {
 123     case 15:      return REG_S;
 124     case 7:       return REG_X;
 125     case 8:       return REG_Y;
 126     case 42:      return REG_D0;
 127     case 43:      return REG_D1;
 128     case 44:      return REG_D2;
 129     case 45:      return REG_D3;
 130     case 46:      return REG_D4;
 131     case 47:      return REG_D5;
 132     case 48:      return REG_D6;
 133     case 49:      return REG_D7;
 134     }
 135   return -1;
 136 }
 137
 138
 139 /* Support functions for frame handling.  */
 140
 141 /* Copy of gdb_buffered_insn_length_fprintf from disasm.c.  */
 142
 143 static int ATTRIBUTE_PRINTF (2, 3)
 144 s12z_fprintf_disasm (void *stream, const char *format, ...)
 145 {
 146   return 0;
 147 }
 148
 149 struct disassemble_info
 150 s12z_disassemble_info (struct gdbarch *gdbarch)
 151 {
 152   struct disassemble_info di;
 153   init_disassemble_info (&di, &null_stream, s12z_fprintf_disasm);
 154   di.arch = gdbarch_bfd_arch_info (gdbarch)->arch;
 155   di.mach = gdbarch_bfd_arch_info (gdbarch)->mach;
 156   di.endian = gdbarch_byte_order (gdbarch);
 157   di.read_memory_func = [](bfd_vma memaddr, gdb_byte *myaddr,
 158                            unsigned int len, struct disassemble_info *info)
 159     {
 160       return target_read_code (memaddr, myaddr, len);
 161     };
 162   return di;
 163 }
 164
 165 /* Initialize a prologue cache.  */
 166
 167 static struct trad_frame_cache *
 168 s12z_frame_cache (struct frame_info *this_frame, void **prologue_cache)
 169 {
 170   struct trad_frame_cache *info;
 171
 172   CORE_ADDR this_sp;
 173   CORE_ADDR this_sp_for_id;
 174
 175   CORE_ADDR start_addr;
 176   CORE_ADDR end_addr;
 177
 178   /* Nothing to do if we already have this info.  */
 179   if (NULL != *prologue_cache)
 180     return (struct trad_frame_cache *) *prologue_cache;
 181
 182   /* Get a new prologue cache and populate it with default values.  */
 183   info = trad_frame_cache_zalloc (this_frame);
 184   *prologue_cache = info;
 185
 186   /* Find the start address of this function (which is a normal frame, even
 187      if the next frame is the sentinel frame) and the end of its prologue.  */
 188   CORE_ADDR this_pc = get_frame_pc (this_frame);
 189   struct gdbarch *gdbarch = get_frame_arch (this_frame);
 190   find_pc_partial_function (this_pc, NULL, &start_addr, NULL);
 191
 192   /* Get the stack pointer if we have one (if there's no process executing
 193      yet we won't have a frame.  */
 194   this_sp = (NULL == this_frame) ? 0 :
 195     get_frame_register_unsigned (this_frame, REG_S);
 196
 197   /* Return early if GDB couldn't find the function.  */
 198   if (start_addr == 0)
 199     {
 200       warning (_("Couldn't find function including address %s SP is %s\n"),
 201                paddress (gdbarch, this_pc),
 202                paddress (gdbarch, this_sp));
 203
 204       /* JPB: 28-Apr-11.  This is a temporary patch, to get round GDB
 205          crashing right at the beginning.  Build the frame ID as best we
 206          can.  */
 207       trad_frame_set_id (info, frame_id_build (this_sp, this_pc));
 208
 209       return info;
 210     }
 211
 212   /* The default frame base of this frame (for ID purposes only - frame
 213      base is an overloaded term) is its stack pointer.  For now we use the
 214      value of the SP register in this frame.  However if the PC is in the
 215      prologue of this frame, before the SP has been set up, then the value
 216      will actually be that of the prev frame, and we'll need to adjust it
 217      later.  */
 218   trad_frame_set_this_base (info, this_sp);
 219   this_sp_for_id = this_sp;
 220
 221   /* We should only examine code that is in the prologue.  This is all code
 222      up to (but not including) end_addr.  We should only populate the cache
 223      while the address is up to (but not including) the PC or end_addr,
 224      whichever is first.  */
 225   end_addr = s12z_skip_prologue (gdbarch, start_addr);
 226
 227   /* All the following analysis only occurs if we are in the prologue and
 228      have executed the code.  Check we have a sane prologue size, and if
 229      zero we are frameless and can give up here.  */
 230   if (end_addr < start_addr)
 231     error (_("end addr %s is less than start addr %s"),
 232            paddress (gdbarch, end_addr), paddress (gdbarch, start_addr));
 233
 234   CORE_ADDR addr = start_addr; /* Where we have got to?  */
 235   int frame_size = 0;
 236   int saved_frame_size = 0;
 237   while (this_pc > addr)
 238     {
 239       struct disassemble_info di = s12z_disassemble_info (gdbarch);
 240
 241       /* No instruction can be more than 11 bytes long, I think.  */
 242       gdb_byte buf[11];
 243
 244       int nb = print_insn_s12z (addr, &di);
 245       gdb_assert (nb <= 11);
 246
 247       if (0 != target_read_code (addr, buf, nb))
 248         memory_error (TARGET_XFER_E_IO, addr);
 249
 250       if (buf[0] == 0x05)        /* RTS */
 251         {
 252           frame_size = saved_frame_size;
 253         }
 254       /* Conditional Branches.   If any of these are encountered, then
 255          it is likely that a RTS will terminate it.  So we need to save
 256          the frame size so it can be restored.  */
 257       else if ( (buf[0] == 0x02)      /* BRSET */
 258                 || (buf[0] == 0x0B)   /* DBcc / TBcc */
 259                 || (buf[0] == 0x03))  /* BRCLR */
 260         {
 261           saved_frame_size = frame_size;
 262         }
 263       else if (buf[0] == 0x04)        /* PUL/ PSH .. */
 264         {
 265           bool pull = buf[1] & 0x80;
 266           int stack_adjustment = 0;
 267           if (buf[1] & 0x40)
 268             {
 269               if (buf[1] & 0x01) stack_adjustment += 3;  /* Y */
 270               if (buf[1] & 0x02) stack_adjustment += 3;  /* X */
 271               if (buf[1] & 0x04) stack_adjustment += 4;  /* D7 */
 272               if (buf[1] & 0x08) stack_adjustment += 4;  /* D6 */
 273               if (buf[1] & 0x10) stack_adjustment += 2;  /* D5 */
 274               if (buf[1] & 0x20) stack_adjustment += 2;  /* D4 */
 275             }
 276           else
 277             {
 278               if (buf[1] & 0x01) stack_adjustment += 2;  /* D3 */
 279               if (buf[1] & 0x02) stack_adjustment += 2;  /* D2 */
 280               if (buf[1] & 0x04) stack_adjustment += 1;  /* D1 */
 281               if (buf[1] & 0x08) stack_adjustment += 1;  /* D0 */
 282               if (buf[1] & 0x10) stack_adjustment += 1;  /* CCL */
 283               if (buf[1] & 0x20) stack_adjustment += 1;  /* CCH */
 284             }
 285
 286           if (!pull)
 287             stack_adjustment = -stack_adjustment;
 288           frame_size -= stack_adjustment;
 289         }
 290       else if (buf[0] == 0x0a)   /* LEA S, (xxx, S) */
 291         {
 292           if (0x06 == (buf[1] >> 4))
 293             {
 294               int simm = (signed char) (buf[1] & 0x0F);
 295               frame_size -= simm;
 296             }
 297         }
 298       else if (buf[0] == 0x1a)   /* LEA S, (S, xxxx) */
 299         {
 300           int simm = (signed char) buf[1];
 301           frame_size -= simm;
 302         }
 303       addr += nb;
 304     }
 305
 306   /* If the PC has not actually got to this point, then the frame
 307      base will be wrong, and we adjust it. */
 308   if (this_pc < addr)
 309     {
 310       /* Only do if executing.  */
 311       if (0 != this_sp)
 312         {
 313           this_sp_for_id = this_sp - frame_size;
 314           trad_frame_set_this_base (info, this_sp_for_id);
 315         }
 316       trad_frame_set_reg_value (info, REG_S, this_sp + 3);
 317       trad_frame_set_reg_addr (info, REG_P, this_sp);
 318     }
 319   else
 320     {
 321       gdb_assert (this_sp == this_sp_for_id);
 322       /* The stack pointer of the prev frame is frame_size greater
 323          than the stack pointer of this frame plus one address
 324          size (caused by the JSR or BSR).  */
 325       trad_frame_set_reg_value (info, REG_S,
 326                                 this_sp + frame_size + 3);
 327       trad_frame_set_reg_addr (info, REG_P, this_sp + frame_size);
 328     }
 329
 330
 331   /* Build the frame ID.  */
 332   trad_frame_set_id (info, frame_id_build (this_sp_for_id, start_addr));
 333
 334   return info;
 335 }
 336
 337 /* Implement the this_id function for the stub unwinder.  */
 338 static void
 339 s12z_frame_this_id (struct frame_info *this_frame,
 340                     void **prologue_cache, struct frame_id *this_id)
 341 {
 342   struct trad_frame_cache *info = s12z_frame_cache (this_frame,
 343                                                     prologue_cache);
 344
 345   trad_frame_get_id (info, this_id);
 346 }
 347
 348
 349 /* Implement the prev_register function for the stub unwinder.  */
 350 static struct value *
 351 s12z_frame_prev_register (struct frame_info *this_frame,
 352                           void **prologue_cache, int regnum)
 353 {
 354   struct trad_frame_cache *info = s12z_frame_cache (this_frame,
 355                                                     prologue_cache);
 356
 357   return trad_frame_get_register (info, this_frame, regnum);
 358 }
 359
 360 /* Data structures for the normal prologue-analysis-based unwinder.  */
 361 static const struct frame_unwind s12z_frame_unwind = {
 362   NORMAL_FRAME,
 363   default_frame_unwind_stop_reason,
 364   s12z_frame_this_id,
 365   s12z_frame_prev_register,
 366   NULL,
 367   default_frame_sniffer,
 368   NULL,
 369 };
 370
 371
 372 constexpr gdb_byte s12z_break_insn[] = {0x00};
 373
 374 typedef BP_MANIPULATION (s12z_break_insn) s12z_breakpoint;
 375
 376 struct gdbarch_tdep
 377 {
 378 };
 379
 380 /*  A vector of human readable characters representing the
 381     bits in the CCW register.  Unused bits are represented as '-'.
 382     Lowest significant bit comes first.  */
 383 static const char ccw_bits[] =
 384   {
 385    'C',  /* Carry  */
 386    'V',  /* Two's Complement Overflow  */
 387    'Z',  /* Zero  */
 388    'N',  /* Negative  */
 389    'I',  /* Interrupt  */
 390    '-',
 391    'X',  /* Non-Maskable Interrupt  */
 392    'S',  /* STOP Disable  */
 393    '0',  /*  Interrupt priority level */
 394    '0',  /*  ditto  */
 395    '0',  /*  ditto  */
 396    '-',
 397    '-',
 398    '-',
 399    '-',
 400    'U'   /* User/Supervisor State.  */
 401   };
 402
 403 /* Print a human readable representation of the CCW register.
 404    For example: "u----000SX-Inzvc" corresponds to the value
 405    0xD0.  */
 406 static void
 407 s12z_print_ccw_info (struct gdbarch *gdbarch,
 408                      struct ui_file *file,
 409                      struct frame_info *frame,
 410                      int reg)
 411 {
 412   struct value *v = value_of_register (reg, frame);
 413   const char *name = gdbarch_register_name (gdbarch, reg);
 414   uint32_t ccw = value_as_long (v);
 415   fputs_filtered (name, file);
 416   size_t len = strlen (name);
 417   const int stop_1 = 15;
 418   const int stop_2 = 17;
 419   for (int i = 0; i < stop_1 - len; ++i)
 420     fputc_filtered (' ', file);
 421   fprintf_filtered (file, "0x%04x", ccw);
 422   for (int i = 0; i < stop_2 - len; ++i)
 423     fputc_filtered (' ', file);
 424   for (int b = 15; b >= 0; --b)
 425     {
 426       if (ccw & (0x1u << b))
 427         {
 428           if (ccw_bits[b] == 0)
 429             fputc_filtered ('1', file);
 430           else
 431             fputc_filtered (ccw_bits[b], file);
 432         }
 433       else
 434         fputc_filtered (tolower (ccw_bits[b]), file);
 435     }
 436   fputc_filtered ('\n', file);
 437 }
 438
 439 static void
 440 s12z_print_registers_info (struct gdbarch *gdbarch,
 441                             struct ui_file *file,
 442                             struct frame_info *frame,
 443                             int regnum, int print_all)
 444 {
 445   const int numregs = (gdbarch_num_regs (gdbarch)
 446                        + gdbarch_num_pseudo_regs (gdbarch));
 447
 448   if (regnum == -1)
 449     {
 450       for (int reg = 0; reg < numregs; reg++)
 451         {
 452           if (REG_CCW == reg_perm[reg])
 453             {
 454               s12z_print_ccw_info (gdbarch, file, frame, reg);
 455               continue;
 456             }
 457           default_print_registers_info (gdbarch, file, frame, reg, print_all);
 458         }
 459     }
 460   else if (REG_CCW == reg_perm[regnum])
 461     s12z_print_ccw_info (gdbarch, file, frame, regnum);
 462   else
 463     default_print_registers_info (gdbarch, file, frame, regnum, print_all);
 464 }
 465
 466 \f
 467
 468
 469 static void
 470 s12z_extract_return_value (struct type *type, struct regcache *regcache,
 471                               void *valbuf)
 472 {
 473   int reg = -1;
 474
 475   switch (TYPE_LENGTH (type))
 476     {
 477     case 0:   /* Nothing to do */
 478       return;
 479
 480     case 1:
 481       reg = REG_D0;
 482       break;
 483
 484     case 2:
 485       reg = REG_D2;
 486       break;
 487
 488     case 3:
 489       reg = REG_X;
 490       break;
 491
 492     case 4:
 493       reg = REG_D6;
 494       break;
 495
 496     default:
 497       error (_("bad size for return value"));
 498       return;
 499     }
 500
 501   regcache->cooked_read (inv_reg_perm[reg], (gdb_byte *) valbuf);
 502 }
 503
 504 static enum return_value_convention
 505 s12z_return_value (struct gdbarch *gdbarch, struct value *function,
 506                    struct type *type, struct regcache *regcache,
 507                    gdb_byte *readbuf, const gdb_byte *writebuf)
 508 {
 509   if (TYPE_CODE (type) == TYPE_CODE_STRUCT
 510       || TYPE_CODE (type) == TYPE_CODE_UNION
 511       || TYPE_CODE (type) == TYPE_CODE_ARRAY
 512       || TYPE_LENGTH (type) > 4)
 513     return RETURN_VALUE_STRUCT_CONVENTION;
 514
 515   if (readbuf)
 516     s12z_extract_return_value (type, regcache, readbuf);
 517
 518   return RETURN_VALUE_REGISTER_CONVENTION;
 519 }
 520
 521
 522 static void
 523 show_bdccsr_command (const char *args, int from_tty)
 524 {
 525   struct string_file output;
 526   target_rcmd ("bdccsr", &output);
 527
 528   printf_unfiltered ("The current BDCCSR value is %s\n", output.string().c_str());
 529 }
 530
 531 static struct gdbarch *
 532 s12z_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 533 {
 534   struct gdbarch_tdep *tdep = XNEW (struct gdbarch_tdep);
 535   struct gdbarch *gdbarch = gdbarch_alloc (&info, tdep);
 536
 537   add_cmd ("bdccsr", class_support, show_bdccsr_command,
 538            _("Show the current value of the microcontroller's BDCCSR."),
 539            &maintenanceinfolist);
 540
 541   /* Target data types.  */
 542   set_gdbarch_short_bit (gdbarch, 16);
 543   set_gdbarch_int_bit (gdbarch, 16);
 544   set_gdbarch_long_bit (gdbarch, 32);
 545   set_gdbarch_long_long_bit (gdbarch, 32);
 546   set_gdbarch_ptr_bit (gdbarch, 24);
 547   set_gdbarch_addr_bit (gdbarch, 24);
 548   set_gdbarch_char_signed (gdbarch, 0);
 549
 550   set_gdbarch_ps_regnum (gdbarch, REG_CCW);
 551   set_gdbarch_pc_regnum (gdbarch, REG_P);
 552   set_gdbarch_sp_regnum (gdbarch, REG_S);
 553
 554
 555   set_gdbarch_print_registers_info (gdbarch, s12z_print_registers_info);
 556
 557   set_gdbarch_breakpoint_kind_from_pc (gdbarch,
 558                                        s12z_breakpoint::kind_from_pc);
 559   set_gdbarch_sw_breakpoint_from_kind (gdbarch,
 560                                        s12z_breakpoint::bp_from_kind);
 561
 562   set_gdbarch_num_regs (gdbarch, N_PHYSICAL_REGISTERS);
 563   set_gdbarch_register_name (gdbarch, s12z_register_name);
 564   set_gdbarch_skip_prologue (gdbarch, s12z_skip_prologue);
 565   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
 566   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, s12z_dwarf_reg_to_regnum);
 567
 568   set_gdbarch_register_type (gdbarch, s12z_register_type);
 569
 570   frame_unwind_append_unwinder (gdbarch, &s12z_frame_unwind);
 571   /* Currently, the only known producer for this archtecture, produces buggy
 572      dwarf CFI.   So don't append a dwarf unwinder until the situation is
 573      better understood.  */
 574
 575   set_gdbarch_return_value (gdbarch, s12z_return_value);
 576
 577   return gdbarch;
 578 }
 579
 580 void
 581 _initialize_s12z_tdep (void)
 582 {
 583   gdbarch_register (bfd_arch_s12z, s12z_gdbarch_init, NULL);
 584 }