gdb/sh-tdep.c

   1 /* Target-dependent code for Renesas Super-H, for GDB.
   2
   3    Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
   4    2003, 2004, 2005, 2007, 2008, 2009, 2010, 2011
   5    Free Software Foundation, Inc.
   6
   7    This file is part of GDB.
   8
   9    This program is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3 of the License, or
  12    (at your option) any later version.
  13
  14    This program is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  21
  22 /*
  23    Contributed by Steve Chamberlain
  24    sac@cygnus.com
  25  */
  26
  27 #include "defs.h"
  28 #include "frame.h"
  29 #include "frame-base.h"
  30 #include "frame-unwind.h"
  31 #include "dwarf2-frame.h"
  32 #include "symtab.h"
  33 #include "gdbtypes.h"
  34 #include "gdbcmd.h"
  35 #include "gdbcore.h"
  36 #include "value.h"
  37 #include "dis-asm.h"
  38 #include "inferior.h"
  39 #include "gdb_string.h"
  40 #include "gdb_assert.h"
  41 #include "arch-utils.h"
  42 #include "floatformat.h"
  43 #include "regcache.h"
  44 #include "doublest.h"
  45 #include "osabi.h"
  46 #include "reggroups.h"
  47 #include "regset.h"
  48
  49 #include "sh-tdep.h"
  50
  51 #include "elf-bfd.h"
  52 #include "solib-svr4.h"
  53
  54 /* sh flags */
  55 #include "elf/sh.h"
  56 #include "dwarf2.h"
  57 /* registers numbers shared with the simulator */
  58 #include "gdb/sim-sh.h"
  59
  60 /* List of "set sh ..." and "show sh ..." commands.  */
  61 static struct cmd_list_element *setshcmdlist = NULL;
  62 static struct cmd_list_element *showshcmdlist = NULL;
  63
  64 static const char sh_cc_gcc[] = "gcc";
  65 static const char sh_cc_renesas[] = "renesas";
  66 static const char *sh_cc_enum[] = {
  67   sh_cc_gcc,
  68   sh_cc_renesas,
  69   NULL
  70 };
  71
  72 static const char *sh_active_calling_convention = sh_cc_gcc;
  73
  74 static void (*sh_show_regs) (struct frame_info *);
  75
  76 #define SH_NUM_REGS 67
  77
  78 struct sh_frame_cache
  79 {
  80   /* Base address.  */
  81   CORE_ADDR base;
  82   LONGEST sp_offset;
  83   CORE_ADDR pc;
  84
  85   /* Flag showing that a frame has been created in the prologue code. */
  86   int uses_fp;
  87
  88   /* Saved registers.  */
  89   CORE_ADDR saved_regs[SH_NUM_REGS];
  90   CORE_ADDR saved_sp;
  91 };
  92
  93 static int
  94 sh_is_renesas_calling_convention (struct type *func_type)
  95 {
  96   return ((func_type
  97            && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GNU_renesas_sh)
  98           || sh_active_calling_convention == sh_cc_renesas);
  99 }
 100
 101 static const char *
 102 sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr)
 103 {
 104   static char *register_names[] = {
 105     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 106     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 107     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 108     "", "",
 109     "", "", "", "", "", "", "", "",
 110     "", "", "", "", "", "", "", "",
 111     "", "",
 112     "", "", "", "", "", "", "", "",
 113     "", "", "", "", "", "", "", "",
 114     "", "", "", "", "", "", "", "",
 115   };
 116   if (reg_nr < 0)
 117     return NULL;
 118   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 119     return NULL;
 120   return register_names[reg_nr];
 121 }
 122
 123 static const char *
 124 sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr)
 125 {
 126   static char *register_names[] = {
 127     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 128     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 129     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 130     "", "",
 131     "", "", "", "", "", "", "", "",
 132     "", "", "", "", "", "", "", "",
 133     "ssr", "spc",
 134     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
 135     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
 136     "", "", "", "", "", "", "", "",
 137   };
 138   if (reg_nr < 0)
 139     return NULL;
 140   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 141     return NULL;
 142   return register_names[reg_nr];
 143 }
 144
 145 static const char *
 146 sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr)
 147 {
 148   static char *register_names[] = {
 149     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 150     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 151     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 152     "fpul", "fpscr",
 153     "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
 154     "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
 155     "ssr", "spc",
 156     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
 157     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
 158     "", "", "", "", "", "", "", "",
 159   };
 160   if (reg_nr < 0)
 161     return NULL;
 162   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 163     return NULL;
 164   return register_names[reg_nr];
 165 }
 166
 167 static const char *
 168 sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr)
 169 {
 170   static char *register_names[] = {
 171     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 172     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 173     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 174     "fpul", "fpscr",
 175     "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
 176     "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
 177     "", "",
 178     "", "", "", "", "", "", "", "",
 179     "", "", "", "", "", "", "", "",
 180     "", "", "", "", "", "", "", "",
 181   };
 182   if (reg_nr < 0)
 183     return NULL;
 184   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 185     return NULL;
 186   return register_names[reg_nr];
 187 }
 188
 189 static const char *
 190 sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr)
 191 {
 192   static char *register_names[] = {
 193     /* general registers 0-15 */
 194     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 195     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 196     /* 16 - 22 */
 197     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 198     /* 23, 24 */
 199     "fpul", "fpscr",
 200     /* floating point registers 25 - 40 */
 201     "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
 202     "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
 203     /* 41, 42 */
 204     "", "",
 205     /* 43 - 62.  Banked registers.  The bank number used is determined by
 206        the bank register (63). */
 207     "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
 208     "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
 209     "machb", "ivnb", "prb", "gbrb", "maclb",
 210     /* 63: register bank number, not a real register but used to
 211        communicate the register bank currently get/set.  This register
 212        is hidden to the user, who manipulates it using the pseudo
 213        register called "bank" (67).  See below.  */
 214     "",
 215     /* 64 - 66 */
 216     "ibcr", "ibnr", "tbr",
 217     /* 67: register bank number, the user visible pseudo register.  */
 218     "bank",
 219     /* double precision (pseudo) 68 - 75 */
 220     "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
 221   };
 222   if (reg_nr < 0)
 223     return NULL;
 224   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 225     return NULL;
 226   return register_names[reg_nr];
 227 }
 228
 229 static const char *
 230 sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
 231 {
 232   static char *register_names[] = {
 233     /* general registers 0-15 */
 234     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 235     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 236     /* 16 - 22 */
 237     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 238     /* 23, 24 */
 239     "", "",
 240     /* floating point registers 25 - 40 */
 241     "", "", "", "", "", "", "", "",
 242     "", "", "", "", "", "", "", "",
 243     /* 41, 42 */
 244     "", "",
 245     /* 43 - 62.  Banked registers.  The bank number used is determined by
 246        the bank register (63). */
 247     "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
 248     "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
 249     "machb", "ivnb", "prb", "gbrb", "maclb",
 250     /* 63: register bank number, not a real register but used to
 251        communicate the register bank currently get/set.  This register
 252        is hidden to the user, who manipulates it using the pseudo
 253        register called "bank" (67).  See below.  */
 254     "",
 255     /* 64 - 66 */
 256     "ibcr", "ibnr", "tbr",
 257     /* 67: register bank number, the user visible pseudo register.  */
 258     "bank",
 259     /* double precision (pseudo) 68 - 75 */
 260     "", "", "", "", "", "", "", "",
 261   };
 262   if (reg_nr < 0)
 263     return NULL;
 264   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 265     return NULL;
 266   return register_names[reg_nr];
 267 }
 268
 269 static const char *
 270 sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
 271 {
 272   static char *register_names[] = {
 273     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 274     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 275     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 276     "", "dsr",
 277     "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
 278     "y0", "y1", "", "", "", "", "", "mod",
 279     "", "",
 280     "rs", "re", "", "", "", "", "", "",
 281     "", "", "", "", "", "", "", "",
 282     "", "", "", "", "", "", "", "",
 283   };
 284   if (reg_nr < 0)
 285     return NULL;
 286   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 287     return NULL;
 288   return register_names[reg_nr];
 289 }
 290
 291 static const char *
 292 sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
 293 {
 294   static char *register_names[] = {
 295     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 296     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 297     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 298     "", "dsr",
 299     "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
 300     "y0", "y1", "", "", "", "", "", "mod",
 301     "ssr", "spc",
 302     "rs", "re", "", "", "", "", "", "",
 303     "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
 304     "", "", "", "", "", "", "", "",
 305     "", "", "", "", "", "", "", "",
 306   };
 307   if (reg_nr < 0)
 308     return NULL;
 309   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 310     return NULL;
 311   return register_names[reg_nr];
 312 }
 313
 314 static const char *
 315 sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr)
 316 {
 317   static char *register_names[] = {
 318     /* general registers 0-15 */
 319     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 320     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 321     /* 16 - 22 */
 322     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 323     /* 23, 24 */
 324     "fpul", "fpscr",
 325     /* floating point registers 25 - 40 */
 326     "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
 327     "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
 328     /* 41, 42 */
 329     "ssr", "spc",
 330     /* bank 0 43 - 50 */
 331     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
 332     /* bank 1 51 - 58 */
 333     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
 334     "", "", "", "", "", "", "", "",
 335     /* pseudo bank register. */
 336     "",
 337     /* double precision (pseudo) 59 - 66 */
 338     "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
 339     /* vectors (pseudo) 67 - 70 */
 340     "fv0", "fv4", "fv8", "fv12",
 341     /* FIXME: missing XF 71 - 86 */
 342     /* FIXME: missing XD 87 - 94 */
 343   };
 344   if (reg_nr < 0)
 345     return NULL;
 346   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 347     return NULL;
 348   return register_names[reg_nr];
 349 }
 350
 351 static const char *
 352 sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
 353 {
 354   static char *register_names[] = {
 355     /* general registers 0-15 */
 356     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 357     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 358     /* 16 - 22 */
 359     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 360     /* 23, 24 */
 361     "", "",
 362     /* floating point registers 25 - 40 -- not for nofpu target */
 363     "", "", "", "", "", "", "", "",
 364     "", "", "", "", "", "", "", "",
 365     /* 41, 42 */
 366     "ssr", "spc",
 367     /* bank 0 43 - 50 */
 368     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
 369     /* bank 1 51 - 58 */
 370     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
 371     "", "", "", "", "", "", "", "",
 372     /* pseudo bank register. */
 373     "",
 374     /* double precision (pseudo) 59 - 66 -- not for nofpu target */
 375     "", "", "", "", "", "", "", "",
 376     /* vectors (pseudo) 67 - 70 -- not for nofpu target */
 377     "", "", "", "",
 378   };
 379   if (reg_nr < 0)
 380     return NULL;
 381   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 382     return NULL;
 383   return register_names[reg_nr];
 384 }
 385
 386 static const char *
 387 sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
 388 {
 389   static char *register_names[] = {
 390     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 391     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 392     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 393     "", "dsr",
 394     "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
 395     "y0", "y1", "", "", "", "", "", "mod",
 396     "ssr", "spc",
 397     "rs", "re", "", "", "", "", "", "",
 398     "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
 399     "", "", "", "", "", "", "", "",
 400     "", "", "", "", "", "", "", "",
 401   };
 402   if (reg_nr < 0)
 403     return NULL;
 404   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 405     return NULL;
 406   return register_names[reg_nr];
 407 }
 408
 409 static const unsigned char *
 410 sh_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
 411 {
 412   /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
 413   static unsigned char breakpoint[] = { 0xc3, 0xc3 };
 414
 415   /* For remote stub targets, trapa #20 is used.  */
 416   if (strcmp (target_shortname, "remote") == 0)
 417     {
 418       static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 };
 419       static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 };
 420
 421       if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
 422         {
 423           *lenptr = sizeof (big_remote_breakpoint);
 424           return big_remote_breakpoint;
 425         }
 426       else
 427         {
 428           *lenptr = sizeof (little_remote_breakpoint);
 429           return little_remote_breakpoint;
 430         }
 431     }
 432
 433   *lenptr = sizeof (breakpoint);
 434   return breakpoint;
 435 }
 436
 437 /* Prologue looks like
 438    mov.l        r14,@-r15
 439    sts.l        pr,@-r15
 440    mov.l        <regs>,@-r15
 441    sub          <room_for_loca_vars>,r15
 442    mov          r15,r14
 443
 444    Actually it can be more complicated than this but that's it, basically.
 445  */
 446
 447 #define GET_SOURCE_REG(x)       (((x) >> 4) & 0xf)
 448 #define GET_TARGET_REG(x)       (((x) >> 8) & 0xf)
 449
 450 /* JSR @Rm         0100mmmm00001011 */
 451 #define IS_JSR(x)               (((x) & 0xf0ff) == 0x400b)
 452
 453 /* STS.L PR,@-r15  0100111100100010
 454    r15-4-->r15, PR-->(r15) */
 455 #define IS_STS(x)               ((x) == 0x4f22)
 456
 457 /* STS.L MACL,@-r15  0100111100010010
 458    r15-4-->r15, MACL-->(r15) */
 459 #define IS_MACL_STS(x)          ((x) == 0x4f12)
 460
 461 /* MOV.L Rm,@-r15  00101111mmmm0110
 462    r15-4-->r15, Rm-->(R15) */
 463 #define IS_PUSH(x)              (((x) & 0xff0f) == 0x2f06)
 464
 465 /* MOV r15,r14     0110111011110011
 466    r15-->r14  */
 467 #define IS_MOV_SP_FP(x)         ((x) == 0x6ef3)
 468
 469 /* ADD #imm,r15    01111111iiiiiiii
 470    r15+imm-->r15 */
 471 #define IS_ADD_IMM_SP(x)        (((x) & 0xff00) == 0x7f00)
 472
 473 #define IS_MOV_R3(x)            (((x) & 0xff00) == 0x1a00)
 474 #define IS_SHLL_R3(x)           ((x) == 0x4300)
 475
 476 /* ADD r3,r15      0011111100111100
 477    r15+r3-->r15 */
 478 #define IS_ADD_R3SP(x)          ((x) == 0x3f3c)
 479
 480 /* FMOV.S FRm,@-Rn  Rn-4-->Rn, FRm-->(Rn)     1111nnnnmmmm1011
 481    FMOV DRm,@-Rn    Rn-8-->Rn, DRm-->(Rn)     1111nnnnmmm01011
 482    FMOV XDm,@-Rn    Rn-8-->Rn, XDm-->(Rn)     1111nnnnmmm11011 */
 483 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
 484                    make this entirely clear. */
 485 /* #define IS_FMOV(x)           (((x) & 0xf00f) == 0xf00b) */
 486 #define IS_FPUSH(x)             (((x) & 0xff0f) == 0xff0b)
 487
 488 /* MOV Rm,Rn          Rm-->Rn        0110nnnnmmmm0011  4 <= m <= 7 */
 489 #define IS_MOV_ARG_TO_REG(x) \
 490         (((x) & 0xf00f) == 0x6003 && \
 491          ((x) & 0x00f0) >= 0x0040 && \
 492          ((x) & 0x00f0) <= 0x0070)
 493 /* MOV.L Rm,@Rn               0010nnnnmmmm0010  n = 14, 4 <= m <= 7 */
 494 #define IS_MOV_ARG_TO_IND_R14(x) \
 495         (((x) & 0xff0f) == 0x2e02 && \
 496          ((x) & 0x00f0) >= 0x0040 && \
 497          ((x) & 0x00f0) <= 0x0070)
 498 /* MOV.L Rm,@(disp*4,Rn)      00011110mmmmdddd  n = 14, 4 <= m <= 7 */
 499 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
 500         (((x) & 0xff00) == 0x1e00 && \
 501          ((x) & 0x00f0) >= 0x0040 && \
 502          ((x) & 0x00f0) <= 0x0070)
 503
 504 /* MOV.W @(disp*2,PC),Rn      1001nnnndddddddd */
 505 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
 506 /* MOV.L @(disp*4,PC),Rn      1101nnnndddddddd */
 507 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
 508 /* MOVI20 #imm20,Rn           0000nnnniiii0000 */
 509 #define IS_MOVI20(x)            (((x) & 0xf00f) == 0x0000)
 510 /* SUB Rn,R15                 00111111nnnn1000 */
 511 #define IS_SUB_REG_FROM_SP(x)   (((x) & 0xff0f) == 0x3f08)
 512
 513 #define FPSCR_SZ                (1 << 20)
 514
 515 /* The following instructions are used for epilogue testing. */
 516 #define IS_RESTORE_FP(x)        ((x) == 0x6ef6)
 517 #define IS_RTS(x)               ((x) == 0x000b)
 518 #define IS_LDS(x)               ((x) == 0x4f26)
 519 #define IS_MACL_LDS(x)          ((x) == 0x4f16)
 520 #define IS_MOV_FP_SP(x)         ((x) == 0x6fe3)
 521 #define IS_ADD_REG_TO_FP(x)     (((x) & 0xff0f) == 0x3e0c)
 522 #define IS_ADD_IMM_FP(x)        (((x) & 0xff00) == 0x7e00)
 523
 524 static CORE_ADDR
 525 sh_analyze_prologue (struct gdbarch *gdbarch,
 526                      CORE_ADDR pc, CORE_ADDR current_pc,
 527                      struct sh_frame_cache *cache, ULONGEST fpscr)
 528 {
 529   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 530   ULONGEST inst;
 531   CORE_ADDR opc;
 532   int offset;
 533   int sav_offset = 0;
 534   int r3_val = 0;
 535   int reg, sav_reg = -1;
 536
 537   if (pc >= current_pc)
 538     return current_pc;
 539
 540   cache->uses_fp = 0;
 541   for (opc = pc + (2 * 28); pc < opc; pc += 2)
 542     {
 543       inst = read_memory_unsigned_integer (pc, 2, byte_order);
 544       /* See where the registers will be saved to */
 545       if (IS_PUSH (inst))
 546         {
 547           cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
 548           cache->sp_offset += 4;
 549         }
 550       else if (IS_STS (inst))
 551         {
 552           cache->saved_regs[PR_REGNUM] = cache->sp_offset;
 553           cache->sp_offset += 4;
 554         }
 555       else if (IS_MACL_STS (inst))
 556         {
 557           cache->saved_regs[MACL_REGNUM] = cache->sp_offset;
 558           cache->sp_offset += 4;
 559         }
 560       else if (IS_MOV_R3 (inst))
 561         {
 562           r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
 563         }
 564       else if (IS_SHLL_R3 (inst))
 565         {
 566           r3_val <<= 1;
 567         }
 568       else if (IS_ADD_R3SP (inst))
 569         {
 570           cache->sp_offset += -r3_val;
 571         }
 572       else if (IS_ADD_IMM_SP (inst))
 573         {
 574           offset = ((inst & 0xff) ^ 0x80) - 0x80;
 575           cache->sp_offset -= offset;
 576         }
 577       else if (IS_MOVW_PCREL_TO_REG (inst))
 578         {
 579           if (sav_reg < 0)
 580             {
 581               reg = GET_TARGET_REG (inst);
 582               if (reg < 14)
 583                 {
 584                   sav_reg = reg;
 585                   offset = (inst & 0xff) << 1;
 586                   sav_offset =
 587                     read_memory_integer ((pc + 4) + offset, 2, byte_order);
 588                 }
 589             }
 590         }
 591       else if (IS_MOVL_PCREL_TO_REG (inst))
 592         {
 593           if (sav_reg < 0)
 594             {
 595               reg = GET_TARGET_REG (inst);
 596               if (reg < 14)
 597                 {
 598                   sav_reg = reg;
 599                   offset = (inst & 0xff) << 2;
 600                   sav_offset =
 601                     read_memory_integer (((pc & 0xfffffffc) + 4) + offset,
 602                                          4, byte_order);
 603                 }
 604             }
 605         }
 606       else if (IS_MOVI20 (inst))
 607         {
 608           if (sav_reg < 0)
 609             {
 610               reg = GET_TARGET_REG (inst);
 611               if (reg < 14)
 612                 {
 613                   sav_reg = reg;
 614                   sav_offset = GET_SOURCE_REG (inst) << 16;
 615                   /* MOVI20 is a 32 bit instruction! */
 616                   pc += 2;
 617                   sav_offset
 618                     |= read_memory_unsigned_integer (pc, 2, byte_order);
 619                   /* Now sav_offset contains an unsigned 20 bit value.
 620                      It must still get sign extended.  */
 621                   if (sav_offset & 0x00080000)
 622                     sav_offset |= 0xfff00000;
 623                 }
 624             }
 625         }
 626       else if (IS_SUB_REG_FROM_SP (inst))
 627         {
 628           reg = GET_SOURCE_REG (inst);
 629           if (sav_reg > 0 && reg == sav_reg)
 630             {
 631               sav_reg = -1;
 632             }
 633           cache->sp_offset += sav_offset;
 634         }
 635       else if (IS_FPUSH (inst))
 636         {
 637           if (fpscr & FPSCR_SZ)
 638             {
 639               cache->sp_offset += 8;
 640             }
 641           else
 642             {
 643               cache->sp_offset += 4;
 644             }
 645         }
 646       else if (IS_MOV_SP_FP (inst))
 647         {
 648           cache->uses_fp = 1;
 649           /* At this point, only allow argument register moves to other
 650              registers or argument register moves to @(X,fp) which are
 651              moving the register arguments onto the stack area allocated
 652              by a former add somenumber to SP call.  Don't allow moving
 653              to an fp indirect address above fp + cache->sp_offset. */
 654           pc += 2;
 655           for (opc = pc + 12; pc < opc; pc += 2)
 656             {
 657               inst = read_memory_integer (pc, 2, byte_order);
 658               if (IS_MOV_ARG_TO_IND_R14 (inst))
 659                 {
 660                   reg = GET_SOURCE_REG (inst);
 661                   if (cache->sp_offset > 0)
 662                     cache->saved_regs[reg] = cache->sp_offset;
 663                 }
 664               else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
 665                 {
 666                   reg = GET_SOURCE_REG (inst);
 667                   offset = (inst & 0xf) * 4;
 668                   if (cache->sp_offset > offset)
 669                     cache->saved_regs[reg] = cache->sp_offset - offset;
 670                 }
 671               else if (IS_MOV_ARG_TO_REG (inst))
 672                 continue;
 673               else
 674                 break;
 675             }
 676           break;
 677         }
 678       else if (IS_JSR (inst))
 679         {
 680           /* We have found a jsr that has been scheduled into the prologue.
 681              If we continue the scan and return a pc someplace after this,
 682              then setting a breakpoint on this function will cause it to
 683              appear to be called after the function it is calling via the
 684              jsr, which will be very confusing.  Most likely the next
 685              instruction is going to be IS_MOV_SP_FP in the delay slot.  If
 686              so, note that before returning the current pc. */
 687           inst = read_memory_integer (pc + 2, 2, byte_order);
 688           if (IS_MOV_SP_FP (inst))
 689             cache->uses_fp = 1;
 690           break;
 691         }
 692 #if 0                           /* This used to just stop when it found an instruction that
 693                                    was not considered part of the prologue.  Now, we just
 694                                    keep going looking for likely instructions. */
 695       else
 696         break;
 697 #endif
 698     }
 699
 700   return pc;
 701 }
 702
 703 /* Skip any prologue before the guts of a function */
 704
 705 /* Skip the prologue using the debug information. If this fails we'll
 706    fall back on the 'guess' method below. */
 707 static CORE_ADDR
 708 after_prologue (CORE_ADDR pc)
 709 {
 710   struct symtab_and_line sal;
 711   CORE_ADDR func_addr, func_end;
 712
 713   /* If we can not find the symbol in the partial symbol table, then
 714      there is no hope we can determine the function's start address
 715      with this code.  */
 716   if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
 717     return 0;
 718
 719   /* Get the line associated with FUNC_ADDR.  */
 720   sal = find_pc_line (func_addr, 0);
 721
 722   /* There are only two cases to consider.  First, the end of the source line
 723      is within the function bounds.  In that case we return the end of the
 724      source line.  Second is the end of the source line extends beyond the
 725      bounds of the current function.  We need to use the slow code to
 726      examine instructions in that case.  */
 727   if (sal.end < func_end)
 728     return sal.end;
 729   else
 730     return 0;
 731 }
 732
 733 static CORE_ADDR
 734 sh_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
 735 {
 736   CORE_ADDR pc;
 737   struct sh_frame_cache cache;
 738
 739   /* See if we can determine the end of the prologue via the symbol table.
 740      If so, then return either PC, or the PC after the prologue, whichever
 741      is greater.  */
 742   pc = after_prologue (start_pc);
 743
 744   /* If after_prologue returned a useful address, then use it.  Else
 745      fall back on the instruction skipping code. */
 746   if (pc)
 747     return max (pc, start_pc);
 748
 749   cache.sp_offset = -4;
 750   pc = sh_analyze_prologue (gdbarch, start_pc, (CORE_ADDR) -1, &cache, 0);
 751   if (!cache.uses_fp)
 752     return start_pc;
 753
 754   return pc;
 755 }
 756
 757 /* The ABI says:
 758
 759    Aggregate types not bigger than 8 bytes that have the same size and
 760    alignment as one of the integer scalar types are returned in the
 761    same registers as the integer type they match.
 762
 763    For example, a 2-byte aligned structure with size 2 bytes has the
 764    same size and alignment as a short int, and will be returned in R0.
 765    A 4-byte aligned structure with size 8 bytes has the same size and
 766    alignment as a long long int, and will be returned in R0 and R1.
 767
 768    When an aggregate type is returned in R0 and R1, R0 contains the
 769    first four bytes of the aggregate, and R1 contains the
 770    remainder. If the size of the aggregate type is not a multiple of 4
 771    bytes, the aggregate is tail-padded up to a multiple of 4
 772    bytes. The value of the padding is undefined. For little-endian
 773    targets the padding will appear at the most significant end of the
 774    last element, for big-endian targets the padding appears at the
 775    least significant end of the last element.
 776
 777    All other aggregate types are returned by address. The caller
 778    function passes the address of an area large enough to hold the
 779    aggregate value in R2. The called function stores the result in
 780    this location.
 781
 782    To reiterate, structs smaller than 8 bytes could also be returned
 783    in memory, if they don't pass the "same size and alignment as an
 784    integer type" rule.
 785
 786    For example, in
 787
 788    struct s { char c[3]; } wibble;
 789    struct s foo(void) {  return wibble; }
 790
 791    the return value from foo() will be in memory, not
 792    in R0, because there is no 3-byte integer type.
 793
 794    Similarly, in
 795
 796    struct s { char c[2]; } wibble;
 797    struct s foo(void) {  return wibble; }
 798
 799    because a struct containing two chars has alignment 1, that matches
 800    type char, but size 2, that matches type short.  There's no integer
 801    type that has alignment 1 and size 2, so the struct is returned in
 802    memory.
 803
 804 */
 805
 806 static int
 807 sh_use_struct_convention (int renesas_abi, struct type *type)
 808 {
 809   int len = TYPE_LENGTH (type);
 810   int nelem = TYPE_NFIELDS (type);
 811
 812   /* The Renesas ABI returns aggregate types always on stack.  */
 813   if (renesas_abi && (TYPE_CODE (type) == TYPE_CODE_STRUCT
 814                       || TYPE_CODE (type) == TYPE_CODE_UNION))
 815     return 1;
 816
 817   /* Non-power of 2 length types and types bigger than 8 bytes (which don't
 818      fit in two registers anyway) use struct convention.  */
 819   if (len != 1 && len != 2 && len != 4 && len != 8)
 820     return 1;
 821
 822   /* Scalar types and aggregate types with exactly one field are aligned
 823      by definition.  They are returned in registers.  */
 824   if (nelem <= 1)
 825     return 0;
 826
 827   /* If the first field in the aggregate has the same length as the entire
 828      aggregate type, the type is returned in registers.  */
 829   if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
 830     return 0;
 831
 832   /* If the size of the aggregate is 8 bytes and the first field is
 833      of size 4 bytes its alignment is equal to long long's alignment,
 834      so it's returned in registers.  */
 835   if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
 836     return 0;
 837
 838   /* Otherwise use struct convention.  */
 839   return 1;
 840 }
 841
 842 static int
 843 sh_use_struct_convention_nofpu (int renesas_abi, struct type *type)
 844 {
 845   /* The Renesas ABI returns long longs/doubles etc. always on stack.  */
 846   if (renesas_abi && TYPE_NFIELDS (type) == 0 && TYPE_LENGTH (type) >= 8)
 847     return 1;
 848   return sh_use_struct_convention (renesas_abi, type);
 849 }
 850
 851 static CORE_ADDR
 852 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
 853 {
 854   return sp & ~3;
 855 }
 856
 857 /* Function: push_dummy_call (formerly push_arguments)
 858    Setup the function arguments for calling a function in the inferior.
 859
 860    On the Renesas SH architecture, there are four registers (R4 to R7)
 861    which are dedicated for passing function arguments.  Up to the first
 862    four arguments (depending on size) may go into these registers.
 863    The rest go on the stack.
 864
 865    MVS: Except on SH variants that have floating point registers.
 866    In that case, float and double arguments are passed in the same
 867    manner, but using FP registers instead of GP registers.
 868
 869    Arguments that are smaller than 4 bytes will still take up a whole
 870    register or a whole 32-bit word on the stack, and will be
 871    right-justified in the register or the stack word.  This includes
 872    chars, shorts, and small aggregate types.
 873
 874    Arguments that are larger than 4 bytes may be split between two or
 875    more registers.  If there are not enough registers free, an argument
 876    may be passed partly in a register (or registers), and partly on the
 877    stack.  This includes doubles, long longs, and larger aggregates.
 878    As far as I know, there is no upper limit to the size of aggregates
 879    that will be passed in this way; in other words, the convention of
 880    passing a pointer to a large aggregate instead of a copy is not used.
 881
 882    MVS: The above appears to be true for the SH variants that do not
 883    have an FPU, however those that have an FPU appear to copy the
 884    aggregate argument onto the stack (and not place it in registers)
 885    if it is larger than 16 bytes (four GP registers).
 886
 887    An exceptional case exists for struct arguments (and possibly other
 888    aggregates such as arrays) if the size is larger than 4 bytes but
 889    not a multiple of 4 bytes.  In this case the argument is never split
 890    between the registers and the stack, but instead is copied in its
 891    entirety onto the stack, AND also copied into as many registers as
 892    there is room for.  In other words, space in registers permitting,
 893    two copies of the same argument are passed in.  As far as I can tell,
 894    only the one on the stack is used, although that may be a function
 895    of the level of compiler optimization.  I suspect this is a compiler
 896    bug.  Arguments of these odd sizes are left-justified within the
 897    word (as opposed to arguments smaller than 4 bytes, which are
 898    right-justified).
 899
 900    If the function is to return an aggregate type such as a struct, it
 901    is either returned in the normal return value register R0 (if its
 902    size is no greater than one byte), or else the caller must allocate
 903    space into which the callee will copy the return value (if the size
 904    is greater than one byte).  In this case, a pointer to the return
 905    value location is passed into the callee in register R2, which does
 906    not displace any of the other arguments passed in via registers R4
 907    to R7.   */
 908
 909 /* Helper function to justify value in register according to endianess. */
 910 static char *
 911 sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len)
 912 {
 913   static char valbuf[4];
 914
 915   memset (valbuf, 0, sizeof (valbuf));
 916   if (len < 4)
 917     {
 918       /* value gets right-justified in the register or stack word */
 919       if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
 920         memcpy (valbuf + (4 - len), (char *) value_contents (val), len);
 921       else
 922         memcpy (valbuf, (char *) value_contents (val), len);
 923       return valbuf;
 924     }
 925   return (char *) value_contents (val);
 926 }
 927
 928 /* Helper function to eval number of bytes to allocate on stack. */
 929 static CORE_ADDR
 930 sh_stack_allocsize (int nargs, struct value **args)
 931 {
 932   int stack_alloc = 0;
 933   while (nargs-- > 0)
 934     stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3);
 935   return stack_alloc;
 936 }
 937
 938 /* Helper functions for getting the float arguments right.  Registers usage
 939    depends on the ABI and the endianess.  The comments should enlighten how
 940    it's intended to work. */
 941
 942 /* This array stores which of the float arg registers are already in use. */
 943 static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
 944
 945 /* This function just resets the above array to "no reg used so far". */
 946 static void
 947 sh_init_flt_argreg (void)
 948 {
 949   memset (flt_argreg_array, 0, sizeof flt_argreg_array);
 950 }
 951
 952 /* This function returns the next register to use for float arg passing.
 953    It returns either a valid value between FLOAT_ARG0_REGNUM and
 954    FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
 955    FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
 956
 957    Note that register number 0 in flt_argreg_array corresponds with the
 958    real float register fr4.  In contrast to FLOAT_ARG0_REGNUM (value is
 959    29) the parity of the register number is preserved, which is important
 960    for the double register passing test (see the "argreg & 1" test below). */
 961 static int
 962 sh_next_flt_argreg (struct gdbarch *gdbarch, int len, struct type *func_type)
 963 {
 964   int argreg;
 965
 966   /* First search for the next free register. */
 967   for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
 968        ++argreg)
 969     if (!flt_argreg_array[argreg])
 970       break;
 971
 972   /* No register left? */
 973   if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
 974     return FLOAT_ARGLAST_REGNUM + 1;
 975
 976   if (len == 8)
 977     {
 978       /* Doubles are always starting in a even register number. */
 979       if (argreg & 1)
 980         {
 981           /* In gcc ABI, the skipped register is lost for further argument
 982              passing now.  Not so in Renesas ABI.  */
 983           if (!sh_is_renesas_calling_convention (func_type))
 984             flt_argreg_array[argreg] = 1;
 985
 986           ++argreg;
 987
 988           /* No register left? */
 989           if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
 990             return FLOAT_ARGLAST_REGNUM + 1;
 991         }
 992       /* Also mark the next register as used. */
 993       flt_argreg_array[argreg + 1] = 1;
 994     }
 995   else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
 996            && !sh_is_renesas_calling_convention (func_type))
 997     {
 998       /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
 999       if (!flt_argreg_array[argreg + 1])
1000         ++argreg;
1001     }
1002   flt_argreg_array[argreg] = 1;
1003   return FLOAT_ARG0_REGNUM + argreg;
1004 }
1005
1006 /* Helper function which figures out, if a type is treated like a float type.
1007
1008    The FPU ABIs have a special way how to treat types as float types.
1009    Structures with exactly one member, which is of type float or double, are
1010    treated exactly as the base types float or double:
1011
1012      struct sf {
1013        float f;
1014      };
1015
1016      struct sd {
1017        double d;
1018      };
1019
1020    are handled the same way as just
1021
1022      float f;
1023
1024      double d;
1025
1026    As a result, arguments of these struct types are pushed into floating point
1027    registers exactly as floats or doubles, using the same decision algorithm.
1028
1029    The same is valid if these types are used as function return types.  The
1030    above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
1031    or even using struct convention as it is for other structs.  */
1032
1033 static int
1034 sh_treat_as_flt_p (struct type *type)
1035 {
1036   int len = TYPE_LENGTH (type);
1037
1038   /* Ordinary float types are obviously treated as float.  */
1039   if (TYPE_CODE (type) == TYPE_CODE_FLT)
1040     return 1;
1041   /* Otherwise non-struct types are not treated as float.  */
1042   if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
1043     return 0;
1044   /* Otherwise structs with more than one memeber are not treated as float.  */
1045   if (TYPE_NFIELDS (type) != 1)
1046     return 0;
1047   /* Otherwise if the type of that member is float, the whole type is
1048      treated as float.  */
1049   if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
1050     return 1;
1051   /* Otherwise it's not treated as float.  */
1052   return 0;
1053 }
1054
1055 static CORE_ADDR
1056 sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
1057                         struct value *function,
1058                         struct regcache *regcache,
1059                         CORE_ADDR bp_addr, int nargs,
1060                         struct value **args,
1061                         CORE_ADDR sp, int struct_return,
1062                         CORE_ADDR struct_addr)
1063 {
1064   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1065   int stack_offset = 0;
1066   int argreg = ARG0_REGNUM;
1067   int flt_argreg = 0;
1068   int argnum;
1069   struct type *func_type = value_type (function);
1070   struct type *type;
1071   CORE_ADDR regval;
1072   char *val;
1073   int len, reg_size = 0;
1074   int pass_on_stack = 0;
1075   int treat_as_flt;
1076   int last_reg_arg = INT_MAX;
1077
1078   /* The Renesas ABI expects all varargs arguments, plus the last
1079      non-vararg argument to be on the stack, no matter how many
1080      registers have been used so far.  */
1081   if (sh_is_renesas_calling_convention (func_type)
1082       && TYPE_VARARGS (func_type))
1083     last_reg_arg = TYPE_NFIELDS (func_type) - 2;
1084
1085   /* first force sp to a 4-byte alignment */
1086   sp = sh_frame_align (gdbarch, sp);
1087
1088   /* make room on stack for args */
1089   sp -= sh_stack_allocsize (nargs, args);
1090
1091   /* Initialize float argument mechanism. */
1092   sh_init_flt_argreg ();
1093
1094   /* Now load as many as possible of the first arguments into
1095      registers, and push the rest onto the stack.  There are 16 bytes
1096      in four registers available.  Loop thru args from first to last.  */
1097   for (argnum = 0; argnum < nargs; argnum++)
1098     {
1099       type = value_type (args[argnum]);
1100       len = TYPE_LENGTH (type);
1101       val = sh_justify_value_in_reg (gdbarch, args[argnum], len);
1102
1103       /* Some decisions have to be made how various types are handled.
1104          This also differs in different ABIs. */
1105       pass_on_stack = 0;
1106
1107       /* Find out the next register to use for a floating point value. */
1108       treat_as_flt = sh_treat_as_flt_p (type);
1109       if (treat_as_flt)
1110         flt_argreg = sh_next_flt_argreg (gdbarch, len, func_type);
1111       /* In Renesas ABI, long longs and aggregate types are always passed
1112          on stack.  */
1113       else if (sh_is_renesas_calling_convention (func_type)
1114                && ((TYPE_CODE (type) == TYPE_CODE_INT && len == 8)
1115                    || TYPE_CODE (type) == TYPE_CODE_STRUCT
1116                    || TYPE_CODE (type) == TYPE_CODE_UNION))
1117         pass_on_stack = 1;
1118       /* In contrast to non-FPU CPUs, arguments are never split between
1119          registers and stack.  If an argument doesn't fit in the remaining
1120          registers it's always pushed entirely on the stack.  */
1121       else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
1122         pass_on_stack = 1;
1123
1124       while (len > 0)
1125         {
1126           if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
1127               || (!treat_as_flt && (argreg > ARGLAST_REGNUM
1128                                     || pass_on_stack))
1129               || argnum > last_reg_arg)
1130             {
1131               /* The data goes entirely on the stack, 4-byte aligned. */
1132               reg_size = (len + 3) & ~3;
1133               write_memory (sp + stack_offset, val, reg_size);
1134               stack_offset += reg_size;
1135             }
1136           else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
1137             {
1138               /* Argument goes in a float argument register.  */
1139               reg_size = register_size (gdbarch, flt_argreg);
1140               regval = extract_unsigned_integer (val, reg_size, byte_order);
1141               /* In little endian mode, float types taking two registers
1142                  (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1143                  be stored swapped in the argument registers.  The below
1144                  code first writes the first 32 bits in the next but one
1145                  register, increments the val and len values accordingly
1146                  and then proceeds as normal by writing the second 32 bits
1147                  into the next register. */
1148               if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
1149                   && TYPE_LENGTH (type) == 2 * reg_size)
1150                 {
1151                   regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
1152                                                   regval);
1153                   val += reg_size;
1154                   len -= reg_size;
1155                   regval = extract_unsigned_integer (val, reg_size, byte_order);
1156                 }
1157               regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
1158             }
1159           else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
1160             {
1161               /* there's room in a register */
1162               reg_size = register_size (gdbarch, argreg);
1163               regval = extract_unsigned_integer (val, reg_size, byte_order);
1164               regcache_cooked_write_unsigned (regcache, argreg++, regval);
1165             }
1166           /* Store the value one register at a time or in one step on stack.  */
1167           len -= reg_size;
1168           val += reg_size;
1169         }
1170     }
1171
1172   if (struct_return)
1173     {
1174       if (sh_is_renesas_calling_convention (func_type))
1175         /* If the function uses the Renesas ABI, subtract another 4 bytes from
1176            the stack and store the struct return address there.  */
1177         write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
1178       else
1179         /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1180            its own dedicated register.  */
1181         regcache_cooked_write_unsigned (regcache,
1182                                         STRUCT_RETURN_REGNUM, struct_addr);
1183     }
1184
1185   /* Store return address. */
1186   regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1187
1188   /* Update stack pointer.  */
1189   regcache_cooked_write_unsigned (regcache,
1190                                   gdbarch_sp_regnum (gdbarch), sp);
1191
1192   return sp;
1193 }
1194
1195 static CORE_ADDR
1196 sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
1197                           struct value *function,
1198                           struct regcache *regcache,
1199                           CORE_ADDR bp_addr,
1200                           int nargs, struct value **args,
1201                           CORE_ADDR sp, int struct_return,
1202                           CORE_ADDR struct_addr)
1203 {
1204   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1205   int stack_offset = 0;
1206   int argreg = ARG0_REGNUM;
1207   int argnum;
1208   struct type *func_type = value_type (function);
1209   struct type *type;
1210   CORE_ADDR regval;
1211   char *val;
1212   int len, reg_size = 0;
1213   int pass_on_stack = 0;
1214   int last_reg_arg = INT_MAX;
1215
1216   /* The Renesas ABI expects all varargs arguments, plus the last
1217      non-vararg argument to be on the stack, no matter how many
1218      registers have been used so far.  */
1219   if (sh_is_renesas_calling_convention (func_type)
1220       && TYPE_VARARGS (func_type))
1221     last_reg_arg = TYPE_NFIELDS (func_type) - 2;
1222
1223   /* first force sp to a 4-byte alignment */
1224   sp = sh_frame_align (gdbarch, sp);
1225
1226   /* make room on stack for args */
1227   sp -= sh_stack_allocsize (nargs, args);
1228
1229   /* Now load as many as possible of the first arguments into
1230      registers, and push the rest onto the stack.  There are 16 bytes
1231      in four registers available.  Loop thru args from first to last.  */
1232   for (argnum = 0; argnum < nargs; argnum++)
1233     {
1234       type = value_type (args[argnum]);
1235       len = TYPE_LENGTH (type);
1236       val = sh_justify_value_in_reg (gdbarch, args[argnum], len);
1237
1238       /* Some decisions have to be made how various types are handled.
1239          This also differs in different ABIs. */
1240       pass_on_stack = 0;
1241       /* Renesas ABI pushes doubles and long longs entirely on stack.
1242          Same goes for aggregate types.  */
1243       if (sh_is_renesas_calling_convention (func_type)
1244           && ((TYPE_CODE (type) == TYPE_CODE_INT && len >= 8)
1245               || (TYPE_CODE (type) == TYPE_CODE_FLT && len >= 8)
1246               || TYPE_CODE (type) == TYPE_CODE_STRUCT
1247               || TYPE_CODE (type) == TYPE_CODE_UNION))
1248         pass_on_stack = 1;
1249       while (len > 0)
1250         {
1251           if (argreg > ARGLAST_REGNUM || pass_on_stack
1252               || argnum > last_reg_arg)
1253             {
1254               /* The remainder of the data goes entirely on the stack,
1255                  4-byte aligned. */
1256               reg_size = (len + 3) & ~3;
1257               write_memory (sp + stack_offset, val, reg_size);
1258               stack_offset += reg_size;
1259             }
1260           else if (argreg <= ARGLAST_REGNUM)
1261             {
1262               /* there's room in a register */
1263               reg_size = register_size (gdbarch, argreg);
1264               regval = extract_unsigned_integer (val, reg_size, byte_order);
1265               regcache_cooked_write_unsigned (regcache, argreg++, regval);
1266             }
1267           /* Store the value reg_size bytes at a time.  This means that things
1268              larger than reg_size bytes may go partly in registers and partly
1269              on the stack.  */
1270           len -= reg_size;
1271           val += reg_size;
1272         }
1273     }
1274
1275   if (struct_return)
1276     {
1277       if (sh_is_renesas_calling_convention (func_type))
1278         /* If the function uses the Renesas ABI, subtract another 4 bytes from
1279            the stack and store the struct return address there.  */
1280         write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
1281       else
1282         /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1283            its own dedicated register.  */
1284         regcache_cooked_write_unsigned (regcache,
1285                                         STRUCT_RETURN_REGNUM, struct_addr);
1286     }
1287
1288   /* Store return address. */
1289   regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1290
1291   /* Update stack pointer.  */
1292   regcache_cooked_write_unsigned (regcache,
1293                                   gdbarch_sp_regnum (gdbarch), sp);
1294
1295   return sp;
1296 }
1297
1298 /* Find a function's return value in the appropriate registers (in
1299    regbuf), and copy it into valbuf.  Extract from an array REGBUF
1300    containing the (raw) register state a function return value of type
1301    TYPE, and copy that, in virtual format, into VALBUF.  */
1302 static void
1303 sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache,
1304                                void *valbuf)
1305 {
1306   struct gdbarch *gdbarch = get_regcache_arch (regcache);
1307   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1308   int len = TYPE_LENGTH (type);
1309   int return_register = R0_REGNUM;
1310   int offset;
1311
1312   if (len <= 4)
1313     {
1314       ULONGEST c;
1315
1316       regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
1317       store_unsigned_integer (valbuf, len, byte_order, c);
1318     }
1319   else if (len == 8)
1320     {
1321       int i, regnum = R0_REGNUM;
1322       for (i = 0; i < len; i += 4)
1323         regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1324     }
1325   else
1326     error (_("bad size for return value"));
1327 }
1328
1329 static void
1330 sh_extract_return_value_fpu (struct type *type, struct regcache *regcache,
1331                              void *valbuf)
1332 {
1333   struct gdbarch *gdbarch = get_regcache_arch (regcache);
1334   if (sh_treat_as_flt_p (type))
1335     {
1336       int len = TYPE_LENGTH (type);
1337       int i, regnum = gdbarch_fp0_regnum (gdbarch);
1338       for (i = 0; i < len; i += 4)
1339         if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1340           regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i);
1341         else
1342           regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1343     }
1344   else
1345     sh_extract_return_value_nofpu (type, regcache, valbuf);
1346 }
1347
1348 /* Write into appropriate registers a function return value
1349    of type TYPE, given in virtual format.
1350    If the architecture is sh4 or sh3e, store a function's return value
1351    in the R0 general register or in the FP0 floating point register,
1352    depending on the type of the return value. In all the other cases
1353    the result is stored in r0, left-justified. */
1354 static void
1355 sh_store_return_value_nofpu (struct type *type, struct regcache *regcache,
1356                              const void *valbuf)
1357 {
1358   struct gdbarch *gdbarch = get_regcache_arch (regcache);
1359   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1360   ULONGEST val;
1361   int len = TYPE_LENGTH (type);
1362
1363   if (len <= 4)
1364     {
1365       val = extract_unsigned_integer (valbuf, len, byte_order);
1366       regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
1367     }
1368   else
1369     {
1370       int i, regnum = R0_REGNUM;
1371       for (i = 0; i < len; i += 4)
1372         regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1373     }
1374 }
1375
1376 static void
1377 sh_store_return_value_fpu (struct type *type, struct regcache *regcache,
1378                            const void *valbuf)
1379 {
1380   struct gdbarch *gdbarch = get_regcache_arch (regcache);
1381   if (sh_treat_as_flt_p (type))
1382     {
1383       int len = TYPE_LENGTH (type);
1384       int i, regnum = gdbarch_fp0_regnum (gdbarch);
1385       for (i = 0; i < len; i += 4)
1386         if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1387           regcache_raw_write (regcache, regnum++,
1388                               (char *) valbuf + len - 4 - i);
1389         else
1390           regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1391     }
1392   else
1393     sh_store_return_value_nofpu (type, regcache, valbuf);
1394 }
1395
1396 static enum return_value_convention
1397 sh_return_value_nofpu (struct gdbarch *gdbarch, struct type *func_type,
1398                        struct type *type, struct regcache *regcache,
1399                        gdb_byte *readbuf, const gdb_byte *writebuf)
1400 {
1401   if (sh_use_struct_convention_nofpu (
1402         sh_is_renesas_calling_convention (func_type), type))
1403     return RETURN_VALUE_STRUCT_CONVENTION;
1404   if (writebuf)
1405     sh_store_return_value_nofpu (type, regcache, writebuf);
1406   else if (readbuf)
1407     sh_extract_return_value_nofpu (type, regcache, readbuf);
1408   return RETURN_VALUE_REGISTER_CONVENTION;
1409 }
1410
1411 static enum return_value_convention
1412 sh_return_value_fpu (struct gdbarch *gdbarch, struct type *func_type,
1413                      struct type *type, struct regcache *regcache,
1414                      gdb_byte *readbuf, const gdb_byte *writebuf)
1415 {
1416   if (sh_use_struct_convention (
1417         sh_is_renesas_calling_convention (func_type), type))
1418     return RETURN_VALUE_STRUCT_CONVENTION;
1419   if (writebuf)
1420     sh_store_return_value_fpu (type, regcache, writebuf);
1421   else if (readbuf)
1422     sh_extract_return_value_fpu (type, regcache, readbuf);
1423   return RETURN_VALUE_REGISTER_CONVENTION;
1424 }
1425
1426 /* Print the registers in a form similar to the E7000 */
1427
1428 static void
1429 sh_generic_show_regs (struct frame_info *frame)
1430 {
1431   printf_filtered
1432     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1433      phex (get_frame_register_unsigned (frame,
1434                                         gdbarch_pc_regnum
1435                                            (get_frame_arch (frame))), 4),
1436      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1437      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1438      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1439
1440   printf_filtered
1441     ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1442      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1443      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1444      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1445
1446   printf_filtered
1447     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1448      (long) get_frame_register_unsigned (frame, 0),
1449      (long) get_frame_register_unsigned (frame, 1),
1450      (long) get_frame_register_unsigned (frame, 2),
1451      (long) get_frame_register_unsigned (frame, 3),
1452      (long) get_frame_register_unsigned (frame, 4),
1453      (long) get_frame_register_unsigned (frame, 5),
1454      (long) get_frame_register_unsigned (frame, 6),
1455      (long) get_frame_register_unsigned (frame, 7));
1456   printf_filtered
1457     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1458      (long) get_frame_register_unsigned (frame, 8),
1459      (long) get_frame_register_unsigned (frame, 9),
1460      (long) get_frame_register_unsigned (frame, 10),
1461      (long) get_frame_register_unsigned (frame, 11),
1462      (long) get_frame_register_unsigned (frame, 12),
1463      (long) get_frame_register_unsigned (frame, 13),
1464      (long) get_frame_register_unsigned (frame, 14),
1465      (long) get_frame_register_unsigned (frame, 15));
1466 }
1467
1468 static void
1469 sh3_show_regs (struct frame_info *frame)
1470 {
1471   printf_filtered
1472     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1473      phex (get_frame_register_unsigned (frame,
1474                                         gdbarch_pc_regnum
1475                                           (get_frame_arch (frame))), 4),
1476      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1477      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1478      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1479
1480   printf_filtered
1481     ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1482      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1483      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1484      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1485   printf_filtered
1486     ("     SSR %08lx      SPC %08lx\n",
1487      (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1488      (long) get_frame_register_unsigned (frame, SPC_REGNUM));
1489
1490   printf_filtered
1491     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1492      (long) get_frame_register_unsigned (frame, 0),
1493      (long) get_frame_register_unsigned (frame, 1),
1494      (long) get_frame_register_unsigned (frame, 2),
1495      (long) get_frame_register_unsigned (frame, 3),
1496      (long) get_frame_register_unsigned (frame, 4),
1497      (long) get_frame_register_unsigned (frame, 5),
1498      (long) get_frame_register_unsigned (frame, 6),
1499      (long) get_frame_register_unsigned (frame, 7));
1500   printf_filtered
1501     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1502      (long) get_frame_register_unsigned (frame, 8),
1503      (long) get_frame_register_unsigned (frame, 9),
1504      (long) get_frame_register_unsigned (frame, 10),
1505      (long) get_frame_register_unsigned (frame, 11),
1506      (long) get_frame_register_unsigned (frame, 12),
1507      (long) get_frame_register_unsigned (frame, 13),
1508      (long) get_frame_register_unsigned (frame, 14),
1509      (long) get_frame_register_unsigned (frame, 15));
1510 }
1511
1512 static void
1513 sh2e_show_regs (struct frame_info *frame)
1514 {
1515   struct gdbarch *gdbarch = get_frame_arch (frame);
1516   printf_filtered
1517     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1518      phex (get_frame_register_unsigned (frame,
1519                                         gdbarch_pc_regnum (gdbarch)), 4),
1520      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1521      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1522      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1523
1524   printf_filtered
1525     ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1526      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1527      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1528      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1529   printf_filtered
1530     ("     SSR %08lx      SPC %08lx     FPUL %08lx    FPSCR %08lx\n",
1531      (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1532      (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1533      (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1534      (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1535
1536   printf_filtered
1537     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1538      (long) get_frame_register_unsigned (frame, 0),
1539      (long) get_frame_register_unsigned (frame, 1),
1540      (long) get_frame_register_unsigned (frame, 2),
1541      (long) get_frame_register_unsigned (frame, 3),
1542      (long) get_frame_register_unsigned (frame, 4),
1543      (long) get_frame_register_unsigned (frame, 5),
1544      (long) get_frame_register_unsigned (frame, 6),
1545      (long) get_frame_register_unsigned (frame, 7));
1546   printf_filtered
1547     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1548      (long) get_frame_register_unsigned (frame, 8),
1549      (long) get_frame_register_unsigned (frame, 9),
1550      (long) get_frame_register_unsigned (frame, 10),
1551      (long) get_frame_register_unsigned (frame, 11),
1552      (long) get_frame_register_unsigned (frame, 12),
1553      (long) get_frame_register_unsigned (frame, 13),
1554      (long) get_frame_register_unsigned (frame, 14),
1555      (long) get_frame_register_unsigned (frame, 15));
1556
1557   printf_filtered
1558     ("FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1559      (long) get_frame_register_unsigned
1560               (frame, gdbarch_fp0_regnum (gdbarch) + 0),
1561      (long) get_frame_register_unsigned
1562               (frame, gdbarch_fp0_regnum (gdbarch) + 1),
1563      (long) get_frame_register_unsigned
1564               (frame, gdbarch_fp0_regnum (gdbarch) + 2),
1565      (long) get_frame_register_unsigned
1566               (frame, gdbarch_fp0_regnum (gdbarch) + 3),
1567      (long) get_frame_register_unsigned
1568               (frame, gdbarch_fp0_regnum (gdbarch) + 4),
1569      (long) get_frame_register_unsigned
1570               (frame, gdbarch_fp0_regnum (gdbarch) + 5),
1571      (long) get_frame_register_unsigned
1572               (frame, gdbarch_fp0_regnum (gdbarch) + 6),
1573      (long) get_frame_register_unsigned
1574               (frame, gdbarch_fp0_regnum (gdbarch) + 7));
1575   printf_filtered
1576     ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1577      (long) get_frame_register_unsigned
1578               (frame, gdbarch_fp0_regnum (gdbarch) + 8),
1579      (long) get_frame_register_unsigned
1580               (frame, gdbarch_fp0_regnum (gdbarch) + 9),
1581      (long) get_frame_register_unsigned
1582               (frame, gdbarch_fp0_regnum (gdbarch) + 10),
1583      (long) get_frame_register_unsigned
1584               (frame, gdbarch_fp0_regnum (gdbarch) + 11),
1585      (long) get_frame_register_unsigned
1586               (frame, gdbarch_fp0_regnum (gdbarch) + 12),
1587      (long) get_frame_register_unsigned
1588               (frame, gdbarch_fp0_regnum (gdbarch) + 13),
1589      (long) get_frame_register_unsigned
1590               (frame, gdbarch_fp0_regnum (gdbarch) + 14),
1591      (long) get_frame_register_unsigned
1592               (frame, gdbarch_fp0_regnum (gdbarch) + 15));
1593 }
1594
1595 static void
1596 sh2a_show_regs (struct frame_info *frame)
1597 {
1598   struct gdbarch *gdbarch = get_frame_arch (frame);
1599   int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1600
1601   printf_filtered
1602     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1603      phex (get_frame_register_unsigned (frame,
1604                                         gdbarch_pc_regnum (gdbarch)), 4),
1605      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1606      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1607      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1608
1609   printf_filtered
1610     ("     GBR %08lx      VBR %08lx      TBR %08lx     MACL %08lx\n",
1611      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1612      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1613      (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1614      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1615   printf_filtered
1616     ("     SSR %08lx      SPC %08lx     FPUL %08lx    FPSCR %08lx\n",
1617      (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1618      (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1619      (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1620      (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1621
1622   printf_filtered
1623     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1624      (long) get_frame_register_unsigned (frame, 0),
1625      (long) get_frame_register_unsigned (frame, 1),
1626      (long) get_frame_register_unsigned (frame, 2),
1627      (long) get_frame_register_unsigned (frame, 3),
1628      (long) get_frame_register_unsigned (frame, 4),
1629      (long) get_frame_register_unsigned (frame, 5),
1630      (long) get_frame_register_unsigned (frame, 6),
1631      (long) get_frame_register_unsigned (frame, 7));
1632   printf_filtered
1633     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1634      (long) get_frame_register_unsigned (frame, 8),
1635      (long) get_frame_register_unsigned (frame, 9),
1636      (long) get_frame_register_unsigned (frame, 10),
1637      (long) get_frame_register_unsigned (frame, 11),
1638      (long) get_frame_register_unsigned (frame, 12),
1639      (long) get_frame_register_unsigned (frame, 13),
1640      (long) get_frame_register_unsigned (frame, 14),
1641      (long) get_frame_register_unsigned (frame, 15));
1642
1643   printf_filtered
1644     (pr ? "DR0-DR6  %08lx%08lx  %08lx%08lx  %08lx%08lx  %08lx%08lx\n"
1645         : "FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1646      (long) get_frame_register_unsigned
1647               (frame, gdbarch_fp0_regnum (gdbarch) + 0),
1648      (long) get_frame_register_unsigned
1649               (frame, gdbarch_fp0_regnum (gdbarch) + 1),
1650      (long) get_frame_register_unsigned
1651               (frame, gdbarch_fp0_regnum (gdbarch) + 2),
1652      (long) get_frame_register_unsigned
1653               (frame, gdbarch_fp0_regnum (gdbarch) + 3),
1654      (long) get_frame_register_unsigned
1655               (frame, gdbarch_fp0_regnum (gdbarch) + 4),
1656      (long) get_frame_register_unsigned
1657               (frame, gdbarch_fp0_regnum (gdbarch) + 5),
1658      (long) get_frame_register_unsigned
1659               (frame, gdbarch_fp0_regnum (gdbarch) + 6),
1660      (long) get_frame_register_unsigned
1661               (frame, gdbarch_fp0_regnum (gdbarch) + 7));
1662   printf_filtered
1663     (pr ? "DR8-DR14 %08lx%08lx  %08lx%08lx  %08lx%08lx  %08lx%08lx\n"
1664         : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1665      (long) get_frame_register_unsigned
1666               (frame, gdbarch_fp0_regnum (gdbarch) + 8),
1667      (long) get_frame_register_unsigned
1668               (frame, gdbarch_fp0_regnum (gdbarch) + 9),
1669      (long) get_frame_register_unsigned
1670               (frame, gdbarch_fp0_regnum (gdbarch) + 10),
1671      (long) get_frame_register_unsigned
1672               (frame, gdbarch_fp0_regnum (gdbarch) + 11),
1673      (long) get_frame_register_unsigned
1674               (frame, gdbarch_fp0_regnum (gdbarch) + 12),
1675      (long) get_frame_register_unsigned
1676               (frame, gdbarch_fp0_regnum (gdbarch) + 13),
1677      (long) get_frame_register_unsigned
1678               (frame, gdbarch_fp0_regnum (gdbarch) + 14),
1679      (long) get_frame_register_unsigned
1680               (frame, gdbarch_fp0_regnum (gdbarch) + 15));
1681   printf_filtered
1682     ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1683   printf_filtered
1684     ("R0b-R7b  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1685      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1686      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1687      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1688      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1689      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1690      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1691      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1692      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1693   printf_filtered
1694     ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1695      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1696      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1697      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1698      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1699      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1700      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1701      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1702   printf_filtered
1703     ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1704      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1705      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1706      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1707      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1708      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
1709 }
1710
1711 static void
1712 sh2a_nofpu_show_regs (struct frame_info *frame)
1713 {
1714   int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1715
1716   printf_filtered
1717     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1718      phex (get_frame_register_unsigned (frame,
1719                                         gdbarch_pc_regnum
1720                                           (get_frame_arch (frame))), 4),
1721      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1722      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1723      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1724
1725   printf_filtered
1726     ("     GBR %08lx      VBR %08lx      TBR %08lx     MACL %08lx\n",
1727      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1728      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1729      (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1730      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1731   printf_filtered
1732     ("     SSR %08lx      SPC %08lx     FPUL %08lx    FPSCR %08lx\n",
1733      (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1734      (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1735      (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1736      (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1737
1738   printf_filtered
1739     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1740      (long) get_frame_register_unsigned (frame, 0),
1741      (long) get_frame_register_unsigned (frame, 1),
1742      (long) get_frame_register_unsigned (frame, 2),
1743      (long) get_frame_register_unsigned (frame, 3),
1744      (long) get_frame_register_unsigned (frame, 4),
1745      (long) get_frame_register_unsigned (frame, 5),
1746      (long) get_frame_register_unsigned (frame, 6),
1747      (long) get_frame_register_unsigned (frame, 7));
1748   printf_filtered
1749     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1750      (long) get_frame_register_unsigned (frame, 8),
1751      (long) get_frame_register_unsigned (frame, 9),
1752      (long) get_frame_register_unsigned (frame, 10),
1753      (long) get_frame_register_unsigned (frame, 11),
1754      (long) get_frame_register_unsigned (frame, 12),
1755      (long) get_frame_register_unsigned (frame, 13),
1756      (long) get_frame_register_unsigned (frame, 14),
1757      (long) get_frame_register_unsigned (frame, 15));
1758
1759   printf_filtered
1760     ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1761   printf_filtered
1762     ("R0b-R7b  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1763      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1764      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1765      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1766      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1767      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1768      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1769      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1770      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1771   printf_filtered
1772     ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1773      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1774      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1775      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1776      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1777      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1778      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1779      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1780   printf_filtered
1781     ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1782      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1783      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1784      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1785      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1786      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
1787 }
1788
1789 static void
1790 sh3e_show_regs (struct frame_info *frame)
1791 {
1792   struct gdbarch *gdbarch = get_frame_arch (frame);
1793   printf_filtered
1794     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1795      phex (get_frame_register_unsigned (frame,
1796                                         gdbarch_pc_regnum (gdbarch)), 4),
1797      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1798      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1799      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1800
1801   printf_filtered
1802     ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1803      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1804      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1805      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1806   printf_filtered
1807     ("     SSR %08lx      SPC %08lx     FPUL %08lx    FPSCR %08lx\n",
1808      (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1809      (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1810      (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1811      (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1812
1813   printf_filtered
1814     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1815      (long) get_frame_register_unsigned (frame, 0),
1816      (long) get_frame_register_unsigned (frame, 1),
1817      (long) get_frame_register_unsigned (frame, 2),
1818      (long) get_frame_register_unsigned (frame, 3),
1819      (long) get_frame_register_unsigned (frame, 4),
1820      (long) get_frame_register_unsigned (frame, 5),
1821      (long) get_frame_register_unsigned (frame, 6),
1822      (long) get_frame_register_unsigned (frame, 7));
1823   printf_filtered
1824     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1825      (long) get_frame_register_unsigned (frame, 8),
1826      (long) get_frame_register_unsigned (frame, 9),
1827      (long) get_frame_register_unsigned (frame, 10),
1828      (long) get_frame_register_unsigned (frame, 11),
1829      (long) get_frame_register_unsigned (frame, 12),
1830      (long) get_frame_register_unsigned (frame, 13),
1831      (long) get_frame_register_unsigned (frame, 14),
1832      (long) get_frame_register_unsigned (frame, 15));
1833
1834   printf_filtered
1835     ("FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1836      (long) get_frame_register_unsigned
1837               (frame, gdbarch_fp0_regnum (gdbarch) + 0),
1838      (long) get_frame_register_unsigned
1839               (frame, gdbarch_fp0_regnum (gdbarch) + 1),
1840      (long) get_frame_register_unsigned
1841               (frame, gdbarch_fp0_regnum (gdbarch) + 2),
1842      (long) get_frame_register_unsigned
1843               (frame, gdbarch_fp0_regnum (gdbarch) + 3),
1844      (long) get_frame_register_unsigned
1845               (frame, gdbarch_fp0_regnum (gdbarch) + 4),
1846      (long) get_frame_register_unsigned
1847               (frame, gdbarch_fp0_regnum (gdbarch) + 5),
1848      (long) get_frame_register_unsigned
1849               (frame, gdbarch_fp0_regnum (gdbarch) + 6),
1850      (long) get_frame_register_unsigned
1851               (frame, gdbarch_fp0_regnum (gdbarch) + 7));
1852   printf_filtered
1853     ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1854      (long) get_frame_register_unsigned
1855               (frame, gdbarch_fp0_regnum (gdbarch) + 8),
1856      (long) get_frame_register_unsigned
1857               (frame, gdbarch_fp0_regnum (gdbarch) + 9),
1858      (long) get_frame_register_unsigned
1859               (frame, gdbarch_fp0_regnum (gdbarch) + 10),
1860      (long) get_frame_register_unsigned
1861               (frame, gdbarch_fp0_regnum (gdbarch) + 11),
1862      (long) get_frame_register_unsigned
1863               (frame, gdbarch_fp0_regnum (gdbarch) + 12),
1864      (long) get_frame_register_unsigned
1865               (frame, gdbarch_fp0_regnum (gdbarch) + 13),
1866      (long) get_frame_register_unsigned
1867               (frame, gdbarch_fp0_regnum (gdbarch) + 14),
1868      (long) get_frame_register_unsigned
1869               (frame, gdbarch_fp0_regnum (gdbarch) + 15));
1870 }
1871
1872 static void
1873 sh3_dsp_show_regs (struct frame_info *frame)
1874 {
1875   printf_filtered
1876     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1877      phex (get_frame_register_unsigned (frame,
1878                                         gdbarch_pc_regnum
1879                                           (get_frame_arch (frame))), 4),
1880      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1881      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1882      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1883
1884   printf_filtered
1885     ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1886      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1887      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1888      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1889
1890   printf_filtered
1891     ("     SSR %08lx      SPC %08lx      DSR %08lx\n",
1892      (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1893      (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1894      (long) get_frame_register_unsigned (frame, DSR_REGNUM));
1895
1896   printf_filtered
1897     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1898      (long) get_frame_register_unsigned (frame, 0),
1899      (long) get_frame_register_unsigned (frame, 1),
1900      (long) get_frame_register_unsigned (frame, 2),
1901      (long) get_frame_register_unsigned (frame, 3),
1902      (long) get_frame_register_unsigned (frame, 4),
1903      (long) get_frame_register_unsigned (frame, 5),
1904      (long) get_frame_register_unsigned (frame, 6),
1905      (long) get_frame_register_unsigned (frame, 7));
1906   printf_filtered
1907     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1908      (long) get_frame_register_unsigned (frame, 8),
1909      (long) get_frame_register_unsigned (frame, 9),
1910      (long) get_frame_register_unsigned (frame, 10),
1911      (long) get_frame_register_unsigned (frame, 11),
1912      (long) get_frame_register_unsigned (frame, 12),
1913      (long) get_frame_register_unsigned (frame, 13),
1914      (long) get_frame_register_unsigned (frame, 14),
1915      (long) get_frame_register_unsigned (frame, 15));
1916
1917   printf_filtered
1918     ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1919      (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
1920      (long) get_frame_register_unsigned (frame, A0_REGNUM),
1921      (long) get_frame_register_unsigned (frame, M0_REGNUM),
1922      (long) get_frame_register_unsigned (frame, X0_REGNUM),
1923      (long) get_frame_register_unsigned (frame, Y0_REGNUM),
1924      (long) get_frame_register_unsigned (frame, RS_REGNUM),
1925      (long) get_frame_register_unsigned (frame, MOD_REGNUM));
1926   printf_filtered
1927     ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1928      (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
1929      (long) get_frame_register_unsigned (frame, A1_REGNUM),
1930      (long) get_frame_register_unsigned (frame, M1_REGNUM),
1931      (long) get_frame_register_unsigned (frame, X1_REGNUM),
1932      (long) get_frame_register_unsigned (frame, Y1_REGNUM),
1933      (long) get_frame_register_unsigned (frame, RE_REGNUM));
1934 }
1935
1936 static void
1937 sh4_show_regs (struct frame_info *frame)
1938 {
1939   struct gdbarch *gdbarch = get_frame_arch (frame);
1940   int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1941
1942   printf_filtered
1943     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1944      phex (get_frame_register_unsigned (frame,
1945                                         gdbarch_pc_regnum (gdbarch)), 4),
1946      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1947      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1948      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1949
1950   printf_filtered
1951     ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1952      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1953      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1954      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1955   printf_filtered
1956     ("     SSR %08lx      SPC %08lx     FPUL %08lx    FPSCR %08lx\n",
1957      (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1958      (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1959      (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1960      (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1961
1962   printf_filtered
1963     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1964      (long) get_frame_register_unsigned (frame, 0),
1965      (long) get_frame_register_unsigned (frame, 1),
1966      (long) get_frame_register_unsigned (frame, 2),
1967      (long) get_frame_register_unsigned (frame, 3),
1968      (long) get_frame_register_unsigned (frame, 4),
1969      (long) get_frame_register_unsigned (frame, 5),
1970      (long) get_frame_register_unsigned (frame, 6),
1971      (long) get_frame_register_unsigned (frame, 7));
1972   printf_filtered
1973     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1974      (long) get_frame_register_unsigned (frame, 8),
1975      (long) get_frame_register_unsigned (frame, 9),
1976      (long) get_frame_register_unsigned (frame, 10),
1977      (long) get_frame_register_unsigned (frame, 11),
1978      (long) get_frame_register_unsigned (frame, 12),
1979      (long) get_frame_register_unsigned (frame, 13),
1980      (long) get_frame_register_unsigned (frame, 14),
1981      (long) get_frame_register_unsigned (frame, 15));
1982
1983   printf_filtered
1984     (pr ? "DR0-DR6  %08lx%08lx  %08lx%08lx  %08lx%08lx  %08lx%08lx\n"
1985         : "FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1986      (long) get_frame_register_unsigned
1987               (frame, gdbarch_fp0_regnum (gdbarch) + 0),
1988      (long) get_frame_register_unsigned
1989               (frame, gdbarch_fp0_regnum (gdbarch) + 1),
1990      (long) get_frame_register_unsigned
1991               (frame, gdbarch_fp0_regnum (gdbarch) + 2),
1992      (long) get_frame_register_unsigned
1993               (frame, gdbarch_fp0_regnum (gdbarch) + 3),
1994      (long) get_frame_register_unsigned
1995               (frame, gdbarch_fp0_regnum (gdbarch) + 4),
1996      (long) get_frame_register_unsigned
1997               (frame, gdbarch_fp0_regnum (gdbarch) + 5),
1998      (long) get_frame_register_unsigned
1999               (frame, gdbarch_fp0_regnum (gdbarch) + 6),
2000      (long) get_frame_register_unsigned
2001               (frame, gdbarch_fp0_regnum (gdbarch) + 7));
2002   printf_filtered
2003     (pr ? "DR8-DR14 %08lx%08lx  %08lx%08lx  %08lx%08lx  %08lx%08lx\n"
2004         : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2005      (long) get_frame_register_unsigned
2006               (frame, gdbarch_fp0_regnum (gdbarch) + 8),
2007      (long) get_frame_register_unsigned
2008               (frame, gdbarch_fp0_regnum (gdbarch) + 9),
2009      (long) get_frame_register_unsigned
2010               (frame, gdbarch_fp0_regnum (gdbarch) + 10),
2011      (long) get_frame_register_unsigned
2012               (frame, gdbarch_fp0_regnum (gdbarch) + 11),
2013      (long) get_frame_register_unsigned
2014               (frame, gdbarch_fp0_regnum (gdbarch) + 12),
2015      (long) get_frame_register_unsigned
2016               (frame, gdbarch_fp0_regnum (gdbarch) + 13),
2017      (long) get_frame_register_unsigned
2018               (frame, gdbarch_fp0_regnum (gdbarch) + 14),
2019      (long) get_frame_register_unsigned
2020               (frame, gdbarch_fp0_regnum (gdbarch) + 15));
2021 }
2022
2023 static void
2024 sh4_nofpu_show_regs (struct frame_info *frame)
2025 {
2026   printf_filtered
2027     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
2028      phex (get_frame_register_unsigned (frame,
2029                                         gdbarch_pc_regnum
2030                                           (get_frame_arch (frame))), 4),
2031      (long) get_frame_register_unsigned (frame, SR_REGNUM),
2032      (long) get_frame_register_unsigned (frame, PR_REGNUM),
2033      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
2034
2035   printf_filtered
2036     ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
2037      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
2038      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
2039      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
2040   printf_filtered
2041     ("     SSR %08lx      SPC %08lx     FPUL %08lx    FPSCR %08lx\n",
2042      (long) get_frame_register_unsigned (frame, SSR_REGNUM),
2043      (long) get_frame_register_unsigned (frame, SPC_REGNUM),
2044      (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
2045      (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
2046
2047   printf_filtered
2048     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2049      (long) get_frame_register_unsigned (frame, 0),
2050      (long) get_frame_register_unsigned (frame, 1),
2051      (long) get_frame_register_unsigned (frame, 2),
2052      (long) get_frame_register_unsigned (frame, 3),
2053      (long) get_frame_register_unsigned (frame, 4),
2054      (long) get_frame_register_unsigned (frame, 5),
2055      (long) get_frame_register_unsigned (frame, 6),
2056      (long) get_frame_register_unsigned (frame, 7));
2057   printf_filtered
2058     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2059      (long) get_frame_register_unsigned (frame, 8),
2060      (long) get_frame_register_unsigned (frame, 9),
2061      (long) get_frame_register_unsigned (frame, 10),
2062      (long) get_frame_register_unsigned (frame, 11),
2063      (long) get_frame_register_unsigned (frame, 12),
2064      (long) get_frame_register_unsigned (frame, 13),
2065      (long) get_frame_register_unsigned (frame, 14),
2066      (long) get_frame_register_unsigned (frame, 15));
2067 }
2068
2069 static void
2070 sh_dsp_show_regs (struct frame_info *frame)
2071 {
2072   printf_filtered
2073     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
2074      phex (get_frame_register_unsigned (frame,
2075                                         gdbarch_pc_regnum
2076                                           (get_frame_arch (frame))), 4),
2077      (long) get_frame_register_unsigned (frame, SR_REGNUM),
2078      (long) get_frame_register_unsigned (frame, PR_REGNUM),
2079      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
2080
2081   printf_filtered
2082     ("     GBR %08lx      VBR %08lx      DSR %08lx     MACL %08lx\n",
2083      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
2084      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
2085      (long) get_frame_register_unsigned (frame, DSR_REGNUM),
2086      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
2087
2088   printf_filtered
2089     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2090      (long) get_frame_register_unsigned (frame, 0),
2091      (long) get_frame_register_unsigned (frame, 1),
2092      (long) get_frame_register_unsigned (frame, 2),
2093      (long) get_frame_register_unsigned (frame, 3),
2094      (long) get_frame_register_unsigned (frame, 4),
2095      (long) get_frame_register_unsigned (frame, 5),
2096      (long) get_frame_register_unsigned (frame, 6),
2097      (long) get_frame_register_unsigned (frame, 7));
2098   printf_filtered
2099     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2100      (long) get_frame_register_unsigned (frame, 8),
2101      (long) get_frame_register_unsigned (frame, 9),
2102      (long) get_frame_register_unsigned (frame, 10),
2103      (long) get_frame_register_unsigned (frame, 11),
2104      (long) get_frame_register_unsigned (frame, 12),
2105      (long) get_frame_register_unsigned (frame, 13),
2106      (long) get_frame_register_unsigned (frame, 14),
2107      (long) get_frame_register_unsigned (frame, 15));
2108
2109   printf_filtered
2110     ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2111      (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
2112      (long) get_frame_register_unsigned (frame, A0_REGNUM),
2113      (long) get_frame_register_unsigned (frame, M0_REGNUM),
2114      (long) get_frame_register_unsigned (frame, X0_REGNUM),
2115      (long) get_frame_register_unsigned (frame, Y0_REGNUM),
2116      (long) get_frame_register_unsigned (frame, RS_REGNUM),
2117      (long) get_frame_register_unsigned (frame, MOD_REGNUM));
2118   printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2119      (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
2120      (long) get_frame_register_unsigned (frame, A1_REGNUM),
2121      (long) get_frame_register_unsigned (frame, M1_REGNUM),
2122      (long) get_frame_register_unsigned (frame, X1_REGNUM),
2123      (long) get_frame_register_unsigned (frame, Y1_REGNUM),
2124      (long) get_frame_register_unsigned (frame, RE_REGNUM));
2125 }
2126
2127 static void
2128 sh_show_regs_command (char *args, int from_tty)
2129 {
2130   if (sh_show_regs)
2131     (*sh_show_regs) (get_current_frame ());
2132 }
2133
2134 static struct type *
2135 sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr)
2136 {
2137   if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
2138        && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2139     return builtin_type (gdbarch)->builtin_float;
2140   else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2141     return builtin_type (gdbarch)->builtin_double;
2142   else
2143     return builtin_type (gdbarch)->builtin_int;
2144 }
2145
2146 /* Return the GDB type object for the "standard" data type
2147    of data in register N.  */
2148 static struct type *
2149 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
2150 {
2151   if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
2152        && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2153     return builtin_type (gdbarch)->builtin_float;
2154   else
2155     return builtin_type (gdbarch)->builtin_int;
2156 }
2157
2158 static struct type *
2159 sh_sh4_build_float_register_type (struct gdbarch *gdbarch, int high)
2160 {
2161   return lookup_array_range_type (builtin_type (gdbarch)->builtin_float,
2162                                   0, high);
2163 }
2164
2165 static struct type *
2166 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
2167 {
2168   if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
2169        && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2170     return builtin_type (gdbarch)->builtin_float;
2171   else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2172     return builtin_type (gdbarch)->builtin_double;
2173   else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2174     return sh_sh4_build_float_register_type (gdbarch, 3);
2175   else
2176     return builtin_type (gdbarch)->builtin_int;
2177 }
2178
2179 static struct type *
2180 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
2181 {
2182   return builtin_type (gdbarch)->builtin_int;
2183 }
2184
2185 /* Is a register in a reggroup?
2186    The default code in reggroup.c doesn't identify system registers, some
2187    float registers or any of the vector registers.
2188    TODO: sh2a and dsp registers.  */
2189 static int
2190 sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2191                         struct reggroup *reggroup)
2192 {
2193   if (gdbarch_register_name (gdbarch, regnum) == NULL
2194       || *gdbarch_register_name (gdbarch, regnum) == '\0')
2195     return 0;
2196
2197   if (reggroup == float_reggroup
2198       && (regnum == FPUL_REGNUM
2199           || regnum == FPSCR_REGNUM))
2200     return 1;
2201
2202   if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
2203     {
2204       if (reggroup == vector_reggroup || reggroup == float_reggroup)
2205         return 1;
2206       if (reggroup == general_reggroup)
2207         return 0;
2208     }
2209
2210   if (regnum == VBR_REGNUM
2211       || regnum == SR_REGNUM
2212       || regnum == FPSCR_REGNUM
2213       || regnum == SSR_REGNUM
2214       || regnum == SPC_REGNUM)
2215     {
2216       if (reggroup == system_reggroup)
2217         return 1;
2218       if (reggroup == general_reggroup)
2219         return 0;
2220     }
2221
2222   /* The default code can cope with any other registers.  */
2223   return default_register_reggroup_p (gdbarch, regnum, reggroup);
2224 }
2225
2226 /* On the sh4, the DRi pseudo registers are problematic if the target
2227    is little endian. When the user writes one of those registers, for
2228    instance with 'ser var $dr0=1', we want the double to be stored
2229    like this:
2230    fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2231    fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2232
2233    This corresponds to little endian byte order & big endian word
2234    order.  However if we let gdb write the register w/o conversion, it
2235    will write fr0 and fr1 this way:
2236    fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2237    fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2238    because it will consider fr0 and fr1 as a single LE stretch of memory.
2239
2240    To achieve what we want we must force gdb to store things in
2241    floatformat_ieee_double_littlebyte_bigword (which is defined in
2242    include/floatformat.h and libiberty/floatformat.c.
2243
2244    In case the target is big endian, there is no problem, the
2245    raw bytes will look like:
2246    fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
2247    fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2248
2249    The other pseudo registers (the FVs) also don't pose a problem
2250    because they are stored as 4 individual FP elements. */
2251
2252 static void
2253 sh_register_convert_to_virtual (int regnum, struct type *type,
2254                                 char *from, char *to)
2255 {
2256   if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
2257     {
2258       DOUBLEST val;
2259       floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2260                                from, &val);
2261       store_typed_floating (to, type, val);
2262     }
2263   else
2264     error
2265       ("sh_register_convert_to_virtual called with non DR register number");
2266 }
2267
2268 static void
2269 sh_register_convert_to_raw (struct type *type, int regnum,
2270                             const void *from, void *to)
2271 {
2272   if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
2273     {
2274       DOUBLEST val = extract_typed_floating (from, type);
2275       floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
2276                                  &val, to);
2277     }
2278   else
2279     error (_("sh_register_convert_to_raw called with non DR register number"));
2280 }
2281
2282 /* For vectors of 4 floating point registers. */
2283 static int
2284 fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum)
2285 {
2286   int fp_regnum;
2287
2288   fp_regnum = gdbarch_fp0_regnum (gdbarch)
2289               + (fv_regnum - FV0_REGNUM) * 4;
2290   return fp_regnum;
2291 }
2292
2293 /* For double precision floating point registers, i.e 2 fp regs.*/
2294 static int
2295 dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum)
2296 {
2297   int fp_regnum;
2298
2299   fp_regnum = gdbarch_fp0_regnum (gdbarch)
2300               + (dr_regnum - DR0_REGNUM) * 2;
2301   return fp_regnum;
2302 }
2303
2304 static void
2305 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2306                          int reg_nr, gdb_byte *buffer)
2307 {
2308   int base_regnum, portion;
2309   char temp_buffer[MAX_REGISTER_SIZE];
2310
2311   if (reg_nr == PSEUDO_BANK_REGNUM)
2312     regcache_raw_read (regcache, BANK_REGNUM, buffer);
2313   else
2314   if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2315     {
2316       base_regnum = dr_reg_base_num (gdbarch, reg_nr);
2317
2318       /* Build the value in the provided buffer. */
2319       /* Read the real regs for which this one is an alias.  */
2320       for (portion = 0; portion < 2; portion++)
2321         regcache_raw_read (regcache, base_regnum + portion,
2322                            (temp_buffer
2323                             + register_size (gdbarch,
2324                                              base_regnum) * portion));
2325       /* We must pay attention to the endiannes. */
2326       sh_register_convert_to_virtual (reg_nr,
2327                                       register_type (gdbarch, reg_nr),
2328                                       temp_buffer, buffer);
2329     }
2330   else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2331     {
2332       base_regnum = fv_reg_base_num (gdbarch, reg_nr);
2333
2334       /* Read the real regs for which this one is an alias.  */
2335       for (portion = 0; portion < 4; portion++)
2336         regcache_raw_read (regcache, base_regnum + portion,
2337                            ((char *) buffer
2338                             + register_size (gdbarch,
2339                                              base_regnum) * portion));
2340     }
2341 }
2342
2343 static void
2344 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2345                           int reg_nr, const gdb_byte *buffer)
2346 {
2347   int base_regnum, portion;
2348   char temp_buffer[MAX_REGISTER_SIZE];
2349
2350   if (reg_nr == PSEUDO_BANK_REGNUM)
2351     {
2352       /* When the bank register is written to, the whole register bank
2353          is switched and all values in the bank registers must be read
2354          from the target/sim again. We're just invalidating the regcache
2355          so that a re-read happens next time it's necessary.  */
2356       int bregnum;
2357
2358       regcache_raw_write (regcache, BANK_REGNUM, buffer);
2359       for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum)
2360         regcache_invalidate (regcache, bregnum);
2361     }
2362   else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2363     {
2364       base_regnum = dr_reg_base_num (gdbarch, reg_nr);
2365
2366       /* We must pay attention to the endiannes. */
2367       sh_register_convert_to_raw (register_type (gdbarch, reg_nr),
2368                                   reg_nr, buffer, temp_buffer);
2369
2370       /* Write the real regs for which this one is an alias.  */
2371       for (portion = 0; portion < 2; portion++)
2372         regcache_raw_write (regcache, base_regnum + portion,
2373                             (temp_buffer
2374                              + register_size (gdbarch,
2375                                               base_regnum) * portion));
2376     }
2377   else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2378     {
2379       base_regnum = fv_reg_base_num (gdbarch, reg_nr);
2380
2381       /* Write the real regs for which this one is an alias.  */
2382       for (portion = 0; portion < 4; portion++)
2383         regcache_raw_write (regcache, base_regnum + portion,
2384                             ((char *) buffer
2385                              + register_size (gdbarch,
2386                                               base_regnum) * portion));
2387     }
2388 }
2389
2390 static int
2391 sh_dsp_register_sim_regno (struct gdbarch *gdbarch, int nr)
2392 {
2393   if (legacy_register_sim_regno (gdbarch, nr) < 0)
2394     return legacy_register_sim_regno (gdbarch, nr);
2395   if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
2396     return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
2397   if (nr == MOD_REGNUM)
2398     return SIM_SH_MOD_REGNUM;
2399   if (nr == RS_REGNUM)
2400     return SIM_SH_RS_REGNUM;
2401   if (nr == RE_REGNUM)
2402     return SIM_SH_RE_REGNUM;
2403   if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
2404     return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
2405   return nr;
2406 }
2407
2408 static int
2409 sh_sh2a_register_sim_regno (struct gdbarch *gdbarch, int nr)
2410 {
2411   switch (nr)
2412     {
2413       case TBR_REGNUM:
2414         return SIM_SH_TBR_REGNUM;
2415       case IBNR_REGNUM:
2416         return SIM_SH_IBNR_REGNUM;
2417       case IBCR_REGNUM:
2418         return SIM_SH_IBCR_REGNUM;
2419       case BANK_REGNUM:
2420         return SIM_SH_BANK_REGNUM;
2421       case MACLB_REGNUM:
2422         return SIM_SH_BANK_MACL_REGNUM;
2423       case GBRB_REGNUM:
2424         return SIM_SH_BANK_GBR_REGNUM;
2425       case PRB_REGNUM:
2426         return SIM_SH_BANK_PR_REGNUM;
2427       case IVNB_REGNUM:
2428         return SIM_SH_BANK_IVN_REGNUM;
2429       case MACHB_REGNUM:
2430         return SIM_SH_BANK_MACH_REGNUM;
2431       default:
2432         break;
2433     }
2434   return legacy_register_sim_regno (gdbarch, nr);
2435 }
2436
2437 /* Set up the register unwinding such that call-clobbered registers are
2438    not displayed in frames >0 because the true value is not certain.
2439    The 'undefined' registers will show up as 'not available' unless the
2440    CFI says otherwise.
2441
2442    This function is currently set up for SH4 and compatible only.  */
2443
2444 static void
2445 sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
2446                           struct dwarf2_frame_state_reg *reg,
2447                           struct frame_info *this_frame)
2448 {
2449   /* Mark the PC as the destination for the return address.  */
2450   if (regnum == gdbarch_pc_regnum (gdbarch))
2451     reg->how = DWARF2_FRAME_REG_RA;
2452
2453   /* Mark the stack pointer as the call frame address.  */
2454   else if (regnum == gdbarch_sp_regnum (gdbarch))
2455     reg->how = DWARF2_FRAME_REG_CFA;
2456
2457   /* The above was taken from the default init_reg in dwarf2-frame.c
2458      while the below is SH specific.  */
2459
2460   /* Caller save registers.  */
2461   else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7)
2462            || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11)
2463            || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5)
2464            || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2)
2465            || (regnum == MACH_REGNUM)
2466            || (regnum == MACL_REGNUM)
2467            || (regnum == FPUL_REGNUM)
2468            || (regnum == SR_REGNUM))
2469     reg->how = DWARF2_FRAME_REG_UNDEFINED;
2470
2471   /* Callee save registers.  */
2472   else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15)
2473            || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15)
2474            || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8)
2475            || (regnum == FV0_REGNUM+3))
2476     reg->how = DWARF2_FRAME_REG_SAME_VALUE;
2477
2478   /* Other registers.  These are not in the ABI and may or may not
2479      mean anything in frames >0 so don't show them.  */
2480   else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15)
2481            || (regnum == GBR_REGNUM)
2482            || (regnum == VBR_REGNUM)
2483            || (regnum == FPSCR_REGNUM)
2484            || (regnum == SSR_REGNUM)
2485            || (regnum == SPC_REGNUM))
2486     reg->how = DWARF2_FRAME_REG_UNDEFINED;
2487 }
2488
2489 static struct sh_frame_cache *
2490 sh_alloc_frame_cache (void)
2491 {
2492   struct sh_frame_cache *cache;
2493   int i;
2494
2495   cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
2496
2497   /* Base address.  */
2498   cache->base = 0;
2499   cache->saved_sp = 0;
2500   cache->sp_offset = 0;
2501   cache->pc = 0;
2502
2503   /* Frameless until proven otherwise.  */
2504   cache->uses_fp = 0;
2505
2506   /* Saved registers.  We initialize these to -1 since zero is a valid
2507      offset (that's where fp is supposed to be stored).  */
2508   for (i = 0; i < SH_NUM_REGS; i++)
2509     {
2510       cache->saved_regs[i] = -1;
2511     }
2512
2513   return cache;
2514 }
2515
2516 static struct sh_frame_cache *
2517 sh_frame_cache (struct frame_info *this_frame, void **this_cache)
2518 {
2519   struct gdbarch *gdbarch = get_frame_arch (this_frame);
2520   struct sh_frame_cache *cache;
2521   CORE_ADDR current_pc;
2522   int i;
2523
2524   if (*this_cache)
2525     return *this_cache;
2526
2527   cache = sh_alloc_frame_cache ();
2528   *this_cache = cache;
2529
2530   /* In principle, for normal frames, fp holds the frame pointer,
2531      which holds the base address for the current stack frame.
2532      However, for functions that don't need it, the frame pointer is
2533      optional.  For these "frameless" functions the frame pointer is
2534      actually the frame pointer of the calling frame. */
2535   cache->base = get_frame_register_unsigned (this_frame, FP_REGNUM);
2536   if (cache->base == 0)
2537     return cache;
2538
2539   cache->pc = get_frame_func (this_frame);
2540   current_pc = get_frame_pc (this_frame);
2541   if (cache->pc != 0)
2542     {
2543       ULONGEST fpscr;
2544       fpscr = get_frame_register_unsigned (this_frame, FPSCR_REGNUM);
2545       sh_analyze_prologue (gdbarch, cache->pc, current_pc, cache, fpscr);
2546     }
2547
2548   if (!cache->uses_fp)
2549     {
2550       /* We didn't find a valid frame, which means that CACHE->base
2551          currently holds the frame pointer for our calling frame.  If
2552          we're at the start of a function, or somewhere half-way its
2553          prologue, the function's frame probably hasn't been fully
2554          setup yet.  Try to reconstruct the base address for the stack
2555          frame by looking at the stack pointer.  For truly "frameless"
2556          functions this might work too.  */
2557       cache->base = get_frame_register_unsigned
2558                      (this_frame, gdbarch_sp_regnum (gdbarch));
2559     }
2560
2561   /* Now that we have the base address for the stack frame we can
2562      calculate the value of sp in the calling frame.  */
2563   cache->saved_sp = cache->base + cache->sp_offset;
2564
2565   /* Adjust all the saved registers such that they contain addresses
2566      instead of offsets.  */
2567   for (i = 0; i < SH_NUM_REGS; i++)
2568     if (cache->saved_regs[i] != -1)
2569       cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
2570
2571   return cache;
2572 }
2573
2574 static struct value *
2575 sh_frame_prev_register (struct frame_info *this_frame,
2576                         void **this_cache, int regnum)
2577 {
2578   struct gdbarch *gdbarch = get_frame_arch (this_frame);
2579   struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
2580
2581   gdb_assert (regnum >= 0);
2582
2583   if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
2584     return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
2585
2586   /* The PC of the previous frame is stored in the PR register of
2587      the current frame.  Frob regnum so that we pull the value from
2588      the correct place.  */
2589   if (regnum == gdbarch_pc_regnum (gdbarch))
2590     regnum = PR_REGNUM;
2591
2592   if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
2593     return frame_unwind_got_memory (this_frame, regnum,
2594                                     cache->saved_regs[regnum]);
2595
2596   return frame_unwind_got_register (this_frame, regnum, regnum);
2597 }
2598
2599 static void
2600 sh_frame_this_id (struct frame_info *this_frame, void **this_cache,
2601                   struct frame_id *this_id)
2602 {
2603   struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
2604
2605   /* This marks the outermost frame.  */
2606   if (cache->base == 0)
2607     return;
2608
2609   *this_id = frame_id_build (cache->saved_sp, cache->pc);
2610 }
2611
2612 static const struct frame_unwind sh_frame_unwind = {
2613   NORMAL_FRAME,
2614   sh_frame_this_id,
2615   sh_frame_prev_register,
2616   NULL,
2617   default_frame_sniffer
2618 };
2619
2620 static CORE_ADDR
2621 sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2622 {
2623   return frame_unwind_register_unsigned (next_frame,
2624                                          gdbarch_sp_regnum (gdbarch));
2625 }
2626
2627 static CORE_ADDR
2628 sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2629 {
2630   return frame_unwind_register_unsigned (next_frame,
2631                                          gdbarch_pc_regnum (gdbarch));
2632 }
2633
2634 static struct frame_id
2635 sh_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2636 {
2637   CORE_ADDR sp = get_frame_register_unsigned (this_frame,
2638                                               gdbarch_sp_regnum (gdbarch));
2639   return frame_id_build (sp, get_frame_pc (this_frame));
2640 }
2641
2642 static CORE_ADDR
2643 sh_frame_base_address (struct frame_info *this_frame, void **this_cache)
2644 {
2645   struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
2646
2647   return cache->base;
2648 }
2649
2650 static const struct frame_base sh_frame_base = {
2651   &sh_frame_unwind,
2652   sh_frame_base_address,
2653   sh_frame_base_address,
2654   sh_frame_base_address
2655 };
2656
2657 /* The epilogue is defined here as the area at the end of a function,
2658    either on the `ret' instruction itself or after an instruction which
2659    destroys the function's stack frame. */
2660 static int
2661 sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2662 {
2663   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2664   CORE_ADDR func_addr = 0, func_end = 0;
2665
2666   if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2667     {
2668       ULONGEST inst;
2669       /* The sh epilogue is max. 14 bytes long.  Give another 14 bytes
2670          for a nop and some fixed data (e.g. big offsets) which are
2671          unfortunately also treated as part of the function (which
2672          means, they are below func_end. */
2673       CORE_ADDR addr = func_end - 28;
2674       if (addr < func_addr + 4)
2675         addr = func_addr + 4;
2676       if (pc < addr)
2677         return 0;
2678
2679       /* First search forward until hitting an rts. */
2680       while (addr < func_end
2681              && !IS_RTS (read_memory_unsigned_integer (addr, 2, byte_order)))
2682         addr += 2;
2683       if (addr >= func_end)
2684         return 0;
2685
2686       /* At this point we should find a mov.l @r15+,r14 instruction,
2687          either before or after the rts.  If not, then the function has
2688          probably no "normal" epilogue and we bail out here. */
2689       inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2690       if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2,
2691                                                        byte_order)))
2692         addr -= 2;
2693       else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2,
2694                                                              byte_order)))
2695         return 0;
2696
2697       inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2698
2699       /* Step over possible lds.l @r15+,macl. */
2700       if (IS_MACL_LDS (inst))
2701         {
2702           addr -= 2;
2703           inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2704         }
2705
2706       /* Step over possible lds.l @r15+,pr. */
2707       if (IS_LDS (inst))
2708         {
2709           addr -= 2;
2710           inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2711         }
2712
2713       /* Step over possible mov r14,r15. */
2714       if (IS_MOV_FP_SP (inst))
2715         {
2716           addr -= 2;
2717           inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2718         }
2719
2720       /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2721          instructions. */
2722       while (addr > func_addr + 4
2723              && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
2724         {
2725           addr -= 2;
2726           inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2727         }
2728
2729       /* On SH2a check if the previous instruction was perhaps a MOVI20.
2730          That's allowed for the epilogue.  */
2731       if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a
2732            || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu)
2733           && addr > func_addr + 6
2734           && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2,
2735                                                       byte_order)))
2736         addr -= 4;
2737
2738       if (pc >= addr)
2739         return 1;
2740     }
2741   return 0;
2742 }
2743
2744
2745 /* Supply register REGNUM from the buffer specified by REGS and LEN
2746    in the register set REGSET to register cache REGCACHE.
2747    REGTABLE specifies where each register can be found in REGS.
2748    If REGNUM is -1, do this for all registers in REGSET.  */
2749
2750 void
2751 sh_corefile_supply_regset (const struct regset *regset,
2752                            struct regcache *regcache,
2753                            int regnum, const void *regs, size_t len)
2754 {
2755   struct gdbarch *gdbarch = get_regcache_arch (regcache);
2756   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2757   const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset
2758                                              ? tdep->core_gregmap
2759                                              : tdep->core_fpregmap);
2760   int i;
2761
2762   for (i = 0; regmap[i].regnum != -1; i++)
2763     {
2764       if ((regnum == -1 || regnum == regmap[i].regnum)
2765           && regmap[i].offset + 4 <= len)
2766         regcache_raw_supply (regcache, regmap[i].regnum,
2767                              (char *)regs + regmap[i].offset);
2768     }
2769 }
2770
2771 /* Collect register REGNUM in the register set REGSET from register cache
2772    REGCACHE into the buffer specified by REGS and LEN.
2773    REGTABLE specifies where each register can be found in REGS.
2774    If REGNUM is -1, do this for all registers in REGSET.  */
2775
2776 void
2777 sh_corefile_collect_regset (const struct regset *regset,
2778                             const struct regcache *regcache,
2779                             int regnum, void *regs, size_t len)
2780 {
2781   struct gdbarch *gdbarch = get_regcache_arch (regcache);
2782   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2783   const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset
2784                                              ? tdep->core_gregmap
2785                                              : tdep->core_fpregmap);
2786   int i;
2787
2788   for (i = 0; regmap[i].regnum != -1; i++)
2789     {
2790       if ((regnum == -1 || regnum == regmap[i].regnum)
2791           && regmap[i].offset + 4 <= len)
2792         regcache_raw_collect (regcache, regmap[i].regnum,
2793                               (char *)regs + regmap[i].offset);
2794     }
2795 }
2796
2797 /* The following two regsets have the same contents, so it is tempting to
2798    unify them, but they are distiguished by their address, so don't.  */
2799
2800 struct regset sh_corefile_gregset =
2801 {
2802   NULL,
2803   sh_corefile_supply_regset,
2804   sh_corefile_collect_regset
2805 };
2806
2807 static struct regset sh_corefile_fpregset =
2808 {
2809   NULL,
2810   sh_corefile_supply_regset,
2811   sh_corefile_collect_regset
2812 };
2813
2814 static const struct regset *
2815 sh_regset_from_core_section (struct gdbarch *gdbarch, const char *sect_name,
2816                              size_t sect_size)
2817 {
2818   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2819
2820   if (tdep->core_gregmap && strcmp (sect_name, ".reg") == 0)
2821     return &sh_corefile_gregset;
2822
2823   if (tdep->core_fpregmap && strcmp (sect_name, ".reg2") == 0)
2824     return &sh_corefile_fpregset;
2825
2826   return NULL;
2827 }
2828 \f
2829
2830 static struct gdbarch *
2831 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2832 {
2833   struct gdbarch *gdbarch;
2834   struct gdbarch_tdep *tdep;
2835
2836   sh_show_regs = sh_generic_show_regs;
2837   switch (info.bfd_arch_info->mach)
2838     {
2839     case bfd_mach_sh2e:
2840       sh_show_regs = sh2e_show_regs;
2841       break;
2842     case bfd_mach_sh2a:
2843       sh_show_regs = sh2a_show_regs;
2844       break;
2845     case bfd_mach_sh2a_nofpu:
2846       sh_show_regs = sh2a_nofpu_show_regs;
2847       break;
2848     case bfd_mach_sh_dsp:
2849       sh_show_regs = sh_dsp_show_regs;
2850       break;
2851
2852     case bfd_mach_sh3:
2853     case bfd_mach_sh3_nommu:
2854     case bfd_mach_sh2a_nofpu_or_sh3_nommu:
2855       sh_show_regs = sh3_show_regs;
2856       break;
2857
2858     case bfd_mach_sh3e:
2859     case bfd_mach_sh2a_or_sh3e:
2860       sh_show_regs = sh3e_show_regs;
2861       break;
2862
2863     case bfd_mach_sh3_dsp:
2864     case bfd_mach_sh4al_dsp:
2865       sh_show_regs = sh3_dsp_show_regs;
2866       break;
2867
2868     case bfd_mach_sh4:
2869     case bfd_mach_sh4a:
2870     case bfd_mach_sh2a_or_sh4:
2871       sh_show_regs = sh4_show_regs;
2872       break;
2873
2874     case bfd_mach_sh4_nofpu:
2875     case bfd_mach_sh4_nommu_nofpu:
2876     case bfd_mach_sh4a_nofpu:
2877     case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
2878       sh_show_regs = sh4_nofpu_show_regs;
2879       break;
2880
2881     case bfd_mach_sh5:
2882       sh_show_regs = sh64_show_regs;
2883       /* SH5 is handled entirely in sh64-tdep.c */
2884       return sh64_gdbarch_init (info, arches);
2885     }
2886
2887   /* If there is already a candidate, use it.  */
2888   arches = gdbarch_list_lookup_by_info (arches, &info);
2889   if (arches != NULL)
2890     return arches->gdbarch;
2891
2892   /* None found, create a new architecture from the information
2893      provided. */
2894   tdep = XZALLOC (struct gdbarch_tdep);
2895   gdbarch = gdbarch_alloc (&info, tdep);
2896
2897   set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2898   set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2899   set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2900   set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2901   set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2902   set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2903   set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2904   set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2905
2906   set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
2907   set_gdbarch_sp_regnum (gdbarch, 15);
2908   set_gdbarch_pc_regnum (gdbarch, 16);
2909   set_gdbarch_fp0_regnum (gdbarch, -1);
2910   set_gdbarch_num_pseudo_regs (gdbarch, 0);
2911
2912   set_gdbarch_register_type (gdbarch, sh_default_register_type);
2913   set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p);
2914
2915   set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2916
2917   set_gdbarch_print_insn (gdbarch, print_insn_sh);
2918   set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2919
2920   set_gdbarch_return_value (gdbarch, sh_return_value_nofpu);
2921
2922   set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2923   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2924
2925   set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2926
2927   set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2928
2929   set_gdbarch_frame_align (gdbarch, sh_frame_align);
2930   set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2931   set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2932   set_gdbarch_dummy_id (gdbarch, sh_dummy_id);
2933   frame_base_set_default (gdbarch, &sh_frame_base);
2934
2935   set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
2936
2937   dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg);
2938
2939   set_gdbarch_regset_from_core_section (gdbarch, sh_regset_from_core_section);
2940
2941   switch (info.bfd_arch_info->mach)
2942     {
2943     case bfd_mach_sh:
2944       set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2945       break;
2946
2947     case bfd_mach_sh2:
2948       set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2949       break;
2950
2951     case bfd_mach_sh2e:
2952       /* doubles on sh2e and sh3e are actually 4 byte. */
2953       set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2954
2955       set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
2956       set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2957       set_gdbarch_fp0_regnum (gdbarch, 25);
2958       set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2959       set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2960       break;
2961
2962     case bfd_mach_sh2a:
2963       set_gdbarch_register_name (gdbarch, sh_sh2a_register_name);
2964       set_gdbarch_register_type (gdbarch, sh_sh2a_register_type);
2965       set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2966
2967       set_gdbarch_fp0_regnum (gdbarch, 25);
2968       set_gdbarch_num_pseudo_regs (gdbarch, 9);
2969       set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2970       set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2971       set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2972       set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2973       break;
2974
2975     case bfd_mach_sh2a_nofpu:
2976       set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name);
2977       set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2978
2979       set_gdbarch_num_pseudo_regs (gdbarch, 1);
2980       set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2981       set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2982       break;
2983
2984     case bfd_mach_sh_dsp:
2985       set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2986       set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2987       break;
2988
2989     case bfd_mach_sh3:
2990     case bfd_mach_sh3_nommu:
2991     case bfd_mach_sh2a_nofpu_or_sh3_nommu:
2992       set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
2993       break;
2994
2995     case bfd_mach_sh3e:
2996     case bfd_mach_sh2a_or_sh3e:
2997       /* doubles on sh2e and sh3e are actually 4 byte. */
2998       set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2999
3000       set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
3001       set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
3002       set_gdbarch_fp0_regnum (gdbarch, 25);
3003       set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
3004       set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
3005       break;
3006
3007     case bfd_mach_sh3_dsp:
3008       set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
3009       set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
3010       break;
3011
3012     case bfd_mach_sh4:
3013     case bfd_mach_sh4a:
3014     case bfd_mach_sh2a_or_sh4:
3015       set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
3016       set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
3017       set_gdbarch_fp0_regnum (gdbarch, 25);
3018       set_gdbarch_num_pseudo_regs (gdbarch, 13);
3019       set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
3020       set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
3021       set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
3022       set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
3023       break;
3024
3025     case bfd_mach_sh4_nofpu:
3026     case bfd_mach_sh4a_nofpu:
3027     case bfd_mach_sh4_nommu_nofpu:
3028     case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
3029       set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
3030       break;
3031
3032     case bfd_mach_sh4al_dsp:
3033       set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
3034       set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
3035       break;
3036
3037     default:
3038       set_gdbarch_register_name (gdbarch, sh_sh_register_name);
3039       break;
3040     }
3041
3042   /* Hook in ABI-specific overrides, if they have been registered.  */
3043   gdbarch_init_osabi (info, gdbarch);
3044
3045   dwarf2_append_unwinders (gdbarch);
3046   frame_unwind_append_unwinder (gdbarch, &sh_frame_unwind);
3047
3048   return gdbarch;
3049 }
3050
3051 static void
3052 show_sh_command (char *args, int from_tty)
3053 {
3054   help_list (showshcmdlist, "show sh ", all_commands, gdb_stdout);
3055 }
3056
3057 static void
3058 set_sh_command (char *args, int from_tty)
3059 {
3060   printf_unfiltered
3061     ("\"set sh\" must be followed by an appropriate subcommand.\n");
3062   help_list (setshcmdlist, "set sh ", all_commands, gdb_stdout);
3063 }
3064
3065 extern initialize_file_ftype _initialize_sh_tdep;       /* -Wmissing-prototypes */
3066
3067 void
3068 _initialize_sh_tdep (void)
3069 {
3070   struct cmd_list_element *c;
3071
3072   gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
3073
3074   add_com ("regs", class_vars, sh_show_regs_command, _("Print all registers"));
3075
3076   add_prefix_cmd ("sh", no_class, set_sh_command, "SH specific commands.",
3077                   &setshcmdlist, "set sh ", 0, &setlist);
3078   add_prefix_cmd ("sh", no_class, show_sh_command, "SH specific commands.",
3079                   &showshcmdlist, "show sh ", 0, &showlist);
3080
3081   add_setshow_enum_cmd ("calling-convention", class_vars, sh_cc_enum,
3082                         &sh_active_calling_convention,
3083                         _("Set calling convention used when calling target "
3084                           "functions from GDB."),
3085                         _("Show calling convention used when calling target "
3086                           "functions from GDB."),
3087                         _("gcc       - Use GCC calling convention (default).\n"
3088                           "renesas   - Enforce Renesas calling convention."),
3089                         NULL, NULL,
3090                         &setshcmdlist, &showshcmdlist);
3091 }