gdb/sh-tdep.c

   1 /* Target-dependent code for Renesas Super-H, for GDB.
   2
   3    Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
   4    2003, 2004, 2005, 2007, 2008 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 /*
  22    Contributed by Steve Chamberlain
  23    sac@cygnus.com
  24  */
  25
  26 #include "defs.h"
  27 #include "frame.h"
  28 #include "frame-base.h"
  29 #include "frame-unwind.h"
  30 #include "dwarf2-frame.h"
  31 #include "symtab.h"
  32 #include "gdbtypes.h"
  33 #include "gdbcmd.h"
  34 #include "gdbcore.h"
  35 #include "value.h"
  36 #include "dis-asm.h"
  37 #include "inferior.h"
  38 #include "gdb_string.h"
  39 #include "gdb_assert.h"
  40 #include "arch-utils.h"
  41 #include "floatformat.h"
  42 #include "regcache.h"
  43 #include "doublest.h"
  44 #include "osabi.h"
  45 #include "reggroups.h"
  46
  47 #include "sh-tdep.h"
  48
  49 #include "elf-bfd.h"
  50 #include "solib-svr4.h"
  51
  52 /* sh flags */
  53 #include "elf/sh.h"
  54 #include "elf/dwarf2.h"
  55 /* registers numbers shared with the simulator */
  56 #include "gdb/sim-sh.h"
  57
  58 /* List of "set sh ..." and "show sh ..." commands.  */
  59 static struct cmd_list_element *setshcmdlist = NULL;
  60 static struct cmd_list_element *showshcmdlist = NULL;
  61
  62 static const char sh_cc_gcc[] = "gcc";
  63 static const char sh_cc_renesas[] = "renesas";
  64 static const char *sh_cc_enum[] = {
  65   sh_cc_gcc,
  66   sh_cc_renesas,
  67   NULL
  68 };
  69
  70 static const char *sh_active_calling_convention = sh_cc_gcc;
  71
  72 static void (*sh_show_regs) (struct frame_info *);
  73
  74 #define SH_NUM_REGS 67
  75
  76 struct sh_frame_cache
  77 {
  78   /* Base address.  */
  79   CORE_ADDR base;
  80   LONGEST sp_offset;
  81   CORE_ADDR pc;
  82
  83   /* Flag showing that a frame has been created in the prologue code. */
  84   int uses_fp;
  85
  86   /* Saved registers.  */
  87   CORE_ADDR saved_regs[SH_NUM_REGS];
  88   CORE_ADDR saved_sp;
  89 };
  90
  91 static int
  92 sh_is_renesas_calling_convention (struct type *func_type)
  93 {
  94   return ((func_type
  95            && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GNU_renesas_sh)
  96           || sh_active_calling_convention == sh_cc_renesas);
  97 }
  98
  99 static const char *
 100 sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr)
 101 {
 102   static char *register_names[] = {
 103     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 104     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 105     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 106     "", "",
 107     "", "", "", "", "", "", "", "",
 108     "", "", "", "", "", "", "", "",
 109     "", "",
 110     "", "", "", "", "", "", "", "",
 111     "", "", "", "", "", "", "", "",
 112     "", "", "", "", "", "", "", "",
 113   };
 114   if (reg_nr < 0)
 115     return NULL;
 116   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 117     return NULL;
 118   return register_names[reg_nr];
 119 }
 120
 121 static const char *
 122 sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr)
 123 {
 124   static char *register_names[] = {
 125     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 126     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 127     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 128     "", "",
 129     "", "", "", "", "", "", "", "",
 130     "", "", "", "", "", "", "", "",
 131     "ssr", "spc",
 132     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
 133     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
 134     "", "", "", "", "", "", "", "",
 135   };
 136   if (reg_nr < 0)
 137     return NULL;
 138   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 139     return NULL;
 140   return register_names[reg_nr];
 141 }
 142
 143 static const char *
 144 sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr)
 145 {
 146   static char *register_names[] = {
 147     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 148     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 149     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 150     "fpul", "fpscr",
 151     "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
 152     "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
 153     "ssr", "spc",
 154     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
 155     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
 156     "", "", "", "", "", "", "", "",
 157   };
 158   if (reg_nr < 0)
 159     return NULL;
 160   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 161     return NULL;
 162   return register_names[reg_nr];
 163 }
 164
 165 static const char *
 166 sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr)
 167 {
 168   static char *register_names[] = {
 169     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 170     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 171     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 172     "fpul", "fpscr",
 173     "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
 174     "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
 175     "", "",
 176     "", "", "", "", "", "", "", "",
 177     "", "", "", "", "", "", "", "",
 178     "", "", "", "", "", "", "", "",
 179   };
 180   if (reg_nr < 0)
 181     return NULL;
 182   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 183     return NULL;
 184   return register_names[reg_nr];
 185 }
 186
 187 static const char *
 188 sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr)
 189 {
 190   static char *register_names[] = {
 191     /* general registers 0-15 */
 192     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 193     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 194     /* 16 - 22 */
 195     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 196     /* 23, 24 */
 197     "fpul", "fpscr",
 198     /* floating point registers 25 - 40 */
 199     "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
 200     "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
 201     /* 41, 42 */
 202     "", "",
 203     /* 43 - 62.  Banked registers.  The bank number used is determined by
 204        the bank register (63). */
 205     "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
 206     "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
 207     "machb", "ivnb", "prb", "gbrb", "maclb",
 208     /* 63: register bank number, not a real register but used to
 209        communicate the register bank currently get/set.  This register
 210        is hidden to the user, who manipulates it using the pseudo
 211        register called "bank" (67).  See below.  */
 212     "",
 213     /* 64 - 66 */
 214     "ibcr", "ibnr", "tbr",
 215     /* 67: register bank number, the user visible pseudo register.  */
 216     "bank",
 217     /* double precision (pseudo) 68 - 75 */
 218     "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
 219   };
 220   if (reg_nr < 0)
 221     return NULL;
 222   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 223     return NULL;
 224   return register_names[reg_nr];
 225 }
 226
 227 static const char *
 228 sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
 229 {
 230   static char *register_names[] = {
 231     /* general registers 0-15 */
 232     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 233     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 234     /* 16 - 22 */
 235     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 236     /* 23, 24 */
 237     "", "",
 238     /* floating point registers 25 - 40 */
 239     "", "", "", "", "", "", "", "",
 240     "", "", "", "", "", "", "", "",
 241     /* 41, 42 */
 242     "", "",
 243     /* 43 - 62.  Banked registers.  The bank number used is determined by
 244        the bank register (63). */
 245     "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
 246     "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
 247     "machb", "ivnb", "prb", "gbrb", "maclb",
 248     /* 63: register bank number, not a real register but used to
 249        communicate the register bank currently get/set.  This register
 250        is hidden to the user, who manipulates it using the pseudo
 251        register called "bank" (67).  See below.  */
 252     "",
 253     /* 64 - 66 */
 254     "ibcr", "ibnr", "tbr",
 255     /* 67: register bank number, the user visible pseudo register.  */
 256     "bank",
 257     /* double precision (pseudo) 68 - 75 */
 258     "", "", "", "", "", "", "", "",
 259   };
 260   if (reg_nr < 0)
 261     return NULL;
 262   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 263     return NULL;
 264   return register_names[reg_nr];
 265 }
 266
 267 static const char *
 268 sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
 269 {
 270   static char *register_names[] = {
 271     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 272     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 273     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 274     "", "dsr",
 275     "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
 276     "y0", "y1", "", "", "", "", "", "mod",
 277     "", "",
 278     "rs", "re", "", "", "", "", "", "",
 279     "", "", "", "", "", "", "", "",
 280     "", "", "", "", "", "", "", "",
 281   };
 282   if (reg_nr < 0)
 283     return NULL;
 284   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 285     return NULL;
 286   return register_names[reg_nr];
 287 }
 288
 289 static const char *
 290 sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
 291 {
 292   static char *register_names[] = {
 293     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 294     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 295     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 296     "", "dsr",
 297     "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
 298     "y0", "y1", "", "", "", "", "", "mod",
 299     "ssr", "spc",
 300     "rs", "re", "", "", "", "", "", "",
 301     "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
 302     "", "", "", "", "", "", "", "",
 303     "", "", "", "", "", "", "", "",
 304   };
 305   if (reg_nr < 0)
 306     return NULL;
 307   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 308     return NULL;
 309   return register_names[reg_nr];
 310 }
 311
 312 static const char *
 313 sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr)
 314 {
 315   static char *register_names[] = {
 316     /* general registers 0-15 */
 317     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 318     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 319     /* 16 - 22 */
 320     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 321     /* 23, 24 */
 322     "fpul", "fpscr",
 323     /* floating point registers 25 - 40 */
 324     "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
 325     "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
 326     /* 41, 42 */
 327     "ssr", "spc",
 328     /* bank 0 43 - 50 */
 329     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
 330     /* bank 1 51 - 58 */
 331     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
 332     "", "", "", "", "", "", "", "",
 333     /* pseudo bank register. */
 334     "",
 335     /* double precision (pseudo) 59 - 66 */
 336     "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
 337     /* vectors (pseudo) 67 - 70 */
 338     "fv0", "fv4", "fv8", "fv12",
 339     /* FIXME: missing XF 71 - 86 */
 340     /* FIXME: missing XD 87 - 94 */
 341   };
 342   if (reg_nr < 0)
 343     return NULL;
 344   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 345     return NULL;
 346   return register_names[reg_nr];
 347 }
 348
 349 static const char *
 350 sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
 351 {
 352   static char *register_names[] = {
 353     /* general registers 0-15 */
 354     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 355     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 356     /* 16 - 22 */
 357     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 358     /* 23, 24 */
 359     "", "",
 360     /* floating point registers 25 - 40 -- not for nofpu target */
 361     "", "", "", "", "", "", "", "",
 362     "", "", "", "", "", "", "", "",
 363     /* 41, 42 */
 364     "ssr", "spc",
 365     /* bank 0 43 - 50 */
 366     "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
 367     /* bank 1 51 - 58 */
 368     "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
 369     "", "", "", "", "", "", "", "",
 370     /* pseudo bank register. */
 371     "",
 372     /* double precision (pseudo) 59 - 66 -- not for nofpu target */
 373     "", "", "", "", "", "", "", "",
 374     /* vectors (pseudo) 67 - 70 -- not for nofpu target */
 375     "", "", "", "",
 376   };
 377   if (reg_nr < 0)
 378     return NULL;
 379   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 380     return NULL;
 381   return register_names[reg_nr];
 382 }
 383
 384 static const char *
 385 sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
 386 {
 387   static char *register_names[] = {
 388     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 389     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 390     "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
 391     "", "dsr",
 392     "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
 393     "y0", "y1", "", "", "", "", "", "mod",
 394     "ssr", "spc",
 395     "rs", "re", "", "", "", "", "", "",
 396     "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
 397     "", "", "", "", "", "", "", "",
 398     "", "", "", "", "", "", "", "",
 399   };
 400   if (reg_nr < 0)
 401     return NULL;
 402   if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
 403     return NULL;
 404   return register_names[reg_nr];
 405 }
 406
 407 static const unsigned char *
 408 sh_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
 409 {
 410   /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
 411   static unsigned char breakpoint[] = { 0xc3, 0xc3 };
 412
 413   /* For remote stub targets, trapa #20 is used.  */
 414   if (strcmp (target_shortname, "remote") == 0)
 415     {
 416       static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 };
 417       static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 };
 418
 419       if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
 420         {
 421           *lenptr = sizeof (big_remote_breakpoint);
 422           return big_remote_breakpoint;
 423         }
 424       else
 425         {
 426           *lenptr = sizeof (little_remote_breakpoint);
 427           return little_remote_breakpoint;
 428         }
 429     }
 430
 431   *lenptr = sizeof (breakpoint);
 432   return breakpoint;
 433 }
 434
 435 /* Prologue looks like
 436    mov.l        r14,@-r15
 437    sts.l        pr,@-r15
 438    mov.l        <regs>,@-r15
 439    sub          <room_for_loca_vars>,r15
 440    mov          r15,r14
 441
 442    Actually it can be more complicated than this but that's it, basically.
 443  */
 444
 445 #define GET_SOURCE_REG(x)       (((x) >> 4) & 0xf)
 446 #define GET_TARGET_REG(x)       (((x) >> 8) & 0xf)
 447
 448 /* JSR @Rm         0100mmmm00001011 */
 449 #define IS_JSR(x)               (((x) & 0xf0ff) == 0x400b)
 450
 451 /* STS.L PR,@-r15  0100111100100010
 452    r15-4-->r15, PR-->(r15) */
 453 #define IS_STS(x)               ((x) == 0x4f22)
 454
 455 /* STS.L MACL,@-r15  0100111100010010
 456    r15-4-->r15, MACL-->(r15) */
 457 #define IS_MACL_STS(x)          ((x) == 0x4f12)
 458
 459 /* MOV.L Rm,@-r15  00101111mmmm0110
 460    r15-4-->r15, Rm-->(R15) */
 461 #define IS_PUSH(x)              (((x) & 0xff0f) == 0x2f06)
 462
 463 /* MOV r15,r14     0110111011110011
 464    r15-->r14  */
 465 #define IS_MOV_SP_FP(x)         ((x) == 0x6ef3)
 466
 467 /* ADD #imm,r15    01111111iiiiiiii
 468    r15+imm-->r15 */
 469 #define IS_ADD_IMM_SP(x)        (((x) & 0xff00) == 0x7f00)
 470
 471 #define IS_MOV_R3(x)            (((x) & 0xff00) == 0x1a00)
 472 #define IS_SHLL_R3(x)           ((x) == 0x4300)
 473
 474 /* ADD r3,r15      0011111100111100
 475    r15+r3-->r15 */
 476 #define IS_ADD_R3SP(x)          ((x) == 0x3f3c)
 477
 478 /* FMOV.S FRm,@-Rn  Rn-4-->Rn, FRm-->(Rn)     1111nnnnmmmm1011
 479    FMOV DRm,@-Rn    Rn-8-->Rn, DRm-->(Rn)     1111nnnnmmm01011
 480    FMOV XDm,@-Rn    Rn-8-->Rn, XDm-->(Rn)     1111nnnnmmm11011 */
 481 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
 482                    make this entirely clear. */
 483 /* #define IS_FMOV(x)           (((x) & 0xf00f) == 0xf00b) */
 484 #define IS_FPUSH(x)             (((x) & 0xff0f) == 0xff0b)
 485
 486 /* MOV Rm,Rn          Rm-->Rn        0110nnnnmmmm0011  4 <= m <= 7 */
 487 #define IS_MOV_ARG_TO_REG(x) \
 488         (((x) & 0xf00f) == 0x6003 && \
 489          ((x) & 0x00f0) >= 0x0040 && \
 490          ((x) & 0x00f0) <= 0x0070)
 491 /* MOV.L Rm,@Rn               0010nnnnmmmm0010  n = 14, 4 <= m <= 7 */
 492 #define IS_MOV_ARG_TO_IND_R14(x) \
 493         (((x) & 0xff0f) == 0x2e02 && \
 494          ((x) & 0x00f0) >= 0x0040 && \
 495          ((x) & 0x00f0) <= 0x0070)
 496 /* MOV.L Rm,@(disp*4,Rn)      00011110mmmmdddd  n = 14, 4 <= m <= 7 */
 497 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
 498         (((x) & 0xff00) == 0x1e00 && \
 499          ((x) & 0x00f0) >= 0x0040 && \
 500          ((x) & 0x00f0) <= 0x0070)
 501
 502 /* MOV.W @(disp*2,PC),Rn      1001nnnndddddddd */
 503 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
 504 /* MOV.L @(disp*4,PC),Rn      1101nnnndddddddd */
 505 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
 506 /* MOVI20 #imm20,Rn           0000nnnniiii0000 */
 507 #define IS_MOVI20(x)            (((x) & 0xf00f) == 0x0000)
 508 /* SUB Rn,R15                 00111111nnnn1000 */
 509 #define IS_SUB_REG_FROM_SP(x)   (((x) & 0xff0f) == 0x3f08)
 510
 511 #define FPSCR_SZ                (1 << 20)
 512
 513 /* The following instructions are used for epilogue testing. */
 514 #define IS_RESTORE_FP(x)        ((x) == 0x6ef6)
 515 #define IS_RTS(x)               ((x) == 0x000b)
 516 #define IS_LDS(x)               ((x) == 0x4f26)
 517 #define IS_MACL_LDS(x)          ((x) == 0x4f16)
 518 #define IS_MOV_FP_SP(x)         ((x) == 0x6fe3)
 519 #define IS_ADD_REG_TO_FP(x)     (((x) & 0xff0f) == 0x3e0c)
 520 #define IS_ADD_IMM_FP(x)        (((x) & 0xff00) == 0x7e00)
 521
 522 static CORE_ADDR
 523 sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
 524                      struct sh_frame_cache *cache, ULONGEST fpscr)
 525 {
 526   ULONGEST inst;
 527   CORE_ADDR opc;
 528   int offset;
 529   int sav_offset = 0;
 530   int r3_val = 0;
 531   int reg, sav_reg = -1;
 532
 533   if (pc >= current_pc)
 534     return current_pc;
 535
 536   cache->uses_fp = 0;
 537   for (opc = pc + (2 * 28); pc < opc; pc += 2)
 538     {
 539       inst = read_memory_unsigned_integer (pc, 2);
 540       /* See where the registers will be saved to */
 541       if (IS_PUSH (inst))
 542         {
 543           cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
 544           cache->sp_offset += 4;
 545         }
 546       else if (IS_STS (inst))
 547         {
 548           cache->saved_regs[PR_REGNUM] = cache->sp_offset;
 549           cache->sp_offset += 4;
 550         }
 551       else if (IS_MACL_STS (inst))
 552         {
 553           cache->saved_regs[MACL_REGNUM] = cache->sp_offset;
 554           cache->sp_offset += 4;
 555         }
 556       else if (IS_MOV_R3 (inst))
 557         {
 558           r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
 559         }
 560       else if (IS_SHLL_R3 (inst))
 561         {
 562           r3_val <<= 1;
 563         }
 564       else if (IS_ADD_R3SP (inst))
 565         {
 566           cache->sp_offset += -r3_val;
 567         }
 568       else if (IS_ADD_IMM_SP (inst))
 569         {
 570           offset = ((inst & 0xff) ^ 0x80) - 0x80;
 571           cache->sp_offset -= offset;
 572         }
 573       else if (IS_MOVW_PCREL_TO_REG (inst))
 574         {
 575           if (sav_reg < 0)
 576             {
 577               reg = GET_TARGET_REG (inst);
 578               if (reg < 14)
 579                 {
 580                   sav_reg = reg;
 581                   offset = (inst & 0xff) << 1;
 582                   sav_offset =
 583                     read_memory_integer ((pc + 4) + offset, 2);
 584                 }
 585             }
 586         }
 587       else if (IS_MOVL_PCREL_TO_REG (inst))
 588         {
 589           if (sav_reg < 0)
 590             {
 591               reg = GET_TARGET_REG (inst);
 592               if (reg < 14)
 593                 {
 594                   sav_reg = reg;
 595                   offset = (inst & 0xff) << 2;
 596                   sav_offset =
 597                     read_memory_integer (((pc & 0xfffffffc) + 4) + offset, 4);
 598                 }
 599             }
 600         }
 601       else if (IS_MOVI20 (inst))
 602         {
 603           if (sav_reg < 0)
 604             {
 605               reg = GET_TARGET_REG (inst);
 606               if (reg < 14)
 607                 {
 608                   sav_reg = reg;
 609                   sav_offset = GET_SOURCE_REG (inst) << 16;
 610                   /* MOVI20 is a 32 bit instruction! */
 611                   pc += 2;
 612                   sav_offset |= read_memory_unsigned_integer (pc, 2);
 613                   /* Now sav_offset contains an unsigned 20 bit value.
 614                      It must still get sign extended.  */
 615                   if (sav_offset & 0x00080000)
 616                     sav_offset |= 0xfff00000;
 617                 }
 618             }
 619         }
 620       else if (IS_SUB_REG_FROM_SP (inst))
 621         {
 622           reg = GET_SOURCE_REG (inst);
 623           if (sav_reg > 0 && reg == sav_reg)
 624             {
 625               sav_reg = -1;
 626             }
 627           cache->sp_offset += sav_offset;
 628         }
 629       else if (IS_FPUSH (inst))
 630         {
 631           if (fpscr & FPSCR_SZ)
 632             {
 633               cache->sp_offset += 8;
 634             }
 635           else
 636             {
 637               cache->sp_offset += 4;
 638             }
 639         }
 640       else if (IS_MOV_SP_FP (inst))
 641         {
 642           cache->uses_fp = 1;
 643           /* At this point, only allow argument register moves to other
 644              registers or argument register moves to @(X,fp) which are
 645              moving the register arguments onto the stack area allocated
 646              by a former add somenumber to SP call.  Don't allow moving
 647              to an fp indirect address above fp + cache->sp_offset. */
 648           pc += 2;
 649           for (opc = pc + 12; pc < opc; pc += 2)
 650             {
 651               inst = read_memory_integer (pc, 2);
 652               if (IS_MOV_ARG_TO_IND_R14 (inst))
 653                 {
 654                   reg = GET_SOURCE_REG (inst);
 655                   if (cache->sp_offset > 0)
 656                     cache->saved_regs[reg] = cache->sp_offset;
 657                 }
 658               else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
 659                 {
 660                   reg = GET_SOURCE_REG (inst);
 661                   offset = (inst & 0xf) * 4;
 662                   if (cache->sp_offset > offset)
 663                     cache->saved_regs[reg] = cache->sp_offset - offset;
 664                 }
 665               else if (IS_MOV_ARG_TO_REG (inst))
 666                 continue;
 667               else
 668                 break;
 669             }
 670           break;
 671         }
 672       else if (IS_JSR (inst))
 673         {
 674           /* We have found a jsr that has been scheduled into the prologue.
 675              If we continue the scan and return a pc someplace after this,
 676              then setting a breakpoint on this function will cause it to
 677              appear to be called after the function it is calling via the
 678              jsr, which will be very confusing.  Most likely the next
 679              instruction is going to be IS_MOV_SP_FP in the delay slot.  If
 680              so, note that before returning the current pc. */
 681           inst = read_memory_integer (pc + 2, 2);
 682           if (IS_MOV_SP_FP (inst))
 683             cache->uses_fp = 1;
 684           break;
 685         }
 686 #if 0                           /* This used to just stop when it found an instruction that
 687                                    was not considered part of the prologue.  Now, we just
 688                                    keep going looking for likely instructions. */
 689       else
 690         break;
 691 #endif
 692     }
 693
 694   return pc;
 695 }
 696
 697 /* Skip any prologue before the guts of a function */
 698
 699 /* Skip the prologue using the debug information. If this fails we'll
 700    fall back on the 'guess' method below. */
 701 static CORE_ADDR
 702 after_prologue (CORE_ADDR pc)
 703 {
 704   struct symtab_and_line sal;
 705   CORE_ADDR func_addr, func_end;
 706
 707   /* If we can not find the symbol in the partial symbol table, then
 708      there is no hope we can determine the function's start address
 709      with this code.  */
 710   if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
 711     return 0;
 712
 713   /* Get the line associated with FUNC_ADDR.  */
 714   sal = find_pc_line (func_addr, 0);
 715
 716   /* There are only two cases to consider.  First, the end of the source line
 717      is within the function bounds.  In that case we return the end of the
 718      source line.  Second is the end of the source line extends beyond the
 719      bounds of the current function.  We need to use the slow code to
 720      examine instructions in that case.  */
 721   if (sal.end < func_end)
 722     return sal.end;
 723   else
 724     return 0;
 725 }
 726
 727 static CORE_ADDR
 728 sh_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
 729 {
 730   CORE_ADDR pc;
 731   struct sh_frame_cache cache;
 732
 733   /* See if we can determine the end of the prologue via the symbol table.
 734      If so, then return either PC, or the PC after the prologue, whichever
 735      is greater.  */
 736   pc = after_prologue (start_pc);
 737
 738   /* If after_prologue returned a useful address, then use it.  Else
 739      fall back on the instruction skipping code. */
 740   if (pc)
 741     return max (pc, start_pc);
 742
 743   cache.sp_offset = -4;
 744   pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache, 0);
 745   if (!cache.uses_fp)
 746     return start_pc;
 747
 748   return pc;
 749 }
 750
 751 /* The ABI says:
 752
 753    Aggregate types not bigger than 8 bytes that have the same size and
 754    alignment as one of the integer scalar types are returned in the
 755    same registers as the integer type they match.
 756
 757    For example, a 2-byte aligned structure with size 2 bytes has the
 758    same size and alignment as a short int, and will be returned in R0.
 759    A 4-byte aligned structure with size 8 bytes has the same size and
 760    alignment as a long long int, and will be returned in R0 and R1.
 761
 762    When an aggregate type is returned in R0 and R1, R0 contains the
 763    first four bytes of the aggregate, and R1 contains the
 764    remainder. If the size of the aggregate type is not a multiple of 4
 765    bytes, the aggregate is tail-padded up to a multiple of 4
 766    bytes. The value of the padding is undefined. For little-endian
 767    targets the padding will appear at the most significant end of the
 768    last element, for big-endian targets the padding appears at the
 769    least significant end of the last element.
 770
 771    All other aggregate types are returned by address. The caller
 772    function passes the address of an area large enough to hold the
 773    aggregate value in R2. The called function stores the result in
 774    this location.
 775
 776    To reiterate, structs smaller than 8 bytes could also be returned
 777    in memory, if they don't pass the "same size and alignment as an
 778    integer type" rule.
 779
 780    For example, in
 781
 782    struct s { char c[3]; } wibble;
 783    struct s foo(void) {  return wibble; }
 784
 785    the return value from foo() will be in memory, not
 786    in R0, because there is no 3-byte integer type.
 787
 788    Similarly, in
 789
 790    struct s { char c[2]; } wibble;
 791    struct s foo(void) {  return wibble; }
 792
 793    because a struct containing two chars has alignment 1, that matches
 794    type char, but size 2, that matches type short.  There's no integer
 795    type that has alignment 1 and size 2, so the struct is returned in
 796    memory.
 797
 798 */
 799
 800 static int
 801 sh_use_struct_convention (int renesas_abi, struct type *type)
 802 {
 803   int len = TYPE_LENGTH (type);
 804   int nelem = TYPE_NFIELDS (type);
 805
 806   /* The Renesas ABI returns aggregate types always on stack.  */
 807   if (renesas_abi && (TYPE_CODE (type) == TYPE_CODE_STRUCT
 808                       || TYPE_CODE (type) == TYPE_CODE_UNION))
 809     return 1;
 810
 811   /* Non-power of 2 length types and types bigger than 8 bytes (which don't
 812      fit in two registers anyway) use struct convention.  */
 813   if (len != 1 && len != 2 && len != 4 && len != 8)
 814     return 1;
 815
 816   /* Scalar types and aggregate types with exactly one field are aligned
 817      by definition.  They are returned in registers.  */
 818   if (nelem <= 1)
 819     return 0;
 820
 821   /* If the first field in the aggregate has the same length as the entire
 822      aggregate type, the type is returned in registers.  */
 823   if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
 824     return 0;
 825
 826   /* If the size of the aggregate is 8 bytes and the first field is
 827      of size 4 bytes its alignment is equal to long long's alignment,
 828      so it's returned in registers.  */
 829   if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
 830     return 0;
 831
 832   /* Otherwise use struct convention.  */
 833   return 1;
 834 }
 835
 836 static int
 837 sh_use_struct_convention_nofpu (int renesas_abi, struct type *type)
 838 {
 839   /* The Renesas ABI returns long longs/doubles etc. always on stack.  */
 840   if (renesas_abi && TYPE_NFIELDS (type) == 0 && TYPE_LENGTH (type) >= 8)
 841     return 1;
 842   return sh_use_struct_convention (renesas_abi, type);
 843 }
 844
 845 static CORE_ADDR
 846 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
 847 {
 848   return sp & ~3;
 849 }
 850
 851 /* Function: push_dummy_call (formerly push_arguments)
 852    Setup the function arguments for calling a function in the inferior.
 853
 854    On the Renesas SH architecture, there are four registers (R4 to R7)
 855    which are dedicated for passing function arguments.  Up to the first
 856    four arguments (depending on size) may go into these registers.
 857    The rest go on the stack.
 858
 859    MVS: Except on SH variants that have floating point registers.
 860    In that case, float and double arguments are passed in the same
 861    manner, but using FP registers instead of GP registers.
 862
 863    Arguments that are smaller than 4 bytes will still take up a whole
 864    register or a whole 32-bit word on the stack, and will be
 865    right-justified in the register or the stack word.  This includes
 866    chars, shorts, and small aggregate types.
 867
 868    Arguments that are larger than 4 bytes may be split between two or
 869    more registers.  If there are not enough registers free, an argument
 870    may be passed partly in a register (or registers), and partly on the
 871    stack.  This includes doubles, long longs, and larger aggregates.
 872    As far as I know, there is no upper limit to the size of aggregates
 873    that will be passed in this way; in other words, the convention of
 874    passing a pointer to a large aggregate instead of a copy is not used.
 875
 876    MVS: The above appears to be true for the SH variants that do not
 877    have an FPU, however those that have an FPU appear to copy the
 878    aggregate argument onto the stack (and not place it in registers)
 879    if it is larger than 16 bytes (four GP registers).
 880
 881    An exceptional case exists for struct arguments (and possibly other
 882    aggregates such as arrays) if the size is larger than 4 bytes but
 883    not a multiple of 4 bytes.  In this case the argument is never split
 884    between the registers and the stack, but instead is copied in its
 885    entirety onto the stack, AND also copied into as many registers as
 886    there is room for.  In other words, space in registers permitting,
 887    two copies of the same argument are passed in.  As far as I can tell,
 888    only the one on the stack is used, although that may be a function
 889    of the level of compiler optimization.  I suspect this is a compiler
 890    bug.  Arguments of these odd sizes are left-justified within the
 891    word (as opposed to arguments smaller than 4 bytes, which are
 892    right-justified).
 893
 894    If the function is to return an aggregate type such as a struct, it
 895    is either returned in the normal return value register R0 (if its
 896    size is no greater than one byte), or else the caller must allocate
 897    space into which the callee will copy the return value (if the size
 898    is greater than one byte).  In this case, a pointer to the return
 899    value location is passed into the callee in register R2, which does
 900    not displace any of the other arguments passed in via registers R4
 901    to R7.   */
 902
 903 /* Helper function to justify value in register according to endianess. */
 904 static char *
 905 sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len)
 906 {
 907   static char valbuf[4];
 908
 909   memset (valbuf, 0, sizeof (valbuf));
 910   if (len < 4)
 911     {
 912       /* value gets right-justified in the register or stack word */
 913       if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
 914         memcpy (valbuf + (4 - len), (char *) value_contents (val), len);
 915       else
 916         memcpy (valbuf, (char *) value_contents (val), len);
 917       return valbuf;
 918     }
 919   return (char *) value_contents (val);
 920 }
 921
 922 /* Helper function to eval number of bytes to allocate on stack. */
 923 static CORE_ADDR
 924 sh_stack_allocsize (int nargs, struct value **args)
 925 {
 926   int stack_alloc = 0;
 927   while (nargs-- > 0)
 928     stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3);
 929   return stack_alloc;
 930 }
 931
 932 /* Helper functions for getting the float arguments right.  Registers usage
 933    depends on the ABI and the endianess.  The comments should enlighten how
 934    it's intended to work. */
 935
 936 /* This array stores which of the float arg registers are already in use. */
 937 static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
 938
 939 /* This function just resets the above array to "no reg used so far". */
 940 static void
 941 sh_init_flt_argreg (void)
 942 {
 943   memset (flt_argreg_array, 0, sizeof flt_argreg_array);
 944 }
 945
 946 /* This function returns the next register to use for float arg passing.
 947    It returns either a valid value between FLOAT_ARG0_REGNUM and
 948    FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
 949    FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
 950
 951    Note that register number 0 in flt_argreg_array corresponds with the
 952    real float register fr4.  In contrast to FLOAT_ARG0_REGNUM (value is
 953    29) the parity of the register number is preserved, which is important
 954    for the double register passing test (see the "argreg & 1" test below). */
 955 static int
 956 sh_next_flt_argreg (struct gdbarch *gdbarch, int len, struct type *func_type)
 957 {
 958   int argreg;
 959
 960   /* First search for the next free register. */
 961   for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
 962        ++argreg)
 963     if (!flt_argreg_array[argreg])
 964       break;
 965
 966   /* No register left? */
 967   if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
 968     return FLOAT_ARGLAST_REGNUM + 1;
 969
 970   if (len == 8)
 971     {
 972       /* Doubles are always starting in a even register number. */
 973       if (argreg & 1)
 974         {
 975           /* In gcc ABI, the skipped register is lost for further argument
 976              passing now.  Not so in Renesas ABI.  */
 977           if (!sh_is_renesas_calling_convention (func_type))
 978             flt_argreg_array[argreg] = 1;
 979
 980           ++argreg;
 981
 982           /* No register left? */
 983           if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
 984             return FLOAT_ARGLAST_REGNUM + 1;
 985         }
 986       /* Also mark the next register as used. */
 987       flt_argreg_array[argreg + 1] = 1;
 988     }
 989   else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
 990            && !sh_is_renesas_calling_convention (func_type))
 991     {
 992       /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
 993       if (!flt_argreg_array[argreg + 1])
 994         ++argreg;
 995     }
 996   flt_argreg_array[argreg] = 1;
 997   return FLOAT_ARG0_REGNUM + argreg;
 998 }
 999
1000 /* Helper function which figures out, if a type is treated like a float type.
1001
1002    The FPU ABIs have a special way how to treat types as float types.
1003    Structures with exactly one member, which is of type float or double, are
1004    treated exactly as the base types float or double:
1005
1006      struct sf {
1007        float f;
1008      };
1009
1010      struct sd {
1011        double d;
1012      };
1013
1014    are handled the same way as just
1015
1016      float f;
1017
1018      double d;
1019
1020    As a result, arguments of these struct types are pushed into floating point
1021    registers exactly as floats or doubles, using the same decision algorithm.
1022
1023    The same is valid if these types are used as function return types.  The
1024    above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
1025    or even using struct convention as it is for other structs.  */
1026
1027 static int
1028 sh_treat_as_flt_p (struct type *type)
1029 {
1030   int len = TYPE_LENGTH (type);
1031
1032   /* Ordinary float types are obviously treated as float.  */
1033   if (TYPE_CODE (type) == TYPE_CODE_FLT)
1034     return 1;
1035   /* Otherwise non-struct types are not treated as float.  */
1036   if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
1037     return 0;
1038   /* Otherwise structs with more than one memeber are not treated as float.  */
1039   if (TYPE_NFIELDS (type) != 1)
1040     return 0;
1041   /* Otherwise if the type of that member is float, the whole type is
1042      treated as float.  */
1043   if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
1044     return 1;
1045   /* Otherwise it's not treated as float.  */
1046   return 0;
1047 }
1048
1049 static CORE_ADDR
1050 sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
1051                         struct value *function,
1052                         struct regcache *regcache,
1053                         CORE_ADDR bp_addr, int nargs,
1054                         struct value **args,
1055                         CORE_ADDR sp, int struct_return,
1056                         CORE_ADDR struct_addr)
1057 {
1058   int stack_offset = 0;
1059   int argreg = ARG0_REGNUM;
1060   int flt_argreg = 0;
1061   int argnum;
1062   struct type *func_type = value_type (function);
1063   struct type *type;
1064   CORE_ADDR regval;
1065   char *val;
1066   int len, reg_size = 0;
1067   int pass_on_stack = 0;
1068   int treat_as_flt;
1069   int last_reg_arg = INT_MAX;
1070
1071   /* The Renesas ABI expects all varargs arguments, plus the last
1072      non-vararg argument to be on the stack, no matter how many
1073      registers have been used so far.  */
1074   if (sh_is_renesas_calling_convention (func_type)
1075       && TYPE_VARARGS (func_type))
1076     last_reg_arg = TYPE_NFIELDS (func_type) - 2;
1077
1078   /* first force sp to a 4-byte alignment */
1079   sp = sh_frame_align (gdbarch, sp);
1080
1081   /* make room on stack for args */
1082   sp -= sh_stack_allocsize (nargs, args);
1083
1084   /* Initialize float argument mechanism. */
1085   sh_init_flt_argreg ();
1086
1087   /* Now load as many as possible of the first arguments into
1088      registers, and push the rest onto the stack.  There are 16 bytes
1089      in four registers available.  Loop thru args from first to last.  */
1090   for (argnum = 0; argnum < nargs; argnum++)
1091     {
1092       type = value_type (args[argnum]);
1093       len = TYPE_LENGTH (type);
1094       val = sh_justify_value_in_reg (gdbarch, args[argnum], len);
1095
1096       /* Some decisions have to be made how various types are handled.
1097          This also differs in different ABIs. */
1098       pass_on_stack = 0;
1099
1100       /* Find out the next register to use for a floating point value. */
1101       treat_as_flt = sh_treat_as_flt_p (type);
1102       if (treat_as_flt)
1103         flt_argreg = sh_next_flt_argreg (gdbarch, len, func_type);
1104       /* In Renesas ABI, long longs and aggregate types are always passed
1105          on stack.  */
1106       else if (sh_is_renesas_calling_convention (func_type)
1107                && ((TYPE_CODE (type) == TYPE_CODE_INT && len == 8)
1108                    || TYPE_CODE (type) == TYPE_CODE_STRUCT
1109                    || TYPE_CODE (type) == TYPE_CODE_UNION))
1110         pass_on_stack = 1;
1111       /* In contrast to non-FPU CPUs, arguments are never split between
1112          registers and stack.  If an argument doesn't fit in the remaining
1113          registers it's always pushed entirely on the stack.  */
1114       else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
1115         pass_on_stack = 1;
1116
1117       while (len > 0)
1118         {
1119           if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
1120               || (!treat_as_flt && (argreg > ARGLAST_REGNUM
1121                                     || pass_on_stack))
1122               || argnum > last_reg_arg)
1123             {
1124               /* The data goes entirely on the stack, 4-byte aligned. */
1125               reg_size = (len + 3) & ~3;
1126               write_memory (sp + stack_offset, val, reg_size);
1127               stack_offset += reg_size;
1128             }
1129           else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
1130             {
1131               /* Argument goes in a float argument register.  */
1132               reg_size = register_size (gdbarch, flt_argreg);
1133               regval = extract_unsigned_integer (val, reg_size);
1134               /* In little endian mode, float types taking two registers
1135                  (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1136                  be stored swapped in the argument registers.  The below
1137                  code first writes the first 32 bits in the next but one
1138                  register, increments the val and len values accordingly
1139                  and then proceeds as normal by writing the second 32 bits
1140                  into the next register. */
1141               if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
1142                   && TYPE_LENGTH (type) == 2 * reg_size)
1143                 {
1144                   regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
1145                                                   regval);
1146                   val += reg_size;
1147                   len -= reg_size;
1148                   regval = extract_unsigned_integer (val, reg_size);
1149                 }
1150               regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
1151             }
1152           else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
1153             {
1154               /* there's room in a register */
1155               reg_size = register_size (gdbarch, argreg);
1156               regval = extract_unsigned_integer (val, reg_size);
1157               regcache_cooked_write_unsigned (regcache, argreg++, regval);
1158             }
1159           /* Store the value one register at a time or in one step on stack.  */
1160           len -= reg_size;
1161           val += reg_size;
1162         }
1163     }
1164
1165   if (struct_return)
1166     {
1167       if (sh_is_renesas_calling_convention (func_type))
1168         /* If the function uses the Renesas ABI, subtract another 4 bytes from
1169            the stack and store the struct return address there.  */
1170         write_memory_unsigned_integer (sp -= 4, 4, struct_addr);
1171       else
1172         /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1173            its own dedicated register.  */
1174         regcache_cooked_write_unsigned (regcache,
1175                                         STRUCT_RETURN_REGNUM, struct_addr);
1176     }
1177
1178   /* Store return address. */
1179   regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1180
1181   /* Update stack pointer.  */
1182   regcache_cooked_write_unsigned (regcache,
1183                                   gdbarch_sp_regnum (gdbarch), sp);
1184
1185   return sp;
1186 }
1187
1188 static CORE_ADDR
1189 sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
1190                           struct value *function,
1191                           struct regcache *regcache,
1192                           CORE_ADDR bp_addr,
1193                           int nargs, struct value **args,
1194                           CORE_ADDR sp, int struct_return,
1195                           CORE_ADDR struct_addr)
1196 {
1197   int stack_offset = 0;
1198   int argreg = ARG0_REGNUM;
1199   int argnum;
1200   struct type *func_type = value_type (function);
1201   struct type *type;
1202   CORE_ADDR regval;
1203   char *val;
1204   int len, reg_size = 0;
1205   int pass_on_stack = 0;
1206   int last_reg_arg = INT_MAX;
1207
1208   /* The Renesas ABI expects all varargs arguments, plus the last
1209      non-vararg argument to be on the stack, no matter how many
1210      registers have been used so far.  */
1211   if (sh_is_renesas_calling_convention (func_type)
1212       && TYPE_VARARGS (func_type))
1213     last_reg_arg = TYPE_NFIELDS (func_type) - 2;
1214
1215   /* first force sp to a 4-byte alignment */
1216   sp = sh_frame_align (gdbarch, sp);
1217
1218   /* make room on stack for args */
1219   sp -= sh_stack_allocsize (nargs, args);
1220
1221   /* Now load as many as possible of the first arguments into
1222      registers, and push the rest onto the stack.  There are 16 bytes
1223      in four registers available.  Loop thru args from first to last.  */
1224   for (argnum = 0; argnum < nargs; argnum++)
1225     {
1226       type = value_type (args[argnum]);
1227       len = TYPE_LENGTH (type);
1228       val = sh_justify_value_in_reg (gdbarch, args[argnum], len);
1229
1230       /* Some decisions have to be made how various types are handled.
1231          This also differs in different ABIs. */
1232       pass_on_stack = 0;
1233       /* Renesas ABI pushes doubles and long longs entirely on stack.
1234          Same goes for aggregate types.  */
1235       if (sh_is_renesas_calling_convention (func_type)
1236           && ((TYPE_CODE (type) == TYPE_CODE_INT && len >= 8)
1237               || (TYPE_CODE (type) == TYPE_CODE_FLT && len >= 8)
1238               || TYPE_CODE (type) == TYPE_CODE_STRUCT
1239               || TYPE_CODE (type) == TYPE_CODE_UNION))
1240         pass_on_stack = 1;
1241       while (len > 0)
1242         {
1243           if (argreg > ARGLAST_REGNUM || pass_on_stack
1244               || argnum > last_reg_arg)
1245             {
1246               /* The remainder of the data goes entirely on the stack,
1247                  4-byte aligned. */
1248               reg_size = (len + 3) & ~3;
1249               write_memory (sp + stack_offset, val, reg_size);
1250               stack_offset += reg_size;
1251             }
1252           else if (argreg <= ARGLAST_REGNUM)
1253             {
1254               /* there's room in a register */
1255               reg_size = register_size (gdbarch, argreg);
1256               regval = extract_unsigned_integer (val, reg_size);
1257               regcache_cooked_write_unsigned (regcache, argreg++, regval);
1258             }
1259           /* Store the value reg_size bytes at a time.  This means that things
1260              larger than reg_size bytes may go partly in registers and partly
1261              on the stack.  */
1262           len -= reg_size;
1263           val += reg_size;
1264         }
1265     }
1266
1267   if (struct_return)
1268     {
1269       if (sh_is_renesas_calling_convention (func_type))
1270         /* If the function uses the Renesas ABI, subtract another 4 bytes from
1271            the stack and store the struct return address there.  */
1272         write_memory_unsigned_integer (sp -= 4, 4, struct_addr);
1273       else
1274         /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1275            its own dedicated register.  */
1276         regcache_cooked_write_unsigned (regcache,
1277                                         STRUCT_RETURN_REGNUM, struct_addr);
1278     }
1279
1280   /* Store return address. */
1281   regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1282
1283   /* Update stack pointer.  */
1284   regcache_cooked_write_unsigned (regcache,
1285                                   gdbarch_sp_regnum (gdbarch), sp);
1286
1287   return sp;
1288 }
1289
1290 /* Find a function's return value in the appropriate registers (in
1291    regbuf), and copy it into valbuf.  Extract from an array REGBUF
1292    containing the (raw) register state a function return value of type
1293    TYPE, and copy that, in virtual format, into VALBUF.  */
1294 static void
1295 sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache,
1296                                void *valbuf)
1297 {
1298   int len = TYPE_LENGTH (type);
1299   int return_register = R0_REGNUM;
1300   int offset;
1301
1302   if (len <= 4)
1303     {
1304       ULONGEST c;
1305
1306       regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
1307       store_unsigned_integer (valbuf, len, c);
1308     }
1309   else if (len == 8)
1310     {
1311       int i, regnum = R0_REGNUM;
1312       for (i = 0; i < len; i += 4)
1313         regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1314     }
1315   else
1316     error (_("bad size for return value"));
1317 }
1318
1319 static void
1320 sh_extract_return_value_fpu (struct type *type, struct regcache *regcache,
1321                              void *valbuf)
1322 {
1323   struct gdbarch *gdbarch = get_regcache_arch (regcache);
1324   if (sh_treat_as_flt_p (type))
1325     {
1326       int len = TYPE_LENGTH (type);
1327       int i, regnum = gdbarch_fp0_regnum (gdbarch);
1328       for (i = 0; i < len; i += 4)
1329         if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1330           regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i);
1331         else
1332           regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1333     }
1334   else
1335     sh_extract_return_value_nofpu (type, regcache, valbuf);
1336 }
1337
1338 /* Write into appropriate registers a function return value
1339    of type TYPE, given in virtual format.
1340    If the architecture is sh4 or sh3e, store a function's return value
1341    in the R0 general register or in the FP0 floating point register,
1342    depending on the type of the return value. In all the other cases
1343    the result is stored in r0, left-justified. */
1344 static void
1345 sh_store_return_value_nofpu (struct type *type, struct regcache *regcache,
1346                              const void *valbuf)
1347 {
1348   ULONGEST val;
1349   int len = TYPE_LENGTH (type);
1350
1351   if (len <= 4)
1352     {
1353       val = extract_unsigned_integer (valbuf, len);
1354       regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
1355     }
1356   else
1357     {
1358       int i, regnum = R0_REGNUM;
1359       for (i = 0; i < len; i += 4)
1360         regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1361     }
1362 }
1363
1364 static void
1365 sh_store_return_value_fpu (struct type *type, struct regcache *regcache,
1366                            const void *valbuf)
1367 {
1368   struct gdbarch *gdbarch = get_regcache_arch (regcache);
1369   if (sh_treat_as_flt_p (type))
1370     {
1371       int len = TYPE_LENGTH (type);
1372       int i, regnum = gdbarch_fp0_regnum (gdbarch);
1373       for (i = 0; i < len; i += 4)
1374         if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1375           regcache_raw_write (regcache, regnum++,
1376                               (char *) valbuf + len - 4 - i);
1377         else
1378           regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1379     }
1380   else
1381     sh_store_return_value_nofpu (type, regcache, valbuf);
1382 }
1383
1384 static enum return_value_convention
1385 sh_return_value_nofpu (struct gdbarch *gdbarch, struct type *func_type,
1386                        struct type *type, struct regcache *regcache,
1387                        gdb_byte *readbuf, const gdb_byte *writebuf)
1388 {
1389   if (sh_use_struct_convention_nofpu (
1390         sh_is_renesas_calling_convention (func_type), type))
1391     return RETURN_VALUE_STRUCT_CONVENTION;
1392   if (writebuf)
1393     sh_store_return_value_nofpu (type, regcache, writebuf);
1394   else if (readbuf)
1395     sh_extract_return_value_nofpu (type, regcache, readbuf);
1396   return RETURN_VALUE_REGISTER_CONVENTION;
1397 }
1398
1399 static enum return_value_convention
1400 sh_return_value_fpu (struct gdbarch *gdbarch, struct type *func_type,
1401                      struct type *type, struct regcache *regcache,
1402                      gdb_byte *readbuf, const gdb_byte *writebuf)
1403 {
1404   if (sh_use_struct_convention (
1405         sh_is_renesas_calling_convention (func_type), type))
1406     return RETURN_VALUE_STRUCT_CONVENTION;
1407   if (writebuf)
1408     sh_store_return_value_fpu (type, regcache, writebuf);
1409   else if (readbuf)
1410     sh_extract_return_value_fpu (type, regcache, readbuf);
1411   return RETURN_VALUE_REGISTER_CONVENTION;
1412 }
1413
1414 /* Print the registers in a form similar to the E7000 */
1415
1416 static void
1417 sh_generic_show_regs (struct frame_info *frame)
1418 {
1419   printf_filtered
1420     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1421      paddr (get_frame_register_unsigned (frame,
1422                                          gdbarch_pc_regnum
1423                                            (get_frame_arch (frame)))),
1424      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1425      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1426      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1427
1428   printf_filtered
1429     ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1430      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1431      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1432      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1433
1434   printf_filtered
1435     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1436      (long) get_frame_register_unsigned (frame, 0),
1437      (long) get_frame_register_unsigned (frame, 1),
1438      (long) get_frame_register_unsigned (frame, 2),
1439      (long) get_frame_register_unsigned (frame, 3),
1440      (long) get_frame_register_unsigned (frame, 4),
1441      (long) get_frame_register_unsigned (frame, 5),
1442      (long) get_frame_register_unsigned (frame, 6),
1443      (long) get_frame_register_unsigned (frame, 7));
1444   printf_filtered
1445     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1446      (long) get_frame_register_unsigned (frame, 8),
1447      (long) get_frame_register_unsigned (frame, 9),
1448      (long) get_frame_register_unsigned (frame, 10),
1449      (long) get_frame_register_unsigned (frame, 11),
1450      (long) get_frame_register_unsigned (frame, 12),
1451      (long) get_frame_register_unsigned (frame, 13),
1452      (long) get_frame_register_unsigned (frame, 14),
1453      (long) get_frame_register_unsigned (frame, 15));
1454 }
1455
1456 static void
1457 sh3_show_regs (struct frame_info *frame)
1458 {
1459   printf_filtered
1460     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1461      paddr (get_frame_register_unsigned (frame,
1462                                          gdbarch_pc_regnum
1463                                            (get_frame_arch (frame)))),
1464      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1465      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1466      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1467
1468   printf_filtered
1469     ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1470      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1471      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1472      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1473   printf_filtered
1474     ("     SSR %08lx      SPC %08lx\n",
1475      (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1476      (long) get_frame_register_unsigned (frame, SPC_REGNUM));
1477
1478   printf_filtered
1479     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1480      (long) get_frame_register_unsigned (frame, 0),
1481      (long) get_frame_register_unsigned (frame, 1),
1482      (long) get_frame_register_unsigned (frame, 2),
1483      (long) get_frame_register_unsigned (frame, 3),
1484      (long) get_frame_register_unsigned (frame, 4),
1485      (long) get_frame_register_unsigned (frame, 5),
1486      (long) get_frame_register_unsigned (frame, 6),
1487      (long) get_frame_register_unsigned (frame, 7));
1488   printf_filtered
1489     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1490      (long) get_frame_register_unsigned (frame, 8),
1491      (long) get_frame_register_unsigned (frame, 9),
1492      (long) get_frame_register_unsigned (frame, 10),
1493      (long) get_frame_register_unsigned (frame, 11),
1494      (long) get_frame_register_unsigned (frame, 12),
1495      (long) get_frame_register_unsigned (frame, 13),
1496      (long) get_frame_register_unsigned (frame, 14),
1497      (long) get_frame_register_unsigned (frame, 15));
1498 }
1499
1500 static void
1501 sh2e_show_regs (struct frame_info *frame)
1502 {
1503   struct gdbarch *gdbarch = get_frame_arch (frame);
1504   printf_filtered
1505     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1506      paddr (get_frame_register_unsigned (frame,
1507                                          gdbarch_pc_regnum (gdbarch))),
1508      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1509      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1510      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1511
1512   printf_filtered
1513     ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1514      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1515      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1516      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1517   printf_filtered
1518     ("     SSR %08lx      SPC %08lx     FPUL %08lx    FPSCR %08lx\n",
1519      (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1520      (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1521      (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1522      (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1523
1524   printf_filtered
1525     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1526      (long) get_frame_register_unsigned (frame, 0),
1527      (long) get_frame_register_unsigned (frame, 1),
1528      (long) get_frame_register_unsigned (frame, 2),
1529      (long) get_frame_register_unsigned (frame, 3),
1530      (long) get_frame_register_unsigned (frame, 4),
1531      (long) get_frame_register_unsigned (frame, 5),
1532      (long) get_frame_register_unsigned (frame, 6),
1533      (long) get_frame_register_unsigned (frame, 7));
1534   printf_filtered
1535     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1536      (long) get_frame_register_unsigned (frame, 8),
1537      (long) get_frame_register_unsigned (frame, 9),
1538      (long) get_frame_register_unsigned (frame, 10),
1539      (long) get_frame_register_unsigned (frame, 11),
1540      (long) get_frame_register_unsigned (frame, 12),
1541      (long) get_frame_register_unsigned (frame, 13),
1542      (long) get_frame_register_unsigned (frame, 14),
1543      (long) get_frame_register_unsigned (frame, 15));
1544
1545   printf_filtered
1546     ("FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1547      (long) get_frame_register_unsigned
1548               (frame, gdbarch_fp0_regnum (gdbarch) + 0),
1549      (long) get_frame_register_unsigned
1550               (frame, gdbarch_fp0_regnum (gdbarch) + 1),
1551      (long) get_frame_register_unsigned
1552               (frame, gdbarch_fp0_regnum (gdbarch) + 2),
1553      (long) get_frame_register_unsigned
1554               (frame, gdbarch_fp0_regnum (gdbarch) + 3),
1555      (long) get_frame_register_unsigned
1556               (frame, gdbarch_fp0_regnum (gdbarch) + 4),
1557      (long) get_frame_register_unsigned
1558               (frame, gdbarch_fp0_regnum (gdbarch) + 5),
1559      (long) get_frame_register_unsigned
1560               (frame, gdbarch_fp0_regnum (gdbarch) + 6),
1561      (long) get_frame_register_unsigned
1562               (frame, gdbarch_fp0_regnum (gdbarch) + 7));
1563   printf_filtered
1564     ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1565      (long) get_frame_register_unsigned
1566               (frame, gdbarch_fp0_regnum (gdbarch) + 8),
1567      (long) get_frame_register_unsigned
1568               (frame, gdbarch_fp0_regnum (gdbarch) + 9),
1569      (long) get_frame_register_unsigned
1570               (frame, gdbarch_fp0_regnum (gdbarch) + 10),
1571      (long) get_frame_register_unsigned
1572               (frame, gdbarch_fp0_regnum (gdbarch) + 11),
1573      (long) get_frame_register_unsigned
1574               (frame, gdbarch_fp0_regnum (gdbarch) + 12),
1575      (long) get_frame_register_unsigned
1576               (frame, gdbarch_fp0_regnum (gdbarch) + 13),
1577      (long) get_frame_register_unsigned
1578               (frame, gdbarch_fp0_regnum (gdbarch) + 14),
1579      (long) get_frame_register_unsigned
1580               (frame, gdbarch_fp0_regnum (gdbarch) + 15));
1581 }
1582
1583 static void
1584 sh2a_show_regs (struct frame_info *frame)
1585 {
1586   struct gdbarch *gdbarch = get_frame_arch (frame);
1587   int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1588
1589   printf_filtered
1590     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1591      paddr (get_frame_register_unsigned (frame,
1592                                          gdbarch_pc_regnum (gdbarch))),
1593      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1594      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1595      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1596
1597   printf_filtered
1598     ("     GBR %08lx      VBR %08lx      TBR %08lx     MACL %08lx\n",
1599      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1600      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1601      (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1602      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1603   printf_filtered
1604     ("     SSR %08lx      SPC %08lx     FPUL %08lx    FPSCR %08lx\n",
1605      (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1606      (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1607      (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1608      (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1609
1610   printf_filtered
1611     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1612      (long) get_frame_register_unsigned (frame, 0),
1613      (long) get_frame_register_unsigned (frame, 1),
1614      (long) get_frame_register_unsigned (frame, 2),
1615      (long) get_frame_register_unsigned (frame, 3),
1616      (long) get_frame_register_unsigned (frame, 4),
1617      (long) get_frame_register_unsigned (frame, 5),
1618      (long) get_frame_register_unsigned (frame, 6),
1619      (long) get_frame_register_unsigned (frame, 7));
1620   printf_filtered
1621     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1622      (long) get_frame_register_unsigned (frame, 8),
1623      (long) get_frame_register_unsigned (frame, 9),
1624      (long) get_frame_register_unsigned (frame, 10),
1625      (long) get_frame_register_unsigned (frame, 11),
1626      (long) get_frame_register_unsigned (frame, 12),
1627      (long) get_frame_register_unsigned (frame, 13),
1628      (long) get_frame_register_unsigned (frame, 14),
1629      (long) get_frame_register_unsigned (frame, 15));
1630
1631   printf_filtered
1632     (pr ? "DR0-DR6  %08lx%08lx  %08lx%08lx  %08lx%08lx  %08lx%08lx\n"
1633         : "FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1634      (long) get_frame_register_unsigned
1635               (frame, gdbarch_fp0_regnum (gdbarch) + 0),
1636      (long) get_frame_register_unsigned
1637               (frame, gdbarch_fp0_regnum (gdbarch) + 1),
1638      (long) get_frame_register_unsigned
1639               (frame, gdbarch_fp0_regnum (gdbarch) + 2),
1640      (long) get_frame_register_unsigned
1641               (frame, gdbarch_fp0_regnum (gdbarch) + 3),
1642      (long) get_frame_register_unsigned
1643               (frame, gdbarch_fp0_regnum (gdbarch) + 4),
1644      (long) get_frame_register_unsigned
1645               (frame, gdbarch_fp0_regnum (gdbarch) + 5),
1646      (long) get_frame_register_unsigned
1647               (frame, gdbarch_fp0_regnum (gdbarch) + 6),
1648      (long) get_frame_register_unsigned
1649               (frame, gdbarch_fp0_regnum (gdbarch) + 7));
1650   printf_filtered
1651     (pr ? "DR8-DR14 %08lx%08lx  %08lx%08lx  %08lx%08lx  %08lx%08lx\n"
1652         : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1653      (long) get_frame_register_unsigned
1654               (frame, gdbarch_fp0_regnum (gdbarch) + 8),
1655      (long) get_frame_register_unsigned
1656               (frame, gdbarch_fp0_regnum (gdbarch) + 9),
1657      (long) get_frame_register_unsigned
1658               (frame, gdbarch_fp0_regnum (gdbarch) + 10),
1659      (long) get_frame_register_unsigned
1660               (frame, gdbarch_fp0_regnum (gdbarch) + 11),
1661      (long) get_frame_register_unsigned
1662               (frame, gdbarch_fp0_regnum (gdbarch) + 12),
1663      (long) get_frame_register_unsigned
1664               (frame, gdbarch_fp0_regnum (gdbarch) + 13),
1665      (long) get_frame_register_unsigned
1666               (frame, gdbarch_fp0_regnum (gdbarch) + 14),
1667      (long) get_frame_register_unsigned
1668               (frame, gdbarch_fp0_regnum (gdbarch) + 15));
1669   printf_filtered
1670     ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1671   printf_filtered
1672     ("R0b-R7b  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1673      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1674      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1675      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1676      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1677      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1678      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1679      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1680      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1681   printf_filtered
1682     ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1683      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1684      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1685      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1686      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1687      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1688      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1689      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1690   printf_filtered
1691     ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1692      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1693      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1694      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1695      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1696      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
1697 }
1698
1699 static void
1700 sh2a_nofpu_show_regs (struct frame_info *frame)
1701 {
1702   int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1703
1704   printf_filtered
1705     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1706      paddr (get_frame_register_unsigned (frame,
1707                                          gdbarch_pc_regnum
1708                                            (get_frame_arch (frame)))),
1709      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1710      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1711      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1712
1713   printf_filtered
1714     ("     GBR %08lx      VBR %08lx      TBR %08lx     MACL %08lx\n",
1715      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1716      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1717      (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1718      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1719   printf_filtered
1720     ("     SSR %08lx      SPC %08lx     FPUL %08lx    FPSCR %08lx\n",
1721      (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1722      (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1723      (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1724      (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1725
1726   printf_filtered
1727     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1728      (long) get_frame_register_unsigned (frame, 0),
1729      (long) get_frame_register_unsigned (frame, 1),
1730      (long) get_frame_register_unsigned (frame, 2),
1731      (long) get_frame_register_unsigned (frame, 3),
1732      (long) get_frame_register_unsigned (frame, 4),
1733      (long) get_frame_register_unsigned (frame, 5),
1734      (long) get_frame_register_unsigned (frame, 6),
1735      (long) get_frame_register_unsigned (frame, 7));
1736   printf_filtered
1737     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1738      (long) get_frame_register_unsigned (frame, 8),
1739      (long) get_frame_register_unsigned (frame, 9),
1740      (long) get_frame_register_unsigned (frame, 10),
1741      (long) get_frame_register_unsigned (frame, 11),
1742      (long) get_frame_register_unsigned (frame, 12),
1743      (long) get_frame_register_unsigned (frame, 13),
1744      (long) get_frame_register_unsigned (frame, 14),
1745      (long) get_frame_register_unsigned (frame, 15));
1746
1747   printf_filtered
1748     ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1749   printf_filtered
1750     ("R0b-R7b  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1751      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1752      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1753      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1754      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1755      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1756      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1757      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1758      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1759   printf_filtered
1760     ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1761      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1762      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1763      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1764      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1765      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1766      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1767      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1768   printf_filtered
1769     ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1770      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1771      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1772      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1773      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1774      (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
1775 }
1776
1777 static void
1778 sh3e_show_regs (struct frame_info *frame)
1779 {
1780   struct gdbarch *gdbarch = get_frame_arch (frame);
1781   printf_filtered
1782     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1783      paddr (get_frame_register_unsigned (frame,
1784                                          gdbarch_pc_regnum (gdbarch))),
1785      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1786      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1787      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1788
1789   printf_filtered
1790     ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1791      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1792      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1793      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1794   printf_filtered
1795     ("     SSR %08lx      SPC %08lx     FPUL %08lx    FPSCR %08lx\n",
1796      (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1797      (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1798      (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1799      (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1800
1801   printf_filtered
1802     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1803      (long) get_frame_register_unsigned (frame, 0),
1804      (long) get_frame_register_unsigned (frame, 1),
1805      (long) get_frame_register_unsigned (frame, 2),
1806      (long) get_frame_register_unsigned (frame, 3),
1807      (long) get_frame_register_unsigned (frame, 4),
1808      (long) get_frame_register_unsigned (frame, 5),
1809      (long) get_frame_register_unsigned (frame, 6),
1810      (long) get_frame_register_unsigned (frame, 7));
1811   printf_filtered
1812     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1813      (long) get_frame_register_unsigned (frame, 8),
1814      (long) get_frame_register_unsigned (frame, 9),
1815      (long) get_frame_register_unsigned (frame, 10),
1816      (long) get_frame_register_unsigned (frame, 11),
1817      (long) get_frame_register_unsigned (frame, 12),
1818      (long) get_frame_register_unsigned (frame, 13),
1819      (long) get_frame_register_unsigned (frame, 14),
1820      (long) get_frame_register_unsigned (frame, 15));
1821
1822   printf_filtered
1823     ("FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1824      (long) get_frame_register_unsigned
1825               (frame, gdbarch_fp0_regnum (gdbarch) + 0),
1826      (long) get_frame_register_unsigned
1827               (frame, gdbarch_fp0_regnum (gdbarch) + 1),
1828      (long) get_frame_register_unsigned
1829               (frame, gdbarch_fp0_regnum (gdbarch) + 2),
1830      (long) get_frame_register_unsigned
1831               (frame, gdbarch_fp0_regnum (gdbarch) + 3),
1832      (long) get_frame_register_unsigned
1833               (frame, gdbarch_fp0_regnum (gdbarch) + 4),
1834      (long) get_frame_register_unsigned
1835               (frame, gdbarch_fp0_regnum (gdbarch) + 5),
1836      (long) get_frame_register_unsigned
1837               (frame, gdbarch_fp0_regnum (gdbarch) + 6),
1838      (long) get_frame_register_unsigned
1839               (frame, gdbarch_fp0_regnum (gdbarch) + 7));
1840   printf_filtered
1841     ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1842      (long) get_frame_register_unsigned
1843               (frame, gdbarch_fp0_regnum (gdbarch) + 8),
1844      (long) get_frame_register_unsigned
1845               (frame, gdbarch_fp0_regnum (gdbarch) + 9),
1846      (long) get_frame_register_unsigned
1847               (frame, gdbarch_fp0_regnum (gdbarch) + 10),
1848      (long) get_frame_register_unsigned
1849               (frame, gdbarch_fp0_regnum (gdbarch) + 11),
1850      (long) get_frame_register_unsigned
1851               (frame, gdbarch_fp0_regnum (gdbarch) + 12),
1852      (long) get_frame_register_unsigned
1853               (frame, gdbarch_fp0_regnum (gdbarch) + 13),
1854      (long) get_frame_register_unsigned
1855               (frame, gdbarch_fp0_regnum (gdbarch) + 14),
1856      (long) get_frame_register_unsigned
1857               (frame, gdbarch_fp0_regnum (gdbarch) + 15));
1858 }
1859
1860 static void
1861 sh3_dsp_show_regs (struct frame_info *frame)
1862 {
1863   printf_filtered
1864     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1865      paddr (get_frame_register_unsigned (frame,
1866                                          gdbarch_pc_regnum
1867                                            (get_frame_arch (frame)))),
1868      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1869      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1870      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1871
1872   printf_filtered
1873     ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1874      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1875      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1876      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1877
1878   printf_filtered
1879     ("     SSR %08lx      SPC %08lx      DSR %08lx\n",
1880      (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1881      (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1882      (long) get_frame_register_unsigned (frame, DSR_REGNUM));
1883
1884   printf_filtered
1885     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1886      (long) get_frame_register_unsigned (frame, 0),
1887      (long) get_frame_register_unsigned (frame, 1),
1888      (long) get_frame_register_unsigned (frame, 2),
1889      (long) get_frame_register_unsigned (frame, 3),
1890      (long) get_frame_register_unsigned (frame, 4),
1891      (long) get_frame_register_unsigned (frame, 5),
1892      (long) get_frame_register_unsigned (frame, 6),
1893      (long) get_frame_register_unsigned (frame, 7));
1894   printf_filtered
1895     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1896      (long) get_frame_register_unsigned (frame, 8),
1897      (long) get_frame_register_unsigned (frame, 9),
1898      (long) get_frame_register_unsigned (frame, 10),
1899      (long) get_frame_register_unsigned (frame, 11),
1900      (long) get_frame_register_unsigned (frame, 12),
1901      (long) get_frame_register_unsigned (frame, 13),
1902      (long) get_frame_register_unsigned (frame, 14),
1903      (long) get_frame_register_unsigned (frame, 15));
1904
1905   printf_filtered
1906     ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1907      (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
1908      (long) get_frame_register_unsigned (frame, A0_REGNUM),
1909      (long) get_frame_register_unsigned (frame, M0_REGNUM),
1910      (long) get_frame_register_unsigned (frame, X0_REGNUM),
1911      (long) get_frame_register_unsigned (frame, Y0_REGNUM),
1912      (long) get_frame_register_unsigned (frame, RS_REGNUM),
1913      (long) get_frame_register_unsigned (frame, MOD_REGNUM));
1914   printf_filtered
1915     ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1916      (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
1917      (long) get_frame_register_unsigned (frame, A1_REGNUM),
1918      (long) get_frame_register_unsigned (frame, M1_REGNUM),
1919      (long) get_frame_register_unsigned (frame, X1_REGNUM),
1920      (long) get_frame_register_unsigned (frame, Y1_REGNUM),
1921      (long) get_frame_register_unsigned (frame, RE_REGNUM));
1922 }
1923
1924 static void
1925 sh4_show_regs (struct frame_info *frame)
1926 {
1927   struct gdbarch *gdbarch = get_frame_arch (frame);
1928   int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1929
1930   printf_filtered
1931     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
1932      paddr (get_frame_register_unsigned (frame,
1933                                          gdbarch_pc_regnum (gdbarch))),
1934      (long) get_frame_register_unsigned (frame, SR_REGNUM),
1935      (long) get_frame_register_unsigned (frame, PR_REGNUM),
1936      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1937
1938   printf_filtered
1939     ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
1940      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1941      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1942      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1943   printf_filtered
1944     ("     SSR %08lx      SPC %08lx     FPUL %08lx    FPSCR %08lx\n",
1945      (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1946      (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1947      (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1948      (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1949
1950   printf_filtered
1951     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1952      (long) get_frame_register_unsigned (frame, 0),
1953      (long) get_frame_register_unsigned (frame, 1),
1954      (long) get_frame_register_unsigned (frame, 2),
1955      (long) get_frame_register_unsigned (frame, 3),
1956      (long) get_frame_register_unsigned (frame, 4),
1957      (long) get_frame_register_unsigned (frame, 5),
1958      (long) get_frame_register_unsigned (frame, 6),
1959      (long) get_frame_register_unsigned (frame, 7));
1960   printf_filtered
1961     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1962      (long) get_frame_register_unsigned (frame, 8),
1963      (long) get_frame_register_unsigned (frame, 9),
1964      (long) get_frame_register_unsigned (frame, 10),
1965      (long) get_frame_register_unsigned (frame, 11),
1966      (long) get_frame_register_unsigned (frame, 12),
1967      (long) get_frame_register_unsigned (frame, 13),
1968      (long) get_frame_register_unsigned (frame, 14),
1969      (long) get_frame_register_unsigned (frame, 15));
1970
1971   printf_filtered
1972     (pr ? "DR0-DR6  %08lx%08lx  %08lx%08lx  %08lx%08lx  %08lx%08lx\n"
1973         : "FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1974      (long) get_frame_register_unsigned
1975               (frame, gdbarch_fp0_regnum (gdbarch) + 0),
1976      (long) get_frame_register_unsigned
1977               (frame, gdbarch_fp0_regnum (gdbarch) + 1),
1978      (long) get_frame_register_unsigned
1979               (frame, gdbarch_fp0_regnum (gdbarch) + 2),
1980      (long) get_frame_register_unsigned
1981               (frame, gdbarch_fp0_regnum (gdbarch) + 3),
1982      (long) get_frame_register_unsigned
1983               (frame, gdbarch_fp0_regnum (gdbarch) + 4),
1984      (long) get_frame_register_unsigned
1985               (frame, gdbarch_fp0_regnum (gdbarch) + 5),
1986      (long) get_frame_register_unsigned
1987               (frame, gdbarch_fp0_regnum (gdbarch) + 6),
1988      (long) get_frame_register_unsigned
1989               (frame, gdbarch_fp0_regnum (gdbarch) + 7));
1990   printf_filtered
1991     (pr ? "DR8-DR14 %08lx%08lx  %08lx%08lx  %08lx%08lx  %08lx%08lx\n"
1992         : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1993      (long) get_frame_register_unsigned
1994               (frame, gdbarch_fp0_regnum (gdbarch) + 8),
1995      (long) get_frame_register_unsigned
1996               (frame, gdbarch_fp0_regnum (gdbarch) + 9),
1997      (long) get_frame_register_unsigned
1998               (frame, gdbarch_fp0_regnum (gdbarch) + 10),
1999      (long) get_frame_register_unsigned
2000               (frame, gdbarch_fp0_regnum (gdbarch) + 11),
2001      (long) get_frame_register_unsigned
2002               (frame, gdbarch_fp0_regnum (gdbarch) + 12),
2003      (long) get_frame_register_unsigned
2004               (frame, gdbarch_fp0_regnum (gdbarch) + 13),
2005      (long) get_frame_register_unsigned
2006               (frame, gdbarch_fp0_regnum (gdbarch) + 14),
2007      (long) get_frame_register_unsigned
2008               (frame, gdbarch_fp0_regnum (gdbarch) + 15));
2009 }
2010
2011 static void
2012 sh4_nofpu_show_regs (struct frame_info *frame)
2013 {
2014   printf_filtered
2015     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
2016      paddr (get_frame_register_unsigned (frame,
2017                                          gdbarch_pc_regnum
2018                                            (get_frame_arch (frame)))),
2019      (long) get_frame_register_unsigned (frame, SR_REGNUM),
2020      (long) get_frame_register_unsigned (frame, PR_REGNUM),
2021      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
2022
2023   printf_filtered
2024     ("     GBR %08lx      VBR %08lx                       MACL %08lx\n",
2025      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
2026      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
2027      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
2028   printf_filtered
2029     ("     SSR %08lx      SPC %08lx     FPUL %08lx    FPSCR %08lx\n",
2030      (long) get_frame_register_unsigned (frame, SSR_REGNUM),
2031      (long) get_frame_register_unsigned (frame, SPC_REGNUM),
2032      (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
2033      (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
2034
2035   printf_filtered
2036     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2037      (long) get_frame_register_unsigned (frame, 0),
2038      (long) get_frame_register_unsigned (frame, 1),
2039      (long) get_frame_register_unsigned (frame, 2),
2040      (long) get_frame_register_unsigned (frame, 3),
2041      (long) get_frame_register_unsigned (frame, 4),
2042      (long) get_frame_register_unsigned (frame, 5),
2043      (long) get_frame_register_unsigned (frame, 6),
2044      (long) get_frame_register_unsigned (frame, 7));
2045   printf_filtered
2046     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2047      (long) get_frame_register_unsigned (frame, 8),
2048      (long) get_frame_register_unsigned (frame, 9),
2049      (long) get_frame_register_unsigned (frame, 10),
2050      (long) get_frame_register_unsigned (frame, 11),
2051      (long) get_frame_register_unsigned (frame, 12),
2052      (long) get_frame_register_unsigned (frame, 13),
2053      (long) get_frame_register_unsigned (frame, 14),
2054      (long) get_frame_register_unsigned (frame, 15));
2055 }
2056
2057 static void
2058 sh_dsp_show_regs (struct frame_info *frame)
2059 {
2060   printf_filtered
2061     ("      PC %s       SR %08lx       PR %08lx     MACH %08lx\n",
2062      paddr (get_frame_register_unsigned (frame,
2063                                          gdbarch_pc_regnum
2064                                            (get_frame_arch (frame)))),
2065      (long) get_frame_register_unsigned (frame, SR_REGNUM),
2066      (long) get_frame_register_unsigned (frame, PR_REGNUM),
2067      (long) get_frame_register_unsigned (frame, MACH_REGNUM));
2068
2069   printf_filtered
2070     ("     GBR %08lx      VBR %08lx      DSR %08lx     MACL %08lx\n",
2071      (long) get_frame_register_unsigned (frame, GBR_REGNUM),
2072      (long) get_frame_register_unsigned (frame, VBR_REGNUM),
2073      (long) get_frame_register_unsigned (frame, DSR_REGNUM),
2074      (long) get_frame_register_unsigned (frame, MACL_REGNUM));
2075
2076   printf_filtered
2077     ("R0-R7    %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2078      (long) get_frame_register_unsigned (frame, 0),
2079      (long) get_frame_register_unsigned (frame, 1),
2080      (long) get_frame_register_unsigned (frame, 2),
2081      (long) get_frame_register_unsigned (frame, 3),
2082      (long) get_frame_register_unsigned (frame, 4),
2083      (long) get_frame_register_unsigned (frame, 5),
2084      (long) get_frame_register_unsigned (frame, 6),
2085      (long) get_frame_register_unsigned (frame, 7));
2086   printf_filtered
2087     ("R8-R15   %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2088      (long) get_frame_register_unsigned (frame, 8),
2089      (long) get_frame_register_unsigned (frame, 9),
2090      (long) get_frame_register_unsigned (frame, 10),
2091      (long) get_frame_register_unsigned (frame, 11),
2092      (long) get_frame_register_unsigned (frame, 12),
2093      (long) get_frame_register_unsigned (frame, 13),
2094      (long) get_frame_register_unsigned (frame, 14),
2095      (long) get_frame_register_unsigned (frame, 15));
2096
2097   printf_filtered
2098     ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2099      (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
2100      (long) get_frame_register_unsigned (frame, A0_REGNUM),
2101      (long) get_frame_register_unsigned (frame, M0_REGNUM),
2102      (long) get_frame_register_unsigned (frame, X0_REGNUM),
2103      (long) get_frame_register_unsigned (frame, Y0_REGNUM),
2104      (long) get_frame_register_unsigned (frame, RS_REGNUM),
2105      (long) get_frame_register_unsigned (frame, MOD_REGNUM));
2106   printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2107      (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
2108      (long) get_frame_register_unsigned (frame, A1_REGNUM),
2109      (long) get_frame_register_unsigned (frame, M1_REGNUM),
2110      (long) get_frame_register_unsigned (frame, X1_REGNUM),
2111      (long) get_frame_register_unsigned (frame, Y1_REGNUM),
2112      (long) get_frame_register_unsigned (frame, RE_REGNUM));
2113 }
2114
2115 static void
2116 sh_show_regs_command (char *args, int from_tty)
2117 {
2118   if (sh_show_regs)
2119     (*sh_show_regs) (get_current_frame ());
2120 }
2121
2122 static struct type *
2123 sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr)
2124 {
2125   if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
2126        && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2127     return builtin_type_float;
2128   else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2129     return builtin_type_double;
2130   else
2131     return builtin_type_int;
2132 }
2133
2134 /* Return the GDB type object for the "standard" data type
2135    of data in register N.  */
2136 static struct type *
2137 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
2138 {
2139   if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
2140        && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2141     return builtin_type_float;
2142   else
2143     return builtin_type_int;
2144 }
2145
2146 static struct type *
2147 sh_sh4_build_float_register_type (int high)
2148 {
2149   struct type *temp;
2150
2151   temp = create_range_type (NULL, builtin_type_int, 0, high);
2152   return create_array_type (NULL, builtin_type_float, temp);
2153 }
2154
2155 static struct type *
2156 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
2157 {
2158   if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
2159        && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2160     return builtin_type_float;
2161   else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2162     return builtin_type_double;
2163   else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2164     return sh_sh4_build_float_register_type (3);
2165   else
2166     return builtin_type_int;
2167 }
2168
2169 static struct type *
2170 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
2171 {
2172   return builtin_type_int;
2173 }
2174
2175 /* Is a register in a reggroup?
2176    The default code in reggroup.c doesn't identify system registers, some
2177    float registers or any of the vector registers.
2178    TODO: sh2a and dsp registers.  */
2179 int
2180 sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2181                         struct reggroup *reggroup)
2182 {
2183   if (gdbarch_register_name (gdbarch, regnum) == NULL
2184       || *gdbarch_register_name (gdbarch, regnum) == '\0')
2185     return 0;
2186
2187   if (reggroup == float_reggroup
2188       && (regnum == FPUL_REGNUM
2189           || regnum == FPSCR_REGNUM))
2190     return 1;
2191
2192   if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
2193     {
2194       if (reggroup == vector_reggroup || reggroup == float_reggroup)
2195         return 1;
2196       if (reggroup == general_reggroup)
2197         return 0;
2198     }
2199
2200   if (regnum == VBR_REGNUM
2201       || regnum == SR_REGNUM
2202       || regnum == FPSCR_REGNUM
2203       || regnum == SSR_REGNUM
2204       || regnum == SPC_REGNUM)
2205     {
2206       if (reggroup == system_reggroup)
2207         return 1;
2208       if (reggroup == general_reggroup)
2209         return 0;
2210     }
2211
2212   /* The default code can cope with any other registers.  */
2213   return default_register_reggroup_p (gdbarch, regnum, reggroup);
2214 }
2215
2216 /* On the sh4, the DRi pseudo registers are problematic if the target
2217    is little endian. When the user writes one of those registers, for
2218    instance with 'ser var $dr0=1', we want the double to be stored
2219    like this:
2220    fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2221    fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2222
2223    This corresponds to little endian byte order & big endian word
2224    order.  However if we let gdb write the register w/o conversion, it
2225    will write fr0 and fr1 this way:
2226    fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2227    fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2228    because it will consider fr0 and fr1 as a single LE stretch of memory.
2229
2230    To achieve what we want we must force gdb to store things in
2231    floatformat_ieee_double_littlebyte_bigword (which is defined in
2232    include/floatformat.h and libiberty/floatformat.c.
2233
2234    In case the target is big endian, there is no problem, the
2235    raw bytes will look like:
2236    fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
2237    fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2238
2239    The other pseudo registers (the FVs) also don't pose a problem
2240    because they are stored as 4 individual FP elements. */
2241
2242 static void
2243 sh_register_convert_to_virtual (int regnum, struct type *type,
2244                                 char *from, char *to)
2245 {
2246   if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
2247     {
2248       DOUBLEST val;
2249       floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2250                                from, &val);
2251       store_typed_floating (to, type, val);
2252     }
2253   else
2254     error
2255       ("sh_register_convert_to_virtual called with non DR register number");
2256 }
2257
2258 static void
2259 sh_register_convert_to_raw (struct type *type, int regnum,
2260                             const void *from, void *to)
2261 {
2262   if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
2263     {
2264       DOUBLEST val = extract_typed_floating (from, type);
2265       floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
2266                                  &val, to);
2267     }
2268   else
2269     error (_("sh_register_convert_to_raw called with non DR register number"));
2270 }
2271
2272 /* For vectors of 4 floating point registers. */
2273 static int
2274 fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum)
2275 {
2276   int fp_regnum;
2277
2278   fp_regnum = gdbarch_fp0_regnum (gdbarch)
2279               + (fv_regnum - FV0_REGNUM) * 4;
2280   return fp_regnum;
2281 }
2282
2283 /* For double precision floating point registers, i.e 2 fp regs.*/
2284 static int
2285 dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum)
2286 {
2287   int fp_regnum;
2288
2289   fp_regnum = gdbarch_fp0_regnum (gdbarch)
2290               + (dr_regnum - DR0_REGNUM) * 2;
2291   return fp_regnum;
2292 }
2293
2294 static void
2295 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2296                          int reg_nr, gdb_byte *buffer)
2297 {
2298   int base_regnum, portion;
2299   char temp_buffer[MAX_REGISTER_SIZE];
2300
2301   if (reg_nr == PSEUDO_BANK_REGNUM)
2302     regcache_raw_read (regcache, BANK_REGNUM, buffer);
2303   else
2304   if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2305     {
2306       base_regnum = dr_reg_base_num (gdbarch, reg_nr);
2307
2308       /* Build the value in the provided buffer. */
2309       /* Read the real regs for which this one is an alias.  */
2310       for (portion = 0; portion < 2; portion++)
2311         regcache_raw_read (regcache, base_regnum + portion,
2312                            (temp_buffer
2313                             + register_size (gdbarch,
2314                                              base_regnum) * portion));
2315       /* We must pay attention to the endiannes. */
2316       sh_register_convert_to_virtual (reg_nr,
2317                                       register_type (gdbarch, reg_nr),
2318                                       temp_buffer, buffer);
2319     }
2320   else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2321     {
2322       base_regnum = fv_reg_base_num (gdbarch, reg_nr);
2323
2324       /* Read the real regs for which this one is an alias.  */
2325       for (portion = 0; portion < 4; portion++)
2326         regcache_raw_read (regcache, base_regnum + portion,
2327                            ((char *) buffer
2328                             + register_size (gdbarch,
2329                                              base_regnum) * portion));
2330     }
2331 }
2332
2333 static void
2334 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2335                           int reg_nr, const gdb_byte *buffer)
2336 {
2337   int base_regnum, portion;
2338   char temp_buffer[MAX_REGISTER_SIZE];
2339
2340   if (reg_nr == PSEUDO_BANK_REGNUM)
2341     {
2342       /* When the bank register is written to, the whole register bank
2343          is switched and all values in the bank registers must be read
2344          from the target/sim again. We're just invalidating the regcache
2345          so that a re-read happens next time it's necessary.  */
2346       int bregnum;
2347
2348       regcache_raw_write (regcache, BANK_REGNUM, buffer);
2349       for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum)
2350         regcache_invalidate (regcache, bregnum);
2351     }
2352   else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2353     {
2354       base_regnum = dr_reg_base_num (gdbarch, reg_nr);
2355
2356       /* We must pay attention to the endiannes. */
2357       sh_register_convert_to_raw (register_type (gdbarch, reg_nr),
2358                                   reg_nr, buffer, temp_buffer);
2359
2360       /* Write the real regs for which this one is an alias.  */
2361       for (portion = 0; portion < 2; portion++)
2362         regcache_raw_write (regcache, base_regnum + portion,
2363                             (temp_buffer
2364                              + register_size (gdbarch,
2365                                               base_regnum) * portion));
2366     }
2367   else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2368     {
2369       base_regnum = fv_reg_base_num (gdbarch, reg_nr);
2370
2371       /* Write the real regs for which this one is an alias.  */
2372       for (portion = 0; portion < 4; portion++)
2373         regcache_raw_write (regcache, base_regnum + portion,
2374                             ((char *) buffer
2375                              + register_size (gdbarch,
2376                                               base_regnum) * portion));
2377     }
2378 }
2379
2380 static int
2381 sh_dsp_register_sim_regno (struct gdbarch *gdbarch, int nr)
2382 {
2383   if (legacy_register_sim_regno (gdbarch, nr) < 0)
2384     return legacy_register_sim_regno (gdbarch, nr);
2385   if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
2386     return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
2387   if (nr == MOD_REGNUM)
2388     return SIM_SH_MOD_REGNUM;
2389   if (nr == RS_REGNUM)
2390     return SIM_SH_RS_REGNUM;
2391   if (nr == RE_REGNUM)
2392     return SIM_SH_RE_REGNUM;
2393   if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
2394     return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
2395   return nr;
2396 }
2397
2398 static int
2399 sh_sh2a_register_sim_regno (struct gdbarch *gdbarch, int nr)
2400 {
2401   switch (nr)
2402     {
2403       case TBR_REGNUM:
2404         return SIM_SH_TBR_REGNUM;
2405       case IBNR_REGNUM:
2406         return SIM_SH_IBNR_REGNUM;
2407       case IBCR_REGNUM:
2408         return SIM_SH_IBCR_REGNUM;
2409       case BANK_REGNUM:
2410         return SIM_SH_BANK_REGNUM;
2411       case MACLB_REGNUM:
2412         return SIM_SH_BANK_MACL_REGNUM;
2413       case GBRB_REGNUM:
2414         return SIM_SH_BANK_GBR_REGNUM;
2415       case PRB_REGNUM:
2416         return SIM_SH_BANK_PR_REGNUM;
2417       case IVNB_REGNUM:
2418         return SIM_SH_BANK_IVN_REGNUM;
2419       case MACHB_REGNUM:
2420         return SIM_SH_BANK_MACH_REGNUM;
2421       default:
2422         break;
2423     }
2424   return legacy_register_sim_regno (gdbarch, nr);
2425 }
2426
2427 /* Set up the register unwinding such that call-clobbered registers are
2428    not displayed in frames >0 because the true value is not certain.
2429    The 'undefined' registers will show up as 'not available' unless the
2430    CFI says otherwise.
2431
2432    This function is currently set up for SH4 and compatible only.  */
2433
2434 static void
2435 sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
2436                           struct dwarf2_frame_state_reg *reg,
2437                           struct frame_info *this_frame)
2438 {
2439   /* Mark the PC as the destination for the return address.  */
2440   if (regnum == gdbarch_pc_regnum (gdbarch))
2441     reg->how = DWARF2_FRAME_REG_RA;
2442
2443   /* Mark the stack pointer as the call frame address.  */
2444   else if (regnum == gdbarch_sp_regnum (gdbarch))
2445     reg->how = DWARF2_FRAME_REG_CFA;
2446
2447   /* The above was taken from the default init_reg in dwarf2-frame.c
2448      while the below is SH specific.  */
2449
2450   /* Caller save registers.  */
2451   else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7)
2452            || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11)
2453            || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5)
2454            || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2)
2455            || (regnum == MACH_REGNUM)
2456            || (regnum == MACL_REGNUM)
2457            || (regnum == FPUL_REGNUM)
2458            || (regnum == SR_REGNUM))
2459     reg->how = DWARF2_FRAME_REG_UNDEFINED;
2460
2461   /* Callee save registers.  */
2462   else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15)
2463            || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15)
2464            || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8)
2465            || (regnum == FV0_REGNUM+3))
2466     reg->how = DWARF2_FRAME_REG_SAME_VALUE;
2467
2468   /* Other registers.  These are not in the ABI and may or may not
2469      mean anything in frames >0 so don't show them.  */
2470   else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15)
2471            || (regnum == GBR_REGNUM)
2472            || (regnum == VBR_REGNUM)
2473            || (regnum == FPSCR_REGNUM)
2474            || (regnum == SSR_REGNUM)
2475            || (regnum == SPC_REGNUM))
2476     reg->how = DWARF2_FRAME_REG_UNDEFINED;
2477 }
2478
2479 static struct sh_frame_cache *
2480 sh_alloc_frame_cache (void)
2481 {
2482   struct sh_frame_cache *cache;
2483   int i;
2484
2485   cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
2486
2487   /* Base address.  */
2488   cache->base = 0;
2489   cache->saved_sp = 0;
2490   cache->sp_offset = 0;
2491   cache->pc = 0;
2492
2493   /* Frameless until proven otherwise.  */
2494   cache->uses_fp = 0;
2495
2496   /* Saved registers.  We initialize these to -1 since zero is a valid
2497      offset (that's where fp is supposed to be stored).  */
2498   for (i = 0; i < SH_NUM_REGS; i++)
2499     {
2500       cache->saved_regs[i] = -1;
2501     }
2502
2503   return cache;
2504 }
2505
2506 static struct sh_frame_cache *
2507 sh_frame_cache (struct frame_info *this_frame, void **this_cache)
2508 {
2509   struct sh_frame_cache *cache;
2510   CORE_ADDR current_pc;
2511   int i;
2512
2513   if (*this_cache)
2514     return *this_cache;
2515
2516   cache = sh_alloc_frame_cache ();
2517   *this_cache = cache;
2518
2519   /* In principle, for normal frames, fp holds the frame pointer,
2520      which holds the base address for the current stack frame.
2521      However, for functions that don't need it, the frame pointer is
2522      optional.  For these "frameless" functions the frame pointer is
2523      actually the frame pointer of the calling frame. */
2524   cache->base = get_frame_register_unsigned (this_frame, FP_REGNUM);
2525   if (cache->base == 0)
2526     return cache;
2527
2528   cache->pc = get_frame_func (this_frame);
2529   current_pc = get_frame_pc (this_frame);
2530   if (cache->pc != 0)
2531     {
2532       ULONGEST fpscr;
2533       fpscr = get_frame_register_unsigned (this_frame, FPSCR_REGNUM);
2534       sh_analyze_prologue (cache->pc, current_pc, cache, fpscr);
2535     }
2536
2537   if (!cache->uses_fp)
2538     {
2539       /* We didn't find a valid frame, which means that CACHE->base
2540          currently holds the frame pointer for our calling frame.  If
2541          we're at the start of a function, or somewhere half-way its
2542          prologue, the function's frame probably hasn't been fully
2543          setup yet.  Try to reconstruct the base address for the stack
2544          frame by looking at the stack pointer.  For truly "frameless"
2545          functions this might work too.  */
2546       cache->base = get_frame_register_unsigned
2547                     (this_frame,
2548                      gdbarch_sp_regnum (get_frame_arch (this_frame)));
2549     }
2550
2551   /* Now that we have the base address for the stack frame we can
2552      calculate the value of sp in the calling frame.  */
2553   cache->saved_sp = cache->base + cache->sp_offset;
2554
2555   /* Adjust all the saved registers such that they contain addresses
2556      instead of offsets.  */
2557   for (i = 0; i < SH_NUM_REGS; i++)
2558     if (cache->saved_regs[i] != -1)
2559       cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
2560
2561   return cache;
2562 }
2563
2564 static struct value *
2565 sh_frame_prev_register (struct frame_info *this_frame,
2566                         void **this_cache, int regnum)
2567 {
2568   struct gdbarch *gdbarch = get_frame_arch (this_frame);
2569   struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
2570
2571   gdb_assert (regnum >= 0);
2572
2573   if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
2574     return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
2575
2576   /* The PC of the previous frame is stored in the PR register of
2577      the current frame.  Frob regnum so that we pull the value from
2578      the correct place.  */
2579   if (regnum == gdbarch_pc_regnum (gdbarch))
2580     regnum = PR_REGNUM;
2581
2582   if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
2583     return frame_unwind_got_memory (this_frame, regnum,
2584                                     cache->saved_regs[regnum]);
2585
2586   return frame_unwind_got_register (this_frame, regnum, regnum);
2587 }
2588
2589 static void
2590 sh_frame_this_id (struct frame_info *this_frame, void **this_cache,
2591                   struct frame_id *this_id)
2592 {
2593   struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
2594
2595   /* This marks the outermost frame.  */
2596   if (cache->base == 0)
2597     return;
2598
2599   *this_id = frame_id_build (cache->saved_sp, cache->pc);
2600 }
2601
2602 static const struct frame_unwind sh_frame_unwind = {
2603   NORMAL_FRAME,
2604   sh_frame_this_id,
2605   sh_frame_prev_register,
2606   NULL,
2607   default_frame_sniffer
2608 };
2609
2610 static CORE_ADDR
2611 sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2612 {
2613   return frame_unwind_register_unsigned (next_frame,
2614                                          gdbarch_sp_regnum (gdbarch));
2615 }
2616
2617 static CORE_ADDR
2618 sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2619 {
2620   return frame_unwind_register_unsigned (next_frame,
2621                                          gdbarch_pc_regnum (gdbarch));
2622 }
2623
2624 static struct frame_id
2625 sh_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2626 {
2627   CORE_ADDR sp = get_frame_register_unsigned (this_frame,
2628                                               gdbarch_sp_regnum (gdbarch));
2629   return frame_id_build (sp, get_frame_pc (this_frame));
2630 }
2631
2632 static CORE_ADDR
2633 sh_frame_base_address (struct frame_info *this_frame, void **this_cache)
2634 {
2635   struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
2636
2637   return cache->base;
2638 }
2639
2640 static const struct frame_base sh_frame_base = {
2641   &sh_frame_unwind,
2642   sh_frame_base_address,
2643   sh_frame_base_address,
2644   sh_frame_base_address
2645 };
2646
2647 /* The epilogue is defined here as the area at the end of a function,
2648    either on the `ret' instruction itself or after an instruction which
2649    destroys the function's stack frame. */
2650 static int
2651 sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2652 {
2653   CORE_ADDR func_addr = 0, func_end = 0;
2654
2655   if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2656     {
2657       ULONGEST inst;
2658       /* The sh epilogue is max. 14 bytes long.  Give another 14 bytes
2659          for a nop and some fixed data (e.g. big offsets) which are
2660          unfortunately also treated as part of the function (which
2661          means, they are below func_end. */
2662       CORE_ADDR addr = func_end - 28;
2663       if (addr < func_addr + 4)
2664         addr = func_addr + 4;
2665       if (pc < addr)
2666         return 0;
2667
2668       /* First search forward until hitting an rts. */
2669       while (addr < func_end
2670              && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
2671         addr += 2;
2672       if (addr >= func_end)
2673         return 0;
2674
2675       /* At this point we should find a mov.l @r15+,r14 instruction,
2676          either before or after the rts.  If not, then the function has
2677          probably no "normal" epilogue and we bail out here. */
2678       inst = read_memory_unsigned_integer (addr - 2, 2);
2679       if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
2680         addr -= 2;
2681       else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
2682         return 0;
2683
2684       inst = read_memory_unsigned_integer (addr - 2, 2);
2685
2686       /* Step over possible lds.l @r15+,macl. */
2687       if (IS_MACL_LDS (inst))
2688         {
2689           addr -= 2;
2690           inst = read_memory_unsigned_integer (addr - 2, 2);
2691         }
2692
2693       /* Step over possible lds.l @r15+,pr. */
2694       if (IS_LDS (inst))
2695         {
2696           addr -= 2;
2697           inst = read_memory_unsigned_integer (addr - 2, 2);
2698         }
2699
2700       /* Step over possible mov r14,r15. */
2701       if (IS_MOV_FP_SP (inst))
2702         {
2703           addr -= 2;
2704           inst = read_memory_unsigned_integer (addr - 2, 2);
2705         }
2706
2707       /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2708          instructions. */
2709       while (addr > func_addr + 4
2710              && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
2711         {
2712           addr -= 2;
2713           inst = read_memory_unsigned_integer (addr - 2, 2);
2714         }
2715
2716       /* On SH2a check if the previous instruction was perhaps a MOVI20.
2717          That's allowed for the epilogue.  */
2718       if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a
2719            || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu)
2720           && addr > func_addr + 6
2721           && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2)))
2722         addr -= 4;
2723
2724       if (pc >= addr)
2725         return 1;
2726     }
2727   return 0;
2728 }
2729 \f
2730
2731 static struct gdbarch *
2732 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2733 {
2734   struct gdbarch *gdbarch;
2735
2736   sh_show_regs = sh_generic_show_regs;
2737   switch (info.bfd_arch_info->mach)
2738     {
2739     case bfd_mach_sh2e:
2740       sh_show_regs = sh2e_show_regs;
2741       break;
2742     case bfd_mach_sh2a:
2743       sh_show_regs = sh2a_show_regs;
2744       break;
2745     case bfd_mach_sh2a_nofpu:
2746       sh_show_regs = sh2a_nofpu_show_regs;
2747       break;
2748     case bfd_mach_sh_dsp:
2749       sh_show_regs = sh_dsp_show_regs;
2750       break;
2751
2752     case bfd_mach_sh3:
2753       sh_show_regs = sh3_show_regs;
2754       break;
2755
2756     case bfd_mach_sh3e:
2757       sh_show_regs = sh3e_show_regs;
2758       break;
2759
2760     case bfd_mach_sh3_dsp:
2761     case bfd_mach_sh4al_dsp:
2762       sh_show_regs = sh3_dsp_show_regs;
2763       break;
2764
2765     case bfd_mach_sh4:
2766     case bfd_mach_sh4a:
2767       sh_show_regs = sh4_show_regs;
2768       break;
2769
2770     case bfd_mach_sh4_nofpu:
2771     case bfd_mach_sh4a_nofpu:
2772       sh_show_regs = sh4_nofpu_show_regs;
2773       break;
2774
2775     case bfd_mach_sh5:
2776       sh_show_regs = sh64_show_regs;
2777       /* SH5 is handled entirely in sh64-tdep.c */
2778       return sh64_gdbarch_init (info, arches);
2779     }
2780
2781   /* If there is already a candidate, use it.  */
2782   arches = gdbarch_list_lookup_by_info (arches, &info);
2783   if (arches != NULL)
2784     return arches->gdbarch;
2785
2786   /* None found, create a new architecture from the information
2787      provided. */
2788   gdbarch = gdbarch_alloc (&info, NULL);
2789
2790   set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2791   set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2792   set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2793   set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2794   set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2795   set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2796   set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2797   set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2798
2799   set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
2800   set_gdbarch_sp_regnum (gdbarch, 15);
2801   set_gdbarch_pc_regnum (gdbarch, 16);
2802   set_gdbarch_fp0_regnum (gdbarch, -1);
2803   set_gdbarch_num_pseudo_regs (gdbarch, 0);
2804
2805   set_gdbarch_register_type (gdbarch, sh_default_register_type);
2806   set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p);
2807
2808   set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2809
2810   set_gdbarch_print_insn (gdbarch, print_insn_sh);
2811   set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2812
2813   set_gdbarch_return_value (gdbarch, sh_return_value_nofpu);
2814
2815   set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2816   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2817
2818   set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2819
2820   set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2821
2822   set_gdbarch_frame_align (gdbarch, sh_frame_align);
2823   set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2824   set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2825   set_gdbarch_dummy_id (gdbarch, sh_dummy_id);
2826   frame_base_set_default (gdbarch, &sh_frame_base);
2827
2828   set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
2829
2830   dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg);
2831
2832   switch (info.bfd_arch_info->mach)
2833     {
2834     case bfd_mach_sh:
2835       set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2836       break;
2837
2838     case bfd_mach_sh2:
2839       set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2840       break;
2841
2842     case bfd_mach_sh2e:
2843       /* doubles on sh2e and sh3e are actually 4 byte. */
2844       set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2845
2846       set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
2847       set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2848       set_gdbarch_fp0_regnum (gdbarch, 25);
2849       set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2850       set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2851       break;
2852
2853     case bfd_mach_sh2a:
2854       set_gdbarch_register_name (gdbarch, sh_sh2a_register_name);
2855       set_gdbarch_register_type (gdbarch, sh_sh2a_register_type);
2856       set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2857
2858       set_gdbarch_fp0_regnum (gdbarch, 25);
2859       set_gdbarch_num_pseudo_regs (gdbarch, 9);
2860       set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2861       set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2862       set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2863       set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2864       break;
2865
2866     case bfd_mach_sh2a_nofpu:
2867       set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name);
2868       set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2869
2870       set_gdbarch_num_pseudo_regs (gdbarch, 1);
2871       set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2872       set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2873       break;
2874
2875     case bfd_mach_sh_dsp:
2876       set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2877       set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2878       break;
2879
2880     case bfd_mach_sh3:
2881     case bfd_mach_sh3_nommu:
2882     case bfd_mach_sh2a_nofpu_or_sh3_nommu:
2883       set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
2884       break;
2885
2886     case bfd_mach_sh3e:
2887     case bfd_mach_sh2a_or_sh3e:
2888       /* doubles on sh2e and sh3e are actually 4 byte. */
2889       set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2890
2891       set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
2892       set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2893       set_gdbarch_fp0_regnum (gdbarch, 25);
2894       set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2895       set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2896       break;
2897
2898     case bfd_mach_sh3_dsp:
2899       set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
2900       set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2901       break;
2902
2903     case bfd_mach_sh4:
2904     case bfd_mach_sh4a:
2905       set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
2906       set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
2907       set_gdbarch_fp0_regnum (gdbarch, 25);
2908       set_gdbarch_num_pseudo_regs (gdbarch, 13);
2909       set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2910       set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2911       set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2912       set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2913       break;
2914
2915     case bfd_mach_sh4_nofpu:
2916     case bfd_mach_sh4a_nofpu:
2917     case bfd_mach_sh4_nommu_nofpu:
2918     case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
2919     case bfd_mach_sh2a_or_sh4:
2920       set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
2921       break;
2922
2923     case bfd_mach_sh4al_dsp:
2924       set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
2925       set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2926       break;
2927
2928     default:
2929       set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2930       break;
2931     }
2932
2933   /* Hook in ABI-specific overrides, if they have been registered.  */
2934   gdbarch_init_osabi (info, gdbarch);
2935
2936   dwarf2_append_unwinders (gdbarch);
2937   frame_unwind_append_unwinder (gdbarch, &sh_frame_unwind);
2938
2939   return gdbarch;
2940 }
2941
2942 static void
2943 show_sh_command (char *args, int from_tty)
2944 {
2945   help_list (showshcmdlist, "show sh ", all_commands, gdb_stdout);
2946 }
2947
2948 static void
2949 set_sh_command (char *args, int from_tty)
2950 {
2951   printf_unfiltered
2952     ("\"set sh\" must be followed by an appropriate subcommand.\n");
2953   help_list (setshcmdlist, "set sh ", all_commands, gdb_stdout);
2954 }
2955
2956 extern initialize_file_ftype _initialize_sh_tdep;       /* -Wmissing-prototypes */
2957
2958 void
2959 _initialize_sh_tdep (void)
2960 {
2961   struct cmd_list_element *c;
2962
2963   gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
2964
2965   add_com ("regs", class_vars, sh_show_regs_command, _("Print all registers"));
2966
2967   add_prefix_cmd ("sh", no_class, set_sh_command, "SH specific commands.",
2968                   &setshcmdlist, "set sh ", 0, &setlist);
2969   add_prefix_cmd ("sh", no_class, show_sh_command, "SH specific commands.",
2970                   &showshcmdlist, "show sh ", 0, &showlist);
2971
2972   add_setshow_enum_cmd ("calling-convention", class_vars, sh_cc_enum,
2973                         &sh_active_calling_convention,
2974                         _("Set calling convention used when calling target "
2975                           "functions from GDB."),
2976                         _("Show calling convention used when calling target "
2977                           "functions from GDB."),
2978                         _("gcc       - Use GCC calling convention (default).\n"
2979                           "renesas   - Enforce Renesas calling convention."),
2980                         NULL, NULL,
2981                         &setshcmdlist, &showshcmdlist);
2982 }