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2007-10-08 Markus Deuling <deuling@de.ibm.com>
[deliverable/binutils-gdb.git] / gdb / sh-tdep.c
1 /* Target-dependent code for Renesas Super-H, for GDB.
2
3 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
4 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21 /*
22 Contributed by Steve Chamberlain
23 sac@cygnus.com
24 */
25
26 #include "defs.h"
27 #include "frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
30 #include "dwarf2-frame.h"
31 #include "symtab.h"
32 #include "gdbtypes.h"
33 #include "gdbcmd.h"
34 #include "gdbcore.h"
35 #include "value.h"
36 #include "dis-asm.h"
37 #include "inferior.h"
38 #include "gdb_string.h"
39 #include "gdb_assert.h"
40 #include "arch-utils.h"
41 #include "floatformat.h"
42 #include "regcache.h"
43 #include "doublest.h"
44 #include "osabi.h"
45 #include "reggroups.h"
46
47 #include "sh-tdep.h"
48
49 #include "elf-bfd.h"
50 #include "solib-svr4.h"
51
52 /* sh flags */
53 #include "elf/sh.h"
54 /* registers numbers shared with the simulator */
55 #include "gdb/sim-sh.h"
56
57 static void (*sh_show_regs) (struct frame_info *);
58
59 #define SH_NUM_REGS 67
60
61 struct sh_frame_cache
62 {
63 /* Base address. */
64 CORE_ADDR base;
65 LONGEST sp_offset;
66 CORE_ADDR pc;
67
68 /* Flag showing that a frame has been created in the prologue code. */
69 int uses_fp;
70
71 /* Saved registers. */
72 CORE_ADDR saved_regs[SH_NUM_REGS];
73 CORE_ADDR saved_sp;
74 };
75
76 static const char *
77 sh_sh_register_name (int reg_nr)
78 {
79 static char *register_names[] = {
80 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
81 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
82 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
83 "", "",
84 "", "", "", "", "", "", "", "",
85 "", "", "", "", "", "", "", "",
86 "", "",
87 "", "", "", "", "", "", "", "",
88 "", "", "", "", "", "", "", "",
89 "", "", "", "", "", "", "", "",
90 };
91 if (reg_nr < 0)
92 return NULL;
93 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
94 return NULL;
95 return register_names[reg_nr];
96 }
97
98 static const char *
99 sh_sh3_register_name (int reg_nr)
100 {
101 static char *register_names[] = {
102 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
103 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
104 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
105 "", "",
106 "", "", "", "", "", "", "", "",
107 "", "", "", "", "", "", "", "",
108 "ssr", "spc",
109 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
110 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
111 "", "", "", "", "", "", "", "",
112 };
113 if (reg_nr < 0)
114 return NULL;
115 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
116 return NULL;
117 return register_names[reg_nr];
118 }
119
120 static const char *
121 sh_sh3e_register_name (int reg_nr)
122 {
123 static char *register_names[] = {
124 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
125 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
126 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
127 "fpul", "fpscr",
128 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
129 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
130 "ssr", "spc",
131 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
132 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
133 "", "", "", "", "", "", "", "",
134 };
135 if (reg_nr < 0)
136 return NULL;
137 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
138 return NULL;
139 return register_names[reg_nr];
140 }
141
142 static const char *
143 sh_sh2e_register_name (int reg_nr)
144 {
145 static char *register_names[] = {
146 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
147 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
148 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
149 "fpul", "fpscr",
150 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
151 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
152 "", "",
153 "", "", "", "", "", "", "", "",
154 "", "", "", "", "", "", "", "",
155 "", "", "", "", "", "", "", "",
156 };
157 if (reg_nr < 0)
158 return NULL;
159 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
160 return NULL;
161 return register_names[reg_nr];
162 }
163
164 static const char *
165 sh_sh2a_register_name (int reg_nr)
166 {
167 static char *register_names[] = {
168 /* general registers 0-15 */
169 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
170 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
171 /* 16 - 22 */
172 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
173 /* 23, 24 */
174 "fpul", "fpscr",
175 /* floating point registers 25 - 40 */
176 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
177 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
178 /* 41, 42 */
179 "", "",
180 /* 43 - 62. Banked registers. The bank number used is determined by
181 the bank register (63). */
182 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
183 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
184 "machb", "ivnb", "prb", "gbrb", "maclb",
185 /* 63: register bank number, not a real register but used to
186 communicate the register bank currently get/set. This register
187 is hidden to the user, who manipulates it using the pseudo
188 register called "bank" (67). See below. */
189 "",
190 /* 64 - 66 */
191 "ibcr", "ibnr", "tbr",
192 /* 67: register bank number, the user visible pseudo register. */
193 "bank",
194 /* double precision (pseudo) 68 - 75 */
195 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
196 };
197 if (reg_nr < 0)
198 return NULL;
199 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
200 return NULL;
201 return register_names[reg_nr];
202 }
203
204 static const char *
205 sh_sh2a_nofpu_register_name (int reg_nr)
206 {
207 static char *register_names[] = {
208 /* general registers 0-15 */
209 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
210 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
211 /* 16 - 22 */
212 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
213 /* 23, 24 */
214 "", "",
215 /* floating point registers 25 - 40 */
216 "", "", "", "", "", "", "", "",
217 "", "", "", "", "", "", "", "",
218 /* 41, 42 */
219 "", "",
220 /* 43 - 62. Banked registers. The bank number used is determined by
221 the bank register (63). */
222 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
223 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
224 "machb", "ivnb", "prb", "gbrb", "maclb",
225 /* 63: register bank number, not a real register but used to
226 communicate the register bank currently get/set. This register
227 is hidden to the user, who manipulates it using the pseudo
228 register called "bank" (67). See below. */
229 "",
230 /* 64 - 66 */
231 "ibcr", "ibnr", "tbr",
232 /* 67: register bank number, the user visible pseudo register. */
233 "bank",
234 /* double precision (pseudo) 68 - 75 */
235 "", "", "", "", "", "", "", "",
236 };
237 if (reg_nr < 0)
238 return NULL;
239 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
240 return NULL;
241 return register_names[reg_nr];
242 }
243
244 static const char *
245 sh_sh_dsp_register_name (int reg_nr)
246 {
247 static char *register_names[] = {
248 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
249 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
250 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
251 "", "dsr",
252 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
253 "y0", "y1", "", "", "", "", "", "mod",
254 "", "",
255 "rs", "re", "", "", "", "", "", "",
256 "", "", "", "", "", "", "", "",
257 "", "", "", "", "", "", "", "",
258 };
259 if (reg_nr < 0)
260 return NULL;
261 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
262 return NULL;
263 return register_names[reg_nr];
264 }
265
266 static const char *
267 sh_sh3_dsp_register_name (int reg_nr)
268 {
269 static char *register_names[] = {
270 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
271 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
272 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
273 "", "dsr",
274 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
275 "y0", "y1", "", "", "", "", "", "mod",
276 "ssr", "spc",
277 "rs", "re", "", "", "", "", "", "",
278 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
279 "", "", "", "", "", "", "", "",
280 "", "", "", "", "", "", "", "",
281 };
282 if (reg_nr < 0)
283 return NULL;
284 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
285 return NULL;
286 return register_names[reg_nr];
287 }
288
289 static const char *
290 sh_sh4_register_name (int reg_nr)
291 {
292 static char *register_names[] = {
293 /* general registers 0-15 */
294 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
295 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
296 /* 16 - 22 */
297 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
298 /* 23, 24 */
299 "fpul", "fpscr",
300 /* floating point registers 25 - 40 */
301 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
302 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
303 /* 41, 42 */
304 "ssr", "spc",
305 /* bank 0 43 - 50 */
306 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
307 /* bank 1 51 - 58 */
308 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
309 "", "", "", "", "", "", "", "",
310 /* pseudo bank register. */
311 "",
312 /* double precision (pseudo) 59 - 66 */
313 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
314 /* vectors (pseudo) 67 - 70 */
315 "fv0", "fv4", "fv8", "fv12",
316 /* FIXME: missing XF 71 - 86 */
317 /* FIXME: missing XD 87 - 94 */
318 };
319 if (reg_nr < 0)
320 return NULL;
321 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
322 return NULL;
323 return register_names[reg_nr];
324 }
325
326 static const char *
327 sh_sh4_nofpu_register_name (int reg_nr)
328 {
329 static char *register_names[] = {
330 /* general registers 0-15 */
331 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
332 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
333 /* 16 - 22 */
334 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
335 /* 23, 24 */
336 "", "",
337 /* floating point registers 25 - 40 -- not for nofpu target */
338 "", "", "", "", "", "", "", "",
339 "", "", "", "", "", "", "", "",
340 /* 41, 42 */
341 "ssr", "spc",
342 /* bank 0 43 - 50 */
343 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
344 /* bank 1 51 - 58 */
345 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
346 "", "", "", "", "", "", "", "",
347 /* pseudo bank register. */
348 "",
349 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
350 "", "", "", "", "", "", "", "",
351 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
352 "", "", "", "",
353 };
354 if (reg_nr < 0)
355 return NULL;
356 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
357 return NULL;
358 return register_names[reg_nr];
359 }
360
361 static const char *
362 sh_sh4al_dsp_register_name (int reg_nr)
363 {
364 static char *register_names[] = {
365 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
366 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
367 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
368 "", "dsr",
369 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
370 "y0", "y1", "", "", "", "", "", "mod",
371 "ssr", "spc",
372 "rs", "re", "", "", "", "", "", "",
373 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
374 "", "", "", "", "", "", "", "",
375 "", "", "", "", "", "", "", "",
376 };
377 if (reg_nr < 0)
378 return NULL;
379 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
380 return NULL;
381 return register_names[reg_nr];
382 }
383
384 static const unsigned char *
385 sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
386 {
387 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
388 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
389
390 /* For remote stub targets, trapa #20 is used. */
391 if (strcmp (target_shortname, "remote") == 0)
392 {
393 static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 };
394 static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 };
395
396 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
397 {
398 *lenptr = sizeof (big_remote_breakpoint);
399 return big_remote_breakpoint;
400 }
401 else
402 {
403 *lenptr = sizeof (little_remote_breakpoint);
404 return little_remote_breakpoint;
405 }
406 }
407
408 *lenptr = sizeof (breakpoint);
409 return breakpoint;
410 }
411
412 /* Prologue looks like
413 mov.l r14,@-r15
414 sts.l pr,@-r15
415 mov.l <regs>,@-r15
416 sub <room_for_loca_vars>,r15
417 mov r15,r14
418
419 Actually it can be more complicated than this but that's it, basically.
420 */
421
422 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
423 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
424
425 /* JSR @Rm 0100mmmm00001011 */
426 #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
427
428 /* STS.L PR,@-r15 0100111100100010
429 r15-4-->r15, PR-->(r15) */
430 #define IS_STS(x) ((x) == 0x4f22)
431
432 /* STS.L MACL,@-r15 0100111100010010
433 r15-4-->r15, MACL-->(r15) */
434 #define IS_MACL_STS(x) ((x) == 0x4f12)
435
436 /* MOV.L Rm,@-r15 00101111mmmm0110
437 r15-4-->r15, Rm-->(R15) */
438 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
439
440 /* MOV r15,r14 0110111011110011
441 r15-->r14 */
442 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
443
444 /* ADD #imm,r15 01111111iiiiiiii
445 r15+imm-->r15 */
446 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
447
448 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
449 #define IS_SHLL_R3(x) ((x) == 0x4300)
450
451 /* ADD r3,r15 0011111100111100
452 r15+r3-->r15 */
453 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
454
455 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
456 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
457 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
458 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
459 make this entirely clear. */
460 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
461 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
462
463 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
464 #define IS_MOV_ARG_TO_REG(x) \
465 (((x) & 0xf00f) == 0x6003 && \
466 ((x) & 0x00f0) >= 0x0040 && \
467 ((x) & 0x00f0) <= 0x0070)
468 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
469 #define IS_MOV_ARG_TO_IND_R14(x) \
470 (((x) & 0xff0f) == 0x2e02 && \
471 ((x) & 0x00f0) >= 0x0040 && \
472 ((x) & 0x00f0) <= 0x0070)
473 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
474 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
475 (((x) & 0xff00) == 0x1e00 && \
476 ((x) & 0x00f0) >= 0x0040 && \
477 ((x) & 0x00f0) <= 0x0070)
478
479 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
480 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
481 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
482 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
483 /* MOVI20 #imm20,Rn 0000nnnniiii0000 */
484 #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
485 /* SUB Rn,R15 00111111nnnn1000 */
486 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
487
488 #define FPSCR_SZ (1 << 20)
489
490 /* The following instructions are used for epilogue testing. */
491 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
492 #define IS_RTS(x) ((x) == 0x000b)
493 #define IS_LDS(x) ((x) == 0x4f26)
494 #define IS_MACL_LDS(x) ((x) == 0x4f16)
495 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
496 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
497 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
498
499 /* Disassemble an instruction. */
500 static int
501 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info)
502 {
503 info->endian = gdbarch_byte_order (current_gdbarch);
504 return print_insn_sh (memaddr, info);
505 }
506
507 static CORE_ADDR
508 sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
509 struct sh_frame_cache *cache, ULONGEST fpscr)
510 {
511 ULONGEST inst;
512 CORE_ADDR opc;
513 int offset;
514 int sav_offset = 0;
515 int r3_val = 0;
516 int reg, sav_reg = -1;
517
518 if (pc >= current_pc)
519 return current_pc;
520
521 cache->uses_fp = 0;
522 for (opc = pc + (2 * 28); pc < opc; pc += 2)
523 {
524 inst = read_memory_unsigned_integer (pc, 2);
525 /* See where the registers will be saved to */
526 if (IS_PUSH (inst))
527 {
528 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
529 cache->sp_offset += 4;
530 }
531 else if (IS_STS (inst))
532 {
533 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
534 cache->sp_offset += 4;
535 }
536 else if (IS_MACL_STS (inst))
537 {
538 cache->saved_regs[MACL_REGNUM] = cache->sp_offset;
539 cache->sp_offset += 4;
540 }
541 else if (IS_MOV_R3 (inst))
542 {
543 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
544 }
545 else if (IS_SHLL_R3 (inst))
546 {
547 r3_val <<= 1;
548 }
549 else if (IS_ADD_R3SP (inst))
550 {
551 cache->sp_offset += -r3_val;
552 }
553 else if (IS_ADD_IMM_SP (inst))
554 {
555 offset = ((inst & 0xff) ^ 0x80) - 0x80;
556 cache->sp_offset -= offset;
557 }
558 else if (IS_MOVW_PCREL_TO_REG (inst))
559 {
560 if (sav_reg < 0)
561 {
562 reg = GET_TARGET_REG (inst);
563 if (reg < 14)
564 {
565 sav_reg = reg;
566 offset = (inst & 0xff) << 1;
567 sav_offset =
568 read_memory_integer ((pc + 4) + offset, 2);
569 }
570 }
571 }
572 else if (IS_MOVL_PCREL_TO_REG (inst))
573 {
574 if (sav_reg < 0)
575 {
576 reg = GET_TARGET_REG (inst);
577 if (reg < 14)
578 {
579 sav_reg = reg;
580 offset = (inst & 0xff) << 2;
581 sav_offset =
582 read_memory_integer (((pc & 0xfffffffc) + 4) + offset, 4);
583 }
584 }
585 }
586 else if (IS_MOVI20 (inst))
587 {
588 if (sav_reg < 0)
589 {
590 reg = GET_TARGET_REG (inst);
591 if (reg < 14)
592 {
593 sav_reg = reg;
594 sav_offset = GET_SOURCE_REG (inst) << 16;
595 /* MOVI20 is a 32 bit instruction! */
596 pc += 2;
597 sav_offset |= read_memory_unsigned_integer (pc, 2);
598 /* Now sav_offset contains an unsigned 20 bit value.
599 It must still get sign extended. */
600 if (sav_offset & 0x00080000)
601 sav_offset |= 0xfff00000;
602 }
603 }
604 }
605 else if (IS_SUB_REG_FROM_SP (inst))
606 {
607 reg = GET_SOURCE_REG (inst);
608 if (sav_reg > 0 && reg == sav_reg)
609 {
610 sav_reg = -1;
611 }
612 cache->sp_offset += sav_offset;
613 }
614 else if (IS_FPUSH (inst))
615 {
616 if (fpscr & FPSCR_SZ)
617 {
618 cache->sp_offset += 8;
619 }
620 else
621 {
622 cache->sp_offset += 4;
623 }
624 }
625 else if (IS_MOV_SP_FP (inst))
626 {
627 cache->uses_fp = 1;
628 /* At this point, only allow argument register moves to other
629 registers or argument register moves to @(X,fp) which are
630 moving the register arguments onto the stack area allocated
631 by a former add somenumber to SP call. Don't allow moving
632 to an fp indirect address above fp + cache->sp_offset. */
633 pc += 2;
634 for (opc = pc + 12; pc < opc; pc += 2)
635 {
636 inst = read_memory_integer (pc, 2);
637 if (IS_MOV_ARG_TO_IND_R14 (inst))
638 {
639 reg = GET_SOURCE_REG (inst);
640 if (cache->sp_offset > 0)
641 cache->saved_regs[reg] = cache->sp_offset;
642 }
643 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
644 {
645 reg = GET_SOURCE_REG (inst);
646 offset = (inst & 0xf) * 4;
647 if (cache->sp_offset > offset)
648 cache->saved_regs[reg] = cache->sp_offset - offset;
649 }
650 else if (IS_MOV_ARG_TO_REG (inst))
651 continue;
652 else
653 break;
654 }
655 break;
656 }
657 else if (IS_JSR (inst))
658 {
659 /* We have found a jsr that has been scheduled into the prologue.
660 If we continue the scan and return a pc someplace after this,
661 then setting a breakpoint on this function will cause it to
662 appear to be called after the function it is calling via the
663 jsr, which will be very confusing. Most likely the next
664 instruction is going to be IS_MOV_SP_FP in the delay slot. If
665 so, note that before returning the current pc. */
666 inst = read_memory_integer (pc + 2, 2);
667 if (IS_MOV_SP_FP (inst))
668 cache->uses_fp = 1;
669 break;
670 }
671 #if 0 /* This used to just stop when it found an instruction that
672 was not considered part of the prologue. Now, we just
673 keep going looking for likely instructions. */
674 else
675 break;
676 #endif
677 }
678
679 return pc;
680 }
681
682 /* Skip any prologue before the guts of a function */
683
684 /* Skip the prologue using the debug information. If this fails we'll
685 fall back on the 'guess' method below. */
686 static CORE_ADDR
687 after_prologue (CORE_ADDR pc)
688 {
689 struct symtab_and_line sal;
690 CORE_ADDR func_addr, func_end;
691
692 /* If we can not find the symbol in the partial symbol table, then
693 there is no hope we can determine the function's start address
694 with this code. */
695 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
696 return 0;
697
698 /* Get the line associated with FUNC_ADDR. */
699 sal = find_pc_line (func_addr, 0);
700
701 /* There are only two cases to consider. First, the end of the source line
702 is within the function bounds. In that case we return the end of the
703 source line. Second is the end of the source line extends beyond the
704 bounds of the current function. We need to use the slow code to
705 examine instructions in that case. */
706 if (sal.end < func_end)
707 return sal.end;
708 else
709 return 0;
710 }
711
712 static CORE_ADDR
713 sh_skip_prologue (CORE_ADDR start_pc)
714 {
715 CORE_ADDR pc;
716 struct sh_frame_cache cache;
717
718 /* See if we can determine the end of the prologue via the symbol table.
719 If so, then return either PC, or the PC after the prologue, whichever
720 is greater. */
721 pc = after_prologue (start_pc);
722
723 /* If after_prologue returned a useful address, then use it. Else
724 fall back on the instruction skipping code. */
725 if (pc)
726 return max (pc, start_pc);
727
728 cache.sp_offset = -4;
729 pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache, 0);
730 if (!cache.uses_fp)
731 return start_pc;
732
733 return pc;
734 }
735
736 /* The ABI says:
737
738 Aggregate types not bigger than 8 bytes that have the same size and
739 alignment as one of the integer scalar types are returned in the
740 same registers as the integer type they match.
741
742 For example, a 2-byte aligned structure with size 2 bytes has the
743 same size and alignment as a short int, and will be returned in R0.
744 A 4-byte aligned structure with size 8 bytes has the same size and
745 alignment as a long long int, and will be returned in R0 and R1.
746
747 When an aggregate type is returned in R0 and R1, R0 contains the
748 first four bytes of the aggregate, and R1 contains the
749 remainder. If the size of the aggregate type is not a multiple of 4
750 bytes, the aggregate is tail-padded up to a multiple of 4
751 bytes. The value of the padding is undefined. For little-endian
752 targets the padding will appear at the most significant end of the
753 last element, for big-endian targets the padding appears at the
754 least significant end of the last element.
755
756 All other aggregate types are returned by address. The caller
757 function passes the address of an area large enough to hold the
758 aggregate value in R2. The called function stores the result in
759 this location.
760
761 To reiterate, structs smaller than 8 bytes could also be returned
762 in memory, if they don't pass the "same size and alignment as an
763 integer type" rule.
764
765 For example, in
766
767 struct s { char c[3]; } wibble;
768 struct s foo(void) { return wibble; }
769
770 the return value from foo() will be in memory, not
771 in R0, because there is no 3-byte integer type.
772
773 Similarly, in
774
775 struct s { char c[2]; } wibble;
776 struct s foo(void) { return wibble; }
777
778 because a struct containing two chars has alignment 1, that matches
779 type char, but size 2, that matches type short. There's no integer
780 type that has alignment 1 and size 2, so the struct is returned in
781 memory.
782
783 */
784
785 static int
786 sh_use_struct_convention (int gcc_p, struct type *type)
787 {
788 int len = TYPE_LENGTH (type);
789 int nelem = TYPE_NFIELDS (type);
790
791 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
792 fit in two registers anyway) use struct convention. */
793 if (len != 1 && len != 2 && len != 4 && len != 8)
794 return 1;
795
796 /* Scalar types and aggregate types with exactly one field are aligned
797 by definition. They are returned in registers. */
798 if (nelem <= 1)
799 return 0;
800
801 /* If the first field in the aggregate has the same length as the entire
802 aggregate type, the type is returned in registers. */
803 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
804 return 0;
805
806 /* If the size of the aggregate is 8 bytes and the first field is
807 of size 4 bytes its alignment is equal to long long's alignment,
808 so it's returned in registers. */
809 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
810 return 0;
811
812 /* Otherwise use struct convention. */
813 return 1;
814 }
815
816 static CORE_ADDR
817 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
818 {
819 return sp & ~3;
820 }
821
822 /* Function: push_dummy_call (formerly push_arguments)
823 Setup the function arguments for calling a function in the inferior.
824
825 On the Renesas SH architecture, there are four registers (R4 to R7)
826 which are dedicated for passing function arguments. Up to the first
827 four arguments (depending on size) may go into these registers.
828 The rest go on the stack.
829
830 MVS: Except on SH variants that have floating point registers.
831 In that case, float and double arguments are passed in the same
832 manner, but using FP registers instead of GP registers.
833
834 Arguments that are smaller than 4 bytes will still take up a whole
835 register or a whole 32-bit word on the stack, and will be
836 right-justified in the register or the stack word. This includes
837 chars, shorts, and small aggregate types.
838
839 Arguments that are larger than 4 bytes may be split between two or
840 more registers. If there are not enough registers free, an argument
841 may be passed partly in a register (or registers), and partly on the
842 stack. This includes doubles, long longs, and larger aggregates.
843 As far as I know, there is no upper limit to the size of aggregates
844 that will be passed in this way; in other words, the convention of
845 passing a pointer to a large aggregate instead of a copy is not used.
846
847 MVS: The above appears to be true for the SH variants that do not
848 have an FPU, however those that have an FPU appear to copy the
849 aggregate argument onto the stack (and not place it in registers)
850 if it is larger than 16 bytes (four GP registers).
851
852 An exceptional case exists for struct arguments (and possibly other
853 aggregates such as arrays) if the size is larger than 4 bytes but
854 not a multiple of 4 bytes. In this case the argument is never split
855 between the registers and the stack, but instead is copied in its
856 entirety onto the stack, AND also copied into as many registers as
857 there is room for. In other words, space in registers permitting,
858 two copies of the same argument are passed in. As far as I can tell,
859 only the one on the stack is used, although that may be a function
860 of the level of compiler optimization. I suspect this is a compiler
861 bug. Arguments of these odd sizes are left-justified within the
862 word (as opposed to arguments smaller than 4 bytes, which are
863 right-justified).
864
865 If the function is to return an aggregate type such as a struct, it
866 is either returned in the normal return value register R0 (if its
867 size is no greater than one byte), or else the caller must allocate
868 space into which the callee will copy the return value (if the size
869 is greater than one byte). In this case, a pointer to the return
870 value location is passed into the callee in register R2, which does
871 not displace any of the other arguments passed in via registers R4
872 to R7. */
873
874 /* Helper function to justify value in register according to endianess. */
875 static char *
876 sh_justify_value_in_reg (struct value *val, int len)
877 {
878 static char valbuf[4];
879
880 memset (valbuf, 0, sizeof (valbuf));
881 if (len < 4)
882 {
883 /* value gets right-justified in the register or stack word */
884 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
885 memcpy (valbuf + (4 - len), (char *) value_contents (val), len);
886 else
887 memcpy (valbuf, (char *) value_contents (val), len);
888 return valbuf;
889 }
890 return (char *) value_contents (val);
891 }
892
893 /* Helper function to eval number of bytes to allocate on stack. */
894 static CORE_ADDR
895 sh_stack_allocsize (int nargs, struct value **args)
896 {
897 int stack_alloc = 0;
898 while (nargs-- > 0)
899 stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3);
900 return stack_alloc;
901 }
902
903 /* Helper functions for getting the float arguments right. Registers usage
904 depends on the ABI and the endianess. The comments should enlighten how
905 it's intended to work. */
906
907 /* This array stores which of the float arg registers are already in use. */
908 static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
909
910 /* This function just resets the above array to "no reg used so far". */
911 static void
912 sh_init_flt_argreg (void)
913 {
914 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
915 }
916
917 /* This function returns the next register to use for float arg passing.
918 It returns either a valid value between FLOAT_ARG0_REGNUM and
919 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
920 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
921
922 Note that register number 0 in flt_argreg_array corresponds with the
923 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
924 29) the parity of the register number is preserved, which is important
925 for the double register passing test (see the "argreg & 1" test below). */
926 static int
927 sh_next_flt_argreg (int len)
928 {
929 int argreg;
930
931 /* First search for the next free register. */
932 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
933 ++argreg)
934 if (!flt_argreg_array[argreg])
935 break;
936
937 /* No register left? */
938 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
939 return FLOAT_ARGLAST_REGNUM + 1;
940
941 if (len == 8)
942 {
943 /* Doubles are always starting in a even register number. */
944 if (argreg & 1)
945 {
946 flt_argreg_array[argreg] = 1;
947
948 ++argreg;
949
950 /* No register left? */
951 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
952 return FLOAT_ARGLAST_REGNUM + 1;
953 }
954 /* Also mark the next register as used. */
955 flt_argreg_array[argreg + 1] = 1;
956 }
957 else if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
958 {
959 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
960 if (!flt_argreg_array[argreg + 1])
961 ++argreg;
962 }
963 flt_argreg_array[argreg] = 1;
964 return FLOAT_ARG0_REGNUM + argreg;
965 }
966
967 /* Helper function which figures out, if a type is treated like a float type.
968
969 The FPU ABIs have a special way how to treat types as float types.
970 Structures with exactly one member, which is of type float or double, are
971 treated exactly as the base types float or double:
972
973 struct sf {
974 float f;
975 };
976
977 struct sd {
978 double d;
979 };
980
981 are handled the same way as just
982
983 float f;
984
985 double d;
986
987 As a result, arguments of these struct types are pushed into floating point
988 registers exactly as floats or doubles, using the same decision algorithm.
989
990 The same is valid if these types are used as function return types. The
991 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
992 or even using struct convention as it is for other structs. */
993
994 static int
995 sh_treat_as_flt_p (struct type *type)
996 {
997 int len = TYPE_LENGTH (type);
998
999 /* Ordinary float types are obviously treated as float. */
1000 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1001 return 1;
1002 /* Otherwise non-struct types are not treated as float. */
1003 if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
1004 return 0;
1005 /* Otherwise structs with more than one memeber are not treated as float. */
1006 if (TYPE_NFIELDS (type) != 1)
1007 return 0;
1008 /* Otherwise if the type of that member is float, the whole type is
1009 treated as float. */
1010 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
1011 return 1;
1012 /* Otherwise it's not treated as float. */
1013 return 0;
1014 }
1015
1016 static CORE_ADDR
1017 sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
1018 struct value *function,
1019 struct regcache *regcache,
1020 CORE_ADDR bp_addr, int nargs,
1021 struct value **args,
1022 CORE_ADDR sp, int struct_return,
1023 CORE_ADDR struct_addr)
1024 {
1025 int stack_offset = 0;
1026 int argreg = ARG0_REGNUM;
1027 int flt_argreg = 0;
1028 int argnum;
1029 struct type *type;
1030 CORE_ADDR regval;
1031 char *val;
1032 int len, reg_size = 0;
1033 int pass_on_stack = 0;
1034 int treat_as_flt;
1035
1036 /* first force sp to a 4-byte alignment */
1037 sp = sh_frame_align (gdbarch, sp);
1038
1039 if (struct_return)
1040 regcache_cooked_write_unsigned (regcache,
1041 STRUCT_RETURN_REGNUM, struct_addr);
1042
1043 /* make room on stack for args */
1044 sp -= sh_stack_allocsize (nargs, args);
1045
1046 /* Initialize float argument mechanism. */
1047 sh_init_flt_argreg ();
1048
1049 /* Now load as many as possible of the first arguments into
1050 registers, and push the rest onto the stack. There are 16 bytes
1051 in four registers available. Loop thru args from first to last. */
1052 for (argnum = 0; argnum < nargs; argnum++)
1053 {
1054 type = value_type (args[argnum]);
1055 len = TYPE_LENGTH (type);
1056 val = sh_justify_value_in_reg (args[argnum], len);
1057
1058 /* Some decisions have to be made how various types are handled.
1059 This also differs in different ABIs. */
1060 pass_on_stack = 0;
1061
1062 /* Find out the next register to use for a floating point value. */
1063 treat_as_flt = sh_treat_as_flt_p (type);
1064 if (treat_as_flt)
1065 flt_argreg = sh_next_flt_argreg (len);
1066 /* In contrast to non-FPU CPUs, arguments are never split between
1067 registers and stack. If an argument doesn't fit in the remaining
1068 registers it's always pushed entirely on the stack. */
1069 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
1070 pass_on_stack = 1;
1071
1072 while (len > 0)
1073 {
1074 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
1075 || (!treat_as_flt && (argreg > ARGLAST_REGNUM
1076 || pass_on_stack)))
1077 {
1078 /* The data goes entirely on the stack, 4-byte aligned. */
1079 reg_size = (len + 3) & ~3;
1080 write_memory (sp + stack_offset, val, reg_size);
1081 stack_offset += reg_size;
1082 }
1083 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
1084 {
1085 /* Argument goes in a float argument register. */
1086 reg_size = register_size (gdbarch, flt_argreg);
1087 regval = extract_unsigned_integer (val, reg_size);
1088 /* In little endian mode, float types taking two registers
1089 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1090 be stored swapped in the argument registers. The below
1091 code first writes the first 32 bits in the next but one
1092 register, increments the val and len values accordingly
1093 and then proceeds as normal by writing the second 32 bits
1094 into the next register. */
1095 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
1096 && TYPE_LENGTH (type) == 2 * reg_size)
1097 {
1098 regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
1099 regval);
1100 val += reg_size;
1101 len -= reg_size;
1102 regval = extract_unsigned_integer (val, reg_size);
1103 }
1104 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
1105 }
1106 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
1107 {
1108 /* there's room in a register */
1109 reg_size = register_size (gdbarch, argreg);
1110 regval = extract_unsigned_integer (val, reg_size);
1111 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1112 }
1113 /* Store the value one register at a time or in one step on stack. */
1114 len -= reg_size;
1115 val += reg_size;
1116 }
1117 }
1118
1119 /* Store return address. */
1120 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1121
1122 /* Update stack pointer. */
1123 regcache_cooked_write_unsigned (regcache,
1124 gdbarch_sp_regnum (gdbarch), sp);
1125
1126 return sp;
1127 }
1128
1129 static CORE_ADDR
1130 sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
1131 struct value *function,
1132 struct regcache *regcache,
1133 CORE_ADDR bp_addr,
1134 int nargs, struct value **args,
1135 CORE_ADDR sp, int struct_return,
1136 CORE_ADDR struct_addr)
1137 {
1138 int stack_offset = 0;
1139 int argreg = ARG0_REGNUM;
1140 int argnum;
1141 struct type *type;
1142 CORE_ADDR regval;
1143 char *val;
1144 int len, reg_size;
1145
1146 /* first force sp to a 4-byte alignment */
1147 sp = sh_frame_align (gdbarch, sp);
1148
1149 if (struct_return)
1150 regcache_cooked_write_unsigned (regcache,
1151 STRUCT_RETURN_REGNUM, struct_addr);
1152
1153 /* make room on stack for args */
1154 sp -= sh_stack_allocsize (nargs, args);
1155
1156 /* Now load as many as possible of the first arguments into
1157 registers, and push the rest onto the stack. There are 16 bytes
1158 in four registers available. Loop thru args from first to last. */
1159 for (argnum = 0; argnum < nargs; argnum++)
1160 {
1161 type = value_type (args[argnum]);
1162 len = TYPE_LENGTH (type);
1163 val = sh_justify_value_in_reg (args[argnum], len);
1164
1165 while (len > 0)
1166 {
1167 if (argreg > ARGLAST_REGNUM)
1168 {
1169 /* The remainder of the data goes entirely on the stack,
1170 4-byte aligned. */
1171 reg_size = (len + 3) & ~3;
1172 write_memory (sp + stack_offset, val, reg_size);
1173 stack_offset += reg_size;
1174 }
1175 else if (argreg <= ARGLAST_REGNUM)
1176 {
1177 /* there's room in a register */
1178 reg_size = register_size (gdbarch, argreg);
1179 regval = extract_unsigned_integer (val, reg_size);
1180 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1181 }
1182 /* Store the value reg_size bytes at a time. This means that things
1183 larger than reg_size bytes may go partly in registers and partly
1184 on the stack. */
1185 len -= reg_size;
1186 val += reg_size;
1187 }
1188 }
1189
1190 /* Store return address. */
1191 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1192
1193 /* Update stack pointer. */
1194 regcache_cooked_write_unsigned (regcache,
1195 gdbarch_sp_regnum (gdbarch), sp);
1196
1197 return sp;
1198 }
1199
1200 /* Find a function's return value in the appropriate registers (in
1201 regbuf), and copy it into valbuf. Extract from an array REGBUF
1202 containing the (raw) register state a function return value of type
1203 TYPE, and copy that, in virtual format, into VALBUF. */
1204 static void
1205 sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache,
1206 void *valbuf)
1207 {
1208 int len = TYPE_LENGTH (type);
1209 int return_register = R0_REGNUM;
1210 int offset;
1211
1212 if (len <= 4)
1213 {
1214 ULONGEST c;
1215
1216 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
1217 store_unsigned_integer (valbuf, len, c);
1218 }
1219 else if (len == 8)
1220 {
1221 int i, regnum = R0_REGNUM;
1222 for (i = 0; i < len; i += 4)
1223 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1224 }
1225 else
1226 error (_("bad size for return value"));
1227 }
1228
1229 static void
1230 sh_extract_return_value_fpu (struct type *type, struct regcache *regcache,
1231 void *valbuf)
1232 {
1233 if (sh_treat_as_flt_p (type))
1234 {
1235 int len = TYPE_LENGTH (type);
1236 int i, regnum = gdbarch_fp0_regnum (current_gdbarch);
1237 for (i = 0; i < len; i += 4)
1238 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
1239 regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i);
1240 else
1241 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1242 }
1243 else
1244 sh_extract_return_value_nofpu (type, regcache, valbuf);
1245 }
1246
1247 /* Write into appropriate registers a function return value
1248 of type TYPE, given in virtual format.
1249 If the architecture is sh4 or sh3e, store a function's return value
1250 in the R0 general register or in the FP0 floating point register,
1251 depending on the type of the return value. In all the other cases
1252 the result is stored in r0, left-justified. */
1253 static void
1254 sh_store_return_value_nofpu (struct type *type, struct regcache *regcache,
1255 const void *valbuf)
1256 {
1257 ULONGEST val;
1258 int len = TYPE_LENGTH (type);
1259
1260 if (len <= 4)
1261 {
1262 val = extract_unsigned_integer (valbuf, len);
1263 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
1264 }
1265 else
1266 {
1267 int i, regnum = R0_REGNUM;
1268 for (i = 0; i < len; i += 4)
1269 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1270 }
1271 }
1272
1273 static void
1274 sh_store_return_value_fpu (struct type *type, struct regcache *regcache,
1275 const void *valbuf)
1276 {
1277 if (sh_treat_as_flt_p (type))
1278 {
1279 int len = TYPE_LENGTH (type);
1280 int i, regnum = gdbarch_fp0_regnum (current_gdbarch);
1281 for (i = 0; i < len; i += 4)
1282 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
1283 regcache_raw_write (regcache, regnum++,
1284 (char *) valbuf + len - 4 - i);
1285 else
1286 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1287 }
1288 else
1289 sh_store_return_value_nofpu (type, regcache, valbuf);
1290 }
1291
1292 static enum return_value_convention
1293 sh_return_value_nofpu (struct gdbarch *gdbarch, struct type *type,
1294 struct regcache *regcache,
1295 gdb_byte *readbuf, const gdb_byte *writebuf)
1296 {
1297 if (sh_use_struct_convention (0, type))
1298 return RETURN_VALUE_STRUCT_CONVENTION;
1299 if (writebuf)
1300 sh_store_return_value_nofpu (type, regcache, writebuf);
1301 else if (readbuf)
1302 sh_extract_return_value_nofpu (type, regcache, readbuf);
1303 return RETURN_VALUE_REGISTER_CONVENTION;
1304 }
1305
1306 static enum return_value_convention
1307 sh_return_value_fpu (struct gdbarch *gdbarch, struct type *type,
1308 struct regcache *regcache,
1309 gdb_byte *readbuf, const gdb_byte *writebuf)
1310 {
1311 if (sh_use_struct_convention (0, type))
1312 return RETURN_VALUE_STRUCT_CONVENTION;
1313 if (writebuf)
1314 sh_store_return_value_fpu (type, regcache, writebuf);
1315 else if (readbuf)
1316 sh_extract_return_value_fpu (type, regcache, readbuf);
1317 return RETURN_VALUE_REGISTER_CONVENTION;
1318 }
1319
1320 /* Print the registers in a form similar to the E7000 */
1321
1322 static void
1323 sh_generic_show_regs (struct frame_info *frame)
1324 {
1325 printf_filtered
1326 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1327 paddr (get_frame_register_unsigned (frame,
1328 gdbarch_pc_regnum
1329 (get_frame_arch (frame)))),
1330 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1331 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1332 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1333
1334 printf_filtered
1335 (" GBR %08lx VBR %08lx MACL %08lx\n",
1336 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1337 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1338 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1339
1340 printf_filtered
1341 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1342 (long) get_frame_register_unsigned (frame, 0),
1343 (long) get_frame_register_unsigned (frame, 1),
1344 (long) get_frame_register_unsigned (frame, 2),
1345 (long) get_frame_register_unsigned (frame, 3),
1346 (long) get_frame_register_unsigned (frame, 4),
1347 (long) get_frame_register_unsigned (frame, 5),
1348 (long) get_frame_register_unsigned (frame, 6),
1349 (long) get_frame_register_unsigned (frame, 7));
1350 printf_filtered
1351 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1352 (long) get_frame_register_unsigned (frame, 8),
1353 (long) get_frame_register_unsigned (frame, 9),
1354 (long) get_frame_register_unsigned (frame, 10),
1355 (long) get_frame_register_unsigned (frame, 11),
1356 (long) get_frame_register_unsigned (frame, 12),
1357 (long) get_frame_register_unsigned (frame, 13),
1358 (long) get_frame_register_unsigned (frame, 14),
1359 (long) get_frame_register_unsigned (frame, 15));
1360 }
1361
1362 static void
1363 sh3_show_regs (struct frame_info *frame)
1364 {
1365 printf_filtered
1366 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1367 paddr (get_frame_register_unsigned (frame,
1368 gdbarch_pc_regnum
1369 (get_frame_arch (frame)))),
1370 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1371 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1372 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1373
1374 printf_filtered
1375 (" GBR %08lx VBR %08lx MACL %08lx\n",
1376 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1377 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1378 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1379 printf_filtered
1380 (" SSR %08lx SPC %08lx\n",
1381 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1382 (long) get_frame_register_unsigned (frame, SPC_REGNUM));
1383
1384 printf_filtered
1385 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1386 (long) get_frame_register_unsigned (frame, 0),
1387 (long) get_frame_register_unsigned (frame, 1),
1388 (long) get_frame_register_unsigned (frame, 2),
1389 (long) get_frame_register_unsigned (frame, 3),
1390 (long) get_frame_register_unsigned (frame, 4),
1391 (long) get_frame_register_unsigned (frame, 5),
1392 (long) get_frame_register_unsigned (frame, 6),
1393 (long) get_frame_register_unsigned (frame, 7));
1394 printf_filtered
1395 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1396 (long) get_frame_register_unsigned (frame, 8),
1397 (long) get_frame_register_unsigned (frame, 9),
1398 (long) get_frame_register_unsigned (frame, 10),
1399 (long) get_frame_register_unsigned (frame, 11),
1400 (long) get_frame_register_unsigned (frame, 12),
1401 (long) get_frame_register_unsigned (frame, 13),
1402 (long) get_frame_register_unsigned (frame, 14),
1403 (long) get_frame_register_unsigned (frame, 15));
1404 }
1405
1406 static void
1407 sh2e_show_regs (struct frame_info *frame)
1408 {
1409 struct gdbarch *gdbarch = get_frame_arch (frame);
1410 printf_filtered
1411 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1412 paddr (get_frame_register_unsigned (frame,
1413 gdbarch_pc_regnum (gdbarch))),
1414 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1415 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1416 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1417
1418 printf_filtered
1419 (" GBR %08lx VBR %08lx MACL %08lx\n",
1420 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1421 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1422 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1423 printf_filtered
1424 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1425 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1426 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1427 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1428 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1429
1430 printf_filtered
1431 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1432 (long) get_frame_register_unsigned (frame, 0),
1433 (long) get_frame_register_unsigned (frame, 1),
1434 (long) get_frame_register_unsigned (frame, 2),
1435 (long) get_frame_register_unsigned (frame, 3),
1436 (long) get_frame_register_unsigned (frame, 4),
1437 (long) get_frame_register_unsigned (frame, 5),
1438 (long) get_frame_register_unsigned (frame, 6),
1439 (long) get_frame_register_unsigned (frame, 7));
1440 printf_filtered
1441 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1442 (long) get_frame_register_unsigned (frame, 8),
1443 (long) get_frame_register_unsigned (frame, 9),
1444 (long) get_frame_register_unsigned (frame, 10),
1445 (long) get_frame_register_unsigned (frame, 11),
1446 (long) get_frame_register_unsigned (frame, 12),
1447 (long) get_frame_register_unsigned (frame, 13),
1448 (long) get_frame_register_unsigned (frame, 14),
1449 (long) get_frame_register_unsigned (frame, 15));
1450
1451 printf_filtered
1452 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1453 (long) get_frame_register_unsigned
1454 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
1455 (long) get_frame_register_unsigned
1456 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
1457 (long) get_frame_register_unsigned
1458 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
1459 (long) get_frame_register_unsigned
1460 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
1461 (long) get_frame_register_unsigned
1462 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
1463 (long) get_frame_register_unsigned
1464 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
1465 (long) get_frame_register_unsigned
1466 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
1467 (long) get_frame_register_unsigned
1468 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
1469 printf_filtered
1470 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1471 (long) get_frame_register_unsigned
1472 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
1473 (long) get_frame_register_unsigned
1474 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
1475 (long) get_frame_register_unsigned
1476 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
1477 (long) get_frame_register_unsigned
1478 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
1479 (long) get_frame_register_unsigned
1480 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
1481 (long) get_frame_register_unsigned
1482 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
1483 (long) get_frame_register_unsigned
1484 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
1485 (long) get_frame_register_unsigned
1486 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
1487 }
1488
1489 static void
1490 sh2a_show_regs (struct frame_info *frame)
1491 {
1492 struct gdbarch *gdbarch = get_frame_arch (frame);
1493 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1494
1495 printf_filtered
1496 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1497 paddr (get_frame_register_unsigned (frame,
1498 gdbarch_pc_regnum (gdbarch))),
1499 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1500 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1501 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1502
1503 printf_filtered
1504 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1505 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1506 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1507 (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1508 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1509 printf_filtered
1510 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1511 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1512 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1513 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1514 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1515
1516 printf_filtered
1517 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1518 (long) get_frame_register_unsigned (frame, 0),
1519 (long) get_frame_register_unsigned (frame, 1),
1520 (long) get_frame_register_unsigned (frame, 2),
1521 (long) get_frame_register_unsigned (frame, 3),
1522 (long) get_frame_register_unsigned (frame, 4),
1523 (long) get_frame_register_unsigned (frame, 5),
1524 (long) get_frame_register_unsigned (frame, 6),
1525 (long) get_frame_register_unsigned (frame, 7));
1526 printf_filtered
1527 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1528 (long) get_frame_register_unsigned (frame, 8),
1529 (long) get_frame_register_unsigned (frame, 9),
1530 (long) get_frame_register_unsigned (frame, 10),
1531 (long) get_frame_register_unsigned (frame, 11),
1532 (long) get_frame_register_unsigned (frame, 12),
1533 (long) get_frame_register_unsigned (frame, 13),
1534 (long) get_frame_register_unsigned (frame, 14),
1535 (long) get_frame_register_unsigned (frame, 15));
1536
1537 printf_filtered
1538 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1539 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1540 (long) get_frame_register_unsigned
1541 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
1542 (long) get_frame_register_unsigned
1543 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
1544 (long) get_frame_register_unsigned
1545 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
1546 (long) get_frame_register_unsigned
1547 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
1548 (long) get_frame_register_unsigned
1549 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
1550 (long) get_frame_register_unsigned
1551 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
1552 (long) get_frame_register_unsigned
1553 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
1554 (long) get_frame_register_unsigned
1555 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
1556 printf_filtered
1557 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1558 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1559 (long) get_frame_register_unsigned
1560 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
1561 (long) get_frame_register_unsigned
1562 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
1563 (long) get_frame_register_unsigned
1564 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
1565 (long) get_frame_register_unsigned
1566 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
1567 (long) get_frame_register_unsigned
1568 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
1569 (long) get_frame_register_unsigned
1570 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
1571 (long) get_frame_register_unsigned
1572 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
1573 (long) get_frame_register_unsigned
1574 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
1575 printf_filtered
1576 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1577 printf_filtered
1578 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1579 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1580 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1581 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1582 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1583 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1584 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1585 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1586 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1587 printf_filtered
1588 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1589 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1590 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1591 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1592 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1593 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1594 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1595 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1596 printf_filtered
1597 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1598 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1599 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1600 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1601 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1602 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
1603 }
1604
1605 static void
1606 sh2a_nofpu_show_regs (struct frame_info *frame)
1607 {
1608 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1609
1610 printf_filtered
1611 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1612 paddr (get_frame_register_unsigned (frame,
1613 gdbarch_pc_regnum
1614 (get_frame_arch (frame)))),
1615 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1616 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1617 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1618
1619 printf_filtered
1620 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1621 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1622 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1623 (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1624 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1625 printf_filtered
1626 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1627 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1628 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1629 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1630 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1631
1632 printf_filtered
1633 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1634 (long) get_frame_register_unsigned (frame, 0),
1635 (long) get_frame_register_unsigned (frame, 1),
1636 (long) get_frame_register_unsigned (frame, 2),
1637 (long) get_frame_register_unsigned (frame, 3),
1638 (long) get_frame_register_unsigned (frame, 4),
1639 (long) get_frame_register_unsigned (frame, 5),
1640 (long) get_frame_register_unsigned (frame, 6),
1641 (long) get_frame_register_unsigned (frame, 7));
1642 printf_filtered
1643 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1644 (long) get_frame_register_unsigned (frame, 8),
1645 (long) get_frame_register_unsigned (frame, 9),
1646 (long) get_frame_register_unsigned (frame, 10),
1647 (long) get_frame_register_unsigned (frame, 11),
1648 (long) get_frame_register_unsigned (frame, 12),
1649 (long) get_frame_register_unsigned (frame, 13),
1650 (long) get_frame_register_unsigned (frame, 14),
1651 (long) get_frame_register_unsigned (frame, 15));
1652
1653 printf_filtered
1654 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1655 printf_filtered
1656 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1657 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1658 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1659 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1660 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1661 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1662 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1663 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1664 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1665 printf_filtered
1666 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1667 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1668 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1669 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1670 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1671 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1672 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1673 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1674 printf_filtered
1675 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1676 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1677 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1678 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1679 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1680 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
1681 }
1682
1683 static void
1684 sh3e_show_regs (struct frame_info *frame)
1685 {
1686 struct gdbarch *gdbarch = get_frame_arch (frame);
1687 printf_filtered
1688 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1689 paddr (get_frame_register_unsigned (frame,
1690 gdbarch_pc_regnum (gdbarch))),
1691 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1692 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1693 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1694
1695 printf_filtered
1696 (" GBR %08lx VBR %08lx MACL %08lx\n",
1697 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1698 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1699 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1700 printf_filtered
1701 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1702 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1703 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1704 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1705 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1706
1707 printf_filtered
1708 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1709 (long) get_frame_register_unsigned (frame, 0),
1710 (long) get_frame_register_unsigned (frame, 1),
1711 (long) get_frame_register_unsigned (frame, 2),
1712 (long) get_frame_register_unsigned (frame, 3),
1713 (long) get_frame_register_unsigned (frame, 4),
1714 (long) get_frame_register_unsigned (frame, 5),
1715 (long) get_frame_register_unsigned (frame, 6),
1716 (long) get_frame_register_unsigned (frame, 7));
1717 printf_filtered
1718 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1719 (long) get_frame_register_unsigned (frame, 8),
1720 (long) get_frame_register_unsigned (frame, 9),
1721 (long) get_frame_register_unsigned (frame, 10),
1722 (long) get_frame_register_unsigned (frame, 11),
1723 (long) get_frame_register_unsigned (frame, 12),
1724 (long) get_frame_register_unsigned (frame, 13),
1725 (long) get_frame_register_unsigned (frame, 14),
1726 (long) get_frame_register_unsigned (frame, 15));
1727
1728 printf_filtered
1729 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1730 (long) get_frame_register_unsigned
1731 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
1732 (long) get_frame_register_unsigned
1733 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
1734 (long) get_frame_register_unsigned
1735 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
1736 (long) get_frame_register_unsigned
1737 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
1738 (long) get_frame_register_unsigned
1739 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
1740 (long) get_frame_register_unsigned
1741 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
1742 (long) get_frame_register_unsigned
1743 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
1744 (long) get_frame_register_unsigned
1745 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
1746 printf_filtered
1747 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1748 (long) get_frame_register_unsigned
1749 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
1750 (long) get_frame_register_unsigned
1751 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
1752 (long) get_frame_register_unsigned
1753 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
1754 (long) get_frame_register_unsigned
1755 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
1756 (long) get_frame_register_unsigned
1757 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
1758 (long) get_frame_register_unsigned
1759 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
1760 (long) get_frame_register_unsigned
1761 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
1762 (long) get_frame_register_unsigned
1763 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
1764 }
1765
1766 static void
1767 sh3_dsp_show_regs (struct frame_info *frame)
1768 {
1769 printf_filtered
1770 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1771 paddr (get_frame_register_unsigned (frame,
1772 gdbarch_pc_regnum
1773 (get_frame_arch (frame)))),
1774 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1775 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1776 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1777
1778 printf_filtered
1779 (" GBR %08lx VBR %08lx MACL %08lx\n",
1780 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1781 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1782 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1783
1784 printf_filtered
1785 (" SSR %08lx SPC %08lx DSR %08lx\n",
1786 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1787 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1788 (long) get_frame_register_unsigned (frame, DSR_REGNUM));
1789
1790 printf_filtered
1791 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1792 (long) get_frame_register_unsigned (frame, 0),
1793 (long) get_frame_register_unsigned (frame, 1),
1794 (long) get_frame_register_unsigned (frame, 2),
1795 (long) get_frame_register_unsigned (frame, 3),
1796 (long) get_frame_register_unsigned (frame, 4),
1797 (long) get_frame_register_unsigned (frame, 5),
1798 (long) get_frame_register_unsigned (frame, 6),
1799 (long) get_frame_register_unsigned (frame, 7));
1800 printf_filtered
1801 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1802 (long) get_frame_register_unsigned (frame, 8),
1803 (long) get_frame_register_unsigned (frame, 9),
1804 (long) get_frame_register_unsigned (frame, 10),
1805 (long) get_frame_register_unsigned (frame, 11),
1806 (long) get_frame_register_unsigned (frame, 12),
1807 (long) get_frame_register_unsigned (frame, 13),
1808 (long) get_frame_register_unsigned (frame, 14),
1809 (long) get_frame_register_unsigned (frame, 15));
1810
1811 printf_filtered
1812 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1813 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
1814 (long) get_frame_register_unsigned (frame, A0_REGNUM),
1815 (long) get_frame_register_unsigned (frame, M0_REGNUM),
1816 (long) get_frame_register_unsigned (frame, X0_REGNUM),
1817 (long) get_frame_register_unsigned (frame, Y0_REGNUM),
1818 (long) get_frame_register_unsigned (frame, RS_REGNUM),
1819 (long) get_frame_register_unsigned (frame, MOD_REGNUM));
1820 printf_filtered
1821 ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1822 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
1823 (long) get_frame_register_unsigned (frame, A1_REGNUM),
1824 (long) get_frame_register_unsigned (frame, M1_REGNUM),
1825 (long) get_frame_register_unsigned (frame, X1_REGNUM),
1826 (long) get_frame_register_unsigned (frame, Y1_REGNUM),
1827 (long) get_frame_register_unsigned (frame, RE_REGNUM));
1828 }
1829
1830 static void
1831 sh4_show_regs (struct frame_info *frame)
1832 {
1833 struct gdbarch *gdbarch = get_frame_arch (frame);
1834 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1835
1836 printf_filtered
1837 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1838 paddr (get_frame_register_unsigned (frame,
1839 gdbarch_pc_regnum (gdbarch))),
1840 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1841 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1842 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1843
1844 printf_filtered
1845 (" GBR %08lx VBR %08lx MACL %08lx\n",
1846 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1847 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1848 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1849 printf_filtered
1850 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1851 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1852 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1853 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1854 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1855
1856 printf_filtered
1857 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1858 (long) get_frame_register_unsigned (frame, 0),
1859 (long) get_frame_register_unsigned (frame, 1),
1860 (long) get_frame_register_unsigned (frame, 2),
1861 (long) get_frame_register_unsigned (frame, 3),
1862 (long) get_frame_register_unsigned (frame, 4),
1863 (long) get_frame_register_unsigned (frame, 5),
1864 (long) get_frame_register_unsigned (frame, 6),
1865 (long) get_frame_register_unsigned (frame, 7));
1866 printf_filtered
1867 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1868 (long) get_frame_register_unsigned (frame, 8),
1869 (long) get_frame_register_unsigned (frame, 9),
1870 (long) get_frame_register_unsigned (frame, 10),
1871 (long) get_frame_register_unsigned (frame, 11),
1872 (long) get_frame_register_unsigned (frame, 12),
1873 (long) get_frame_register_unsigned (frame, 13),
1874 (long) get_frame_register_unsigned (frame, 14),
1875 (long) get_frame_register_unsigned (frame, 15));
1876
1877 printf_filtered
1878 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1879 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1880 (long) get_frame_register_unsigned
1881 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
1882 (long) get_frame_register_unsigned
1883 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
1884 (long) get_frame_register_unsigned
1885 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
1886 (long) get_frame_register_unsigned
1887 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
1888 (long) get_frame_register_unsigned
1889 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
1890 (long) get_frame_register_unsigned
1891 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
1892 (long) get_frame_register_unsigned
1893 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
1894 (long) get_frame_register_unsigned
1895 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
1896 printf_filtered
1897 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1898 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1899 (long) get_frame_register_unsigned
1900 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
1901 (long) get_frame_register_unsigned
1902 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
1903 (long) get_frame_register_unsigned
1904 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
1905 (long) get_frame_register_unsigned
1906 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
1907 (long) get_frame_register_unsigned
1908 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
1909 (long) get_frame_register_unsigned
1910 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
1911 (long) get_frame_register_unsigned
1912 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
1913 (long) get_frame_register_unsigned
1914 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
1915 }
1916
1917 static void
1918 sh4_nofpu_show_regs (struct frame_info *frame)
1919 {
1920 printf_filtered
1921 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1922 paddr (get_frame_register_unsigned (frame,
1923 gdbarch_pc_regnum
1924 (get_frame_arch (frame)))),
1925 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1926 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1927 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1928
1929 printf_filtered
1930 (" GBR %08lx VBR %08lx MACL %08lx\n",
1931 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1932 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1933 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1934 printf_filtered
1935 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1936 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1937 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1938 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1939 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1940
1941 printf_filtered
1942 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1943 (long) get_frame_register_unsigned (frame, 0),
1944 (long) get_frame_register_unsigned (frame, 1),
1945 (long) get_frame_register_unsigned (frame, 2),
1946 (long) get_frame_register_unsigned (frame, 3),
1947 (long) get_frame_register_unsigned (frame, 4),
1948 (long) get_frame_register_unsigned (frame, 5),
1949 (long) get_frame_register_unsigned (frame, 6),
1950 (long) get_frame_register_unsigned (frame, 7));
1951 printf_filtered
1952 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1953 (long) get_frame_register_unsigned (frame, 8),
1954 (long) get_frame_register_unsigned (frame, 9),
1955 (long) get_frame_register_unsigned (frame, 10),
1956 (long) get_frame_register_unsigned (frame, 11),
1957 (long) get_frame_register_unsigned (frame, 12),
1958 (long) get_frame_register_unsigned (frame, 13),
1959 (long) get_frame_register_unsigned (frame, 14),
1960 (long) get_frame_register_unsigned (frame, 15));
1961 }
1962
1963 static void
1964 sh_dsp_show_regs (struct frame_info *frame)
1965 {
1966 printf_filtered
1967 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1968 paddr (get_frame_register_unsigned (frame,
1969 gdbarch_pc_regnum
1970 (get_frame_arch (frame)))),
1971 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1972 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1973 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1974
1975 printf_filtered
1976 (" GBR %08lx VBR %08lx DSR %08lx MACL %08lx\n",
1977 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1978 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1979 (long) get_frame_register_unsigned (frame, DSR_REGNUM),
1980 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1981
1982 printf_filtered
1983 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1984 (long) get_frame_register_unsigned (frame, 0),
1985 (long) get_frame_register_unsigned (frame, 1),
1986 (long) get_frame_register_unsigned (frame, 2),
1987 (long) get_frame_register_unsigned (frame, 3),
1988 (long) get_frame_register_unsigned (frame, 4),
1989 (long) get_frame_register_unsigned (frame, 5),
1990 (long) get_frame_register_unsigned (frame, 6),
1991 (long) get_frame_register_unsigned (frame, 7));
1992 printf_filtered
1993 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1994 (long) get_frame_register_unsigned (frame, 8),
1995 (long) get_frame_register_unsigned (frame, 9),
1996 (long) get_frame_register_unsigned (frame, 10),
1997 (long) get_frame_register_unsigned (frame, 11),
1998 (long) get_frame_register_unsigned (frame, 12),
1999 (long) get_frame_register_unsigned (frame, 13),
2000 (long) get_frame_register_unsigned (frame, 14),
2001 (long) get_frame_register_unsigned (frame, 15));
2002
2003 printf_filtered
2004 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2005 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
2006 (long) get_frame_register_unsigned (frame, A0_REGNUM),
2007 (long) get_frame_register_unsigned (frame, M0_REGNUM),
2008 (long) get_frame_register_unsigned (frame, X0_REGNUM),
2009 (long) get_frame_register_unsigned (frame, Y0_REGNUM),
2010 (long) get_frame_register_unsigned (frame, RS_REGNUM),
2011 (long) get_frame_register_unsigned (frame, MOD_REGNUM));
2012 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2013 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
2014 (long) get_frame_register_unsigned (frame, A1_REGNUM),
2015 (long) get_frame_register_unsigned (frame, M1_REGNUM),
2016 (long) get_frame_register_unsigned (frame, X1_REGNUM),
2017 (long) get_frame_register_unsigned (frame, Y1_REGNUM),
2018 (long) get_frame_register_unsigned (frame, RE_REGNUM));
2019 }
2020
2021 static void
2022 sh_show_regs_command (char *args, int from_tty)
2023 {
2024 if (sh_show_regs)
2025 (*sh_show_regs) (get_current_frame ());
2026 }
2027
2028 static struct type *
2029 sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr)
2030 {
2031 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
2032 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2033 return builtin_type_float;
2034 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2035 return builtin_type_double;
2036 else
2037 return builtin_type_int;
2038 }
2039
2040 /* Return the GDB type object for the "standard" data type
2041 of data in register N. */
2042 static struct type *
2043 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
2044 {
2045 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
2046 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2047 return builtin_type_float;
2048 else
2049 return builtin_type_int;
2050 }
2051
2052 static struct type *
2053 sh_sh4_build_float_register_type (int high)
2054 {
2055 struct type *temp;
2056
2057 temp = create_range_type (NULL, builtin_type_int, 0, high);
2058 return create_array_type (NULL, builtin_type_float, temp);
2059 }
2060
2061 static struct type *
2062 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
2063 {
2064 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
2065 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2066 return builtin_type_float;
2067 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2068 return builtin_type_double;
2069 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2070 return sh_sh4_build_float_register_type (3);
2071 else
2072 return builtin_type_int;
2073 }
2074
2075 static struct type *
2076 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
2077 {
2078 return builtin_type_int;
2079 }
2080
2081 /* Is a register in a reggroup?
2082 The default code in reggroup.c doesn't identify system registers, some
2083 float registers or any of the vector registers.
2084 TODO: sh2a and dsp registers. */
2085 int
2086 sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2087 struct reggroup *reggroup)
2088 {
2089 if (gdbarch_register_name (gdbarch, regnum) == NULL
2090 || *gdbarch_register_name (gdbarch, regnum) == '\0')
2091 return 0;
2092
2093 if (reggroup == float_reggroup
2094 && (regnum == FPUL_REGNUM
2095 || regnum == FPSCR_REGNUM))
2096 return 1;
2097
2098 if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
2099 {
2100 if (reggroup == vector_reggroup || reggroup == float_reggroup)
2101 return 1;
2102 if (reggroup == general_reggroup)
2103 return 0;
2104 }
2105
2106 if (regnum == VBR_REGNUM
2107 || regnum == SR_REGNUM
2108 || regnum == FPSCR_REGNUM
2109 || regnum == SSR_REGNUM
2110 || regnum == SPC_REGNUM)
2111 {
2112 if (reggroup == system_reggroup)
2113 return 1;
2114 if (reggroup == general_reggroup)
2115 return 0;
2116 }
2117
2118 /* The default code can cope with any other registers. */
2119 return default_register_reggroup_p (gdbarch, regnum, reggroup);
2120 }
2121
2122 /* On the sh4, the DRi pseudo registers are problematic if the target
2123 is little endian. When the user writes one of those registers, for
2124 instance with 'ser var $dr0=1', we want the double to be stored
2125 like this:
2126 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2127 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2128
2129 This corresponds to little endian byte order & big endian word
2130 order. However if we let gdb write the register w/o conversion, it
2131 will write fr0 and fr1 this way:
2132 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2133 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2134 because it will consider fr0 and fr1 as a single LE stretch of memory.
2135
2136 To achieve what we want we must force gdb to store things in
2137 floatformat_ieee_double_littlebyte_bigword (which is defined in
2138 include/floatformat.h and libiberty/floatformat.c.
2139
2140 In case the target is big endian, there is no problem, the
2141 raw bytes will look like:
2142 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
2143 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2144
2145 The other pseudo registers (the FVs) also don't pose a problem
2146 because they are stored as 4 individual FP elements. */
2147
2148 static void
2149 sh_register_convert_to_virtual (int regnum, struct type *type,
2150 char *from, char *to)
2151 {
2152 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
2153 {
2154 DOUBLEST val;
2155 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2156 from, &val);
2157 store_typed_floating (to, type, val);
2158 }
2159 else
2160 error
2161 ("sh_register_convert_to_virtual called with non DR register number");
2162 }
2163
2164 static void
2165 sh_register_convert_to_raw (struct type *type, int regnum,
2166 const void *from, void *to)
2167 {
2168 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
2169 {
2170 DOUBLEST val = extract_typed_floating (from, type);
2171 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
2172 &val, to);
2173 }
2174 else
2175 error (_("sh_register_convert_to_raw called with non DR register number"));
2176 }
2177
2178 /* For vectors of 4 floating point registers. */
2179 static int
2180 fv_reg_base_num (int fv_regnum)
2181 {
2182 int fp_regnum;
2183
2184 fp_regnum = gdbarch_fp0_regnum (current_gdbarch)
2185 + (fv_regnum - FV0_REGNUM) * 4;
2186 return fp_regnum;
2187 }
2188
2189 /* For double precision floating point registers, i.e 2 fp regs.*/
2190 static int
2191 dr_reg_base_num (int dr_regnum)
2192 {
2193 int fp_regnum;
2194
2195 fp_regnum = gdbarch_fp0_regnum (current_gdbarch)
2196 + (dr_regnum - DR0_REGNUM) * 2;
2197 return fp_regnum;
2198 }
2199
2200 static void
2201 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2202 int reg_nr, gdb_byte *buffer)
2203 {
2204 int base_regnum, portion;
2205 char temp_buffer[MAX_REGISTER_SIZE];
2206
2207 if (reg_nr == PSEUDO_BANK_REGNUM)
2208 regcache_raw_read (regcache, BANK_REGNUM, buffer);
2209 else
2210 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2211 {
2212 base_regnum = dr_reg_base_num (reg_nr);
2213
2214 /* Build the value in the provided buffer. */
2215 /* Read the real regs for which this one is an alias. */
2216 for (portion = 0; portion < 2; portion++)
2217 regcache_raw_read (regcache, base_regnum + portion,
2218 (temp_buffer
2219 + register_size (gdbarch,
2220 base_regnum) * portion));
2221 /* We must pay attention to the endiannes. */
2222 sh_register_convert_to_virtual (reg_nr,
2223 register_type (gdbarch, reg_nr),
2224 temp_buffer, buffer);
2225 }
2226 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2227 {
2228 base_regnum = fv_reg_base_num (reg_nr);
2229
2230 /* Read the real regs for which this one is an alias. */
2231 for (portion = 0; portion < 4; portion++)
2232 regcache_raw_read (regcache, base_regnum + portion,
2233 ((char *) buffer
2234 + register_size (gdbarch,
2235 base_regnum) * portion));
2236 }
2237 }
2238
2239 static void
2240 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2241 int reg_nr, const gdb_byte *buffer)
2242 {
2243 int base_regnum, portion;
2244 char temp_buffer[MAX_REGISTER_SIZE];
2245
2246 if (reg_nr == PSEUDO_BANK_REGNUM)
2247 {
2248 /* When the bank register is written to, the whole register bank
2249 is switched and all values in the bank registers must be read
2250 from the target/sim again. We're just invalidating the regcache
2251 so that a re-read happens next time it's necessary. */
2252 int bregnum;
2253
2254 regcache_raw_write (regcache, BANK_REGNUM, buffer);
2255 for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum)
2256 regcache_invalidate (regcache, bregnum);
2257 }
2258 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2259 {
2260 base_regnum = dr_reg_base_num (reg_nr);
2261
2262 /* We must pay attention to the endiannes. */
2263 sh_register_convert_to_raw (register_type (gdbarch, reg_nr),
2264 reg_nr, buffer, temp_buffer);
2265
2266 /* Write the real regs for which this one is an alias. */
2267 for (portion = 0; portion < 2; portion++)
2268 regcache_raw_write (regcache, base_regnum + portion,
2269 (temp_buffer
2270 + register_size (gdbarch,
2271 base_regnum) * portion));
2272 }
2273 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2274 {
2275 base_regnum = fv_reg_base_num (reg_nr);
2276
2277 /* Write the real regs for which this one is an alias. */
2278 for (portion = 0; portion < 4; portion++)
2279 regcache_raw_write (regcache, base_regnum + portion,
2280 ((char *) buffer
2281 + register_size (gdbarch,
2282 base_regnum) * portion));
2283 }
2284 }
2285
2286 static int
2287 sh_dsp_register_sim_regno (int nr)
2288 {
2289 if (legacy_register_sim_regno (nr) < 0)
2290 return legacy_register_sim_regno (nr);
2291 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
2292 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
2293 if (nr == MOD_REGNUM)
2294 return SIM_SH_MOD_REGNUM;
2295 if (nr == RS_REGNUM)
2296 return SIM_SH_RS_REGNUM;
2297 if (nr == RE_REGNUM)
2298 return SIM_SH_RE_REGNUM;
2299 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
2300 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
2301 return nr;
2302 }
2303
2304 static int
2305 sh_sh2a_register_sim_regno (int nr)
2306 {
2307 switch (nr)
2308 {
2309 case TBR_REGNUM:
2310 return SIM_SH_TBR_REGNUM;
2311 case IBNR_REGNUM:
2312 return SIM_SH_IBNR_REGNUM;
2313 case IBCR_REGNUM:
2314 return SIM_SH_IBCR_REGNUM;
2315 case BANK_REGNUM:
2316 return SIM_SH_BANK_REGNUM;
2317 case MACLB_REGNUM:
2318 return SIM_SH_BANK_MACL_REGNUM;
2319 case GBRB_REGNUM:
2320 return SIM_SH_BANK_GBR_REGNUM;
2321 case PRB_REGNUM:
2322 return SIM_SH_BANK_PR_REGNUM;
2323 case IVNB_REGNUM:
2324 return SIM_SH_BANK_IVN_REGNUM;
2325 case MACHB_REGNUM:
2326 return SIM_SH_BANK_MACH_REGNUM;
2327 default:
2328 break;
2329 }
2330 return legacy_register_sim_regno (nr);
2331 }
2332
2333 /* Set up the register unwinding such that call-clobbered registers are
2334 not displayed in frames >0 because the true value is not certain.
2335 The 'undefined' registers will show up as 'not available' unless the
2336 CFI says otherwise.
2337
2338 This function is currently set up for SH4 and compatible only. */
2339
2340 static void
2341 sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
2342 struct dwarf2_frame_state_reg *reg,
2343 struct frame_info *next_frame)
2344 {
2345 /* Mark the PC as the destination for the return address. */
2346 if (regnum == gdbarch_pc_regnum (gdbarch))
2347 reg->how = DWARF2_FRAME_REG_RA;
2348
2349 /* Mark the stack pointer as the call frame address. */
2350 else if (regnum == gdbarch_sp_regnum (gdbarch))
2351 reg->how = DWARF2_FRAME_REG_CFA;
2352
2353 /* The above was taken from the default init_reg in dwarf2-frame.c
2354 while the below is SH specific. */
2355
2356 /* Caller save registers. */
2357 else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7)
2358 || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11)
2359 || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5)
2360 || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2)
2361 || (regnum == MACH_REGNUM)
2362 || (regnum == MACL_REGNUM)
2363 || (regnum == FPUL_REGNUM)
2364 || (regnum == SR_REGNUM))
2365 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2366
2367 /* Callee save registers. */
2368 else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15)
2369 || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15)
2370 || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8)
2371 || (regnum == FV0_REGNUM+3))
2372 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
2373
2374 /* Other registers. These are not in the ABI and may or may not
2375 mean anything in frames >0 so don't show them. */
2376 else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15)
2377 || (regnum == GBR_REGNUM)
2378 || (regnum == VBR_REGNUM)
2379 || (regnum == FPSCR_REGNUM)
2380 || (regnum == SSR_REGNUM)
2381 || (regnum == SPC_REGNUM))
2382 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2383 }
2384
2385 static struct sh_frame_cache *
2386 sh_alloc_frame_cache (void)
2387 {
2388 struct sh_frame_cache *cache;
2389 int i;
2390
2391 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
2392
2393 /* Base address. */
2394 cache->base = 0;
2395 cache->saved_sp = 0;
2396 cache->sp_offset = 0;
2397 cache->pc = 0;
2398
2399 /* Frameless until proven otherwise. */
2400 cache->uses_fp = 0;
2401
2402 /* Saved registers. We initialize these to -1 since zero is a valid
2403 offset (that's where fp is supposed to be stored). */
2404 for (i = 0; i < SH_NUM_REGS; i++)
2405 {
2406 cache->saved_regs[i] = -1;
2407 }
2408
2409 return cache;
2410 }
2411
2412 static struct sh_frame_cache *
2413 sh_frame_cache (struct frame_info *next_frame, void **this_cache)
2414 {
2415 struct sh_frame_cache *cache;
2416 CORE_ADDR current_pc;
2417 int i;
2418
2419 if (*this_cache)
2420 return *this_cache;
2421
2422 cache = sh_alloc_frame_cache ();
2423 *this_cache = cache;
2424
2425 /* In principle, for normal frames, fp holds the frame pointer,
2426 which holds the base address for the current stack frame.
2427 However, for functions that don't need it, the frame pointer is
2428 optional. For these "frameless" functions the frame pointer is
2429 actually the frame pointer of the calling frame. */
2430 cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM);
2431 if (cache->base == 0)
2432 return cache;
2433
2434 cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME);
2435 current_pc = frame_pc_unwind (next_frame);
2436 if (cache->pc != 0)
2437 {
2438 ULONGEST fpscr;
2439 fpscr = frame_unwind_register_unsigned (next_frame, FPSCR_REGNUM);
2440 sh_analyze_prologue (cache->pc, current_pc, cache, fpscr);
2441 }
2442
2443 if (!cache->uses_fp)
2444 {
2445 /* We didn't find a valid frame, which means that CACHE->base
2446 currently holds the frame pointer for our calling frame. If
2447 we're at the start of a function, or somewhere half-way its
2448 prologue, the function's frame probably hasn't been fully
2449 setup yet. Try to reconstruct the base address for the stack
2450 frame by looking at the stack pointer. For truly "frameless"
2451 functions this might work too. */
2452 cache->base = frame_unwind_register_unsigned
2453 (next_frame,
2454 gdbarch_sp_regnum (get_frame_arch (next_frame)));
2455 }
2456
2457 /* Now that we have the base address for the stack frame we can
2458 calculate the value of sp in the calling frame. */
2459 cache->saved_sp = cache->base + cache->sp_offset;
2460
2461 /* Adjust all the saved registers such that they contain addresses
2462 instead of offsets. */
2463 for (i = 0; i < SH_NUM_REGS; i++)
2464 if (cache->saved_regs[i] != -1)
2465 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
2466
2467 return cache;
2468 }
2469
2470 static void
2471 sh_frame_prev_register (struct frame_info *next_frame, void **this_cache,
2472 int regnum, int *optimizedp,
2473 enum lval_type *lvalp, CORE_ADDR *addrp,
2474 int *realnump, gdb_byte *valuep)
2475 {
2476 struct gdbarch *gdbarch = get_frame_arch (next_frame);
2477 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2478
2479 gdb_assert (regnum >= 0);
2480
2481 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
2482 {
2483 *optimizedp = 0;
2484 *lvalp = not_lval;
2485 *addrp = 0;
2486 *realnump = -1;
2487 if (valuep)
2488 {
2489 /* Store the value. */
2490 store_unsigned_integer (valuep, 4, cache->saved_sp);
2491 }
2492 return;
2493 }
2494
2495 /* The PC of the previous frame is stored in the PR register of
2496 the current frame. Frob regnum so that we pull the value from
2497 the correct place. */
2498 if (regnum == gdbarch_pc_regnum (gdbarch))
2499 regnum = PR_REGNUM;
2500
2501 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
2502 {
2503 *optimizedp = 0;
2504 *lvalp = lval_memory;
2505 *addrp = cache->saved_regs[regnum];
2506 *realnump = -1;
2507 if (valuep)
2508 {
2509 /* Read the value in from memory. */
2510 read_memory (*addrp, valuep,
2511 register_size (gdbarch, regnum));
2512 }
2513 return;
2514 }
2515
2516 *optimizedp = 0;
2517 *lvalp = lval_register;
2518 *addrp = 0;
2519 *realnump = regnum;
2520 if (valuep)
2521 frame_unwind_register (next_frame, (*realnump), valuep);
2522 }
2523
2524 static void
2525 sh_frame_this_id (struct frame_info *next_frame, void **this_cache,
2526 struct frame_id *this_id)
2527 {
2528 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2529
2530 /* This marks the outermost frame. */
2531 if (cache->base == 0)
2532 return;
2533
2534 *this_id = frame_id_build (cache->saved_sp, cache->pc);
2535 }
2536
2537 static const struct frame_unwind sh_frame_unwind = {
2538 NORMAL_FRAME,
2539 sh_frame_this_id,
2540 sh_frame_prev_register
2541 };
2542
2543 static const struct frame_unwind *
2544 sh_frame_sniffer (struct frame_info *next_frame)
2545 {
2546 return &sh_frame_unwind;
2547 }
2548
2549 static CORE_ADDR
2550 sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2551 {
2552 return frame_unwind_register_unsigned (next_frame,
2553 gdbarch_sp_regnum (gdbarch));
2554 }
2555
2556 static CORE_ADDR
2557 sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2558 {
2559 return frame_unwind_register_unsigned (next_frame,
2560 gdbarch_pc_regnum (gdbarch));
2561 }
2562
2563 static struct frame_id
2564 sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2565 {
2566 return frame_id_build (sh_unwind_sp (gdbarch, next_frame),
2567 frame_pc_unwind (next_frame));
2568 }
2569
2570 static CORE_ADDR
2571 sh_frame_base_address (struct frame_info *next_frame, void **this_cache)
2572 {
2573 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2574
2575 return cache->base;
2576 }
2577
2578 static const struct frame_base sh_frame_base = {
2579 &sh_frame_unwind,
2580 sh_frame_base_address,
2581 sh_frame_base_address,
2582 sh_frame_base_address
2583 };
2584
2585 /* The epilogue is defined here as the area at the end of a function,
2586 either on the `ret' instruction itself or after an instruction which
2587 destroys the function's stack frame. */
2588 static int
2589 sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2590 {
2591 CORE_ADDR func_addr = 0, func_end = 0;
2592
2593 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2594 {
2595 ULONGEST inst;
2596 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2597 for a nop and some fixed data (e.g. big offsets) which are
2598 unfortunately also treated as part of the function (which
2599 means, they are below func_end. */
2600 CORE_ADDR addr = func_end - 28;
2601 if (addr < func_addr + 4)
2602 addr = func_addr + 4;
2603 if (pc < addr)
2604 return 0;
2605
2606 /* First search forward until hitting an rts. */
2607 while (addr < func_end
2608 && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
2609 addr += 2;
2610 if (addr >= func_end)
2611 return 0;
2612
2613 /* At this point we should find a mov.l @r15+,r14 instruction,
2614 either before or after the rts. If not, then the function has
2615 probably no "normal" epilogue and we bail out here. */
2616 inst = read_memory_unsigned_integer (addr - 2, 2);
2617 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
2618 addr -= 2;
2619 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
2620 return 0;
2621
2622 inst = read_memory_unsigned_integer (addr - 2, 2);
2623
2624 /* Step over possible lds.l @r15+,macl. */
2625 if (IS_MACL_LDS (inst))
2626 {
2627 addr -= 2;
2628 inst = read_memory_unsigned_integer (addr - 2, 2);
2629 }
2630
2631 /* Step over possible lds.l @r15+,pr. */
2632 if (IS_LDS (inst))
2633 {
2634 addr -= 2;
2635 inst = read_memory_unsigned_integer (addr - 2, 2);
2636 }
2637
2638 /* Step over possible mov r14,r15. */
2639 if (IS_MOV_FP_SP (inst))
2640 {
2641 addr -= 2;
2642 inst = read_memory_unsigned_integer (addr - 2, 2);
2643 }
2644
2645 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2646 instructions. */
2647 while (addr > func_addr + 4
2648 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
2649 {
2650 addr -= 2;
2651 inst = read_memory_unsigned_integer (addr - 2, 2);
2652 }
2653
2654 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2655 That's allowed for the epilogue. */
2656 if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a
2657 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu)
2658 && addr > func_addr + 6
2659 && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2)))
2660 addr -= 4;
2661
2662 if (pc >= addr)
2663 return 1;
2664 }
2665 return 0;
2666 }
2667 \f
2668
2669 static struct gdbarch *
2670 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2671 {
2672 struct gdbarch *gdbarch;
2673
2674 sh_show_regs = sh_generic_show_regs;
2675 switch (info.bfd_arch_info->mach)
2676 {
2677 case bfd_mach_sh2e:
2678 sh_show_regs = sh2e_show_regs;
2679 break;
2680 case bfd_mach_sh2a:
2681 sh_show_regs = sh2a_show_regs;
2682 break;
2683 case bfd_mach_sh2a_nofpu:
2684 sh_show_regs = sh2a_nofpu_show_regs;
2685 break;
2686 case bfd_mach_sh_dsp:
2687 sh_show_regs = sh_dsp_show_regs;
2688 break;
2689
2690 case bfd_mach_sh3:
2691 sh_show_regs = sh3_show_regs;
2692 break;
2693
2694 case bfd_mach_sh3e:
2695 sh_show_regs = sh3e_show_regs;
2696 break;
2697
2698 case bfd_mach_sh3_dsp:
2699 case bfd_mach_sh4al_dsp:
2700 sh_show_regs = sh3_dsp_show_regs;
2701 break;
2702
2703 case bfd_mach_sh4:
2704 case bfd_mach_sh4a:
2705 sh_show_regs = sh4_show_regs;
2706 break;
2707
2708 case bfd_mach_sh4_nofpu:
2709 case bfd_mach_sh4a_nofpu:
2710 sh_show_regs = sh4_nofpu_show_regs;
2711 break;
2712
2713 case bfd_mach_sh5:
2714 sh_show_regs = sh64_show_regs;
2715 /* SH5 is handled entirely in sh64-tdep.c */
2716 return sh64_gdbarch_init (info, arches);
2717 }
2718
2719 /* If there is already a candidate, use it. */
2720 arches = gdbarch_list_lookup_by_info (arches, &info);
2721 if (arches != NULL)
2722 return arches->gdbarch;
2723
2724 /* None found, create a new architecture from the information
2725 provided. */
2726 gdbarch = gdbarch_alloc (&info, NULL);
2727
2728 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2729 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2730 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2731 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2732 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2733 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2734 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2735 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2736
2737 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
2738 set_gdbarch_sp_regnum (gdbarch, 15);
2739 set_gdbarch_pc_regnum (gdbarch, 16);
2740 set_gdbarch_fp0_regnum (gdbarch, -1);
2741 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2742
2743 set_gdbarch_register_type (gdbarch, sh_default_register_type);
2744 set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p);
2745
2746 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2747
2748 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2749 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2750
2751 set_gdbarch_return_value (gdbarch, sh_return_value_nofpu);
2752
2753 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2754 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2755
2756 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2757
2758 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2759
2760 set_gdbarch_frame_align (gdbarch, sh_frame_align);
2761 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2762 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2763 set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id);
2764 frame_base_set_default (gdbarch, &sh_frame_base);
2765
2766 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
2767
2768 dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg);
2769
2770 switch (info.bfd_arch_info->mach)
2771 {
2772 case bfd_mach_sh:
2773 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2774 break;
2775
2776 case bfd_mach_sh2:
2777 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2778 break;
2779
2780 case bfd_mach_sh2e:
2781 /* doubles on sh2e and sh3e are actually 4 byte. */
2782 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2783
2784 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
2785 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2786 set_gdbarch_fp0_regnum (gdbarch, 25);
2787 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2788 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2789 break;
2790
2791 case bfd_mach_sh2a:
2792 set_gdbarch_register_name (gdbarch, sh_sh2a_register_name);
2793 set_gdbarch_register_type (gdbarch, sh_sh2a_register_type);
2794 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2795
2796 set_gdbarch_fp0_regnum (gdbarch, 25);
2797 set_gdbarch_num_pseudo_regs (gdbarch, 9);
2798 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2799 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2800 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2801 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2802 break;
2803
2804 case bfd_mach_sh2a_nofpu:
2805 set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name);
2806 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2807
2808 set_gdbarch_num_pseudo_regs (gdbarch, 1);
2809 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2810 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2811 break;
2812
2813 case bfd_mach_sh_dsp:
2814 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2815 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2816 break;
2817
2818 case bfd_mach_sh3:
2819 case bfd_mach_sh3_nommu:
2820 case bfd_mach_sh2a_nofpu_or_sh3_nommu:
2821 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
2822 break;
2823
2824 case bfd_mach_sh3e:
2825 case bfd_mach_sh2a_or_sh3e:
2826 /* doubles on sh2e and sh3e are actually 4 byte. */
2827 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2828
2829 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
2830 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2831 set_gdbarch_fp0_regnum (gdbarch, 25);
2832 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2833 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2834 break;
2835
2836 case bfd_mach_sh3_dsp:
2837 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
2838 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2839 break;
2840
2841 case bfd_mach_sh4:
2842 case bfd_mach_sh4a:
2843 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
2844 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
2845 set_gdbarch_fp0_regnum (gdbarch, 25);
2846 set_gdbarch_num_pseudo_regs (gdbarch, 13);
2847 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2848 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2849 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2850 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2851 break;
2852
2853 case bfd_mach_sh4_nofpu:
2854 case bfd_mach_sh4a_nofpu:
2855 case bfd_mach_sh4_nommu_nofpu:
2856 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
2857 case bfd_mach_sh2a_or_sh4:
2858 set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
2859 break;
2860
2861 case bfd_mach_sh4al_dsp:
2862 set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
2863 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2864 break;
2865
2866 default:
2867 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2868 break;
2869 }
2870
2871 /* Hook in ABI-specific overrides, if they have been registered. */
2872 gdbarch_init_osabi (info, gdbarch);
2873
2874 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2875 frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer);
2876
2877 return gdbarch;
2878 }
2879
2880 extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
2881
2882 void
2883 _initialize_sh_tdep (void)
2884 {
2885 struct cmd_list_element *c;
2886
2887 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
2888
2889 add_com ("regs", class_vars, sh_show_regs_command, _("Print all registers"));
2890 }
GDB Binutils - Deliverables
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