1 /* Target dependent code for GDB on TI C6x systems.
3 Copyright (C) 2010-2021 Free Software Foundation, Inc.
4 Contributed by Andrew Jenner <andrew@codesourcery.com>
5 Contributed by Yao Qi <yao@codesourcery.com>
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "frame-unwind.h"
25 #include "frame-base.h"
26 #include "trad-frame.h"
27 #include "dwarf2/frame.h"
38 #include "arch-utils.h"
39 #include "glibc-tdep.h"
42 #include "tramp-frame.h"
43 #include "linux-tdep.h"
47 #include "tic6x-tdep.h"
49 #include "target-descriptions.h"
52 #define TIC6X_OPCODE_SIZE 4
53 #define TIC6X_FETCH_PACKET_SIZE 32
55 #define INST_S_BIT(INST) ((INST >> 1) & 1)
56 #define INST_X_BIT(INST) ((INST >> 12) & 1)
58 const gdb_byte tic6x_bkpt_illegal_opcode_be
[] = { 0x56, 0x45, 0x43, 0x14 };
59 const gdb_byte tic6x_bkpt_illegal_opcode_le
[] = { 0x14, 0x43, 0x45, 0x56 };
61 struct tic6x_unwind_cache
63 /* The frame's base, optionally used by the high-level debug info. */
66 /* The previous frame's inner most stack address. Used as this
67 frame ID's stack_addr. */
70 /* The address of the first instruction in this function */
73 /* Which register holds the return address for the frame. */
76 /* The offset of register saved on stack. If register is not saved, the
77 corresponding element is -1. */
78 CORE_ADDR reg_saved
[TIC6X_NUM_CORE_REGS
];
82 /* Name of TI C6x core registers. */
83 static const char *const tic6x_register_names
[] =
85 "A0", "A1", "A2", "A3", /* 0 1 2 3 */
86 "A4", "A5", "A6", "A7", /* 4 5 6 7 */
87 "A8", "A9", "A10", "A11", /* 8 9 10 11 */
88 "A12", "A13", "A14", "A15", /* 12 13 14 15 */
89 "B0", "B1", "B2", "B3", /* 16 17 18 19 */
90 "B4", "B5", "B6", "B7", /* 20 21 22 23 */
91 "B8", "B9", "B10", "B11", /* 24 25 26 27 */
92 "B12", "B13", "B14", "B15", /* 28 29 30 31 */
93 "CSR", "PC", /* 32 33 */
96 /* This array maps the arguments to the register number which passes argument
97 in function call according to C6000 ELF ABI. */
98 static const int arg_regs
[] = { 4, 20, 6, 22, 8, 24, 10, 26, 12, 28 };
100 /* This is the implementation of gdbarch method register_name. */
103 tic6x_register_name (struct gdbarch
*gdbarch
, int regno
)
108 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
109 return tdesc_register_name (gdbarch
, regno
);
110 else if (regno
>= ARRAY_SIZE (tic6x_register_names
))
113 return tic6x_register_names
[regno
];
116 /* This is the implementation of gdbarch method register_type. */
119 tic6x_register_type (struct gdbarch
*gdbarch
, int regno
)
122 if (regno
== TIC6X_PC_REGNUM
)
123 return builtin_type (gdbarch
)->builtin_func_ptr
;
125 return builtin_type (gdbarch
)->builtin_uint32
;
129 tic6x_setup_default (struct tic6x_unwind_cache
*cache
)
133 for (i
= 0; i
< TIC6X_NUM_CORE_REGS
; i
++)
134 cache
->reg_saved
[i
] = -1;
137 static unsigned long tic6x_fetch_instruction (struct gdbarch
*, CORE_ADDR
);
138 static int tic6x_register_number (int reg
, int side
, int crosspath
);
140 /* Do a full analysis of the prologue at START_PC and update CACHE accordingly.
141 Bail out early if CURRENT_PC is reached. Returns the address of the first
142 instruction after the prologue. */
145 tic6x_analyze_prologue (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
,
146 const CORE_ADDR current_pc
,
147 struct tic6x_unwind_cache
*cache
,
148 struct frame_info
*this_frame
)
150 unsigned int src_reg
, base_reg
, dst_reg
;
152 CORE_ADDR pc
= start_pc
;
153 CORE_ADDR return_pc
= start_pc
;
154 int frame_base_offset_to_sp
= 0;
155 /* Counter of non-stw instructions after first insn ` sub sp, xxx, sp'. */
156 int non_stw_insn_counter
= 0;
158 if (start_pc
>= current_pc
)
159 return_pc
= current_pc
;
163 /* The landmarks in prologue is one or two SUB instructions to SP.
164 Instructions on setting up dsbt are in the last part of prologue, if
165 needed. In maxim, prologue can be divided to three parts by two
166 `sub sp, xx, sp' insns. */
168 /* Step 1: Look for the 1st and 2nd insn `sub sp, xx, sp', in which, the
169 2nd one is optional. */
170 while (pc
< current_pc
)
172 unsigned long inst
= tic6x_fetch_instruction (gdbarch
, pc
);
174 if ((inst
& 0x1ffc) == 0x1dc0 || (inst
& 0x1ffc) == 0x1bc0
175 || (inst
& 0x0ffc) == 0x9c0)
177 /* SUBAW/SUBAH/SUB, and src1 is ucst 5. */
178 unsigned int src2
= tic6x_register_number ((inst
>> 18) & 0x1f,
179 INST_S_BIT (inst
), 0);
180 unsigned int dst
= tic6x_register_number ((inst
>> 23) & 0x1f,
181 INST_S_BIT (inst
), 0);
183 if (src2
== TIC6X_SP_REGNUM
&& dst
== TIC6X_SP_REGNUM
)
185 /* Extract const from insn SUBAW/SUBAH/SUB, and translate it to
186 offset. The constant offset is decoded in bit 13-17 in all
187 these three kinds of instructions. */
188 unsigned int ucst5
= (inst
>> 13) & 0x1f;
190 if ((inst
& 0x1ffc) == 0x1dc0) /* SUBAW */
191 frame_base_offset_to_sp
+= ucst5
<< 2;
192 else if ((inst
& 0x1ffc) == 0x1bc0) /* SUBAH */
193 frame_base_offset_to_sp
+= ucst5
<< 1;
194 else if ((inst
& 0x0ffc) == 0x9c0) /* SUB */
195 frame_base_offset_to_sp
+= ucst5
;
197 gdb_assert_not_reached ("unexpected instruction");
202 else if ((inst
& 0x174) == 0x74) /* stw SRC, *+b15(uconst) */
204 /* The y bit determines which file base is read from. */
205 base_reg
= tic6x_register_number ((inst
>> 18) & 0x1f,
208 if (base_reg
== TIC6X_SP_REGNUM
)
210 src_reg
= tic6x_register_number ((inst
>> 23) & 0x1f,
211 INST_S_BIT (inst
), 0);
213 cache
->reg_saved
[src_reg
] = ((inst
>> 13) & 0x1f) << 2;
217 non_stw_insn_counter
= 0;
221 non_stw_insn_counter
++;
222 /* Following instruction sequence may be emitted in prologue:
224 <+0>: subah .D2 b15,28,b15
225 <+4>: or .L2X 0,a4,b0
226 <+8>: || stw .D2T2 b14,*+b15(56)
227 <+12>:[!b0] b .S1 0xe50e4c1c <sleep+220>
228 <+16>:|| stw .D2T1 a10,*+b15(48)
229 <+20>:stw .D2T2 b3,*+b15(52)
230 <+24>:stw .D2T1 a4,*+b15(40)
232 we should look forward for next instruction instead of breaking loop
233 here. So far, we allow almost two sequential non-stw instructions
235 if (non_stw_insn_counter
>= 2)
242 /* Step 2: Skip insn on setting up dsbt if it is. Usually, it looks like,
243 ldw .D2T2 *+b14(0),b14 */
244 unsigned long inst
= tic6x_fetch_instruction (gdbarch
, pc
);
245 /* The s bit determines which file dst will be loaded into, same effect as
247 dst_reg
= tic6x_register_number ((inst
>> 23) & 0x1f, (inst
>> 1) & 1, 0);
248 /* The y bit (bit 7), instead of s bit, determines which file base be
250 base_reg
= tic6x_register_number ((inst
>> 18) & 0x1f, (inst
>> 7) & 1, 0);
252 if ((inst
& 0x164) == 0x64 /* ldw */
253 && dst_reg
== TIC6X_DP_REGNUM
/* dst is B14 */
254 && base_reg
== TIC6X_DP_REGNUM
) /* baseR is B14 */
261 cache
->base
= get_frame_register_unsigned (this_frame
, TIC6X_SP_REGNUM
);
263 if (cache
->reg_saved
[TIC6X_FP_REGNUM
] != -1)
265 /* If the FP now holds an offset from the CFA then this is a frame
266 which uses the frame pointer. */
268 cache
->cfa
= get_frame_register_unsigned (this_frame
,
273 /* FP doesn't hold an offset from the CFA. If SP still holds an
274 offset from the CFA then we might be in a function which omits
275 the frame pointer. */
277 cache
->cfa
= cache
->base
+ frame_base_offset_to_sp
;
281 /* Adjust all the saved registers such that they contain addresses
282 instead of offsets. */
283 for (i
= 0; i
< TIC6X_NUM_CORE_REGS
; i
++)
284 if (cache
->reg_saved
[i
] != -1)
285 cache
->reg_saved
[i
] = cache
->base
+ cache
->reg_saved
[i
];
290 /* This is the implementation of gdbarch method skip_prologue. */
293 tic6x_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
296 struct tic6x_unwind_cache cache
;
298 /* See if we can determine the end of the prologue via the symbol table.
299 If so, then return either PC, or the PC after the prologue, whichever is
301 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
303 CORE_ADDR post_prologue_pc
304 = skip_prologue_using_sal (gdbarch
, func_addr
);
305 if (post_prologue_pc
!= 0)
306 return std::max (start_pc
, post_prologue_pc
);
309 /* Can't determine prologue from the symbol table, need to examine
311 return tic6x_analyze_prologue (gdbarch
, start_pc
, (CORE_ADDR
) -1, &cache
,
315 /* Implement the breakpoint_kind_from_pc gdbarch method. */
318 tic6x_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
323 /* Implement the sw_breakpoint_from_kind gdbarch method. */
325 static const gdb_byte
*
326 tic6x_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
328 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
332 if (tdep
== NULL
|| tdep
->breakpoint
== NULL
)
334 if (BFD_ENDIAN_BIG
== gdbarch_byte_order_for_code (gdbarch
))
335 return tic6x_bkpt_illegal_opcode_be
;
337 return tic6x_bkpt_illegal_opcode_le
;
340 return tdep
->breakpoint
;
344 tic6x_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
345 struct dwarf2_frame_state_reg
*reg
,
346 struct frame_info
*this_frame
)
348 /* Mark the PC as the destination for the return address. */
349 if (regnum
== gdbarch_pc_regnum (gdbarch
))
350 reg
->how
= DWARF2_FRAME_REG_RA
;
352 /* Mark the stack pointer as the call frame address. */
353 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
354 reg
->how
= DWARF2_FRAME_REG_CFA
;
356 /* The above was taken from the default init_reg in dwarf2-frame.c
357 while the below is c6x specific. */
359 /* Callee save registers. The ABI designates A10-A15 and B10-B15 as
361 else if ((regnum
>= 10 && regnum
<= 15) || (regnum
>= 26 && regnum
<= 31))
362 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
364 /* All other registers are caller-save. */
365 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
368 /* This is the implementation of gdbarch method unwind_pc. */
371 tic6x_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
375 frame_unwind_register (next_frame
, TIC6X_PC_REGNUM
, buf
);
376 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
379 /* Frame base handling. */
381 static struct tic6x_unwind_cache
*
382 tic6x_frame_unwind_cache (struct frame_info
*this_frame
,
383 void **this_prologue_cache
)
385 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
386 CORE_ADDR current_pc
;
387 struct tic6x_unwind_cache
*cache
;
389 if (*this_prologue_cache
)
390 return (struct tic6x_unwind_cache
*) *this_prologue_cache
;
392 cache
= FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache
);
393 (*this_prologue_cache
) = cache
;
395 cache
->return_regnum
= TIC6X_RA_REGNUM
;
397 tic6x_setup_default (cache
);
399 cache
->pc
= get_frame_func (this_frame
);
400 current_pc
= get_frame_pc (this_frame
);
402 /* Prologue analysis does the rest... */
404 tic6x_analyze_prologue (gdbarch
, cache
->pc
, current_pc
, cache
, this_frame
);
410 tic6x_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
411 struct frame_id
*this_id
)
413 struct tic6x_unwind_cache
*cache
=
414 tic6x_frame_unwind_cache (this_frame
, this_cache
);
416 /* This marks the outermost frame. */
417 if (cache
->base
== 0)
420 (*this_id
) = frame_id_build (cache
->cfa
, cache
->pc
);
423 static struct value
*
424 tic6x_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
427 struct tic6x_unwind_cache
*cache
=
428 tic6x_frame_unwind_cache (this_frame
, this_cache
);
430 gdb_assert (regnum
>= 0);
432 /* The PC of the previous frame is stored in the RA register of
433 the current frame. Frob regnum so that we pull the value from
434 the correct place. */
435 if (regnum
== TIC6X_PC_REGNUM
)
436 regnum
= cache
->return_regnum
;
438 if (regnum
== TIC6X_SP_REGNUM
&& cache
->cfa
)
439 return frame_unwind_got_constant (this_frame
, regnum
, cache
->cfa
);
441 /* If we've worked out where a register is stored then load it from
443 if (regnum
< TIC6X_NUM_CORE_REGS
&& cache
->reg_saved
[regnum
] != -1)
444 return frame_unwind_got_memory (this_frame
, regnum
,
445 cache
->reg_saved
[regnum
]);
447 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
451 tic6x_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
453 struct tic6x_unwind_cache
*info
454 = tic6x_frame_unwind_cache (this_frame
, this_cache
);
458 static const struct frame_unwind tic6x_frame_unwind
=
462 default_frame_unwind_stop_reason
,
464 tic6x_frame_prev_register
,
466 default_frame_sniffer
469 static const struct frame_base tic6x_frame_base
=
472 tic6x_frame_base_address
,
473 tic6x_frame_base_address
,
474 tic6x_frame_base_address
478 static struct tic6x_unwind_cache
*
479 tic6x_make_stub_cache (struct frame_info
*this_frame
)
481 struct tic6x_unwind_cache
*cache
;
483 cache
= FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache
);
485 cache
->return_regnum
= TIC6X_RA_REGNUM
;
487 tic6x_setup_default (cache
);
489 cache
->cfa
= get_frame_register_unsigned (this_frame
, TIC6X_SP_REGNUM
);
495 tic6x_stub_this_id (struct frame_info
*this_frame
, void **this_cache
,
496 struct frame_id
*this_id
)
498 struct tic6x_unwind_cache
*cache
;
500 if (*this_cache
== NULL
)
501 *this_cache
= tic6x_make_stub_cache (this_frame
);
502 cache
= (struct tic6x_unwind_cache
*) *this_cache
;
504 *this_id
= frame_id_build (cache
->cfa
, get_frame_pc (this_frame
));
508 tic6x_stub_unwind_sniffer (const struct frame_unwind
*self
,
509 struct frame_info
*this_frame
,
510 void **this_prologue_cache
)
512 CORE_ADDR addr_in_block
;
514 addr_in_block
= get_frame_address_in_block (this_frame
);
515 if (in_plt_section (addr_in_block
))
521 static const struct frame_unwind tic6x_stub_unwind
=
525 default_frame_unwind_stop_reason
,
527 tic6x_frame_prev_register
,
529 tic6x_stub_unwind_sniffer
532 /* Return the instruction on address PC. */
535 tic6x_fetch_instruction (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
537 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
538 return read_memory_unsigned_integer (pc
, TIC6X_OPCODE_SIZE
, byte_order
);
541 /* Compute the condition of INST if it is a conditional instruction. Always
542 return 1 if INST is not a conditional instruction. */
545 tic6x_condition_true (struct regcache
*regcache
, unsigned long inst
)
549 static const int register_numbers
[8] = { -1, 16, 17, 18, 1, 2, 0, -1 };
551 register_number
= register_numbers
[(inst
>> 29) & 7];
552 if (register_number
== -1)
555 register_value
= regcache_raw_get_signed (regcache
, register_number
);
556 if ((inst
& 0x10000000) != 0)
557 return register_value
== 0;
558 return register_value
!= 0;
561 /* Get the register number by decoding raw bits REG, SIDE, and CROSSPATH in
565 tic6x_register_number (int reg
, int side
, int crosspath
)
567 int r
= (reg
& 15) | ((crosspath
^ side
) << 4);
568 if ((reg
& 16) != 0) /* A16 - A31, B16 - B31 */
574 tic6x_extract_signed_field (int value
, int low_bit
, int bits
)
576 int mask
= (1 << bits
) - 1;
577 int r
= (value
>> low_bit
) & mask
;
578 if ((r
& (1 << (bits
- 1))) != 0)
583 /* Determine where to set a single step breakpoint. */
586 tic6x_get_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
588 struct gdbarch
*gdbarch
= regcache
->arch ();
595 inst
= tic6x_fetch_instruction (gdbarch
, pc
);
599 if (inst
== TIC6X_INST_SWE
)
601 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
603 if (tdep
->syscall_next_pc
!= NULL
)
604 return tdep
->syscall_next_pc (get_current_frame ());
607 if (tic6x_condition_true (regcache
, inst
))
609 if ((inst
& 0x0000007c) == 0x00000010)
611 /* B with displacement */
612 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
613 pc
+= tic6x_extract_signed_field (inst
, 7, 21) << 2;
616 if ((inst
& 0x0f83effc) == 0x00000360)
618 /* B with register */
620 register_number
= tic6x_register_number ((inst
>> 18) & 0x1f,
623 pc
= regcache_raw_get_unsigned (regcache
, register_number
);
626 if ((inst
& 0x00001ffc) == 0x00001020)
629 register_number
= tic6x_register_number ((inst
>> 23) & 0x1f,
630 INST_S_BIT (inst
), 0);
631 if (regcache_raw_get_signed (regcache
, register_number
) >= 0)
633 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
634 pc
+= tic6x_extract_signed_field (inst
, 7, 10) << 2;
638 if ((inst
& 0x00001ffc) == 0x00000120)
640 /* BNOP with displacement */
641 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
642 pc
+= tic6x_extract_signed_field (inst
, 16, 12) << 2;
645 if ((inst
& 0x0f830ffe) == 0x00800362)
647 /* BNOP with register */
648 register_number
= tic6x_register_number ((inst
>> 18) & 0x1f,
649 1, INST_X_BIT (inst
));
650 pc
= regcache_raw_get_unsigned (regcache
, register_number
);
653 if ((inst
& 0x00001ffc) == 0x00000020)
656 register_number
= tic6x_register_number ((inst
>> 23) & 0x1f,
657 INST_S_BIT (inst
), 0);
658 if (regcache_raw_get_signed (regcache
, register_number
) >= 0)
660 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
661 pc
+= tic6x_extract_signed_field (inst
, 13, 10) << 2;
665 if ((inst
& 0xf000007c) == 0x10000010)
668 pc
&= ~(TIC6X_FETCH_PACKET_SIZE
- 1);
669 pc
+= tic6x_extract_signed_field (inst
, 7, 21) << 2;
673 pc
+= TIC6X_OPCODE_SIZE
;
679 /* This is the implementation of gdbarch method software_single_step. */
681 static std::vector
<CORE_ADDR
>
682 tic6x_software_single_step (struct regcache
*regcache
)
684 CORE_ADDR next_pc
= tic6x_get_next_pc (regcache
, regcache_read_pc (regcache
));
689 /* This is the implementation of gdbarch method frame_align. */
692 tic6x_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
694 return align_down (addr
, 8);
697 /* Given a return value in REGCACHE with a type VALTYPE, extract and copy its
698 value into VALBUF. */
701 tic6x_extract_return_value (struct type
*valtype
, struct regcache
*regcache
,
702 enum bfd_endian byte_order
, gdb_byte
*valbuf
)
704 int len
= TYPE_LENGTH (valtype
);
706 /* pointer types are returned in register A4,
707 up to 32-bit types in A4
708 up to 64-bit types in A5:A4 */
712 - one-byte structure or union occupies the LSB of single even register.
713 - for two-byte structure or union, the first byte occupies byte 1 of
714 register and the second byte occupies byte 0.
715 so, we read the contents in VAL from the LSBs of register. */
716 if (len
< 3 && byte_order
== BFD_ENDIAN_BIG
)
717 regcache
->cooked_read_part (TIC6X_A4_REGNUM
, 4 - len
, len
, valbuf
);
719 regcache
->cooked_read (TIC6X_A4_REGNUM
, valbuf
);
723 /* For a 5-8 byte structure or union in big-endian, the first byte
724 occupies byte 3 (the MSB) of the upper (odd) register and the
725 remaining bytes fill the decreasingly significant bytes. 5-7
726 byte structures or unions have padding in the LSBs of the
727 lower (even) register. */
728 if (byte_order
== BFD_ENDIAN_BIG
)
730 regcache
->cooked_read (TIC6X_A4_REGNUM
, valbuf
+ 4);
731 regcache
->cooked_read (TIC6X_A5_REGNUM
, valbuf
);
735 regcache
->cooked_read (TIC6X_A4_REGNUM
, valbuf
);
736 regcache
->cooked_read (TIC6X_A5_REGNUM
, valbuf
+ 4);
741 /* Write into appropriate registers a function return value
742 of type TYPE, given in virtual format. */
745 tic6x_store_return_value (struct type
*valtype
, struct regcache
*regcache
,
746 enum bfd_endian byte_order
, const gdb_byte
*valbuf
)
748 int len
= TYPE_LENGTH (valtype
);
750 /* return values of up to 8 bytes are returned in A5:A4 */
754 if (len
< 3 && byte_order
== BFD_ENDIAN_BIG
)
755 regcache
->cooked_write_part (TIC6X_A4_REGNUM
, 4 - len
, len
, valbuf
);
757 regcache
->cooked_write (TIC6X_A4_REGNUM
, valbuf
);
761 if (byte_order
== BFD_ENDIAN_BIG
)
763 regcache
->cooked_write (TIC6X_A4_REGNUM
, valbuf
+ 4);
764 regcache
->cooked_write (TIC6X_A5_REGNUM
, valbuf
);
768 regcache
->cooked_write (TIC6X_A4_REGNUM
, valbuf
);
769 regcache
->cooked_write (TIC6X_A5_REGNUM
, valbuf
+ 4);
774 /* This is the implementation of gdbarch method return_value. */
776 static enum return_value_convention
777 tic6x_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
778 struct type
*type
, struct regcache
*regcache
,
779 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
781 /* In C++, when function returns an object, even its size is small
782 enough, it stii has to be passed via reference, pointed by register
784 if (current_language
->la_language
== language_cplus
)
788 type
= check_typedef (type
);
789 if (!(language_pass_by_reference (type
).trivially_copyable
))
790 return RETURN_VALUE_STRUCT_CONVENTION
;
794 if (TYPE_LENGTH (type
) > 8)
795 return RETURN_VALUE_STRUCT_CONVENTION
;
798 tic6x_extract_return_value (type
, regcache
,
799 gdbarch_byte_order (gdbarch
), readbuf
);
801 tic6x_store_return_value (type
, regcache
,
802 gdbarch_byte_order (gdbarch
), writebuf
);
804 return RETURN_VALUE_REGISTER_CONVENTION
;
807 /* Get the alignment requirement of TYPE. */
810 tic6x_arg_type_alignment (struct type
*type
)
812 int len
= TYPE_LENGTH (check_typedef (type
));
813 enum type_code typecode
= check_typedef (type
)->code ();
815 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
817 /* The stack alignment of a structure (and union) passed by value is the
818 smallest power of two greater than or equal to its size.
819 This cannot exceed 8 bytes, which is the largest allowable size for
820 a structure passed by value. */
829 gdb_assert_not_reached ("unexpected length of data");
837 if (typecode
== TYPE_CODE_COMPLEX
)
844 if (typecode
== TYPE_CODE_COMPLEX
)
850 internal_error (__FILE__
, __LINE__
, _("unexpected length %d of type"),
855 /* This is the implementation of gdbarch method push_dummy_call. */
858 tic6x_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
859 struct regcache
*regcache
, CORE_ADDR bp_addr
,
860 int nargs
, struct value
**args
, CORE_ADDR sp
,
861 function_call_return_method return_method
,
862 CORE_ADDR struct_addr
)
866 int stack_offset
= 4;
867 int references_offset
= 4;
868 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
869 struct type
*func_type
= value_type (function
);
870 /* The first arg passed on stack. Mostly the first 10 args are passed by
872 int first_arg_on_stack
= 10;
874 /* Set the return address register to point to the entry point of
875 the program, where a breakpoint lies in wait. */
876 regcache_cooked_write_unsigned (regcache
, TIC6X_RA_REGNUM
, bp_addr
);
878 /* The caller must pass an argument in A3 containing a destination address
879 for the returned value. The callee returns the object by copying it to
880 the address in A3. */
881 if (return_method
== return_method_struct
)
882 regcache_cooked_write_unsigned (regcache
, 3, struct_addr
);
884 /* Determine the type of this function. */
885 func_type
= check_typedef (func_type
);
886 if (func_type
->code () == TYPE_CODE_PTR
)
887 func_type
= check_typedef (TYPE_TARGET_TYPE (func_type
));
889 gdb_assert (func_type
->code () == TYPE_CODE_FUNC
890 || func_type
->code () == TYPE_CODE_METHOD
);
892 /* For a variadic C function, the last explicitly declared argument and all
893 remaining arguments are passed on the stack. */
894 if (func_type
->has_varargs ())
895 first_arg_on_stack
= func_type
->num_fields () - 1;
897 /* Now make space on the stack for the args. */
898 for (argnum
= 0; argnum
< nargs
; argnum
++)
900 int len
= align_up (TYPE_LENGTH (value_type (args
[argnum
])), 4);
901 if (argnum
>= 10 - argreg
)
902 references_offset
+= len
;
906 /* SP should be 8-byte aligned, see C6000 ABI section 4.4.1
908 sp
= align_down (sp
, 8);
911 /* Now load as many as possible of the first arguments into
912 registers, and push the rest onto the stack. Loop through args
913 from first to last. */
914 for (argnum
= 0; argnum
< nargs
; argnum
++)
917 struct value
*arg
= args
[argnum
];
918 struct type
*arg_type
= check_typedef (value_type (arg
));
919 int len
= TYPE_LENGTH (arg_type
);
920 enum type_code typecode
= arg_type
->code ();
922 val
= value_contents (arg
);
924 /* Copy the argument to general registers or the stack in
925 register-sized pieces. */
926 if (argreg
< first_arg_on_stack
)
930 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
933 - one-byte structure or union occupies the LSB of single
935 - for two-byte structure or union, the first byte
936 occupies byte 1 of register and the second byte occupies
938 so, we write the contents in VAL to the lsp of
940 if (len
< 3 && byte_order
== BFD_ENDIAN_BIG
)
941 regcache
->cooked_write_part (arg_regs
[argreg
], 4 - len
, len
,
944 regcache
->cooked_write (arg_regs
[argreg
], val
);
948 /* The argument is being passed by value in a single
950 CORE_ADDR regval
= extract_unsigned_integer (val
, len
,
953 regcache_cooked_write_unsigned (regcache
, arg_regs
[argreg
],
961 if (typecode
== TYPE_CODE_STRUCT
962 || typecode
== TYPE_CODE_UNION
)
964 /* For a 5-8 byte structure or union in big-endian, the
965 first byte occupies byte 3 (the MSB) of the upper (odd)
966 register and the remaining bytes fill the decreasingly
967 significant bytes. 5-7 byte structures or unions have
968 padding in the LSBs of the lower (even) register. */
969 if (byte_order
== BFD_ENDIAN_BIG
)
971 regcache
->cooked_write (arg_regs
[argreg
] + 1, val
);
972 regcache
->cooked_write_part (arg_regs
[argreg
], 0,
977 regcache
->cooked_write (arg_regs
[argreg
], val
);
978 regcache
->cooked_write_part (arg_regs
[argreg
] + 1, 0,
984 /* The argument is being passed by value in a pair of
986 ULONGEST regval
= extract_unsigned_integer (val
, len
,
989 regcache_cooked_write_unsigned (regcache
,
992 regcache_cooked_write_unsigned (regcache
,
993 arg_regs
[argreg
] + 1,
999 /* The argument is being passed by reference in a single
1003 /* It is not necessary to adjust REFERENCES_OFFSET to
1004 8-byte aligned in some cases, in which 4-byte alignment
1005 is sufficient. For simplicity, we adjust
1006 REFERENCES_OFFSET to 8-byte aligned. */
1007 references_offset
= align_up (references_offset
, 8);
1009 addr
= sp
+ references_offset
;
1010 write_memory (addr
, val
, len
);
1011 references_offset
+= align_up (len
, 4);
1012 regcache_cooked_write_unsigned (regcache
, arg_regs
[argreg
],
1020 /* The argument is being passed on the stack. */
1023 /* There are six different cases of alignment, and these rules can
1024 be found in tic6x_arg_type_alignment:
1026 1) 4-byte aligned if size is less than or equal to 4 byte, such
1027 as short, int, struct, union etc.
1028 2) 8-byte aligned if size is less than or equal to 8-byte, such
1029 as double, long long,
1030 3) 4-byte aligned if it is of type _Complex float, even its size
1032 4) 8-byte aligned if it is of type _Complex double or _Complex
1033 long double, even its size is 16-byte. Because, the address of
1034 variable is passed as reference.
1035 5) struct and union larger than 8-byte are passed by reference, so
1036 it is 4-byte aligned.
1037 6) struct and union of size between 4 byte and 8 byte varies.
1038 alignment of struct variable is the alignment of its first field,
1039 while alignment of union variable is the max of all its fields'
1043 ; /* Default is 4-byte aligned. Nothing to be done. */
1045 stack_offset
= align_up (stack_offset
,
1046 tic6x_arg_type_alignment (arg_type
));
1049 /* _Complex double or _Complex long double */
1050 if (typecode
== TYPE_CODE_COMPLEX
)
1052 /* The argument is being passed by reference on stack. */
1053 references_offset
= align_up (references_offset
, 8);
1055 addr
= sp
+ references_offset
;
1056 /* Store variable on stack. */
1057 write_memory (addr
, val
, len
);
1059 references_offset
+= align_up (len
, 4);
1061 /* Pass the address of variable on stack as reference. */
1062 store_unsigned_integer ((gdb_byte
*) val
, 4, byte_order
,
1068 internal_error (__FILE__
, __LINE__
,
1069 _("unexpected type %d of arg %d"),
1073 internal_error (__FILE__
, __LINE__
,
1074 _("unexpected length %d of arg %d"), len
, argnum
);
1076 addr
= sp
+ stack_offset
;
1077 write_memory (addr
, val
, len
);
1078 stack_offset
+= align_up (len
, 4);
1082 regcache_cooked_write_signed (regcache
, TIC6X_SP_REGNUM
, sp
);
1084 /* Return adjusted stack pointer. */
1088 /* This is the implementation of gdbarch method stack_frame_destroyed_p. */
1091 tic6x_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1093 unsigned long inst
= tic6x_fetch_instruction (gdbarch
, pc
);
1094 /* Normally, the epilogue is composed by instruction `b .S2 b3'. */
1095 if ((inst
& 0x0f83effc) == 0x360)
1097 unsigned int src2
= tic6x_register_number ((inst
>> 18) & 0x1f,
1100 if (src2
== TIC6X_RA_REGNUM
)
1107 /* This is the implementation of gdbarch method get_longjmp_target. */
1110 tic6x_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
1112 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1113 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1117 /* JMP_BUF is passed by reference in A4. */
1118 jb_addr
= get_frame_register_unsigned (frame
, 4);
1120 /* JMP_BUF contains 13 elements of type int, and return address is stored
1121 in the last slot. */
1122 if (target_read_memory (jb_addr
+ 12 * 4, buf
, 4))
1125 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
1130 /* This is the implementation of gdbarch method
1131 return_in_first_hidden_param_p. */
1134 tic6x_return_in_first_hidden_param_p (struct gdbarch
*gdbarch
,
1140 static struct gdbarch
*
1141 tic6x_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1143 struct gdbarch
*gdbarch
;
1144 struct gdbarch_tdep
*tdep
;
1145 tdesc_arch_data_up tdesc_data
;
1146 const struct target_desc
*tdesc
= info
.target_desc
;
1149 /* Check any target description for validity. */
1150 if (tdesc_has_registers (tdesc
))
1152 const struct tdesc_feature
*feature
;
1155 feature
= tdesc_find_feature (tdesc
, "org.gnu.gdb.tic6x.core");
1157 if (feature
== NULL
)
1160 tdesc_data
= tdesc_data_alloc ();
1163 for (i
= 0; i
< 32; i
++) /* A0 - A15, B0 - B15 */
1164 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (), i
,
1165 tic6x_register_names
[i
]);
1168 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (), i
++,
1169 tic6x_register_names
[TIC6X_CSR_REGNUM
]);
1170 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (), i
++,
1171 tic6x_register_names
[TIC6X_PC_REGNUM
]);
1176 feature
= tdesc_find_feature (tdesc
, "org.gnu.gdb.tic6x.gp");
1180 static const char *const gp
[] =
1182 "A16", "A17", "A18", "A19", "A20", "A21", "A22", "A23",
1183 "A24", "A25", "A26", "A27", "A28", "A29", "A30", "A31",
1184 "B16", "B17", "B18", "B19", "B20", "B21", "B22", "B23",
1185 "B24", "B25", "B26", "B27", "B28", "B29", "B30", "B31",
1190 for (j
= 0; j
< 32; j
++) /* A16 - A31, B16 - B31 */
1191 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
1198 feature
= tdesc_find_feature (tdesc
, "org.gnu.gdb.tic6x.c6xp");
1201 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
1203 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
1205 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
1214 /* Find a candidate among extant architectures. */
1215 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1217 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
1219 tdep
= gdbarch_tdep (arches
->gdbarch
);
1221 if (has_gp
!= tdep
->has_gp
)
1224 if (tdep
&& tdep
->breakpoint
)
1225 return arches
->gdbarch
;
1228 tdep
= XCNEW (struct gdbarch_tdep
);
1230 tdep
->has_gp
= has_gp
;
1231 gdbarch
= gdbarch_alloc (&info
, tdep
);
1233 /* Data type sizes. */
1234 set_gdbarch_ptr_bit (gdbarch
, 32);
1235 set_gdbarch_addr_bit (gdbarch
, 32);
1236 set_gdbarch_short_bit (gdbarch
, 16);
1237 set_gdbarch_int_bit (gdbarch
, 32);
1238 set_gdbarch_long_bit (gdbarch
, 32);
1239 set_gdbarch_long_long_bit (gdbarch
, 64);
1240 set_gdbarch_float_bit (gdbarch
, 32);
1241 set_gdbarch_double_bit (gdbarch
, 64);
1243 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
1244 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
1246 /* The register set. */
1247 set_gdbarch_num_regs (gdbarch
, TIC6X_NUM_REGS
);
1248 set_gdbarch_sp_regnum (gdbarch
, TIC6X_SP_REGNUM
);
1249 set_gdbarch_pc_regnum (gdbarch
, TIC6X_PC_REGNUM
);
1251 set_gdbarch_register_name (gdbarch
, tic6x_register_name
);
1252 set_gdbarch_register_type (gdbarch
, tic6x_register_type
);
1254 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1256 set_gdbarch_skip_prologue (gdbarch
, tic6x_skip_prologue
);
1257 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
1258 tic6x_breakpoint_kind_from_pc
);
1259 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
1260 tic6x_sw_breakpoint_from_kind
);
1262 set_gdbarch_unwind_pc (gdbarch
, tic6x_unwind_pc
);
1265 dwarf2_append_unwinders (gdbarch
);
1267 frame_unwind_append_unwinder (gdbarch
, &tic6x_stub_unwind
);
1268 frame_unwind_append_unwinder (gdbarch
, &tic6x_frame_unwind
);
1269 frame_base_set_default (gdbarch
, &tic6x_frame_base
);
1271 dwarf2_frame_set_init_reg (gdbarch
, tic6x_dwarf2_frame_init_reg
);
1273 /* Single stepping. */
1274 set_gdbarch_software_single_step (gdbarch
, tic6x_software_single_step
);
1276 /* Call dummy code. */
1277 set_gdbarch_frame_align (gdbarch
, tic6x_frame_align
);
1279 set_gdbarch_return_value (gdbarch
, tic6x_return_value
);
1281 /* Enable inferior call support. */
1282 set_gdbarch_push_dummy_call (gdbarch
, tic6x_push_dummy_call
);
1284 set_gdbarch_get_longjmp_target (gdbarch
, tic6x_get_longjmp_target
);
1286 set_gdbarch_stack_frame_destroyed_p (gdbarch
, tic6x_stack_frame_destroyed_p
);
1288 set_gdbarch_return_in_first_hidden_param_p (gdbarch
,
1289 tic6x_return_in_first_hidden_param_p
);
1291 /* Hook in ABI-specific overrides, if they have been registered. */
1292 gdbarch_init_osabi (info
, gdbarch
);
1294 if (tdesc_data
!= nullptr)
1295 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
));
1300 void _initialize_tic6x_tdep ();
1302 _initialize_tic6x_tdep ()
1304 register_gdbarch_init (bfd_arch_tic6x
, tic6x_gdbarch_init
);