1 /* GNU/Linux/AArch64 specific low level interface, for the remote server for
4 Copyright (C) 2009-2020 Free Software Foundation, Inc.
5 Contributed by ARM Ltd.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "linux-low.h"
24 #include "nat/aarch64-linux.h"
25 #include "nat/aarch64-linux-hw-point.h"
26 #include "arch/aarch64-insn.h"
27 #include "linux-aarch32-low.h"
28 #include "elf/common.h"
30 #include "tracepoint.h"
35 #include "nat/gdb_ptrace.h"
36 #include <asm/ptrace.h>
41 #include "gdb_proc_service.h"
42 #include "arch/aarch64.h"
43 #include "linux-aarch32-tdesc.h"
44 #include "linux-aarch64-tdesc.h"
45 #include "nat/aarch64-sve-linux-ptrace.h"
52 /* Linux target op definitions for the AArch64 architecture. */
54 class aarch64_target
: public linux_process_target
58 const regs_info
*get_regs_info () override
;
60 int breakpoint_kind_from_pc (CORE_ADDR
*pcptr
) override
;
62 int breakpoint_kind_from_current_state (CORE_ADDR
*pcptr
) override
;
64 const gdb_byte
*sw_breakpoint_from_kind (int kind
, int *size
) override
;
66 bool supports_z_point_type (char z_type
) override
;
68 bool supports_tracepoints () override
;
70 bool supports_fast_tracepoints () override
;
72 int install_fast_tracepoint_jump_pad
73 (CORE_ADDR tpoint
, CORE_ADDR tpaddr
, CORE_ADDR collector
,
74 CORE_ADDR lockaddr
, ULONGEST orig_size
, CORE_ADDR
*jump_entry
,
75 CORE_ADDR
*trampoline
, ULONGEST
*trampoline_size
,
76 unsigned char *jjump_pad_insn
, ULONGEST
*jjump_pad_insn_size
,
77 CORE_ADDR
*adjusted_insn_addr
, CORE_ADDR
*adjusted_insn_addr_end
,
80 int get_min_fast_tracepoint_insn_len () override
;
82 struct emit_ops
*emit_ops () override
;
86 void low_arch_setup () override
;
88 bool low_cannot_fetch_register (int regno
) override
;
90 bool low_cannot_store_register (int regno
) override
;
92 bool low_supports_breakpoints () override
;
94 CORE_ADDR
low_get_pc (regcache
*regcache
) override
;
96 void low_set_pc (regcache
*regcache
, CORE_ADDR newpc
) override
;
98 bool low_breakpoint_at (CORE_ADDR pc
) override
;
100 int low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
101 int size
, raw_breakpoint
*bp
) override
;
103 int low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
104 int size
, raw_breakpoint
*bp
) override
;
106 bool low_stopped_by_watchpoint () override
;
108 CORE_ADDR
low_stopped_data_address () override
;
110 bool low_siginfo_fixup (siginfo_t
*native
, gdb_byte
*inf
,
111 int direction
) override
;
113 arch_process_info
*low_new_process () override
;
115 void low_delete_process (arch_process_info
*info
) override
;
117 void low_new_thread (lwp_info
*) override
;
119 void low_delete_thread (arch_lwp_info
*) override
;
121 void low_new_fork (process_info
*parent
, process_info
*child
) override
;
123 void low_prepare_to_resume (lwp_info
*lwp
) override
;
125 int low_get_thread_area (int lwpid
, CORE_ADDR
*addrp
) override
;
128 /* The singleton target ops object. */
130 static aarch64_target the_aarch64_target
;
133 aarch64_target::low_cannot_fetch_register (int regno
)
135 gdb_assert_not_reached ("linux target op low_cannot_fetch_register "
136 "is not implemented by the target");
140 aarch64_target::low_cannot_store_register (int regno
)
142 gdb_assert_not_reached ("linux target op low_cannot_store_register "
143 "is not implemented by the target");
147 aarch64_target::low_prepare_to_resume (lwp_info
*lwp
)
149 aarch64_linux_prepare_to_resume (lwp
);
152 /* Per-process arch-specific data we want to keep. */
154 struct arch_process_info
156 /* Hardware breakpoint/watchpoint data.
157 The reason for them to be per-process rather than per-thread is
158 due to the lack of information in the gdbserver environment;
159 gdbserver is not told that whether a requested hardware
160 breakpoint/watchpoint is thread specific or not, so it has to set
161 each hw bp/wp for every thread in the current process. The
162 higher level bp/wp management in gdb will resume a thread if a hw
163 bp/wp trap is not expected for it. Since the hw bp/wp setting is
164 same for each thread, it is reasonable for the data to live here.
166 struct aarch64_debug_reg_state debug_reg_state
;
169 /* Return true if the size of register 0 is 8 byte. */
172 is_64bit_tdesc (void)
174 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
176 return register_size (regcache
->tdesc
, 0) == 8;
179 /* Return true if the regcache contains the number of SVE registers. */
184 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
186 return tdesc_contains_feature (regcache
->tdesc
, "org.gnu.gdb.aarch64.sve");
190 aarch64_fill_gregset (struct regcache
*regcache
, void *buf
)
192 struct user_pt_regs
*regset
= (struct user_pt_regs
*) buf
;
195 for (i
= 0; i
< AARCH64_X_REGS_NUM
; i
++)
196 collect_register (regcache
, AARCH64_X0_REGNUM
+ i
, ®set
->regs
[i
]);
197 collect_register (regcache
, AARCH64_SP_REGNUM
, ®set
->sp
);
198 collect_register (regcache
, AARCH64_PC_REGNUM
, ®set
->pc
);
199 collect_register (regcache
, AARCH64_CPSR_REGNUM
, ®set
->pstate
);
203 aarch64_store_gregset (struct regcache
*regcache
, const void *buf
)
205 const struct user_pt_regs
*regset
= (const struct user_pt_regs
*) buf
;
208 for (i
= 0; i
< AARCH64_X_REGS_NUM
; i
++)
209 supply_register (regcache
, AARCH64_X0_REGNUM
+ i
, ®set
->regs
[i
]);
210 supply_register (regcache
, AARCH64_SP_REGNUM
, ®set
->sp
);
211 supply_register (regcache
, AARCH64_PC_REGNUM
, ®set
->pc
);
212 supply_register (regcache
, AARCH64_CPSR_REGNUM
, ®set
->pstate
);
216 aarch64_fill_fpregset (struct regcache
*regcache
, void *buf
)
218 struct user_fpsimd_state
*regset
= (struct user_fpsimd_state
*) buf
;
221 for (i
= 0; i
< AARCH64_V_REGS_NUM
; i
++)
222 collect_register (regcache
, AARCH64_V0_REGNUM
+ i
, ®set
->vregs
[i
]);
223 collect_register (regcache
, AARCH64_FPSR_REGNUM
, ®set
->fpsr
);
224 collect_register (regcache
, AARCH64_FPCR_REGNUM
, ®set
->fpcr
);
228 aarch64_store_fpregset (struct regcache
*regcache
, const void *buf
)
230 const struct user_fpsimd_state
*regset
231 = (const struct user_fpsimd_state
*) buf
;
234 for (i
= 0; i
< AARCH64_V_REGS_NUM
; i
++)
235 supply_register (regcache
, AARCH64_V0_REGNUM
+ i
, ®set
->vregs
[i
]);
236 supply_register (regcache
, AARCH64_FPSR_REGNUM
, ®set
->fpsr
);
237 supply_register (regcache
, AARCH64_FPCR_REGNUM
, ®set
->fpcr
);
240 /* Store the pauth registers to regcache. */
243 aarch64_store_pauthregset (struct regcache
*regcache
, const void *buf
)
245 uint64_t *pauth_regset
= (uint64_t *) buf
;
246 int pauth_base
= find_regno (regcache
->tdesc
, "pauth_dmask");
251 supply_register (regcache
, AARCH64_PAUTH_DMASK_REGNUM (pauth_base
),
253 supply_register (regcache
, AARCH64_PAUTH_CMASK_REGNUM (pauth_base
),
258 aarch64_target::low_supports_breakpoints ()
263 /* Implementation of linux target ops method "low_get_pc". */
266 aarch64_target::low_get_pc (regcache
*regcache
)
268 if (register_size (regcache
->tdesc
, 0) == 8)
269 return linux_get_pc_64bit (regcache
);
271 return linux_get_pc_32bit (regcache
);
274 /* Implementation of linux target ops method "low_set_pc". */
277 aarch64_target::low_set_pc (regcache
*regcache
, CORE_ADDR pc
)
279 if (register_size (regcache
->tdesc
, 0) == 8)
280 linux_set_pc_64bit (regcache
, pc
);
282 linux_set_pc_32bit (regcache
, pc
);
285 #define aarch64_breakpoint_len 4
287 /* AArch64 BRK software debug mode instruction.
288 This instruction needs to match gdb/aarch64-tdep.c
289 (aarch64_default_breakpoint). */
290 static const gdb_byte aarch64_breakpoint
[] = {0x00, 0x00, 0x20, 0xd4};
292 /* Implementation of linux target ops method "low_breakpoint_at". */
295 aarch64_target::low_breakpoint_at (CORE_ADDR where
)
297 if (is_64bit_tdesc ())
299 gdb_byte insn
[aarch64_breakpoint_len
];
301 read_memory (where
, (unsigned char *) &insn
, aarch64_breakpoint_len
);
302 if (memcmp (insn
, aarch64_breakpoint
, aarch64_breakpoint_len
) == 0)
308 return arm_breakpoint_at (where
);
312 aarch64_init_debug_reg_state (struct aarch64_debug_reg_state
*state
)
316 for (i
= 0; i
< AARCH64_HBP_MAX_NUM
; ++i
)
318 state
->dr_addr_bp
[i
] = 0;
319 state
->dr_ctrl_bp
[i
] = 0;
320 state
->dr_ref_count_bp
[i
] = 0;
323 for (i
= 0; i
< AARCH64_HWP_MAX_NUM
; ++i
)
325 state
->dr_addr_wp
[i
] = 0;
326 state
->dr_ctrl_wp
[i
] = 0;
327 state
->dr_ref_count_wp
[i
] = 0;
331 /* Return the pointer to the debug register state structure in the
332 current process' arch-specific data area. */
334 struct aarch64_debug_reg_state
*
335 aarch64_get_debug_reg_state (pid_t pid
)
337 struct process_info
*proc
= find_process_pid (pid
);
339 return &proc
->priv
->arch_private
->debug_reg_state
;
342 /* Implementation of target ops method "supports_z_point_type". */
345 aarch64_target::supports_z_point_type (char z_type
)
351 case Z_PACKET_WRITE_WP
:
352 case Z_PACKET_READ_WP
:
353 case Z_PACKET_ACCESS_WP
:
360 /* Implementation of linux target ops method "low_insert_point".
362 It actually only records the info of the to-be-inserted bp/wp;
363 the actual insertion will happen when threads are resumed. */
366 aarch64_target::low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
367 int len
, raw_breakpoint
*bp
)
370 enum target_hw_bp_type targ_type
;
371 struct aarch64_debug_reg_state
*state
372 = aarch64_get_debug_reg_state (pid_of (current_thread
));
375 fprintf (stderr
, "insert_point on entry (addr=0x%08lx, len=%d)\n",
376 (unsigned long) addr
, len
);
378 /* Determine the type from the raw breakpoint type. */
379 targ_type
= raw_bkpt_type_to_target_hw_bp_type (type
);
381 if (targ_type
!= hw_execute
)
383 if (aarch64_linux_region_ok_for_watchpoint (addr
, len
))
384 ret
= aarch64_handle_watchpoint (targ_type
, addr
, len
,
385 1 /* is_insert */, state
);
393 /* LEN is 3 means the breakpoint is set on a 32-bit thumb
394 instruction. Set it to 2 to correctly encode length bit
395 mask in hardware/watchpoint control register. */
398 ret
= aarch64_handle_breakpoint (targ_type
, addr
, len
,
399 1 /* is_insert */, state
);
403 aarch64_show_debug_reg_state (state
, "insert_point", addr
, len
,
409 /* Implementation of linux target ops method "low_remove_point".
411 It actually only records the info of the to-be-removed bp/wp,
412 the actual removal will be done when threads are resumed. */
415 aarch64_target::low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
416 int len
, raw_breakpoint
*bp
)
419 enum target_hw_bp_type targ_type
;
420 struct aarch64_debug_reg_state
*state
421 = aarch64_get_debug_reg_state (pid_of (current_thread
));
424 fprintf (stderr
, "remove_point on entry (addr=0x%08lx, len=%d)\n",
425 (unsigned long) addr
, len
);
427 /* Determine the type from the raw breakpoint type. */
428 targ_type
= raw_bkpt_type_to_target_hw_bp_type (type
);
430 /* Set up state pointers. */
431 if (targ_type
!= hw_execute
)
433 aarch64_handle_watchpoint (targ_type
, addr
, len
, 0 /* is_insert */,
439 /* LEN is 3 means the breakpoint is set on a 32-bit thumb
440 instruction. Set it to 2 to correctly encode length bit
441 mask in hardware/watchpoint control register. */
444 ret
= aarch64_handle_breakpoint (targ_type
, addr
, len
,
445 0 /* is_insert */, state
);
449 aarch64_show_debug_reg_state (state
, "remove_point", addr
, len
,
455 /* Implementation of linux target ops method "low_stopped_data_address". */
458 aarch64_target::low_stopped_data_address ()
462 struct aarch64_debug_reg_state
*state
;
464 pid
= lwpid_of (current_thread
);
466 /* Get the siginfo. */
467 if (ptrace (PTRACE_GETSIGINFO
, pid
, NULL
, &siginfo
) != 0)
468 return (CORE_ADDR
) 0;
470 /* Need to be a hardware breakpoint/watchpoint trap. */
471 if (siginfo
.si_signo
!= SIGTRAP
472 || (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
473 return (CORE_ADDR
) 0;
475 /* Check if the address matches any watched address. */
476 state
= aarch64_get_debug_reg_state (pid_of (current_thread
));
477 for (i
= aarch64_num_wp_regs
- 1; i
>= 0; --i
)
479 const unsigned int offset
480 = aarch64_watchpoint_offset (state
->dr_ctrl_wp
[i
]);
481 const unsigned int len
= aarch64_watchpoint_length (state
->dr_ctrl_wp
[i
]);
482 const CORE_ADDR addr_trap
= (CORE_ADDR
) siginfo
.si_addr
;
483 const CORE_ADDR addr_watch
= state
->dr_addr_wp
[i
] + offset
;
484 const CORE_ADDR addr_watch_aligned
= align_down (state
->dr_addr_wp
[i
], 8);
485 const CORE_ADDR addr_orig
= state
->dr_addr_orig_wp
[i
];
487 if (state
->dr_ref_count_wp
[i
]
488 && DR_CONTROL_ENABLED (state
->dr_ctrl_wp
[i
])
489 && addr_trap
>= addr_watch_aligned
490 && addr_trap
< addr_watch
+ len
)
492 /* ADDR_TRAP reports the first address of the memory range
493 accessed by the CPU, regardless of what was the memory
494 range watched. Thus, a large CPU access that straddles
495 the ADDR_WATCH..ADDR_WATCH+LEN range may result in an
496 ADDR_TRAP that is lower than the
497 ADDR_WATCH..ADDR_WATCH+LEN range. E.g.:
499 addr: | 4 | 5 | 6 | 7 | 8 |
500 |---- range watched ----|
501 |----------- range accessed ------------|
503 In this case, ADDR_TRAP will be 4.
505 To match a watchpoint known to GDB core, we must never
506 report *ADDR_P outside of any ADDR_WATCH..ADDR_WATCH+LEN
507 range. ADDR_WATCH <= ADDR_TRAP < ADDR_ORIG is a false
508 positive on kernels older than 4.10. See PR
514 return (CORE_ADDR
) 0;
517 /* Implementation of linux target ops method "low_stopped_by_watchpoint". */
520 aarch64_target::low_stopped_by_watchpoint ()
522 return (low_stopped_data_address () != 0);
525 /* Fetch the thread-local storage pointer for libthread_db. */
528 ps_get_thread_area (struct ps_prochandle
*ph
,
529 lwpid_t lwpid
, int idx
, void **base
)
531 return aarch64_ps_get_thread_area (ph
, lwpid
, idx
, base
,
535 /* Implementation of linux target ops method "low_siginfo_fixup". */
538 aarch64_target::low_siginfo_fixup (siginfo_t
*native
, gdb_byte
*inf
,
541 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */
542 if (!is_64bit_tdesc ())
545 aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo
*) inf
,
548 aarch64_siginfo_from_compat_siginfo (native
,
549 (struct compat_siginfo
*) inf
);
557 /* Implementation of linux target ops method "low_new_process". */
560 aarch64_target::low_new_process ()
562 struct arch_process_info
*info
= XCNEW (struct arch_process_info
);
564 aarch64_init_debug_reg_state (&info
->debug_reg_state
);
569 /* Implementation of linux target ops method "low_delete_process". */
572 aarch64_target::low_delete_process (arch_process_info
*info
)
578 aarch64_target::low_new_thread (lwp_info
*lwp
)
580 aarch64_linux_new_thread (lwp
);
584 aarch64_target::low_delete_thread (arch_lwp_info
*arch_lwp
)
586 aarch64_linux_delete_thread (arch_lwp
);
589 /* Implementation of linux target ops method "low_new_fork". */
592 aarch64_target::low_new_fork (process_info
*parent
,
595 /* These are allocated by linux_add_process. */
596 gdb_assert (parent
->priv
!= NULL
597 && parent
->priv
->arch_private
!= NULL
);
598 gdb_assert (child
->priv
!= NULL
599 && child
->priv
->arch_private
!= NULL
);
601 /* Linux kernel before 2.6.33 commit
602 72f674d203cd230426437cdcf7dd6f681dad8b0d
603 will inherit hardware debug registers from parent
604 on fork/vfork/clone. Newer Linux kernels create such tasks with
605 zeroed debug registers.
607 GDB core assumes the child inherits the watchpoints/hw
608 breakpoints of the parent, and will remove them all from the
609 forked off process. Copy the debug registers mirrors into the
610 new process so that all breakpoints and watchpoints can be
611 removed together. The debug registers mirror will become zeroed
612 in the end before detaching the forked off process, thus making
613 this compatible with older Linux kernels too. */
615 *child
->priv
->arch_private
= *parent
->priv
->arch_private
;
618 /* Matches HWCAP_PACA in kernel header arch/arm64/include/uapi/asm/hwcap.h. */
619 #define AARCH64_HWCAP_PACA (1 << 30)
621 /* Implementation of linux target ops method "low_arch_setup". */
624 aarch64_target::low_arch_setup ()
626 unsigned int machine
;
630 tid
= lwpid_of (current_thread
);
632 is_elf64
= linux_pid_exe_is_elf_64_file (tid
, &machine
);
636 uint64_t vq
= aarch64_sve_get_vq (tid
);
637 unsigned long hwcap
= linux_get_hwcap (8);
638 bool pauth_p
= hwcap
& AARCH64_HWCAP_PACA
;
640 current_process ()->tdesc
= aarch64_linux_read_description (vq
, pauth_p
);
643 current_process ()->tdesc
= aarch32_linux_read_description ();
645 aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread
));
648 /* Wrapper for aarch64_sve_regs_copy_to_reg_buf. */
651 aarch64_sve_regs_copy_to_regcache (struct regcache
*regcache
, const void *buf
)
653 return aarch64_sve_regs_copy_to_reg_buf (regcache
, buf
);
656 /* Wrapper for aarch64_sve_regs_copy_from_reg_buf. */
659 aarch64_sve_regs_copy_from_regcache (struct regcache
*regcache
, void *buf
)
661 return aarch64_sve_regs_copy_from_reg_buf (regcache
, buf
);
664 static struct regset_info aarch64_regsets
[] =
666 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PRSTATUS
,
667 sizeof (struct user_pt_regs
), GENERAL_REGS
,
668 aarch64_fill_gregset
, aarch64_store_gregset
},
669 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_FPREGSET
,
670 sizeof (struct user_fpsimd_state
), FP_REGS
,
671 aarch64_fill_fpregset
, aarch64_store_fpregset
673 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_ARM_PAC_MASK
,
674 AARCH64_PAUTH_REGS_SIZE
, OPTIONAL_REGS
,
675 NULL
, aarch64_store_pauthregset
},
679 static struct regsets_info aarch64_regsets_info
=
681 aarch64_regsets
, /* regsets */
683 NULL
, /* disabled_regsets */
686 static struct regs_info regs_info_aarch64
=
688 NULL
, /* regset_bitmap */
690 &aarch64_regsets_info
,
693 static struct regset_info aarch64_sve_regsets
[] =
695 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PRSTATUS
,
696 sizeof (struct user_pt_regs
), GENERAL_REGS
,
697 aarch64_fill_gregset
, aarch64_store_gregset
},
698 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_ARM_SVE
,
699 SVE_PT_SIZE (AARCH64_MAX_SVE_VQ
, SVE_PT_REGS_SVE
), EXTENDED_REGS
,
700 aarch64_sve_regs_copy_from_regcache
, aarch64_sve_regs_copy_to_regcache
702 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_ARM_PAC_MASK
,
703 AARCH64_PAUTH_REGS_SIZE
, OPTIONAL_REGS
,
704 NULL
, aarch64_store_pauthregset
},
708 static struct regsets_info aarch64_sve_regsets_info
=
710 aarch64_sve_regsets
, /* regsets. */
711 0, /* num_regsets. */
712 NULL
, /* disabled_regsets. */
715 static struct regs_info regs_info_aarch64_sve
=
717 NULL
, /* regset_bitmap. */
719 &aarch64_sve_regsets_info
,
722 /* Implementation of linux target ops method "get_regs_info". */
725 aarch64_target::get_regs_info ()
727 if (!is_64bit_tdesc ())
728 return ®s_info_aarch32
;
731 return ®s_info_aarch64_sve
;
733 return ®s_info_aarch64
;
736 /* Implementation of target ops method "supports_tracepoints". */
739 aarch64_target::supports_tracepoints ()
741 if (current_thread
== NULL
)
745 /* We don't support tracepoints on aarch32 now. */
746 return is_64bit_tdesc ();
750 /* Implementation of linux target ops method "low_get_thread_area". */
753 aarch64_target::low_get_thread_area (int lwpid
, CORE_ADDR
*addrp
)
758 iovec
.iov_base
= ®
;
759 iovec
.iov_len
= sizeof (reg
);
761 if (ptrace (PTRACE_GETREGSET
, lwpid
, NT_ARM_TLS
, &iovec
) != 0)
769 /* Implementation of linux_target_ops method "get_syscall_trapinfo". */
772 aarch64_get_syscall_trapinfo (struct regcache
*regcache
, int *sysno
)
774 int use_64bit
= register_size (regcache
->tdesc
, 0) == 8;
780 collect_register_by_name (regcache
, "x8", &l_sysno
);
781 *sysno
= (int) l_sysno
;
784 collect_register_by_name (regcache
, "r7", sysno
);
787 /* List of condition codes that we need. */
789 enum aarch64_condition_codes
800 enum aarch64_operand_type
806 /* Representation of an operand. At this time, it only supports register
807 and immediate types. */
809 struct aarch64_operand
811 /* Type of the operand. */
812 enum aarch64_operand_type type
;
814 /* Value of the operand according to the type. */
818 struct aarch64_register reg
;
822 /* List of registers that we are currently using, we can add more here as
823 we need to use them. */
825 /* General purpose scratch registers (64 bit). */
826 static const struct aarch64_register x0
= { 0, 1 };
827 static const struct aarch64_register x1
= { 1, 1 };
828 static const struct aarch64_register x2
= { 2, 1 };
829 static const struct aarch64_register x3
= { 3, 1 };
830 static const struct aarch64_register x4
= { 4, 1 };
832 /* General purpose scratch registers (32 bit). */
833 static const struct aarch64_register w0
= { 0, 0 };
834 static const struct aarch64_register w2
= { 2, 0 };
836 /* Intra-procedure scratch registers. */
837 static const struct aarch64_register ip0
= { 16, 1 };
839 /* Special purpose registers. */
840 static const struct aarch64_register fp
= { 29, 1 };
841 static const struct aarch64_register lr
= { 30, 1 };
842 static const struct aarch64_register sp
= { 31, 1 };
843 static const struct aarch64_register xzr
= { 31, 1 };
845 /* Dynamically allocate a new register. If we know the register
846 statically, we should make it a global as above instead of using this
849 static struct aarch64_register
850 aarch64_register (unsigned num
, int is64
)
852 return (struct aarch64_register
) { num
, is64
};
855 /* Helper function to create a register operand, for instructions with
856 different types of operands.
859 p += emit_mov (p, x0, register_operand (x1)); */
861 static struct aarch64_operand
862 register_operand (struct aarch64_register reg
)
864 struct aarch64_operand operand
;
866 operand
.type
= OPERAND_REGISTER
;
872 /* Helper function to create an immediate operand, for instructions with
873 different types of operands.
876 p += emit_mov (p, x0, immediate_operand (12)); */
878 static struct aarch64_operand
879 immediate_operand (uint32_t imm
)
881 struct aarch64_operand operand
;
883 operand
.type
= OPERAND_IMMEDIATE
;
889 /* Helper function to create an offset memory operand.
892 p += emit_ldr (p, x0, sp, offset_memory_operand (16)); */
894 static struct aarch64_memory_operand
895 offset_memory_operand (int32_t offset
)
897 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_OFFSET
, offset
};
900 /* Helper function to create a pre-index memory operand.
903 p += emit_ldr (p, x0, sp, preindex_memory_operand (16)); */
905 static struct aarch64_memory_operand
906 preindex_memory_operand (int32_t index
)
908 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_PREINDEX
, index
};
911 /* Helper function to create a post-index memory operand.
914 p += emit_ldr (p, x0, sp, postindex_memory_operand (16)); */
916 static struct aarch64_memory_operand
917 postindex_memory_operand (int32_t index
)
919 return (struct aarch64_memory_operand
) { MEMORY_OPERAND_POSTINDEX
, index
};
922 /* System control registers. These special registers can be written and
923 read with the MRS and MSR instructions.
925 - NZCV: Condition flags. GDB refers to this register under the CPSR
927 - FPSR: Floating-point status register.
928 - FPCR: Floating-point control registers.
929 - TPIDR_EL0: Software thread ID register. */
931 enum aarch64_system_control_registers
933 /* op0 op1 crn crm op2 */
934 NZCV
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x2 << 3) | 0x0,
935 FPSR
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x1,
936 FPCR
= (0x1 << 14) | (0x3 << 11) | (0x4 << 7) | (0x4 << 3) | 0x0,
937 TPIDR_EL0
= (0x1 << 14) | (0x3 << 11) | (0xd << 7) | (0x0 << 3) | 0x2
940 /* Write a BLR instruction into *BUF.
944 RN is the register to branch to. */
947 emit_blr (uint32_t *buf
, struct aarch64_register rn
)
949 return aarch64_emit_insn (buf
, BLR
| ENCODE (rn
.num
, 5, 5));
952 /* Write a RET instruction into *BUF.
956 RN is the register to branch to. */
959 emit_ret (uint32_t *buf
, struct aarch64_register rn
)
961 return aarch64_emit_insn (buf
, RET
| ENCODE (rn
.num
, 5, 5));
965 emit_load_store_pair (uint32_t *buf
, enum aarch64_opcodes opcode
,
966 struct aarch64_register rt
,
967 struct aarch64_register rt2
,
968 struct aarch64_register rn
,
969 struct aarch64_memory_operand operand
)
976 opc
= ENCODE (2, 2, 30);
978 opc
= ENCODE (0, 2, 30);
980 switch (operand
.type
)
982 case MEMORY_OPERAND_OFFSET
:
984 pre_index
= ENCODE (1, 1, 24);
985 write_back
= ENCODE (0, 1, 23);
988 case MEMORY_OPERAND_POSTINDEX
:
990 pre_index
= ENCODE (0, 1, 24);
991 write_back
= ENCODE (1, 1, 23);
994 case MEMORY_OPERAND_PREINDEX
:
996 pre_index
= ENCODE (1, 1, 24);
997 write_back
= ENCODE (1, 1, 23);
1004 return aarch64_emit_insn (buf
, opcode
| opc
| pre_index
| write_back
1005 | ENCODE (operand
.index
>> 3, 7, 15)
1006 | ENCODE (rt2
.num
, 5, 10)
1007 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
.num
, 5, 0));
1010 /* Write a STP instruction into *BUF.
1012 STP rt, rt2, [rn, #offset]
1013 STP rt, rt2, [rn, #index]!
1014 STP rt, rt2, [rn], #index
1016 RT and RT2 are the registers to store.
1017 RN is the base address register.
1018 OFFSET is the immediate to add to the base address. It is limited to a
1019 -512 .. 504 range (7 bits << 3). */
1022 emit_stp (uint32_t *buf
, struct aarch64_register rt
,
1023 struct aarch64_register rt2
, struct aarch64_register rn
,
1024 struct aarch64_memory_operand operand
)
1026 return emit_load_store_pair (buf
, STP
, rt
, rt2
, rn
, operand
);
1029 /* Write a LDP instruction into *BUF.
1031 LDP rt, rt2, [rn, #offset]
1032 LDP rt, rt2, [rn, #index]!
1033 LDP rt, rt2, [rn], #index
1035 RT and RT2 are the registers to store.
1036 RN is the base address register.
1037 OFFSET is the immediate to add to the base address. It is limited to a
1038 -512 .. 504 range (7 bits << 3). */
1041 emit_ldp (uint32_t *buf
, struct aarch64_register rt
,
1042 struct aarch64_register rt2
, struct aarch64_register rn
,
1043 struct aarch64_memory_operand operand
)
1045 return emit_load_store_pair (buf
, LDP
, rt
, rt2
, rn
, operand
);
1048 /* Write a LDP (SIMD&VFP) instruction using Q registers into *BUF.
1050 LDP qt, qt2, [rn, #offset]
1052 RT and RT2 are the Q registers to store.
1053 RN is the base address register.
1054 OFFSET is the immediate to add to the base address. It is limited to
1055 -1024 .. 1008 range (7 bits << 4). */
1058 emit_ldp_q_offset (uint32_t *buf
, unsigned rt
, unsigned rt2
,
1059 struct aarch64_register rn
, int32_t offset
)
1061 uint32_t opc
= ENCODE (2, 2, 30);
1062 uint32_t pre_index
= ENCODE (1, 1, 24);
1064 return aarch64_emit_insn (buf
, LDP_SIMD_VFP
| opc
| pre_index
1065 | ENCODE (offset
>> 4, 7, 15)
1066 | ENCODE (rt2
, 5, 10)
1067 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
, 5, 0));
1070 /* Write a STP (SIMD&VFP) instruction using Q registers into *BUF.
1072 STP qt, qt2, [rn, #offset]
1074 RT and RT2 are the Q registers to store.
1075 RN is the base address register.
1076 OFFSET is the immediate to add to the base address. It is limited to
1077 -1024 .. 1008 range (7 bits << 4). */
1080 emit_stp_q_offset (uint32_t *buf
, unsigned rt
, unsigned rt2
,
1081 struct aarch64_register rn
, int32_t offset
)
1083 uint32_t opc
= ENCODE (2, 2, 30);
1084 uint32_t pre_index
= ENCODE (1, 1, 24);
1086 return aarch64_emit_insn (buf
, STP_SIMD_VFP
| opc
| pre_index
1087 | ENCODE (offset
>> 4, 7, 15)
1088 | ENCODE (rt2
, 5, 10)
1089 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
, 5, 0));
1092 /* Write a LDRH instruction into *BUF.
1094 LDRH wt, [xn, #offset]
1095 LDRH wt, [xn, #index]!
1096 LDRH wt, [xn], #index
1098 RT is the register to store.
1099 RN is the base address register.
1100 OFFSET is the immediate to add to the base address. It is limited to
1101 0 .. 32760 range (12 bits << 3). */
1104 emit_ldrh (uint32_t *buf
, struct aarch64_register rt
,
1105 struct aarch64_register rn
,
1106 struct aarch64_memory_operand operand
)
1108 return aarch64_emit_load_store (buf
, 1, LDR
, rt
, rn
, operand
);
1111 /* Write a LDRB instruction into *BUF.
1113 LDRB wt, [xn, #offset]
1114 LDRB wt, [xn, #index]!
1115 LDRB wt, [xn], #index
1117 RT is the register to store.
1118 RN is the base address register.
1119 OFFSET is the immediate to add to the base address. It is limited to
1120 0 .. 32760 range (12 bits << 3). */
1123 emit_ldrb (uint32_t *buf
, struct aarch64_register rt
,
1124 struct aarch64_register rn
,
1125 struct aarch64_memory_operand operand
)
1127 return aarch64_emit_load_store (buf
, 0, LDR
, rt
, rn
, operand
);
1132 /* Write a STR instruction into *BUF.
1134 STR rt, [rn, #offset]
1135 STR rt, [rn, #index]!
1136 STR rt, [rn], #index
1138 RT is the register to store.
1139 RN is the base address register.
1140 OFFSET is the immediate to add to the base address. It is limited to
1141 0 .. 32760 range (12 bits << 3). */
1144 emit_str (uint32_t *buf
, struct aarch64_register rt
,
1145 struct aarch64_register rn
,
1146 struct aarch64_memory_operand operand
)
1148 return aarch64_emit_load_store (buf
, rt
.is64
? 3 : 2, STR
, rt
, rn
, operand
);
1151 /* Helper function emitting an exclusive load or store instruction. */
1154 emit_load_store_exclusive (uint32_t *buf
, uint32_t size
,
1155 enum aarch64_opcodes opcode
,
1156 struct aarch64_register rs
,
1157 struct aarch64_register rt
,
1158 struct aarch64_register rt2
,
1159 struct aarch64_register rn
)
1161 return aarch64_emit_insn (buf
, opcode
| ENCODE (size
, 2, 30)
1162 | ENCODE (rs
.num
, 5, 16) | ENCODE (rt2
.num
, 5, 10)
1163 | ENCODE (rn
.num
, 5, 5) | ENCODE (rt
.num
, 5, 0));
1166 /* Write a LAXR instruction into *BUF.
1170 RT is the destination register.
1171 RN is the base address register. */
1174 emit_ldaxr (uint32_t *buf
, struct aarch64_register rt
,
1175 struct aarch64_register rn
)
1177 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, LDAXR
, xzr
, rt
,
1181 /* Write a STXR instruction into *BUF.
1185 RS is the result register, it indicates if the store succeeded or not.
1186 RT is the destination register.
1187 RN is the base address register. */
1190 emit_stxr (uint32_t *buf
, struct aarch64_register rs
,
1191 struct aarch64_register rt
, struct aarch64_register rn
)
1193 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, STXR
, rs
, rt
,
1197 /* Write a STLR instruction into *BUF.
1201 RT is the register to store.
1202 RN is the base address register. */
1205 emit_stlr (uint32_t *buf
, struct aarch64_register rt
,
1206 struct aarch64_register rn
)
1208 return emit_load_store_exclusive (buf
, rt
.is64
? 3 : 2, STLR
, xzr
, rt
,
1212 /* Helper function for data processing instructions with register sources. */
1215 emit_data_processing_reg (uint32_t *buf
, uint32_t opcode
,
1216 struct aarch64_register rd
,
1217 struct aarch64_register rn
,
1218 struct aarch64_register rm
)
1220 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1222 return aarch64_emit_insn (buf
, opcode
| size
| ENCODE (rm
.num
, 5, 16)
1223 | ENCODE (rn
.num
, 5, 5) | ENCODE (rd
.num
, 5, 0));
1226 /* Helper function for data processing instructions taking either a register
1230 emit_data_processing (uint32_t *buf
, enum aarch64_opcodes opcode
,
1231 struct aarch64_register rd
,
1232 struct aarch64_register rn
,
1233 struct aarch64_operand operand
)
1235 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1236 /* The opcode is different for register and immediate source operands. */
1237 uint32_t operand_opcode
;
1239 if (operand
.type
== OPERAND_IMMEDIATE
)
1241 /* xxx1 000x xxxx xxxx xxxx xxxx xxxx xxxx */
1242 operand_opcode
= ENCODE (8, 4, 25);
1244 return aarch64_emit_insn (buf
, opcode
| operand_opcode
| size
1245 | ENCODE (operand
.imm
, 12, 10)
1246 | ENCODE (rn
.num
, 5, 5)
1247 | ENCODE (rd
.num
, 5, 0));
1251 /* xxx0 101x xxxx xxxx xxxx xxxx xxxx xxxx */
1252 operand_opcode
= ENCODE (5, 4, 25);
1254 return emit_data_processing_reg (buf
, opcode
| operand_opcode
, rd
,
1259 /* Write an ADD instruction into *BUF.
1264 This function handles both an immediate and register add.
1266 RD is the destination register.
1267 RN is the input register.
1268 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
1269 OPERAND_REGISTER. */
1272 emit_add (uint32_t *buf
, struct aarch64_register rd
,
1273 struct aarch64_register rn
, struct aarch64_operand operand
)
1275 return emit_data_processing (buf
, ADD
, rd
, rn
, operand
);
1278 /* Write a SUB instruction into *BUF.
1283 This function handles both an immediate and register sub.
1285 RD is the destination register.
1286 RN is the input register.
1287 IMM is the immediate to substract to RN. */
1290 emit_sub (uint32_t *buf
, struct aarch64_register rd
,
1291 struct aarch64_register rn
, struct aarch64_operand operand
)
1293 return emit_data_processing (buf
, SUB
, rd
, rn
, operand
);
1296 /* Write a MOV instruction into *BUF.
1301 This function handles both a wide immediate move and a register move,
1302 with the condition that the source register is not xzr. xzr and the
1303 stack pointer share the same encoding and this function only supports
1306 RD is the destination register.
1307 OPERAND is the source operand, either of type OPERAND_IMMEDIATE or
1308 OPERAND_REGISTER. */
1311 emit_mov (uint32_t *buf
, struct aarch64_register rd
,
1312 struct aarch64_operand operand
)
1314 if (operand
.type
== OPERAND_IMMEDIATE
)
1316 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1317 /* Do not shift the immediate. */
1318 uint32_t shift
= ENCODE (0, 2, 21);
1320 return aarch64_emit_insn (buf
, MOV
| size
| shift
1321 | ENCODE (operand
.imm
, 16, 5)
1322 | ENCODE (rd
.num
, 5, 0));
1325 return emit_add (buf
, rd
, operand
.reg
, immediate_operand (0));
1328 /* Write a MOVK instruction into *BUF.
1330 MOVK rd, #imm, lsl #shift
1332 RD is the destination register.
1333 IMM is the immediate.
1334 SHIFT is the logical shift left to apply to IMM. */
1337 emit_movk (uint32_t *buf
, struct aarch64_register rd
, uint32_t imm
,
1340 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1342 return aarch64_emit_insn (buf
, MOVK
| size
| ENCODE (shift
, 2, 21) |
1343 ENCODE (imm
, 16, 5) | ENCODE (rd
.num
, 5, 0));
1346 /* Write instructions into *BUF in order to move ADDR into a register.
1347 ADDR can be a 64-bit value.
1349 This function will emit a series of MOV and MOVK instructions, such as:
1352 MOVK xd, #(addr >> 16), lsl #16
1353 MOVK xd, #(addr >> 32), lsl #32
1354 MOVK xd, #(addr >> 48), lsl #48 */
1357 emit_mov_addr (uint32_t *buf
, struct aarch64_register rd
, CORE_ADDR addr
)
1361 /* The MOV (wide immediate) instruction clears to top bits of the
1363 p
+= emit_mov (p
, rd
, immediate_operand (addr
& 0xffff));
1365 if ((addr
>> 16) != 0)
1366 p
+= emit_movk (p
, rd
, (addr
>> 16) & 0xffff, 1);
1370 if ((addr
>> 32) != 0)
1371 p
+= emit_movk (p
, rd
, (addr
>> 32) & 0xffff, 2);
1375 if ((addr
>> 48) != 0)
1376 p
+= emit_movk (p
, rd
, (addr
>> 48) & 0xffff, 3);
1381 /* Write a SUBS instruction into *BUF.
1385 This instruction update the condition flags.
1387 RD is the destination register.
1388 RN and RM are the source registers. */
1391 emit_subs (uint32_t *buf
, struct aarch64_register rd
,
1392 struct aarch64_register rn
, struct aarch64_operand operand
)
1394 return emit_data_processing (buf
, SUBS
, rd
, rn
, operand
);
1397 /* Write a CMP instruction into *BUF.
1401 This instruction is an alias of SUBS xzr, rn, rm.
1403 RN and RM are the registers to compare. */
1406 emit_cmp (uint32_t *buf
, struct aarch64_register rn
,
1407 struct aarch64_operand operand
)
1409 return emit_subs (buf
, xzr
, rn
, operand
);
1412 /* Write a AND instruction into *BUF.
1416 RD is the destination register.
1417 RN and RM are the source registers. */
1420 emit_and (uint32_t *buf
, struct aarch64_register rd
,
1421 struct aarch64_register rn
, struct aarch64_register rm
)
1423 return emit_data_processing_reg (buf
, AND
, rd
, rn
, rm
);
1426 /* Write a ORR instruction into *BUF.
1430 RD is the destination register.
1431 RN and RM are the source registers. */
1434 emit_orr (uint32_t *buf
, struct aarch64_register rd
,
1435 struct aarch64_register rn
, struct aarch64_register rm
)
1437 return emit_data_processing_reg (buf
, ORR
, rd
, rn
, rm
);
1440 /* Write a ORN instruction into *BUF.
1444 RD is the destination register.
1445 RN and RM are the source registers. */
1448 emit_orn (uint32_t *buf
, struct aarch64_register rd
,
1449 struct aarch64_register rn
, struct aarch64_register rm
)
1451 return emit_data_processing_reg (buf
, ORN
, rd
, rn
, rm
);
1454 /* Write a EOR instruction into *BUF.
1458 RD is the destination register.
1459 RN and RM are the source registers. */
1462 emit_eor (uint32_t *buf
, struct aarch64_register rd
,
1463 struct aarch64_register rn
, struct aarch64_register rm
)
1465 return emit_data_processing_reg (buf
, EOR
, rd
, rn
, rm
);
1468 /* Write a MVN instruction into *BUF.
1472 This is an alias for ORN rd, xzr, rm.
1474 RD is the destination register.
1475 RM is the source register. */
1478 emit_mvn (uint32_t *buf
, struct aarch64_register rd
,
1479 struct aarch64_register rm
)
1481 return emit_orn (buf
, rd
, xzr
, rm
);
1484 /* Write a LSLV instruction into *BUF.
1488 RD is the destination register.
1489 RN and RM are the source registers. */
1492 emit_lslv (uint32_t *buf
, struct aarch64_register rd
,
1493 struct aarch64_register rn
, struct aarch64_register rm
)
1495 return emit_data_processing_reg (buf
, LSLV
, rd
, rn
, rm
);
1498 /* Write a LSRV instruction into *BUF.
1502 RD is the destination register.
1503 RN and RM are the source registers. */
1506 emit_lsrv (uint32_t *buf
, struct aarch64_register rd
,
1507 struct aarch64_register rn
, struct aarch64_register rm
)
1509 return emit_data_processing_reg (buf
, LSRV
, rd
, rn
, rm
);
1512 /* Write a ASRV instruction into *BUF.
1516 RD is the destination register.
1517 RN and RM are the source registers. */
1520 emit_asrv (uint32_t *buf
, struct aarch64_register rd
,
1521 struct aarch64_register rn
, struct aarch64_register rm
)
1523 return emit_data_processing_reg (buf
, ASRV
, rd
, rn
, rm
);
1526 /* Write a MUL instruction into *BUF.
1530 RD is the destination register.
1531 RN and RM are the source registers. */
1534 emit_mul (uint32_t *buf
, struct aarch64_register rd
,
1535 struct aarch64_register rn
, struct aarch64_register rm
)
1537 return emit_data_processing_reg (buf
, MUL
, rd
, rn
, rm
);
1540 /* Write a MRS instruction into *BUF. The register size is 64-bit.
1544 RT is the destination register.
1545 SYSTEM_REG is special purpose register to read. */
1548 emit_mrs (uint32_t *buf
, struct aarch64_register rt
,
1549 enum aarch64_system_control_registers system_reg
)
1551 return aarch64_emit_insn (buf
, MRS
| ENCODE (system_reg
, 15, 5)
1552 | ENCODE (rt
.num
, 5, 0));
1555 /* Write a MSR instruction into *BUF. The register size is 64-bit.
1559 SYSTEM_REG is special purpose register to write.
1560 RT is the input register. */
1563 emit_msr (uint32_t *buf
, enum aarch64_system_control_registers system_reg
,
1564 struct aarch64_register rt
)
1566 return aarch64_emit_insn (buf
, MSR
| ENCODE (system_reg
, 15, 5)
1567 | ENCODE (rt
.num
, 5, 0));
1570 /* Write a SEVL instruction into *BUF.
1572 This is a hint instruction telling the hardware to trigger an event. */
1575 emit_sevl (uint32_t *buf
)
1577 return aarch64_emit_insn (buf
, SEVL
);
1580 /* Write a WFE instruction into *BUF.
1582 This is a hint instruction telling the hardware to wait for an event. */
1585 emit_wfe (uint32_t *buf
)
1587 return aarch64_emit_insn (buf
, WFE
);
1590 /* Write a SBFM instruction into *BUF.
1592 SBFM rd, rn, #immr, #imms
1594 This instruction moves the bits from #immr to #imms into the
1595 destination, sign extending the result.
1597 RD is the destination register.
1598 RN is the source register.
1599 IMMR is the bit number to start at (least significant bit).
1600 IMMS is the bit number to stop at (most significant bit). */
1603 emit_sbfm (uint32_t *buf
, struct aarch64_register rd
,
1604 struct aarch64_register rn
, uint32_t immr
, uint32_t imms
)
1606 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1607 uint32_t n
= ENCODE (rd
.is64
, 1, 22);
1609 return aarch64_emit_insn (buf
, SBFM
| size
| n
| ENCODE (immr
, 6, 16)
1610 | ENCODE (imms
, 6, 10) | ENCODE (rn
.num
, 5, 5)
1611 | ENCODE (rd
.num
, 5, 0));
1614 /* Write a SBFX instruction into *BUF.
1616 SBFX rd, rn, #lsb, #width
1618 This instruction moves #width bits from #lsb into the destination, sign
1619 extending the result. This is an alias for:
1621 SBFM rd, rn, #lsb, #(lsb + width - 1)
1623 RD is the destination register.
1624 RN is the source register.
1625 LSB is the bit number to start at (least significant bit).
1626 WIDTH is the number of bits to move. */
1629 emit_sbfx (uint32_t *buf
, struct aarch64_register rd
,
1630 struct aarch64_register rn
, uint32_t lsb
, uint32_t width
)
1632 return emit_sbfm (buf
, rd
, rn
, lsb
, lsb
+ width
- 1);
1635 /* Write a UBFM instruction into *BUF.
1637 UBFM rd, rn, #immr, #imms
1639 This instruction moves the bits from #immr to #imms into the
1640 destination, extending the result with zeros.
1642 RD is the destination register.
1643 RN is the source register.
1644 IMMR is the bit number to start at (least significant bit).
1645 IMMS is the bit number to stop at (most significant bit). */
1648 emit_ubfm (uint32_t *buf
, struct aarch64_register rd
,
1649 struct aarch64_register rn
, uint32_t immr
, uint32_t imms
)
1651 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1652 uint32_t n
= ENCODE (rd
.is64
, 1, 22);
1654 return aarch64_emit_insn (buf
, UBFM
| size
| n
| ENCODE (immr
, 6, 16)
1655 | ENCODE (imms
, 6, 10) | ENCODE (rn
.num
, 5, 5)
1656 | ENCODE (rd
.num
, 5, 0));
1659 /* Write a UBFX instruction into *BUF.
1661 UBFX rd, rn, #lsb, #width
1663 This instruction moves #width bits from #lsb into the destination,
1664 extending the result with zeros. This is an alias for:
1666 UBFM rd, rn, #lsb, #(lsb + width - 1)
1668 RD is the destination register.
1669 RN is the source register.
1670 LSB is the bit number to start at (least significant bit).
1671 WIDTH is the number of bits to move. */
1674 emit_ubfx (uint32_t *buf
, struct aarch64_register rd
,
1675 struct aarch64_register rn
, uint32_t lsb
, uint32_t width
)
1677 return emit_ubfm (buf
, rd
, rn
, lsb
, lsb
+ width
- 1);
1680 /* Write a CSINC instruction into *BUF.
1682 CSINC rd, rn, rm, cond
1684 This instruction conditionally increments rn or rm and places the result
1685 in rd. rn is chosen is the condition is true.
1687 RD is the destination register.
1688 RN and RM are the source registers.
1689 COND is the encoded condition. */
1692 emit_csinc (uint32_t *buf
, struct aarch64_register rd
,
1693 struct aarch64_register rn
, struct aarch64_register rm
,
1696 uint32_t size
= ENCODE (rd
.is64
, 1, 31);
1698 return aarch64_emit_insn (buf
, CSINC
| size
| ENCODE (rm
.num
, 5, 16)
1699 | ENCODE (cond
, 4, 12) | ENCODE (rn
.num
, 5, 5)
1700 | ENCODE (rd
.num
, 5, 0));
1703 /* Write a CSET instruction into *BUF.
1707 This instruction conditionally write 1 or 0 in the destination register.
1708 1 is written if the condition is true. This is an alias for:
1710 CSINC rd, xzr, xzr, !cond
1712 Note that the condition needs to be inverted.
1714 RD is the destination register.
1715 RN and RM are the source registers.
1716 COND is the encoded condition. */
1719 emit_cset (uint32_t *buf
, struct aarch64_register rd
, unsigned cond
)
1721 /* The least significant bit of the condition needs toggling in order to
1723 return emit_csinc (buf
, rd
, xzr
, xzr
, cond
^ 0x1);
1726 /* Write LEN instructions from BUF into the inferior memory at *TO.
1728 Note instructions are always little endian on AArch64, unlike data. */
1731 append_insns (CORE_ADDR
*to
, size_t len
, const uint32_t *buf
)
1733 size_t byte_len
= len
* sizeof (uint32_t);
1734 #if (__BYTE_ORDER == __BIG_ENDIAN)
1735 uint32_t *le_buf
= (uint32_t *) xmalloc (byte_len
);
1738 for (i
= 0; i
< len
; i
++)
1739 le_buf
[i
] = htole32 (buf
[i
]);
1741 target_write_memory (*to
, (const unsigned char *) le_buf
, byte_len
);
1745 target_write_memory (*to
, (const unsigned char *) buf
, byte_len
);
1751 /* Sub-class of struct aarch64_insn_data, store information of
1752 instruction relocation for fast tracepoint. Visitor can
1753 relocate an instruction from BASE.INSN_ADDR to NEW_ADDR and save
1754 the relocated instructions in buffer pointed by INSN_PTR. */
1756 struct aarch64_insn_relocation_data
1758 struct aarch64_insn_data base
;
1760 /* The new address the instruction is relocated to. */
1762 /* Pointer to the buffer of relocated instruction(s). */
1766 /* Implementation of aarch64_insn_visitor method "b". */
1769 aarch64_ftrace_insn_reloc_b (const int is_bl
, const int32_t offset
,
1770 struct aarch64_insn_data
*data
)
1772 struct aarch64_insn_relocation_data
*insn_reloc
1773 = (struct aarch64_insn_relocation_data
*) data
;
1775 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1777 if (can_encode_int32 (new_offset
, 28))
1778 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, is_bl
, new_offset
);
1781 /* Implementation of aarch64_insn_visitor method "b_cond". */
1784 aarch64_ftrace_insn_reloc_b_cond (const unsigned cond
, const int32_t offset
,
1785 struct aarch64_insn_data
*data
)
1787 struct aarch64_insn_relocation_data
*insn_reloc
1788 = (struct aarch64_insn_relocation_data
*) data
;
1790 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1792 if (can_encode_int32 (new_offset
, 21))
1794 insn_reloc
->insn_ptr
+= emit_bcond (insn_reloc
->insn_ptr
, cond
,
1797 else if (can_encode_int32 (new_offset
, 28))
1799 /* The offset is out of range for a conditional branch
1800 instruction but not for a unconditional branch. We can use
1801 the following instructions instead:
1803 B.COND TAKEN ; If cond is true, then jump to TAKEN.
1804 B NOT_TAKEN ; Else jump over TAKEN and continue.
1811 insn_reloc
->insn_ptr
+= emit_bcond (insn_reloc
->insn_ptr
, cond
, 8);
1812 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, 8);
1813 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, new_offset
- 8);
1817 /* Implementation of aarch64_insn_visitor method "cb". */
1820 aarch64_ftrace_insn_reloc_cb (const int32_t offset
, const int is_cbnz
,
1821 const unsigned rn
, int is64
,
1822 struct aarch64_insn_data
*data
)
1824 struct aarch64_insn_relocation_data
*insn_reloc
1825 = (struct aarch64_insn_relocation_data
*) data
;
1827 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1829 if (can_encode_int32 (new_offset
, 21))
1831 insn_reloc
->insn_ptr
+= emit_cb (insn_reloc
->insn_ptr
, is_cbnz
,
1832 aarch64_register (rn
, is64
), new_offset
);
1834 else if (can_encode_int32 (new_offset
, 28))
1836 /* The offset is out of range for a compare and branch
1837 instruction but not for a unconditional branch. We can use
1838 the following instructions instead:
1840 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
1841 B NOT_TAKEN ; Else jump over TAKEN and continue.
1847 insn_reloc
->insn_ptr
+= emit_cb (insn_reloc
->insn_ptr
, is_cbnz
,
1848 aarch64_register (rn
, is64
), 8);
1849 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, 8);
1850 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, new_offset
- 8);
1854 /* Implementation of aarch64_insn_visitor method "tb". */
1857 aarch64_ftrace_insn_reloc_tb (const int32_t offset
, int is_tbnz
,
1858 const unsigned rt
, unsigned bit
,
1859 struct aarch64_insn_data
*data
)
1861 struct aarch64_insn_relocation_data
*insn_reloc
1862 = (struct aarch64_insn_relocation_data
*) data
;
1864 = insn_reloc
->base
.insn_addr
- insn_reloc
->new_addr
+ offset
;
1866 if (can_encode_int32 (new_offset
, 16))
1868 insn_reloc
->insn_ptr
+= emit_tb (insn_reloc
->insn_ptr
, is_tbnz
, bit
,
1869 aarch64_register (rt
, 1), new_offset
);
1871 else if (can_encode_int32 (new_offset
, 28))
1873 /* The offset is out of range for a test bit and branch
1874 instruction but not for a unconditional branch. We can use
1875 the following instructions instead:
1877 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
1878 B NOT_TAKEN ; Else jump over TAKEN and continue.
1884 insn_reloc
->insn_ptr
+= emit_tb (insn_reloc
->insn_ptr
, is_tbnz
, bit
,
1885 aarch64_register (rt
, 1), 8);
1886 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0, 8);
1887 insn_reloc
->insn_ptr
+= emit_b (insn_reloc
->insn_ptr
, 0,
1892 /* Implementation of aarch64_insn_visitor method "adr". */
1895 aarch64_ftrace_insn_reloc_adr (const int32_t offset
, const unsigned rd
,
1897 struct aarch64_insn_data
*data
)
1899 struct aarch64_insn_relocation_data
*insn_reloc
1900 = (struct aarch64_insn_relocation_data
*) data
;
1901 /* We know exactly the address the ADR{P,} instruction will compute.
1902 We can just write it to the destination register. */
1903 CORE_ADDR address
= data
->insn_addr
+ offset
;
1907 /* Clear the lower 12 bits of the offset to get the 4K page. */
1908 insn_reloc
->insn_ptr
+= emit_mov_addr (insn_reloc
->insn_ptr
,
1909 aarch64_register (rd
, 1),
1913 insn_reloc
->insn_ptr
+= emit_mov_addr (insn_reloc
->insn_ptr
,
1914 aarch64_register (rd
, 1), address
);
1917 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
1920 aarch64_ftrace_insn_reloc_ldr_literal (const int32_t offset
, const int is_sw
,
1921 const unsigned rt
, const int is64
,
1922 struct aarch64_insn_data
*data
)
1924 struct aarch64_insn_relocation_data
*insn_reloc
1925 = (struct aarch64_insn_relocation_data
*) data
;
1926 CORE_ADDR address
= data
->insn_addr
+ offset
;
1928 insn_reloc
->insn_ptr
+= emit_mov_addr (insn_reloc
->insn_ptr
,
1929 aarch64_register (rt
, 1), address
);
1931 /* We know exactly what address to load from, and what register we
1934 MOV xd, #(oldloc + offset)
1935 MOVK xd, #((oldloc + offset) >> 16), lsl #16
1938 LDR xd, [xd] ; or LDRSW xd, [xd]
1943 insn_reloc
->insn_ptr
+= emit_ldrsw (insn_reloc
->insn_ptr
,
1944 aarch64_register (rt
, 1),
1945 aarch64_register (rt
, 1),
1946 offset_memory_operand (0));
1948 insn_reloc
->insn_ptr
+= emit_ldr (insn_reloc
->insn_ptr
,
1949 aarch64_register (rt
, is64
),
1950 aarch64_register (rt
, 1),
1951 offset_memory_operand (0));
1954 /* Implementation of aarch64_insn_visitor method "others". */
1957 aarch64_ftrace_insn_reloc_others (const uint32_t insn
,
1958 struct aarch64_insn_data
*data
)
1960 struct aarch64_insn_relocation_data
*insn_reloc
1961 = (struct aarch64_insn_relocation_data
*) data
;
1963 /* The instruction is not PC relative. Just re-emit it at the new
1965 insn_reloc
->insn_ptr
+= aarch64_emit_insn (insn_reloc
->insn_ptr
, insn
);
1968 static const struct aarch64_insn_visitor visitor
=
1970 aarch64_ftrace_insn_reloc_b
,
1971 aarch64_ftrace_insn_reloc_b_cond
,
1972 aarch64_ftrace_insn_reloc_cb
,
1973 aarch64_ftrace_insn_reloc_tb
,
1974 aarch64_ftrace_insn_reloc_adr
,
1975 aarch64_ftrace_insn_reloc_ldr_literal
,
1976 aarch64_ftrace_insn_reloc_others
,
1980 aarch64_target::supports_fast_tracepoints ()
1985 /* Implementation of target ops method
1986 "install_fast_tracepoint_jump_pad". */
1989 aarch64_target::install_fast_tracepoint_jump_pad
1990 (CORE_ADDR tpoint
, CORE_ADDR tpaddr
, CORE_ADDR collector
,
1991 CORE_ADDR lockaddr
, ULONGEST orig_size
, CORE_ADDR
*jump_entry
,
1992 CORE_ADDR
*trampoline
, ULONGEST
*trampoline_size
,
1993 unsigned char *jjump_pad_insn
, ULONGEST
*jjump_pad_insn_size
,
1994 CORE_ADDR
*adjusted_insn_addr
, CORE_ADDR
*adjusted_insn_addr_end
,
2002 CORE_ADDR buildaddr
= *jump_entry
;
2003 struct aarch64_insn_relocation_data insn_data
;
2005 /* We need to save the current state on the stack both to restore it
2006 later and to collect register values when the tracepoint is hit.
2008 The saved registers are pushed in a layout that needs to be in sync
2009 with aarch64_ft_collect_regmap (see linux-aarch64-ipa.c). Later on
2010 the supply_fast_tracepoint_registers function will fill in the
2011 register cache from a pointer to saved registers on the stack we build
2014 For simplicity, we set the size of each cell on the stack to 16 bytes.
2015 This way one cell can hold any register type, from system registers
2016 to the 128 bit SIMD&FP registers. Furthermore, the stack pointer
2017 has to be 16 bytes aligned anyway.
2019 Note that the CPSR register does not exist on AArch64. Instead we
2020 can access system bits describing the process state with the
2021 MRS/MSR instructions, namely the condition flags. We save them as
2022 if they are part of a CPSR register because that's how GDB
2023 interprets these system bits. At the moment, only the condition
2024 flags are saved in CPSR (NZCV).
2026 Stack layout, each cell is 16 bytes (descending):
2028 High *-------- SIMD&FP registers from 31 down to 0. --------*
2034 *---- General purpose registers from 30 down to 0. ----*
2040 *------------- Special purpose registers. -------------*
2043 | CPSR (NZCV) | 5 cells
2046 *------------- collecting_t object --------------------*
2047 | TPIDR_EL0 | struct tracepoint * |
2048 Low *------------------------------------------------------*
2050 After this stack is set up, we issue a call to the collector, passing
2051 it the saved registers at (SP + 16). */
2053 /* Push SIMD&FP registers on the stack:
2055 SUB sp, sp, #(32 * 16)
2057 STP q30, q31, [sp, #(30 * 16)]
2062 p
+= emit_sub (p
, sp
, sp
, immediate_operand (32 * 16));
2063 for (i
= 30; i
>= 0; i
-= 2)
2064 p
+= emit_stp_q_offset (p
, i
, i
+ 1, sp
, i
* 16);
2066 /* Push general purpose registers on the stack. Note that we do not need
2067 to push x31 as it represents the xzr register and not the stack
2068 pointer in a STR instruction.
2070 SUB sp, sp, #(31 * 16)
2072 STR x30, [sp, #(30 * 16)]
2077 p
+= emit_sub (p
, sp
, sp
, immediate_operand (31 * 16));
2078 for (i
= 30; i
>= 0; i
-= 1)
2079 p
+= emit_str (p
, aarch64_register (i
, 1), sp
,
2080 offset_memory_operand (i
* 16));
2082 /* Make space for 5 more cells.
2084 SUB sp, sp, #(5 * 16)
2087 p
+= emit_sub (p
, sp
, sp
, immediate_operand (5 * 16));
2092 ADD x4, sp, #((32 + 31 + 5) * 16)
2093 STR x4, [sp, #(4 * 16)]
2096 p
+= emit_add (p
, x4
, sp
, immediate_operand ((32 + 31 + 5) * 16));
2097 p
+= emit_str (p
, x4
, sp
, offset_memory_operand (4 * 16));
2099 /* Save PC (tracepoint address):
2104 STR x3, [sp, #(3 * 16)]
2108 p
+= emit_mov_addr (p
, x3
, tpaddr
);
2109 p
+= emit_str (p
, x3
, sp
, offset_memory_operand (3 * 16));
2111 /* Save CPSR (NZCV), FPSR and FPCR:
2117 STR x2, [sp, #(2 * 16)]
2118 STR x1, [sp, #(1 * 16)]
2119 STR x0, [sp, #(0 * 16)]
2122 p
+= emit_mrs (p
, x2
, NZCV
);
2123 p
+= emit_mrs (p
, x1
, FPSR
);
2124 p
+= emit_mrs (p
, x0
, FPCR
);
2125 p
+= emit_str (p
, x2
, sp
, offset_memory_operand (2 * 16));
2126 p
+= emit_str (p
, x1
, sp
, offset_memory_operand (1 * 16));
2127 p
+= emit_str (p
, x0
, sp
, offset_memory_operand (0 * 16));
2129 /* Push the collecting_t object. It consist of the address of the
2130 tracepoint and an ID for the current thread. We get the latter by
2131 reading the tpidr_el0 system register. It corresponds to the
2132 NT_ARM_TLS register accessible with ptrace.
2139 STP x0, x1, [sp, #-16]!
2143 p
+= emit_mov_addr (p
, x0
, tpoint
);
2144 p
+= emit_mrs (p
, x1
, TPIDR_EL0
);
2145 p
+= emit_stp (p
, x0
, x1
, sp
, preindex_memory_operand (-16));
2149 The shared memory for the lock is at lockaddr. It will hold zero
2150 if no-one is holding the lock, otherwise it contains the address of
2151 the collecting_t object on the stack of the thread which acquired it.
2153 At this stage, the stack pointer points to this thread's collecting_t
2156 We use the following registers:
2157 - x0: Address of the lock.
2158 - x1: Pointer to collecting_t object.
2159 - x2: Scratch register.
2165 ; Trigger an event local to this core. So the following WFE
2166 ; instruction is ignored.
2169 ; Wait for an event. The event is triggered by either the SEVL
2170 ; or STLR instructions (store release).
2173 ; Atomically read at lockaddr. This marks the memory location as
2174 ; exclusive. This instruction also has memory constraints which
2175 ; make sure all previous data reads and writes are done before
2179 ; Try again if another thread holds the lock.
2182 ; We can lock it! Write the address of the collecting_t object.
2183 ; This instruction will fail if the memory location is not marked
2184 ; as exclusive anymore. If it succeeds, it will remove the
2185 ; exclusive mark on the memory location. This way, if another
2186 ; thread executes this instruction before us, we will fail and try
2193 p
+= emit_mov_addr (p
, x0
, lockaddr
);
2194 p
+= emit_mov (p
, x1
, register_operand (sp
));
2198 p
+= emit_ldaxr (p
, x2
, x0
);
2199 p
+= emit_cb (p
, 1, w2
, -2 * 4);
2200 p
+= emit_stxr (p
, w2
, x1
, x0
);
2201 p
+= emit_cb (p
, 1, x2
, -4 * 4);
2203 /* Call collector (struct tracepoint *, unsigned char *):
2208 ; Saved registers start after the collecting_t object.
2211 ; We use an intra-procedure-call scratch register.
2212 MOV ip0, #(collector)
2215 ; And call back to C!
2220 p
+= emit_mov_addr (p
, x0
, tpoint
);
2221 p
+= emit_add (p
, x1
, sp
, immediate_operand (16));
2223 p
+= emit_mov_addr (p
, ip0
, collector
);
2224 p
+= emit_blr (p
, ip0
);
2226 /* Release the lock.
2231 ; This instruction is a normal store with memory ordering
2232 ; constraints. Thanks to this we do not have to put a data
2233 ; barrier instruction to make sure all data read and writes are done
2234 ; before this instruction is executed. Furthermore, this instruction
2235 ; will trigger an event, letting other threads know they can grab
2240 p
+= emit_mov_addr (p
, x0
, lockaddr
);
2241 p
+= emit_stlr (p
, xzr
, x0
);
2243 /* Free collecting_t object:
2248 p
+= emit_add (p
, sp
, sp
, immediate_operand (16));
2250 /* Restore CPSR (NZCV), FPSR and FPCR. And free all special purpose
2251 registers from the stack.
2253 LDR x2, [sp, #(2 * 16)]
2254 LDR x1, [sp, #(1 * 16)]
2255 LDR x0, [sp, #(0 * 16)]
2261 ADD sp, sp #(5 * 16)
2264 p
+= emit_ldr (p
, x2
, sp
, offset_memory_operand (2 * 16));
2265 p
+= emit_ldr (p
, x1
, sp
, offset_memory_operand (1 * 16));
2266 p
+= emit_ldr (p
, x0
, sp
, offset_memory_operand (0 * 16));
2267 p
+= emit_msr (p
, NZCV
, x2
);
2268 p
+= emit_msr (p
, FPSR
, x1
);
2269 p
+= emit_msr (p
, FPCR
, x0
);
2271 p
+= emit_add (p
, sp
, sp
, immediate_operand (5 * 16));
2273 /* Pop general purpose registers:
2277 LDR x30, [sp, #(30 * 16)]
2279 ADD sp, sp, #(31 * 16)
2282 for (i
= 0; i
<= 30; i
+= 1)
2283 p
+= emit_ldr (p
, aarch64_register (i
, 1), sp
,
2284 offset_memory_operand (i
* 16));
2285 p
+= emit_add (p
, sp
, sp
, immediate_operand (31 * 16));
2287 /* Pop SIMD&FP registers:
2291 LDP q30, q31, [sp, #(30 * 16)]
2293 ADD sp, sp, #(32 * 16)
2296 for (i
= 0; i
<= 30; i
+= 2)
2297 p
+= emit_ldp_q_offset (p
, i
, i
+ 1, sp
, i
* 16);
2298 p
+= emit_add (p
, sp
, sp
, immediate_operand (32 * 16));
2300 /* Write the code into the inferior memory. */
2301 append_insns (&buildaddr
, p
- buf
, buf
);
2303 /* Now emit the relocated instruction. */
2304 *adjusted_insn_addr
= buildaddr
;
2305 target_read_uint32 (tpaddr
, &insn
);
2307 insn_data
.base
.insn_addr
= tpaddr
;
2308 insn_data
.new_addr
= buildaddr
;
2309 insn_data
.insn_ptr
= buf
;
2311 aarch64_relocate_instruction (insn
, &visitor
,
2312 (struct aarch64_insn_data
*) &insn_data
);
2314 /* We may not have been able to relocate the instruction. */
2315 if (insn_data
.insn_ptr
== buf
)
2318 "E.Could not relocate instruction from %s to %s.",
2319 core_addr_to_string_nz (tpaddr
),
2320 core_addr_to_string_nz (buildaddr
));
2324 append_insns (&buildaddr
, insn_data
.insn_ptr
- buf
, buf
);
2325 *adjusted_insn_addr_end
= buildaddr
;
2327 /* Go back to the start of the buffer. */
2330 /* Emit a branch back from the jump pad. */
2331 offset
= (tpaddr
+ orig_size
- buildaddr
);
2332 if (!can_encode_int32 (offset
, 28))
2335 "E.Jump back from jump pad too far from tracepoint "
2336 "(offset 0x%" PRIx64
" cannot be encoded in 28 bits).",
2341 p
+= emit_b (p
, 0, offset
);
2342 append_insns (&buildaddr
, p
- buf
, buf
);
2344 /* Give the caller a branch instruction into the jump pad. */
2345 offset
= (*jump_entry
- tpaddr
);
2346 if (!can_encode_int32 (offset
, 28))
2349 "E.Jump pad too far from tracepoint "
2350 "(offset 0x%" PRIx64
" cannot be encoded in 28 bits).",
2355 emit_b ((uint32_t *) jjump_pad_insn
, 0, offset
);
2356 *jjump_pad_insn_size
= 4;
2358 /* Return the end address of our pad. */
2359 *jump_entry
= buildaddr
;
2364 /* Helper function writing LEN instructions from START into
2365 current_insn_ptr. */
2368 emit_ops_insns (const uint32_t *start
, int len
)
2370 CORE_ADDR buildaddr
= current_insn_ptr
;
2373 debug_printf ("Adding %d instrucions at %s\n",
2374 len
, paddress (buildaddr
));
2376 append_insns (&buildaddr
, len
, start
);
2377 current_insn_ptr
= buildaddr
;
2380 /* Pop a register from the stack. */
2383 emit_pop (uint32_t *buf
, struct aarch64_register rt
)
2385 return emit_ldr (buf
, rt
, sp
, postindex_memory_operand (1 * 16));
2388 /* Push a register on the stack. */
2391 emit_push (uint32_t *buf
, struct aarch64_register rt
)
2393 return emit_str (buf
, rt
, sp
, preindex_memory_operand (-1 * 16));
2396 /* Implementation of emit_ops method "emit_prologue". */
2399 aarch64_emit_prologue (void)
2404 /* This function emit a prologue for the following function prototype:
2406 enum eval_result_type f (unsigned char *regs,
2409 The first argument is a buffer of raw registers. The second
2410 argument is the result of
2411 evaluating the expression, which will be set to whatever is on top of
2412 the stack at the end.
2414 The stack set up by the prologue is as such:
2416 High *------------------------------------------------------*
2419 | x1 (ULONGEST *value) |
2420 | x0 (unsigned char *regs) |
2421 Low *------------------------------------------------------*
2423 As we are implementing a stack machine, each opcode can expand the
2424 stack so we never know how far we are from the data saved by this
2425 prologue. In order to be able refer to value and regs later, we save
2426 the current stack pointer in the frame pointer. This way, it is not
2427 clobbered when calling C functions.
2429 Finally, throughout every operation, we are using register x0 as the
2430 top of the stack, and x1 as a scratch register. */
2432 p
+= emit_stp (p
, x0
, x1
, sp
, preindex_memory_operand (-2 * 16));
2433 p
+= emit_str (p
, lr
, sp
, offset_memory_operand (3 * 8));
2434 p
+= emit_str (p
, fp
, sp
, offset_memory_operand (2 * 8));
2436 p
+= emit_add (p
, fp
, sp
, immediate_operand (2 * 8));
2439 emit_ops_insns (buf
, p
- buf
);
2442 /* Implementation of emit_ops method "emit_epilogue". */
2445 aarch64_emit_epilogue (void)
2450 /* Store the result of the expression (x0) in *value. */
2451 p
+= emit_sub (p
, x1
, fp
, immediate_operand (1 * 8));
2452 p
+= emit_ldr (p
, x1
, x1
, offset_memory_operand (0));
2453 p
+= emit_str (p
, x0
, x1
, offset_memory_operand (0));
2455 /* Restore the previous state. */
2456 p
+= emit_add (p
, sp
, fp
, immediate_operand (2 * 8));
2457 p
+= emit_ldp (p
, fp
, lr
, fp
, offset_memory_operand (0));
2459 /* Return expr_eval_no_error. */
2460 p
+= emit_mov (p
, x0
, immediate_operand (expr_eval_no_error
));
2461 p
+= emit_ret (p
, lr
);
2463 emit_ops_insns (buf
, p
- buf
);
2466 /* Implementation of emit_ops method "emit_add". */
2469 aarch64_emit_add (void)
2474 p
+= emit_pop (p
, x1
);
2475 p
+= emit_add (p
, x0
, x1
, register_operand (x0
));
2477 emit_ops_insns (buf
, p
- buf
);
2480 /* Implementation of emit_ops method "emit_sub". */
2483 aarch64_emit_sub (void)
2488 p
+= emit_pop (p
, x1
);
2489 p
+= emit_sub (p
, x0
, x1
, register_operand (x0
));
2491 emit_ops_insns (buf
, p
- buf
);
2494 /* Implementation of emit_ops method "emit_mul". */
2497 aarch64_emit_mul (void)
2502 p
+= emit_pop (p
, x1
);
2503 p
+= emit_mul (p
, x0
, x1
, x0
);
2505 emit_ops_insns (buf
, p
- buf
);
2508 /* Implementation of emit_ops method "emit_lsh". */
2511 aarch64_emit_lsh (void)
2516 p
+= emit_pop (p
, x1
);
2517 p
+= emit_lslv (p
, x0
, x1
, x0
);
2519 emit_ops_insns (buf
, p
- buf
);
2522 /* Implementation of emit_ops method "emit_rsh_signed". */
2525 aarch64_emit_rsh_signed (void)
2530 p
+= emit_pop (p
, x1
);
2531 p
+= emit_asrv (p
, x0
, x1
, x0
);
2533 emit_ops_insns (buf
, p
- buf
);
2536 /* Implementation of emit_ops method "emit_rsh_unsigned". */
2539 aarch64_emit_rsh_unsigned (void)
2544 p
+= emit_pop (p
, x1
);
2545 p
+= emit_lsrv (p
, x0
, x1
, x0
);
2547 emit_ops_insns (buf
, p
- buf
);
2550 /* Implementation of emit_ops method "emit_ext". */
2553 aarch64_emit_ext (int arg
)
2558 p
+= emit_sbfx (p
, x0
, x0
, 0, arg
);
2560 emit_ops_insns (buf
, p
- buf
);
2563 /* Implementation of emit_ops method "emit_log_not". */
2566 aarch64_emit_log_not (void)
2571 /* If the top of the stack is 0, replace it with 1. Else replace it with
2574 p
+= emit_cmp (p
, x0
, immediate_operand (0));
2575 p
+= emit_cset (p
, x0
, EQ
);
2577 emit_ops_insns (buf
, p
- buf
);
2580 /* Implementation of emit_ops method "emit_bit_and". */
2583 aarch64_emit_bit_and (void)
2588 p
+= emit_pop (p
, x1
);
2589 p
+= emit_and (p
, x0
, x0
, x1
);
2591 emit_ops_insns (buf
, p
- buf
);
2594 /* Implementation of emit_ops method "emit_bit_or". */
2597 aarch64_emit_bit_or (void)
2602 p
+= emit_pop (p
, x1
);
2603 p
+= emit_orr (p
, x0
, x0
, x1
);
2605 emit_ops_insns (buf
, p
- buf
);
2608 /* Implementation of emit_ops method "emit_bit_xor". */
2611 aarch64_emit_bit_xor (void)
2616 p
+= emit_pop (p
, x1
);
2617 p
+= emit_eor (p
, x0
, x0
, x1
);
2619 emit_ops_insns (buf
, p
- buf
);
2622 /* Implementation of emit_ops method "emit_bit_not". */
2625 aarch64_emit_bit_not (void)
2630 p
+= emit_mvn (p
, x0
, x0
);
2632 emit_ops_insns (buf
, p
- buf
);
2635 /* Implementation of emit_ops method "emit_equal". */
2638 aarch64_emit_equal (void)
2643 p
+= emit_pop (p
, x1
);
2644 p
+= emit_cmp (p
, x0
, register_operand (x1
));
2645 p
+= emit_cset (p
, x0
, EQ
);
2647 emit_ops_insns (buf
, p
- buf
);
2650 /* Implementation of emit_ops method "emit_less_signed". */
2653 aarch64_emit_less_signed (void)
2658 p
+= emit_pop (p
, x1
);
2659 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2660 p
+= emit_cset (p
, x0
, LT
);
2662 emit_ops_insns (buf
, p
- buf
);
2665 /* Implementation of emit_ops method "emit_less_unsigned". */
2668 aarch64_emit_less_unsigned (void)
2673 p
+= emit_pop (p
, x1
);
2674 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2675 p
+= emit_cset (p
, x0
, LO
);
2677 emit_ops_insns (buf
, p
- buf
);
2680 /* Implementation of emit_ops method "emit_ref". */
2683 aarch64_emit_ref (int size
)
2691 p
+= emit_ldrb (p
, w0
, x0
, offset_memory_operand (0));
2694 p
+= emit_ldrh (p
, w0
, x0
, offset_memory_operand (0));
2697 p
+= emit_ldr (p
, w0
, x0
, offset_memory_operand (0));
2700 p
+= emit_ldr (p
, x0
, x0
, offset_memory_operand (0));
2703 /* Unknown size, bail on compilation. */
2708 emit_ops_insns (buf
, p
- buf
);
2711 /* Implementation of emit_ops method "emit_if_goto". */
2714 aarch64_emit_if_goto (int *offset_p
, int *size_p
)
2719 /* The Z flag is set or cleared here. */
2720 p
+= emit_cmp (p
, x0
, immediate_operand (0));
2721 /* This instruction must not change the Z flag. */
2722 p
+= emit_pop (p
, x0
);
2723 /* Branch over the next instruction if x0 == 0. */
2724 p
+= emit_bcond (p
, EQ
, 8);
2726 /* The NOP instruction will be patched with an unconditional branch. */
2728 *offset_p
= (p
- buf
) * 4;
2733 emit_ops_insns (buf
, p
- buf
);
2736 /* Implementation of emit_ops method "emit_goto". */
2739 aarch64_emit_goto (int *offset_p
, int *size_p
)
2744 /* The NOP instruction will be patched with an unconditional branch. */
2751 emit_ops_insns (buf
, p
- buf
);
2754 /* Implementation of emit_ops method "write_goto_address". */
2757 aarch64_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2761 emit_b (&insn
, 0, to
- from
);
2762 append_insns (&from
, 1, &insn
);
2765 /* Implementation of emit_ops method "emit_const". */
2768 aarch64_emit_const (LONGEST num
)
2773 p
+= emit_mov_addr (p
, x0
, num
);
2775 emit_ops_insns (buf
, p
- buf
);
2778 /* Implementation of emit_ops method "emit_call". */
2781 aarch64_emit_call (CORE_ADDR fn
)
2786 p
+= emit_mov_addr (p
, ip0
, fn
);
2787 p
+= emit_blr (p
, ip0
);
2789 emit_ops_insns (buf
, p
- buf
);
2792 /* Implementation of emit_ops method "emit_reg". */
2795 aarch64_emit_reg (int reg
)
2800 /* Set x0 to unsigned char *regs. */
2801 p
+= emit_sub (p
, x0
, fp
, immediate_operand (2 * 8));
2802 p
+= emit_ldr (p
, x0
, x0
, offset_memory_operand (0));
2803 p
+= emit_mov (p
, x1
, immediate_operand (reg
));
2805 emit_ops_insns (buf
, p
- buf
);
2807 aarch64_emit_call (get_raw_reg_func_addr ());
2810 /* Implementation of emit_ops method "emit_pop". */
2813 aarch64_emit_pop (void)
2818 p
+= emit_pop (p
, x0
);
2820 emit_ops_insns (buf
, p
- buf
);
2823 /* Implementation of emit_ops method "emit_stack_flush". */
2826 aarch64_emit_stack_flush (void)
2831 p
+= emit_push (p
, x0
);
2833 emit_ops_insns (buf
, p
- buf
);
2836 /* Implementation of emit_ops method "emit_zero_ext". */
2839 aarch64_emit_zero_ext (int arg
)
2844 p
+= emit_ubfx (p
, x0
, x0
, 0, arg
);
2846 emit_ops_insns (buf
, p
- buf
);
2849 /* Implementation of emit_ops method "emit_swap". */
2852 aarch64_emit_swap (void)
2857 p
+= emit_ldr (p
, x1
, sp
, offset_memory_operand (0 * 16));
2858 p
+= emit_str (p
, x0
, sp
, offset_memory_operand (0 * 16));
2859 p
+= emit_mov (p
, x0
, register_operand (x1
));
2861 emit_ops_insns (buf
, p
- buf
);
2864 /* Implementation of emit_ops method "emit_stack_adjust". */
2867 aarch64_emit_stack_adjust (int n
)
2869 /* This is not needed with our design. */
2873 p
+= emit_add (p
, sp
, sp
, immediate_operand (n
* 16));
2875 emit_ops_insns (buf
, p
- buf
);
2878 /* Implementation of emit_ops method "emit_int_call_1". */
2881 aarch64_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2886 p
+= emit_mov (p
, x0
, immediate_operand (arg1
));
2888 emit_ops_insns (buf
, p
- buf
);
2890 aarch64_emit_call (fn
);
2893 /* Implementation of emit_ops method "emit_void_call_2". */
2896 aarch64_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2901 /* Push x0 on the stack. */
2902 aarch64_emit_stack_flush ();
2904 /* Setup arguments for the function call:
2907 x1: top of the stack
2912 p
+= emit_mov (p
, x1
, register_operand (x0
));
2913 p
+= emit_mov (p
, x0
, immediate_operand (arg1
));
2915 emit_ops_insns (buf
, p
- buf
);
2917 aarch64_emit_call (fn
);
2920 aarch64_emit_pop ();
2923 /* Implementation of emit_ops method "emit_eq_goto". */
2926 aarch64_emit_eq_goto (int *offset_p
, int *size_p
)
2931 p
+= emit_pop (p
, x1
);
2932 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2933 /* Branch over the next instruction if x0 != x1. */
2934 p
+= emit_bcond (p
, NE
, 8);
2935 /* The NOP instruction will be patched with an unconditional branch. */
2937 *offset_p
= (p
- buf
) * 4;
2942 emit_ops_insns (buf
, p
- buf
);
2945 /* Implementation of emit_ops method "emit_ne_goto". */
2948 aarch64_emit_ne_goto (int *offset_p
, int *size_p
)
2953 p
+= emit_pop (p
, x1
);
2954 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2955 /* Branch over the next instruction if x0 == x1. */
2956 p
+= emit_bcond (p
, EQ
, 8);
2957 /* The NOP instruction will be patched with an unconditional branch. */
2959 *offset_p
= (p
- buf
) * 4;
2964 emit_ops_insns (buf
, p
- buf
);
2967 /* Implementation of emit_ops method "emit_lt_goto". */
2970 aarch64_emit_lt_goto (int *offset_p
, int *size_p
)
2975 p
+= emit_pop (p
, x1
);
2976 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2977 /* Branch over the next instruction if x0 >= x1. */
2978 p
+= emit_bcond (p
, GE
, 8);
2979 /* The NOP instruction will be patched with an unconditional branch. */
2981 *offset_p
= (p
- buf
) * 4;
2986 emit_ops_insns (buf
, p
- buf
);
2989 /* Implementation of emit_ops method "emit_le_goto". */
2992 aarch64_emit_le_goto (int *offset_p
, int *size_p
)
2997 p
+= emit_pop (p
, x1
);
2998 p
+= emit_cmp (p
, x1
, register_operand (x0
));
2999 /* Branch over the next instruction if x0 > x1. */
3000 p
+= emit_bcond (p
, GT
, 8);
3001 /* The NOP instruction will be patched with an unconditional branch. */
3003 *offset_p
= (p
- buf
) * 4;
3008 emit_ops_insns (buf
, p
- buf
);
3011 /* Implementation of emit_ops method "emit_gt_goto". */
3014 aarch64_emit_gt_goto (int *offset_p
, int *size_p
)
3019 p
+= emit_pop (p
, x1
);
3020 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3021 /* Branch over the next instruction if x0 <= x1. */
3022 p
+= emit_bcond (p
, LE
, 8);
3023 /* The NOP instruction will be patched with an unconditional branch. */
3025 *offset_p
= (p
- buf
) * 4;
3030 emit_ops_insns (buf
, p
- buf
);
3033 /* Implementation of emit_ops method "emit_ge_got". */
3036 aarch64_emit_ge_got (int *offset_p
, int *size_p
)
3041 p
+= emit_pop (p
, x1
);
3042 p
+= emit_cmp (p
, x1
, register_operand (x0
));
3043 /* Branch over the next instruction if x0 <= x1. */
3044 p
+= emit_bcond (p
, LT
, 8);
3045 /* The NOP instruction will be patched with an unconditional branch. */
3047 *offset_p
= (p
- buf
) * 4;
3052 emit_ops_insns (buf
, p
- buf
);
3055 static struct emit_ops aarch64_emit_ops_impl
=
3057 aarch64_emit_prologue
,
3058 aarch64_emit_epilogue
,
3063 aarch64_emit_rsh_signed
,
3064 aarch64_emit_rsh_unsigned
,
3066 aarch64_emit_log_not
,
3067 aarch64_emit_bit_and
,
3068 aarch64_emit_bit_or
,
3069 aarch64_emit_bit_xor
,
3070 aarch64_emit_bit_not
,
3072 aarch64_emit_less_signed
,
3073 aarch64_emit_less_unsigned
,
3075 aarch64_emit_if_goto
,
3077 aarch64_write_goto_address
,
3082 aarch64_emit_stack_flush
,
3083 aarch64_emit_zero_ext
,
3085 aarch64_emit_stack_adjust
,
3086 aarch64_emit_int_call_1
,
3087 aarch64_emit_void_call_2
,
3088 aarch64_emit_eq_goto
,
3089 aarch64_emit_ne_goto
,
3090 aarch64_emit_lt_goto
,
3091 aarch64_emit_le_goto
,
3092 aarch64_emit_gt_goto
,
3093 aarch64_emit_ge_got
,
3096 /* Implementation of target ops method "emit_ops". */
3099 aarch64_target::emit_ops ()
3101 return &aarch64_emit_ops_impl
;
3104 /* Implementation of target ops method
3105 "get_min_fast_tracepoint_insn_len". */
3108 aarch64_target::get_min_fast_tracepoint_insn_len ()
3113 /* Implementation of linux_target_ops method "supports_range_stepping". */
3116 aarch64_supports_range_stepping (void)
3121 /* Implementation of target ops method "sw_breakpoint_from_kind". */
3124 aarch64_target::sw_breakpoint_from_kind (int kind
, int *size
)
3126 if (is_64bit_tdesc ())
3128 *size
= aarch64_breakpoint_len
;
3129 return aarch64_breakpoint
;
3132 return arm_sw_breakpoint_from_kind (kind
, size
);
3135 /* Implementation of target ops method "breakpoint_kind_from_pc". */
3138 aarch64_target::breakpoint_kind_from_pc (CORE_ADDR
*pcptr
)
3140 if (is_64bit_tdesc ())
3141 return aarch64_breakpoint_len
;
3143 return arm_breakpoint_kind_from_pc (pcptr
);
3146 /* Implementation of the target ops method
3147 "breakpoint_kind_from_current_state". */
3150 aarch64_target::breakpoint_kind_from_current_state (CORE_ADDR
*pcptr
)
3152 if (is_64bit_tdesc ())
3153 return aarch64_breakpoint_len
;
3155 return arm_breakpoint_kind_from_current_state (pcptr
);
3158 /* Support for hardware single step. */
3161 aarch64_supports_hardware_single_step (void)
3166 struct linux_target_ops the_low_target
=
3168 aarch64_supports_range_stepping
,
3169 aarch64_supports_hardware_single_step
,
3170 aarch64_get_syscall_trapinfo
,
3173 /* The linux target ops object. */
3175 linux_process_target
*the_linux_target
= &the_aarch64_target
;
3178 initialize_low_arch (void)
3180 initialize_low_arch_aarch32 ();
3182 initialize_regsets_info (&aarch64_regsets_info
);
3183 initialize_regsets_info (&aarch64_sve_regsets_info
);