gdbserver/linux-crisv32-low.cc

   1 /* GNU/Linux/CRIS specific low level interface, for the remote server for GDB.
   2    Copyright (C) 1995-2020 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #include "server.h"
  20 #include "linux-low.h"
  21 #include "nat/gdb_ptrace.h"
  22
  23 /* Linux target op definitions for the CRIS architecture.  */
  24
  25 class crisv32_target : public linux_process_target
  26 {
  27 public:
  28
  29 };
  30
  31 /* The singleton target ops object.  */
  32
  33 static crisv32_target the_crisv32_target;
  34
  35 /* Defined in auto-generated file reg-crisv32.c.  */
  36 void init_registers_crisv32 (void);
  37 extern const struct target_desc *tdesc_crisv32;
  38
  39 /* CRISv32 */
  40 #define cris_num_regs 49
  41
  42 #ifndef PTRACE_GET_THREAD_AREA
  43 #define PTRACE_GET_THREAD_AREA 25
  44 #endif
  45
  46 /* Note: Ignoring USP (having the stack pointer in two locations causes trouble
  47    without any significant gain).  */
  48
  49 /* Locations need to match <include/asm/arch/ptrace.h>.  */
  50 static int cris_regmap[] = {
  51   1*4, 2*4, 3*4, 4*4,
  52   5*4, 6*4, 7*4, 8*4,
  53   9*4, 10*4, 11*4, 12*4,
  54   13*4, 14*4, 24*4, 15*4,
  55
  56   -1, -1, -1, 16*4,
  57   -1, 22*4, 23*4, 17*4,
  58   -1, -1, 21*4, 20*4,
  59   -1, 19*4, -1, 18*4,
  60
  61   25*4,
  62
  63   26*4, -1,   -1,   29*4,
  64   30*4, 31*4, 32*4, 33*4,
  65   34*4, 35*4, 36*4, 37*4,
  66   38*4, 39*4, 40*4, -1
  67
  68 };
  69
  70 static const unsigned short cris_breakpoint = 0xe938;
  71 #define cris_breakpoint_len 2
  72
  73 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind".  */
  74
  75 static const gdb_byte *
  76 cris_sw_breakpoint_from_kind (int kind, int *size)
  77 {
  78   *size = cris_breakpoint_len;
  79   return (const gdb_byte *) &cris_breakpoint;
  80 }
  81
  82 static int
  83 cris_breakpoint_at (CORE_ADDR where)
  84 {
  85   unsigned short insn;
  86
  87   the_target->read_memory (where, (unsigned char *) &insn,
  88                            cris_breakpoint_len);
  89   if (insn == cris_breakpoint)
  90     return 1;
  91
  92   /* If necessary, recognize more trap instructions here.  GDB only uses the
  93      one.  */
  94   return 0;
  95 }
  96
  97 static void
  98 cris_write_data_breakpoint (struct regcache *regcache,
  99                             int bp, unsigned long start, unsigned long end)
 100 {
 101   switch (bp)
 102     {
 103     case 0:
 104       supply_register_by_name (regcache, "s3", &start);
 105       supply_register_by_name (regcache, "s4", &end);
 106       break;
 107     case 1:
 108       supply_register_by_name (regcache, "s5", &start);
 109       supply_register_by_name (regcache, "s6", &end);
 110       break;
 111     case 2:
 112       supply_register_by_name (regcache, "s7", &start);
 113       supply_register_by_name (regcache, "s8", &end);
 114       break;
 115     case 3:
 116       supply_register_by_name (regcache, "s9", &start);
 117       supply_register_by_name (regcache, "s10", &end);
 118       break;
 119     case 4:
 120       supply_register_by_name (regcache, "s11", &start);
 121       supply_register_by_name (regcache, "s12", &end);
 122       break;
 123     case 5:
 124       supply_register_by_name (regcache, "s13", &start);
 125       supply_register_by_name (regcache, "s14", &end);
 126       break;
 127     }
 128 }
 129
 130 static int
 131 cris_supports_z_point_type (char z_type)
 132 {
 133   switch (z_type)
 134     {
 135     case Z_PACKET_WRITE_WP:
 136     case Z_PACKET_READ_WP:
 137     case Z_PACKET_ACCESS_WP:
 138       return 1;
 139     default:
 140       return 0;
 141     }
 142 }
 143
 144 static int
 145 cris_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
 146                    int len, struct raw_breakpoint *bp)
 147 {
 148   int bp;
 149   unsigned long bp_ctrl;
 150   unsigned long start, end;
 151   unsigned long ccs;
 152   struct regcache *regcache;
 153
 154   regcache = get_thread_regcache (current_thread, 1);
 155
 156   /* Read watchpoints are set as access watchpoints, because of GDB's
 157      inability to deal with pure read watchpoints.  */
 158   if (type == raw_bkpt_type_read_wp)
 159     type = raw_bkpt_type_access_wp;
 160
 161   /* Get the configuration register.  */
 162   collect_register_by_name (regcache, "s0", &bp_ctrl);
 163
 164   /* The watchpoint allocation scheme is the simplest possible.
 165      For example, if a region is watched for read and
 166      a write watch is requested, a new watchpoint will
 167      be used.  Also, if a watch for a region that is already
 168      covered by one or more existing watchpoints, a new
 169      watchpoint will be used.  */
 170
 171   /* First, find a free data watchpoint.  */
 172   for (bp = 0; bp < 6; bp++)
 173     {
 174       /* Each data watchpoint's control registers occupy 2 bits
 175          (hence the 3), starting at bit 2 for D0 (hence the 2)
 176          with 4 bits between for each watchpoint (yes, the 4).  */
 177       if (!(bp_ctrl & (0x3 << (2 + (bp * 4)))))
 178         break;
 179     }
 180
 181   if (bp > 5)
 182     {
 183       /* We're out of watchpoints.  */
 184       return -1;
 185     }
 186
 187   /* Configure the control register first.  */
 188   if (type == raw_bkpt_type_read_wp || type == raw_bkpt_type_access_wp)
 189     {
 190       /* Trigger on read.  */
 191       bp_ctrl |= (1 << (2 + bp * 4));
 192     }
 193   if (type == raw_bkpt_type_write_wp || type == raw_bkpt_type_access_wp)
 194     {
 195       /* Trigger on write.  */
 196       bp_ctrl |= (2 << (2 + bp * 4));
 197     }
 198
 199   /* Setup the configuration register.  */
 200   supply_register_by_name (regcache, "s0", &bp_ctrl);
 201
 202   /* Setup the range.  */
 203   start = addr;
 204   end = addr + len - 1;
 205
 206   /* Configure the watchpoint register.  */
 207   cris_write_data_breakpoint (regcache, bp, start, end);
 208
 209   collect_register_by_name (regcache, "ccs", &ccs);
 210   /* Set the S1 flag to enable watchpoints.  */
 211   ccs |= (1 << 19);
 212   supply_register_by_name (regcache, "ccs", &ccs);
 213
 214   return 0;
 215 }
 216
 217 static int
 218 cris_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, int len,
 219                    struct raw_breakpoint *bp)
 220 {
 221   int bp;
 222   unsigned long bp_ctrl;
 223   unsigned long start, end;
 224   struct regcache *regcache;
 225   unsigned long bp_d_regs[12];
 226
 227   regcache = get_thread_regcache (current_thread, 1);
 228
 229   /* Read watchpoints are set as access watchpoints, because of GDB's
 230      inability to deal with pure read watchpoints.  */
 231   if (type == raw_bkpt_type_read_wp)
 232     type = raw_bkpt_type_access_wp;
 233
 234   /* Get the configuration register.  */
 235   collect_register_by_name (regcache, "s0", &bp_ctrl);
 236
 237   /* Try to find a watchpoint that is configured for the
 238      specified range, then check that read/write also matches.  */
 239
 240   /* Ugly pointer arithmetic, since I cannot rely on a
 241      single switch (addr) as there may be several watchpoints with
 242      the same start address for example.  */
 243
 244   /* Get all range registers to simplify search.  */
 245   collect_register_by_name (regcache, "s3", &bp_d_regs[0]);
 246   collect_register_by_name (regcache, "s4", &bp_d_regs[1]);
 247   collect_register_by_name (regcache, "s5", &bp_d_regs[2]);
 248   collect_register_by_name (regcache, "s6", &bp_d_regs[3]);
 249   collect_register_by_name (regcache, "s7", &bp_d_regs[4]);
 250   collect_register_by_name (regcache, "s8", &bp_d_regs[5]);
 251   collect_register_by_name (regcache, "s9", &bp_d_regs[6]);
 252   collect_register_by_name (regcache, "s10", &bp_d_regs[7]);
 253   collect_register_by_name (regcache, "s11", &bp_d_regs[8]);
 254   collect_register_by_name (regcache, "s12", &bp_d_regs[9]);
 255   collect_register_by_name (regcache, "s13", &bp_d_regs[10]);
 256   collect_register_by_name (regcache, "s14", &bp_d_regs[11]);
 257
 258   for (bp = 0; bp < 6; bp++)
 259     {
 260       if (bp_d_regs[bp * 2] == addr
 261           && bp_d_regs[bp * 2 + 1] == (addr + len - 1)) {
 262         /* Matching range.  */
 263         int bitpos = 2 + bp * 4;
 264         int rw_bits;
 265
 266         /* Read/write bits for this BP.  */
 267         rw_bits = (bp_ctrl & (0x3 << bitpos)) >> bitpos;
 268
 269         if ((type == raw_bkpt_type_read_wp && rw_bits == 0x1)
 270             || (type == raw_bkpt_type_write_wp && rw_bits == 0x2)
 271             || (type == raw_bkpt_type_access_wp && rw_bits == 0x3))
 272           {
 273             /* Read/write matched.  */
 274             break;
 275           }
 276       }
 277     }
 278
 279   if (bp > 5)
 280     {
 281       /* No watchpoint matched.  */
 282       return -1;
 283     }
 284
 285   /* Found a matching watchpoint.  Now, deconfigure it by
 286      both disabling read/write in bp_ctrl and zeroing its
 287      start/end addresses.  */
 288   bp_ctrl &= ~(3 << (2 + (bp * 4)));
 289   /* Setup the configuration register.  */
 290   supply_register_by_name (regcache, "s0", &bp_ctrl);
 291
 292   start = end = 0;
 293   /* Configure the watchpoint register.  */
 294   cris_write_data_breakpoint (regcache, bp, start, end);
 295
 296   /* Note that we don't clear the S1 flag here.  It's done when continuing.  */
 297   return 0;
 298 }
 299
 300 static int
 301 cris_stopped_by_watchpoint (void)
 302 {
 303   unsigned long exs;
 304   struct regcache *regcache = get_thread_regcache (current_thread, 1);
 305
 306   collect_register_by_name (regcache, "exs", &exs);
 307
 308   return (((exs & 0xff00) >> 8) == 0xc);
 309 }
 310
 311 static CORE_ADDR
 312 cris_stopped_data_address (void)
 313 {
 314   unsigned long eda;
 315   struct regcache *regcache = get_thread_regcache (current_thread, 1);
 316
 317   collect_register_by_name (regcache, "eda", &eda);
 318
 319   /* FIXME: Possibly adjust to match watched range.  */
 320   return eda;
 321 }
 322
 323 ps_err_e
 324 ps_get_thread_area (struct ps_prochandle *ph,
 325                     lwpid_t lwpid, int idx, void **base)
 326 {
 327   if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
 328     return PS_ERR;
 329
 330   /* IDX is the bias from the thread pointer to the beginning of the
 331      thread descriptor.  It has to be subtracted due to implementation
 332      quirks in libthread_db.  */
 333   *base = (void *) ((char *) *base - idx);
 334   return PS_OK;
 335 }
 336
 337 static void
 338 cris_fill_gregset (struct regcache *regcache, void *buf)
 339 {
 340   int i;
 341
 342   for (i = 0; i < cris_num_regs; i++)
 343     {
 344       if (cris_regmap[i] != -1)
 345         collect_register (regcache, i, ((char *) buf) + cris_regmap[i]);
 346     }
 347 }
 348
 349 static void
 350 cris_store_gregset (struct regcache *regcache, const void *buf)
 351 {
 352   int i;
 353
 354   for (i = 0; i < cris_num_regs; i++)
 355     {
 356       if (cris_regmap[i] != -1)
 357         supply_register (regcache, i, ((char *) buf) + cris_regmap[i]);
 358     }
 359 }
 360
 361 static void
 362 cris_arch_setup (void)
 363 {
 364   current_process ()->tdesc = tdesc_crisv32;
 365 }
 366
 367 /* Support for hardware single step.  */
 368
 369 static int
 370 cris_supports_hardware_single_step (void)
 371 {
 372   return 1;
 373 }
 374
 375 static struct regset_info cris_regsets[] = {
 376   { PTRACE_GETREGS, PTRACE_SETREGS, 0, cris_num_regs * 4,
 377     GENERAL_REGS, cris_fill_gregset, cris_store_gregset },
 378   NULL_REGSET
 379 };
 380
 381
 382 static struct regsets_info cris_regsets_info =
 383   {
 384     cris_regsets, /* regsets */
 385     0, /* num_regsets */
 386     NULL, /* disabled_regsets */
 387   };
 388
 389 static struct usrregs_info cris_usrregs_info =
 390   {
 391     cris_num_regs,
 392     cris_regmap,
 393   };
 394
 395 static struct regs_info regs_info =
 396   {
 397     NULL, /* regset_bitmap */
 398     &cris_usrregs_info,
 399     &cris_regsets_info
 400   };
 401
 402 static const struct regs_info *
 403 cris_regs_info (void)
 404 {
 405   return &regs_info;
 406 }
 407
 408 struct linux_target_ops the_low_target = {
 409   cris_arch_setup,
 410   cris_regs_info,
 411   NULL,
 412   NULL,
 413   NULL, /* fetch_register */
 414   linux_get_pc_32bit,
 415   linux_set_pc_32bit,
 416   NULL, /* breakpoint_kind_from_pc */
 417   cris_sw_breakpoint_from_kind,
 418   NULL, /* get_next_pcs */
 419   0,
 420   cris_breakpoint_at,
 421   cris_supports_z_point_type,
 422   cris_insert_point,
 423   cris_remove_point,
 424   cris_stopped_by_watchpoint,
 425   cris_stopped_data_address,
 426   NULL, /* collect_ptrace_register */
 427   NULL, /* supply_ptrace_register */
 428   NULL, /* siginfo_fixup */
 429   NULL, /* new_process */
 430   NULL, /* delete_process */
 431   NULL, /* new_thread */
 432   NULL, /* delete_thread */
 433   NULL, /* new_fork */
 434   NULL, /* prepare_to_resume */
 435   NULL, /* process_qsupported */
 436   NULL, /* supports_tracepoints */
 437   NULL, /* get_thread_area */
 438   NULL, /* install_fast_tracepoint_jump_pad */
 439   NULL, /* emit_ops */
 440   NULL, /* get_min_fast_tracepoint_insn_len */
 441   NULL, /* supports_range_stepping */
 442   NULL, /* breakpoint_kind_from_current_state */
 443   cris_supports_hardware_single_step,
 444 };
 445
 446 /* The linux target ops object.  */
 447
 448 linux_process_target *the_linux_target = &the_crisv32_target;
 449
 450 void
 451 initialize_low_arch (void)
 452 {
 453   init_registers_crisv32 ();
 454
 455   initialize_regsets_info (&cris_regsets_info);
 456 }