gdbserver/linux-crisv32-low.cc

   1 /* GNU/Linux/CRIS specific low level interface, for the remote server for GDB.
   2    Copyright (C) 1995-2020 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #include "server.h"
  20 #include "linux-low.h"
  21 #include "nat/gdb_ptrace.h"
  22
  23 /* Linux target op definitions for the CRIS architecture.  */
  24
  25 class crisv32_target : public linux_process_target
  26 {
  27 public:
  28
  29   const regs_info *get_regs_info () override;
  30
  31   const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override;
  32
  33   bool supports_z_point_type (char z_type) override;
  34
  35 protected:
  36
  37   void low_arch_setup () override;
  38
  39   bool low_cannot_fetch_register (int regno) override;
  40
  41   bool low_cannot_store_register (int regno) override;
  42
  43   bool low_supports_breakpoints () override;
  44
  45   CORE_ADDR low_get_pc (regcache *regcache) override;
  46
  47   void low_set_pc (regcache *regcache, CORE_ADDR newpc) override;
  48
  49   bool low_breakpoint_at (CORE_ADDR pc) override;
  50 };
  51
  52 /* The singleton target ops object.  */
  53
  54 static crisv32_target the_crisv32_target;
  55
  56 bool
  57 crisv32_target::low_cannot_fetch_register (int regno)
  58 {
  59   gdb_assert_not_reached ("linux target op low_cannot_fetch_register "
  60                           "is not implemented by the target");
  61 }
  62
  63 bool
  64 crisv32_target::low_cannot_store_register (int regno)
  65 {
  66   gdb_assert_not_reached ("linux target op low_cannot_store_register "
  67                           "is not implemented by the target");
  68 }
  69
  70 bool
  71 crisv32_target::low_supports_breakpoints ()
  72 {
  73   return true;
  74 }
  75
  76 CORE_ADDR
  77 crisv32_target::low_get_pc (regcache *regcache)
  78 {
  79   return linux_get_pc_32bit (regcache);
  80 }
  81
  82 void
  83 crisv32_target::low_set_pc (regcache *regcache, CORE_ADDR pc)
  84 {
  85   linux_set_pc_32bit (regcache, pc);
  86 }
  87
  88 /* Defined in auto-generated file reg-crisv32.c.  */
  89 void init_registers_crisv32 (void);
  90 extern const struct target_desc *tdesc_crisv32;
  91
  92 /* CRISv32 */
  93 #define cris_num_regs 49
  94
  95 #ifndef PTRACE_GET_THREAD_AREA
  96 #define PTRACE_GET_THREAD_AREA 25
  97 #endif
  98
  99 /* Note: Ignoring USP (having the stack pointer in two locations causes trouble
 100    without any significant gain).  */
 101
 102 /* Locations need to match <include/asm/arch/ptrace.h>.  */
 103 static int cris_regmap[] = {
 104   1*4, 2*4, 3*4, 4*4,
 105   5*4, 6*4, 7*4, 8*4,
 106   9*4, 10*4, 11*4, 12*4,
 107   13*4, 14*4, 24*4, 15*4,
 108
 109   -1, -1, -1, 16*4,
 110   -1, 22*4, 23*4, 17*4,
 111   -1, -1, 21*4, 20*4,
 112   -1, 19*4, -1, 18*4,
 113
 114   25*4,
 115
 116   26*4, -1,   -1,   29*4,
 117   30*4, 31*4, 32*4, 33*4,
 118   34*4, 35*4, 36*4, 37*4,
 119   38*4, 39*4, 40*4, -1
 120
 121 };
 122
 123 static const unsigned short cris_breakpoint = 0xe938;
 124 #define cris_breakpoint_len 2
 125
 126 /* Implementation of target ops method "sw_breakpoint_from_kind".  */
 127
 128 const gdb_byte *
 129 crisv32_target::sw_breakpoint_from_kind (int kind, int *size)
 130 {
 131   *size = cris_breakpoint_len;
 132   return (const gdb_byte *) &cris_breakpoint;
 133 }
 134
 135 bool
 136 crisv32_target::low_breakpoint_at (CORE_ADDR where)
 137 {
 138   unsigned short insn;
 139
 140   read_memory (where, (unsigned char *) &insn, cris_breakpoint_len);
 141   if (insn == cris_breakpoint)
 142     return true;
 143
 144   /* If necessary, recognize more trap instructions here.  GDB only uses the
 145      one.  */
 146   return false;
 147 }
 148
 149 static void
 150 cris_write_data_breakpoint (struct regcache *regcache,
 151                             int bp, unsigned long start, unsigned long end)
 152 {
 153   switch (bp)
 154     {
 155     case 0:
 156       supply_register_by_name (regcache, "s3", &start);
 157       supply_register_by_name (regcache, "s4", &end);
 158       break;
 159     case 1:
 160       supply_register_by_name (regcache, "s5", &start);
 161       supply_register_by_name (regcache, "s6", &end);
 162       break;
 163     case 2:
 164       supply_register_by_name (regcache, "s7", &start);
 165       supply_register_by_name (regcache, "s8", &end);
 166       break;
 167     case 3:
 168       supply_register_by_name (regcache, "s9", &start);
 169       supply_register_by_name (regcache, "s10", &end);
 170       break;
 171     case 4:
 172       supply_register_by_name (regcache, "s11", &start);
 173       supply_register_by_name (regcache, "s12", &end);
 174       break;
 175     case 5:
 176       supply_register_by_name (regcache, "s13", &start);
 177       supply_register_by_name (regcache, "s14", &end);
 178       break;
 179     }
 180 }
 181
 182 bool
 183 crisv32_target::supports_z_point_type (char z_type)
 184 {
 185   switch (z_type)
 186     {
 187     case Z_PACKET_WRITE_WP:
 188     case Z_PACKET_READ_WP:
 189     case Z_PACKET_ACCESS_WP:
 190       return true;
 191     default:
 192       return false;
 193     }
 194 }
 195
 196 static int
 197 cris_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
 198                    int len, struct raw_breakpoint *bp)
 199 {
 200   int bp;
 201   unsigned long bp_ctrl;
 202   unsigned long start, end;
 203   unsigned long ccs;
 204   struct regcache *regcache;
 205
 206   regcache = get_thread_regcache (current_thread, 1);
 207
 208   /* Read watchpoints are set as access watchpoints, because of GDB's
 209      inability to deal with pure read watchpoints.  */
 210   if (type == raw_bkpt_type_read_wp)
 211     type = raw_bkpt_type_access_wp;
 212
 213   /* Get the configuration register.  */
 214   collect_register_by_name (regcache, "s0", &bp_ctrl);
 215
 216   /* The watchpoint allocation scheme is the simplest possible.
 217      For example, if a region is watched for read and
 218      a write watch is requested, a new watchpoint will
 219      be used.  Also, if a watch for a region that is already
 220      covered by one or more existing watchpoints, a new
 221      watchpoint will be used.  */
 222
 223   /* First, find a free data watchpoint.  */
 224   for (bp = 0; bp < 6; bp++)
 225     {
 226       /* Each data watchpoint's control registers occupy 2 bits
 227          (hence the 3), starting at bit 2 for D0 (hence the 2)
 228          with 4 bits between for each watchpoint (yes, the 4).  */
 229       if (!(bp_ctrl & (0x3 << (2 + (bp * 4)))))
 230         break;
 231     }
 232
 233   if (bp > 5)
 234     {
 235       /* We're out of watchpoints.  */
 236       return -1;
 237     }
 238
 239   /* Configure the control register first.  */
 240   if (type == raw_bkpt_type_read_wp || type == raw_bkpt_type_access_wp)
 241     {
 242       /* Trigger on read.  */
 243       bp_ctrl |= (1 << (2 + bp * 4));
 244     }
 245   if (type == raw_bkpt_type_write_wp || type == raw_bkpt_type_access_wp)
 246     {
 247       /* Trigger on write.  */
 248       bp_ctrl |= (2 << (2 + bp * 4));
 249     }
 250
 251   /* Setup the configuration register.  */
 252   supply_register_by_name (regcache, "s0", &bp_ctrl);
 253
 254   /* Setup the range.  */
 255   start = addr;
 256   end = addr + len - 1;
 257
 258   /* Configure the watchpoint register.  */
 259   cris_write_data_breakpoint (regcache, bp, start, end);
 260
 261   collect_register_by_name (regcache, "ccs", &ccs);
 262   /* Set the S1 flag to enable watchpoints.  */
 263   ccs |= (1 << 19);
 264   supply_register_by_name (regcache, "ccs", &ccs);
 265
 266   return 0;
 267 }
 268
 269 static int
 270 cris_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, int len,
 271                    struct raw_breakpoint *bp)
 272 {
 273   int bp;
 274   unsigned long bp_ctrl;
 275   unsigned long start, end;
 276   struct regcache *regcache;
 277   unsigned long bp_d_regs[12];
 278
 279   regcache = get_thread_regcache (current_thread, 1);
 280
 281   /* Read watchpoints are set as access watchpoints, because of GDB's
 282      inability to deal with pure read watchpoints.  */
 283   if (type == raw_bkpt_type_read_wp)
 284     type = raw_bkpt_type_access_wp;
 285
 286   /* Get the configuration register.  */
 287   collect_register_by_name (regcache, "s0", &bp_ctrl);
 288
 289   /* Try to find a watchpoint that is configured for the
 290      specified range, then check that read/write also matches.  */
 291
 292   /* Ugly pointer arithmetic, since I cannot rely on a
 293      single switch (addr) as there may be several watchpoints with
 294      the same start address for example.  */
 295
 296   /* Get all range registers to simplify search.  */
 297   collect_register_by_name (regcache, "s3", &bp_d_regs[0]);
 298   collect_register_by_name (regcache, "s4", &bp_d_regs[1]);
 299   collect_register_by_name (regcache, "s5", &bp_d_regs[2]);
 300   collect_register_by_name (regcache, "s6", &bp_d_regs[3]);
 301   collect_register_by_name (regcache, "s7", &bp_d_regs[4]);
 302   collect_register_by_name (regcache, "s8", &bp_d_regs[5]);
 303   collect_register_by_name (regcache, "s9", &bp_d_regs[6]);
 304   collect_register_by_name (regcache, "s10", &bp_d_regs[7]);
 305   collect_register_by_name (regcache, "s11", &bp_d_regs[8]);
 306   collect_register_by_name (regcache, "s12", &bp_d_regs[9]);
 307   collect_register_by_name (regcache, "s13", &bp_d_regs[10]);
 308   collect_register_by_name (regcache, "s14", &bp_d_regs[11]);
 309
 310   for (bp = 0; bp < 6; bp++)
 311     {
 312       if (bp_d_regs[bp * 2] == addr
 313           && bp_d_regs[bp * 2 + 1] == (addr + len - 1)) {
 314         /* Matching range.  */
 315         int bitpos = 2 + bp * 4;
 316         int rw_bits;
 317
 318         /* Read/write bits for this BP.  */
 319         rw_bits = (bp_ctrl & (0x3 << bitpos)) >> bitpos;
 320
 321         if ((type == raw_bkpt_type_read_wp && rw_bits == 0x1)
 322             || (type == raw_bkpt_type_write_wp && rw_bits == 0x2)
 323             || (type == raw_bkpt_type_access_wp && rw_bits == 0x3))
 324           {
 325             /* Read/write matched.  */
 326             break;
 327           }
 328       }
 329     }
 330
 331   if (bp > 5)
 332     {
 333       /* No watchpoint matched.  */
 334       return -1;
 335     }
 336
 337   /* Found a matching watchpoint.  Now, deconfigure it by
 338      both disabling read/write in bp_ctrl and zeroing its
 339      start/end addresses.  */
 340   bp_ctrl &= ~(3 << (2 + (bp * 4)));
 341   /* Setup the configuration register.  */
 342   supply_register_by_name (regcache, "s0", &bp_ctrl);
 343
 344   start = end = 0;
 345   /* Configure the watchpoint register.  */
 346   cris_write_data_breakpoint (regcache, bp, start, end);
 347
 348   /* Note that we don't clear the S1 flag here.  It's done when continuing.  */
 349   return 0;
 350 }
 351
 352 static int
 353 cris_stopped_by_watchpoint (void)
 354 {
 355   unsigned long exs;
 356   struct regcache *regcache = get_thread_regcache (current_thread, 1);
 357
 358   collect_register_by_name (regcache, "exs", &exs);
 359
 360   return (((exs & 0xff00) >> 8) == 0xc);
 361 }
 362
 363 static CORE_ADDR
 364 cris_stopped_data_address (void)
 365 {
 366   unsigned long eda;
 367   struct regcache *regcache = get_thread_regcache (current_thread, 1);
 368
 369   collect_register_by_name (regcache, "eda", &eda);
 370
 371   /* FIXME: Possibly adjust to match watched range.  */
 372   return eda;
 373 }
 374
 375 ps_err_e
 376 ps_get_thread_area (struct ps_prochandle *ph,
 377                     lwpid_t lwpid, int idx, void **base)
 378 {
 379   if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
 380     return PS_ERR;
 381
 382   /* IDX is the bias from the thread pointer to the beginning of the
 383      thread descriptor.  It has to be subtracted due to implementation
 384      quirks in libthread_db.  */
 385   *base = (void *) ((char *) *base - idx);
 386   return PS_OK;
 387 }
 388
 389 static void
 390 cris_fill_gregset (struct regcache *regcache, void *buf)
 391 {
 392   int i;
 393
 394   for (i = 0; i < cris_num_regs; i++)
 395     {
 396       if (cris_regmap[i] != -1)
 397         collect_register (regcache, i, ((char *) buf) + cris_regmap[i]);
 398     }
 399 }
 400
 401 static void
 402 cris_store_gregset (struct regcache *regcache, const void *buf)
 403 {
 404   int i;
 405
 406   for (i = 0; i < cris_num_regs; i++)
 407     {
 408       if (cris_regmap[i] != -1)
 409         supply_register (regcache, i, ((char *) buf) + cris_regmap[i]);
 410     }
 411 }
 412
 413 void
 414 crisv32_target::low_arch_setup ()
 415 {
 416   current_process ()->tdesc = tdesc_crisv32;
 417 }
 418
 419 /* Support for hardware single step.  */
 420
 421 static int
 422 cris_supports_hardware_single_step (void)
 423 {
 424   return 1;
 425 }
 426
 427 static struct regset_info cris_regsets[] = {
 428   { PTRACE_GETREGS, PTRACE_SETREGS, 0, cris_num_regs * 4,
 429     GENERAL_REGS, cris_fill_gregset, cris_store_gregset },
 430   NULL_REGSET
 431 };
 432
 433
 434 static struct regsets_info cris_regsets_info =
 435   {
 436     cris_regsets, /* regsets */
 437     0, /* num_regsets */
 438     NULL, /* disabled_regsets */
 439   };
 440
 441 static struct usrregs_info cris_usrregs_info =
 442   {
 443     cris_num_regs,
 444     cris_regmap,
 445   };
 446
 447 static struct regs_info myregs_info =
 448   {
 449     NULL, /* regset_bitmap */
 450     &cris_usrregs_info,
 451     &cris_regsets_info
 452   };
 453
 454 const regs_info *
 455 crisv32_target::get_regs_info ()
 456 {
 457   return &myregs_info;
 458 }
 459
 460 struct linux_target_ops the_low_target = {
 461   cris_insert_point,
 462   cris_remove_point,
 463   cris_stopped_by_watchpoint,
 464   cris_stopped_data_address,
 465   NULL, /* collect_ptrace_register */
 466   NULL, /* supply_ptrace_register */
 467   NULL, /* siginfo_fixup */
 468   NULL, /* new_process */
 469   NULL, /* delete_process */
 470   NULL, /* new_thread */
 471   NULL, /* delete_thread */
 472   NULL, /* new_fork */
 473   NULL, /* prepare_to_resume */
 474   NULL, /* process_qsupported */
 475   NULL, /* supports_tracepoints */
 476   NULL, /* get_thread_area */
 477   NULL, /* install_fast_tracepoint_jump_pad */
 478   NULL, /* emit_ops */
 479   NULL, /* get_min_fast_tracepoint_insn_len */
 480   NULL, /* supports_range_stepping */
 481   cris_supports_hardware_single_step,
 482 };
 483
 484 /* The linux target ops object.  */
 485
 486 linux_process_target *the_linux_target = &the_crisv32_target;
 487
 488 void
 489 initialize_low_arch (void)
 490 {
 491   init_registers_crisv32 ();
 492
 493   initialize_regsets_info (&cris_regsets_info);
 494 }