gdbserver/linux-mips-low.cc

   1 /* GNU/Linux/MIPS specific low level interface, for the remote server for GDB.
   2    Copyright (C) 1995-2020 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #include "server.h"
  20 #include "linux-low.h"
  21
  22 #include "nat/gdb_ptrace.h"
  23 #include <endian.h>
  24
  25 #include "nat/mips-linux-watch.h"
  26 #include "gdb_proc_service.h"
  27
  28 /* Linux target op definitions for the MIPS architecture.  */
  29
  30 class mips_target : public linux_process_target
  31 {
  32 public:
  33
  34   const regs_info *get_regs_info () override;
  35
  36   const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override;
  37
  38   bool supports_z_point_type (char z_type) override;
  39
  40 protected:
  41
  42   void low_arch_setup () override;
  43
  44   bool low_cannot_fetch_register (int regno) override;
  45
  46   bool low_cannot_store_register (int regno) override;
  47
  48   bool low_fetch_register (regcache *regcache, int regno) override;
  49
  50   bool low_supports_breakpoints () override;
  51
  52   CORE_ADDR low_get_pc (regcache *regcache) override;
  53
  54   void low_set_pc (regcache *regcache, CORE_ADDR newpc) override;
  55
  56   bool low_breakpoint_at (CORE_ADDR pc) override;
  57
  58   int low_insert_point (raw_bkpt_type type, CORE_ADDR addr,
  59                         int size, raw_breakpoint *bp) override;
  60
  61   int low_remove_point (raw_bkpt_type type, CORE_ADDR addr,
  62                         int size, raw_breakpoint *bp) override;
  63
  64   bool low_stopped_by_watchpoint () override;
  65
  66   CORE_ADDR low_stopped_data_address () override;
  67 };
  68
  69 /* The singleton target ops object.  */
  70
  71 static mips_target the_mips_target;
  72
  73 /* Defined in auto-generated file mips-linux.c.  */
  74 void init_registers_mips_linux (void);
  75 extern const struct target_desc *tdesc_mips_linux;
  76
  77 /* Defined in auto-generated file mips-dsp-linux.c.  */
  78 void init_registers_mips_dsp_linux (void);
  79 extern const struct target_desc *tdesc_mips_dsp_linux;
  80
  81 /* Defined in auto-generated file mips64-linux.c.  */
  82 void init_registers_mips64_linux (void);
  83 extern const struct target_desc *tdesc_mips64_linux;
  84
  85 /* Defined in auto-generated file mips64-dsp-linux.c.  */
  86 void init_registers_mips64_dsp_linux (void);
  87 extern const struct target_desc *tdesc_mips64_dsp_linux;
  88
  89 #ifdef __mips64
  90 #define tdesc_mips_linux tdesc_mips64_linux
  91 #define tdesc_mips_dsp_linux tdesc_mips64_dsp_linux
  92 #endif
  93
  94 #ifndef PTRACE_GET_THREAD_AREA
  95 #define PTRACE_GET_THREAD_AREA 25
  96 #endif
  97
  98 #ifdef HAVE_SYS_REG_H
  99 #include <sys/reg.h>
 100 #endif
 101
 102 #define mips_num_regs 73
 103 #define mips_dsp_num_regs 80
 104
 105 #include <asm/ptrace.h>
 106
 107 #ifndef DSP_BASE
 108 #define DSP_BASE 71
 109 #define DSP_CONTROL 77
 110 #endif
 111
 112 union mips_register
 113 {
 114   unsigned char buf[8];
 115
 116   /* Deliberately signed, for proper sign extension.  */
 117   int reg32;
 118   long long reg64;
 119 };
 120
 121 /* Return the ptrace ``address'' of register REGNO. */
 122
 123 #define mips_base_regs                                                  \
 124   -1,  1,  2,  3,  4,  5,  6,  7,                                       \
 125   8,  9,  10, 11, 12, 13, 14, 15,                                       \
 126   16, 17, 18, 19, 20, 21, 22, 23,                                       \
 127   24, 25, 26, 27, 28, 29, 30, 31,                                       \
 128                                                                         \
 129   -1, MMLO, MMHI, BADVADDR, CAUSE, PC,                                  \
 130                                                                         \
 131   FPR_BASE,      FPR_BASE + 1,  FPR_BASE + 2,  FPR_BASE + 3,            \
 132   FPR_BASE + 4,  FPR_BASE + 5,  FPR_BASE + 6,  FPR_BASE + 7,            \
 133   FPR_BASE + 8,  FPR_BASE + 9,  FPR_BASE + 10, FPR_BASE + 11,           \
 134   FPR_BASE + 12, FPR_BASE + 13, FPR_BASE + 14, FPR_BASE + 15,           \
 135   FPR_BASE + 16, FPR_BASE + 17, FPR_BASE + 18, FPR_BASE + 19,           \
 136   FPR_BASE + 20, FPR_BASE + 21, FPR_BASE + 22, FPR_BASE + 23,           \
 137   FPR_BASE + 24, FPR_BASE + 25, FPR_BASE + 26, FPR_BASE + 27,           \
 138   FPR_BASE + 28, FPR_BASE + 29, FPR_BASE + 30, FPR_BASE + 31,           \
 139   FPC_CSR, FPC_EIR
 140
 141 #define mips_dsp_regs                                                   \
 142   DSP_BASE,      DSP_BASE + 1,  DSP_BASE + 2,  DSP_BASE + 3,            \
 143   DSP_BASE + 4,  DSP_BASE + 5,                                          \
 144   DSP_CONTROL
 145
 146 static int mips_regmap[mips_num_regs] = {
 147   mips_base_regs,
 148   0
 149 };
 150
 151 static int mips_dsp_regmap[mips_dsp_num_regs] = {
 152   mips_base_regs,
 153   mips_dsp_regs,
 154   0
 155 };
 156
 157 /* DSP registers are not in any regset and can only be accessed
 158    individually.  */
 159
 160 static unsigned char mips_dsp_regset_bitmap[(mips_dsp_num_regs + 7) / 8] = {
 161   0xfe, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x80
 162 };
 163
 164 static int have_dsp = -1;
 165
 166 /* Try peeking at an arbitrarily chosen DSP register and pick the available
 167    user register set accordingly.  */
 168
 169 static const struct target_desc *
 170 mips_read_description (void)
 171 {
 172   if (have_dsp < 0)
 173     {
 174       int pid = lwpid_of (current_thread);
 175
 176       errno = 0;
 177       ptrace (PTRACE_PEEKUSER, pid, DSP_CONTROL, 0);
 178       switch (errno)
 179         {
 180         case 0:
 181           have_dsp = 1;
 182           break;
 183         case EIO:
 184           have_dsp = 0;
 185           break;
 186         default:
 187           perror_with_name ("ptrace");
 188           break;
 189         }
 190     }
 191
 192   return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux;
 193 }
 194
 195 void
 196 mips_target::low_arch_setup ()
 197 {
 198   current_process ()->tdesc = mips_read_description ();
 199 }
 200
 201 /* Per-process arch-specific data we want to keep.  */
 202
 203 struct arch_process_info
 204 {
 205   /* -1 if the kernel and/or CPU do not support watch registers.
 206       1 if watch_readback is valid and we can read style, num_valid
 207         and the masks.
 208       0 if we need to read the watch_readback.  */
 209
 210   int watch_readback_valid;
 211
 212   /* Cached watch register read values.  */
 213
 214   struct pt_watch_regs watch_readback;
 215
 216   /* Current watchpoint requests for this process.  */
 217
 218   struct mips_watchpoint *current_watches;
 219
 220   /* The current set of watch register values for writing the
 221      registers.  */
 222
 223   struct pt_watch_regs watch_mirror;
 224 };
 225
 226 /* Per-thread arch-specific data we want to keep.  */
 227
 228 struct arch_lwp_info
 229 {
 230   /* Non-zero if our copy differs from what's recorded in the thread.  */
 231   int watch_registers_changed;
 232 };
 233
 234 /* From mips-linux-nat.c.  */
 235
 236 /* Pseudo registers can not be read.  ptrace does not provide a way to
 237    read (or set) PS_REGNUM, and there's no point in reading or setting
 238    ZERO_REGNUM, it's always 0.  We also can not set BADVADDR, CAUSE,
 239    or FCRIR via ptrace().  */
 240
 241 bool
 242 mips_target::low_cannot_fetch_register (int regno)
 243 {
 244   const struct target_desc *tdesc;
 245
 246   if (get_regs_info ()->usrregs->regmap[regno] == -1)
 247     return true;
 248
 249   tdesc = current_process ()->tdesc;
 250
 251   /* On n32 we can't access 64-bit registers via PTRACE_PEEKUSR.  */
 252   if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE))
 253     return true;
 254
 255   if (find_regno (tdesc, "r0") == regno)
 256     return true;
 257
 258   return false;
 259 }
 260
 261 bool
 262 mips_target::low_cannot_store_register (int regno)
 263 {
 264   const struct target_desc *tdesc;
 265
 266   if (get_regs_info ()->usrregs->regmap[regno] == -1)
 267     return true;
 268
 269   tdesc = current_process ()->tdesc;
 270
 271   /* On n32 we can't access 64-bit registers via PTRACE_POKEUSR.  */
 272   if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE))
 273     return true;
 274
 275   if (find_regno (tdesc, "r0") == regno)
 276     return true;
 277
 278   if (find_regno (tdesc, "cause") == regno)
 279     return true;
 280
 281   if (find_regno (tdesc, "badvaddr") == regno)
 282     return true;
 283
 284   if (find_regno (tdesc, "fir") == regno)
 285     return true;
 286
 287   return false;
 288 }
 289
 290 bool
 291 mips_target::low_fetch_register (regcache *regcache, int regno)
 292 {
 293   const struct target_desc *tdesc = current_process ()->tdesc;
 294
 295   if (find_regno (tdesc, "r0") == regno)
 296     {
 297       supply_register_zeroed (regcache, regno);
 298       return true;
 299     }
 300
 301   return false;
 302 }
 303
 304 bool
 305 mips_target::low_supports_breakpoints ()
 306 {
 307   return true;
 308 }
 309
 310 CORE_ADDR
 311 mips_target::low_get_pc (regcache *regcache)
 312 {
 313   union mips_register pc;
 314   collect_register_by_name (regcache, "pc", pc.buf);
 315   return register_size (regcache->tdesc, 0) == 4 ? pc.reg32 : pc.reg64;
 316 }
 317
 318 void
 319 mips_target::low_set_pc (regcache *regcache, CORE_ADDR pc)
 320 {
 321   union mips_register newpc;
 322   if (register_size (regcache->tdesc, 0) == 4)
 323     newpc.reg32 = pc;
 324   else
 325     newpc.reg64 = pc;
 326
 327   supply_register_by_name (regcache, "pc", newpc.buf);
 328 }
 329
 330 /* Correct in either endianness.  */
 331 static const unsigned int mips_breakpoint = 0x0005000d;
 332 #define mips_breakpoint_len 4
 333
 334 /* Implementation of target ops method "sw_breakpoint_from_kind".  */
 335
 336 const gdb_byte *
 337 mips_target::sw_breakpoint_from_kind (int kind, int *size)
 338 {
 339   *size = mips_breakpoint_len;
 340   return (const gdb_byte *) &mips_breakpoint;
 341 }
 342
 343 bool
 344 mips_target::low_breakpoint_at (CORE_ADDR where)
 345 {
 346   unsigned int insn;
 347
 348   read_memory (where, (unsigned char *) &insn, 4);
 349   if (insn == mips_breakpoint)
 350     return true;
 351
 352   /* If necessary, recognize more trap instructions here.  GDB only uses the
 353      one.  */
 354   return false;
 355 }
 356
 357 /* Mark the watch registers of lwp, represented by ENTRY, as changed.  */
 358
 359 static void
 360 update_watch_registers_callback (thread_info *thread)
 361 {
 362   struct lwp_info *lwp = get_thread_lwp (thread);
 363
 364   /* The actual update is done later just before resuming the lwp,
 365      we just mark that the registers need updating.  */
 366   lwp->arch_private->watch_registers_changed = 1;
 367
 368   /* If the lwp isn't stopped, force it to momentarily pause, so
 369      we can update its watch registers.  */
 370   if (!lwp->stopped)
 371     linux_stop_lwp (lwp);
 372 }
 373
 374 /* This is the implementation of linux_target_ops method
 375    new_process.  */
 376
 377 static struct arch_process_info *
 378 mips_linux_new_process (void)
 379 {
 380   struct arch_process_info *info = XCNEW (struct arch_process_info);
 381
 382   return info;
 383 }
 384
 385 /* This is the implementation of linux_target_ops method
 386    delete_process.  */
 387
 388 static void
 389 mips_linux_delete_process (struct arch_process_info *info)
 390 {
 391   xfree (info);
 392 }
 393
 394 /* This is the implementation of linux_target_ops method new_thread.
 395    Mark the watch registers as changed, so the threads' copies will
 396    be updated.  */
 397
 398 static void
 399 mips_linux_new_thread (struct lwp_info *lwp)
 400 {
 401   struct arch_lwp_info *info = XCNEW (struct arch_lwp_info);
 402
 403   info->watch_registers_changed = 1;
 404
 405   lwp->arch_private = info;
 406 }
 407
 408 /* Function to call when a thread is being deleted.  */
 409
 410 static void
 411 mips_linux_delete_thread (struct arch_lwp_info *arch_lwp)
 412 {
 413   xfree (arch_lwp);
 414 }
 415
 416 /* Create a new mips_watchpoint and add it to the list.  */
 417
 418 static void
 419 mips_add_watchpoint (struct arch_process_info *priv, CORE_ADDR addr, int len,
 420                      enum target_hw_bp_type watch_type)
 421 {
 422   struct mips_watchpoint *new_watch;
 423   struct mips_watchpoint **pw;
 424
 425   new_watch = XNEW (struct mips_watchpoint);
 426   new_watch->addr = addr;
 427   new_watch->len = len;
 428   new_watch->type = watch_type;
 429   new_watch->next = NULL;
 430
 431   pw = &priv->current_watches;
 432   while (*pw != NULL)
 433     pw = &(*pw)->next;
 434   *pw = new_watch;
 435 }
 436
 437 /* Hook to call when a new fork is attached.  */
 438
 439 static void
 440 mips_linux_new_fork (struct process_info *parent,
 441                         struct process_info *child)
 442 {
 443   struct arch_process_info *parent_private;
 444   struct arch_process_info *child_private;
 445   struct mips_watchpoint *wp;
 446
 447   /* These are allocated by linux_add_process.  */
 448   gdb_assert (parent->priv != NULL
 449               && parent->priv->arch_private != NULL);
 450   gdb_assert (child->priv != NULL
 451               && child->priv->arch_private != NULL);
 452
 453   /* Linux kernel before 2.6.33 commit
 454      72f674d203cd230426437cdcf7dd6f681dad8b0d
 455      will inherit hardware debug registers from parent
 456      on fork/vfork/clone.  Newer Linux kernels create such tasks with
 457      zeroed debug registers.
 458
 459      GDB core assumes the child inherits the watchpoints/hw
 460      breakpoints of the parent, and will remove them all from the
 461      forked off process.  Copy the debug registers mirrors into the
 462      new process so that all breakpoints and watchpoints can be
 463      removed together.  The debug registers mirror will become zeroed
 464      in the end before detaching the forked off process, thus making
 465      this compatible with older Linux kernels too.  */
 466
 467   parent_private = parent->priv->arch_private;
 468   child_private = child->priv->arch_private;
 469
 470   child_private->watch_readback_valid = parent_private->watch_readback_valid;
 471   child_private->watch_readback = parent_private->watch_readback;
 472
 473   for (wp = parent_private->current_watches; wp != NULL; wp = wp->next)
 474     mips_add_watchpoint (child_private, wp->addr, wp->len, wp->type);
 475
 476   child_private->watch_mirror = parent_private->watch_mirror;
 477 }
 478 /* This is the implementation of linux_target_ops method
 479    prepare_to_resume.  If the watch regs have changed, update the
 480    thread's copies.  */
 481
 482 static void
 483 mips_linux_prepare_to_resume (struct lwp_info *lwp)
 484 {
 485   ptid_t ptid = ptid_of (get_lwp_thread (lwp));
 486   struct process_info *proc = find_process_pid (ptid.pid ());
 487   struct arch_process_info *priv = proc->priv->arch_private;
 488
 489   if (lwp->arch_private->watch_registers_changed)
 490     {
 491       /* Only update the watch registers if we have set or unset a
 492          watchpoint already.  */
 493       if (mips_linux_watch_get_num_valid (&priv->watch_mirror) > 0)
 494         {
 495           /* Write the mirrored watch register values.  */
 496           int tid = ptid.lwp ();
 497
 498           if (-1 == ptrace (PTRACE_SET_WATCH_REGS, tid,
 499                             &priv->watch_mirror, NULL))
 500             perror_with_name ("Couldn't write watch register");
 501         }
 502
 503       lwp->arch_private->watch_registers_changed = 0;
 504     }
 505 }
 506
 507 bool
 508 mips_target::supports_z_point_type (char z_type)
 509 {
 510   switch (z_type)
 511     {
 512     case Z_PACKET_WRITE_WP:
 513     case Z_PACKET_READ_WP:
 514     case Z_PACKET_ACCESS_WP:
 515       return true;
 516     default:
 517       return false;
 518     }
 519 }
 520
 521 /* This is the implementation of linux target ops method
 522    low_insert_point.  */
 523
 524 int
 525 mips_target::low_insert_point (raw_bkpt_type type, CORE_ADDR addr,
 526                                int len, raw_breakpoint *bp)
 527 {
 528   struct process_info *proc = current_process ();
 529   struct arch_process_info *priv = proc->priv->arch_private;
 530   struct pt_watch_regs regs;
 531   long lwpid;
 532   enum target_hw_bp_type watch_type;
 533   uint32_t irw;
 534
 535   lwpid = lwpid_of (current_thread);
 536   if (!mips_linux_read_watch_registers (lwpid,
 537                                         &priv->watch_readback,
 538                                         &priv->watch_readback_valid,
 539                                         0))
 540     return -1;
 541
 542   if (len <= 0)
 543     return -1;
 544
 545   regs = priv->watch_readback;
 546   /* Add the current watches.  */
 547   mips_linux_watch_populate_regs (priv->current_watches, &regs);
 548
 549   /* Now try to add the new watch.  */
 550   watch_type = raw_bkpt_type_to_target_hw_bp_type (type);
 551   irw = mips_linux_watch_type_to_irw (watch_type);
 552   if (!mips_linux_watch_try_one_watch (&regs, addr, len, irw))
 553     return -1;
 554
 555   /* It fit.  Stick it on the end of the list.  */
 556   mips_add_watchpoint (priv, addr, len, watch_type);
 557
 558   priv->watch_mirror = regs;
 559
 560   /* Only update the threads of this process.  */
 561   for_each_thread (proc->pid, update_watch_registers_callback);
 562
 563   return 0;
 564 }
 565
 566 /* This is the implementation of linux target ops method
 567    low_remove_point.  */
 568
 569 int
 570 mips_target::low_remove_point (raw_bkpt_type type, CORE_ADDR addr,
 571                                int len, raw_breakpoint *bp)
 572 {
 573   struct process_info *proc = current_process ();
 574   struct arch_process_info *priv = proc->priv->arch_private;
 575
 576   int deleted_one;
 577   enum target_hw_bp_type watch_type;
 578
 579   struct mips_watchpoint **pw;
 580   struct mips_watchpoint *w;
 581
 582   /* Search for a known watch that matches.  Then unlink and free it.  */
 583   watch_type = raw_bkpt_type_to_target_hw_bp_type (type);
 584   deleted_one = 0;
 585   pw = &priv->current_watches;
 586   while ((w = *pw))
 587     {
 588       if (w->addr == addr && w->len == len && w->type == watch_type)
 589         {
 590           *pw = w->next;
 591           free (w);
 592           deleted_one = 1;
 593           break;
 594         }
 595       pw = &(w->next);
 596     }
 597
 598   if (!deleted_one)
 599     return -1;  /* We don't know about it, fail doing nothing.  */
 600
 601   /* At this point watch_readback is known to be valid because we
 602      could not have added the watch without reading it.  */
 603   gdb_assert (priv->watch_readback_valid == 1);
 604
 605   priv->watch_mirror = priv->watch_readback;
 606   mips_linux_watch_populate_regs (priv->current_watches,
 607                                   &priv->watch_mirror);
 608
 609   /* Only update the threads of this process.  */
 610   for_each_thread (proc->pid, update_watch_registers_callback);
 611
 612   return 0;
 613 }
 614
 615 /* This is the implementation of linux target ops method
 616    low_stopped_by_watchpoint.  The watchhi R and W bits indicate
 617    the watch register triggered. */
 618
 619 bool
 620 mips_target::low_stopped_by_watchpoint ()
 621 {
 622   struct process_info *proc = current_process ();
 623   struct arch_process_info *priv = proc->priv->arch_private;
 624   int n;
 625   int num_valid;
 626   long lwpid = lwpid_of (current_thread);
 627
 628   if (!mips_linux_read_watch_registers (lwpid,
 629                                         &priv->watch_readback,
 630                                         &priv->watch_readback_valid,
 631                                         1))
 632     return 0;
 633
 634   num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback);
 635
 636   for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
 637     if (mips_linux_watch_get_watchhi (&priv->watch_readback, n)
 638         & (R_MASK | W_MASK))
 639       return true;
 640
 641   return false;
 642 }
 643
 644 /* This is the implementation of linux target ops method
 645    low_stopped_data_address.  */
 646
 647 CORE_ADDR
 648 mips_target::low_stopped_data_address ()
 649 {
 650   struct process_info *proc = current_process ();
 651   struct arch_process_info *priv = proc->priv->arch_private;
 652   int n;
 653   int num_valid;
 654   long lwpid = lwpid_of (current_thread);
 655
 656   /* On MIPS we don't know the low order 3 bits of the data address.
 657      GDB does not support remote targets that can't report the
 658      watchpoint address.  So, make our best guess; return the starting
 659      address of a watchpoint request which overlaps the one that
 660      triggered.  */
 661
 662   if (!mips_linux_read_watch_registers (lwpid,
 663                                         &priv->watch_readback,
 664                                         &priv->watch_readback_valid,
 665                                         0))
 666     return 0;
 667
 668   num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback);
 669
 670   for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
 671     if (mips_linux_watch_get_watchhi (&priv->watch_readback, n)
 672         & (R_MASK | W_MASK))
 673       {
 674         CORE_ADDR t_low, t_hi;
 675         int t_irw;
 676         struct mips_watchpoint *watch;
 677
 678         t_low = mips_linux_watch_get_watchlo (&priv->watch_readback, n);
 679         t_irw = t_low & IRW_MASK;
 680         t_hi = (mips_linux_watch_get_watchhi (&priv->watch_readback, n)
 681                 | IRW_MASK);
 682         t_low &= ~(CORE_ADDR)t_hi;
 683
 684         for (watch = priv->current_watches;
 685              watch != NULL;
 686              watch = watch->next)
 687           {
 688             CORE_ADDR addr = watch->addr;
 689             CORE_ADDR last_byte = addr + watch->len - 1;
 690
 691             if ((t_irw & mips_linux_watch_type_to_irw (watch->type)) == 0)
 692               {
 693                 /* Different type.  */
 694                 continue;
 695               }
 696             /* Check for overlap of even a single byte.  */
 697             if (last_byte >= t_low && addr <= t_low + t_hi)
 698               return addr;
 699           }
 700       }
 701
 702   /* Shouldn't happen.  */
 703   return 0;
 704 }
 705
 706 /* Fetch the thread-local storage pointer for libthread_db.  */
 707
 708 ps_err_e
 709 ps_get_thread_area (struct ps_prochandle *ph,
 710                     lwpid_t lwpid, int idx, void **base)
 711 {
 712   if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
 713     return PS_ERR;
 714
 715   /* IDX is the bias from the thread pointer to the beginning of the
 716      thread descriptor.  It has to be subtracted due to implementation
 717      quirks in libthread_db.  */
 718   *base = (void *) ((char *)*base - idx);
 719
 720   return PS_OK;
 721 }
 722
 723 static void
 724 mips_collect_register (struct regcache *regcache,
 725                        int use_64bit, int regno, union mips_register *reg)
 726 {
 727   union mips_register tmp_reg;
 728
 729   if (use_64bit)
 730     {
 731       collect_register (regcache, regno, &tmp_reg.reg64);
 732       *reg = tmp_reg;
 733     }
 734   else
 735     {
 736       collect_register (regcache, regno, &tmp_reg.reg32);
 737       reg->reg64 = tmp_reg.reg32;
 738     }
 739 }
 740
 741 static void
 742 mips_supply_register (struct regcache *regcache,
 743                       int use_64bit, int regno, const union mips_register *reg)
 744 {
 745   int offset = 0;
 746
 747   /* For big-endian 32-bit targets, ignore the high four bytes of each
 748      eight-byte slot.  */
 749   if (__BYTE_ORDER == __BIG_ENDIAN && !use_64bit)
 750     offset = 4;
 751
 752   supply_register (regcache, regno, reg->buf + offset);
 753 }
 754
 755 #ifdef HAVE_PTRACE_GETREGS
 756
 757 static void
 758 mips_collect_register_32bit (struct regcache *regcache,
 759                              int use_64bit, int regno, unsigned char *buf)
 760 {
 761   union mips_register tmp_reg;
 762   int reg32;
 763
 764   mips_collect_register (regcache, use_64bit, regno, &tmp_reg);
 765   reg32 = tmp_reg.reg64;
 766   memcpy (buf, &reg32, 4);
 767 }
 768
 769 static void
 770 mips_supply_register_32bit (struct regcache *regcache,
 771                             int use_64bit, int regno, const unsigned char *buf)
 772 {
 773   union mips_register tmp_reg;
 774   int reg32;
 775
 776   memcpy (&reg32, buf, 4);
 777   tmp_reg.reg64 = reg32;
 778   mips_supply_register (regcache, use_64bit, regno, &tmp_reg);
 779 }
 780
 781 static void
 782 mips_fill_gregset (struct regcache *regcache, void *buf)
 783 {
 784   union mips_register *regset = (union mips_register *) buf;
 785   int i, use_64bit;
 786   const struct target_desc *tdesc = regcache->tdesc;
 787
 788   use_64bit = (register_size (tdesc, 0) == 8);
 789
 790   for (i = 1; i < 32; i++)
 791     mips_collect_register (regcache, use_64bit, i, regset + i);
 792
 793   mips_collect_register (regcache, use_64bit,
 794                          find_regno (tdesc, "lo"), regset + 32);
 795   mips_collect_register (regcache, use_64bit,
 796                          find_regno (tdesc, "hi"), regset + 33);
 797   mips_collect_register (regcache, use_64bit,
 798                          find_regno (tdesc, "pc"), regset + 34);
 799   mips_collect_register (regcache, use_64bit,
 800                          find_regno (tdesc, "badvaddr"), regset + 35);
 801   mips_collect_register (regcache, use_64bit,
 802                          find_regno (tdesc, "status"), regset + 36);
 803   mips_collect_register (regcache, use_64bit,
 804                          find_regno (tdesc, "cause"), regset + 37);
 805
 806   mips_collect_register (regcache, use_64bit,
 807                          find_regno (tdesc, "restart"), regset + 0);
 808 }
 809
 810 static void
 811 mips_store_gregset (struct regcache *regcache, const void *buf)
 812 {
 813   const union mips_register *regset = (const union mips_register *) buf;
 814   int i, use_64bit;
 815
 816   use_64bit = (register_size (regcache->tdesc, 0) == 8);
 817
 818   supply_register_by_name_zeroed (regcache, "r0");
 819
 820   for (i = 1; i < 32; i++)
 821     mips_supply_register (regcache, use_64bit, i, regset + i);
 822
 823   mips_supply_register (regcache, use_64bit,
 824                         find_regno (regcache->tdesc, "lo"), regset + 32);
 825   mips_supply_register (regcache, use_64bit,
 826                         find_regno (regcache->tdesc, "hi"), regset + 33);
 827   mips_supply_register (regcache, use_64bit,
 828                         find_regno (regcache->tdesc, "pc"), regset + 34);
 829   mips_supply_register (regcache, use_64bit,
 830                         find_regno (regcache->tdesc, "badvaddr"), regset + 35);
 831   mips_supply_register (regcache, use_64bit,
 832                         find_regno (regcache->tdesc, "status"), regset + 36);
 833   mips_supply_register (regcache, use_64bit,
 834                         find_regno (regcache->tdesc, "cause"), regset + 37);
 835
 836   mips_supply_register (regcache, use_64bit,
 837                         find_regno (regcache->tdesc, "restart"), regset + 0);
 838 }
 839
 840 static void
 841 mips_fill_fpregset (struct regcache *regcache, void *buf)
 842 {
 843   union mips_register *regset = (union mips_register *) buf;
 844   int i, use_64bit, first_fp, big_endian;
 845
 846   use_64bit = (register_size (regcache->tdesc, 0) == 8);
 847   first_fp = find_regno (regcache->tdesc, "f0");
 848   big_endian = (__BYTE_ORDER == __BIG_ENDIAN);
 849
 850   /* See GDB for a discussion of this peculiar layout.  */
 851   for (i = 0; i < 32; i++)
 852     if (use_64bit)
 853       collect_register (regcache, first_fp + i, regset[i].buf);
 854     else
 855       collect_register (regcache, first_fp + i,
 856                         regset[i & ~1].buf + 4 * (big_endian != (i & 1)));
 857
 858   mips_collect_register_32bit (regcache, use_64bit,
 859                                find_regno (regcache->tdesc, "fcsr"), regset[32].buf);
 860   mips_collect_register_32bit (regcache, use_64bit,
 861                                find_regno (regcache->tdesc, "fir"),
 862                                regset[32].buf + 4);
 863 }
 864
 865 static void
 866 mips_store_fpregset (struct regcache *regcache, const void *buf)
 867 {
 868   const union mips_register *regset = (const union mips_register *) buf;
 869   int i, use_64bit, first_fp, big_endian;
 870
 871   use_64bit = (register_size (regcache->tdesc, 0) == 8);
 872   first_fp = find_regno (regcache->tdesc, "f0");
 873   big_endian = (__BYTE_ORDER == __BIG_ENDIAN);
 874
 875   /* See GDB for a discussion of this peculiar layout.  */
 876   for (i = 0; i < 32; i++)
 877     if (use_64bit)
 878       supply_register (regcache, first_fp + i, regset[i].buf);
 879     else
 880       supply_register (regcache, first_fp + i,
 881                        regset[i & ~1].buf + 4 * (big_endian != (i & 1)));
 882
 883   mips_supply_register_32bit (regcache, use_64bit,
 884                               find_regno (regcache->tdesc, "fcsr"),
 885                               regset[32].buf);
 886   mips_supply_register_32bit (regcache, use_64bit,
 887                               find_regno (regcache->tdesc, "fir"),
 888                               regset[32].buf + 4);
 889 }
 890 #endif /* HAVE_PTRACE_GETREGS */
 891
 892 /* Take care of 32-bit registers with 64-bit ptrace, POKEUSER side.  */
 893
 894 static void
 895 mips_collect_ptrace_register (struct regcache *regcache,
 896                               int regno, char *buf)
 897 {
 898   int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8;
 899
 900   if (use_64bit && register_size (regcache->tdesc, regno) == 4)
 901     {
 902       union mips_register reg;
 903
 904       mips_collect_register (regcache, 0, regno, &reg);
 905       memcpy (buf, &reg, sizeof (reg));
 906     }
 907   else
 908     collect_register (regcache, regno, buf);
 909 }
 910
 911 /* Take care of 32-bit registers with 64-bit ptrace, PEEKUSER side.  */
 912
 913 static void
 914 mips_supply_ptrace_register (struct regcache *regcache,
 915                              int regno, const char *buf)
 916 {
 917   int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8;
 918
 919   if (use_64bit && register_size (regcache->tdesc, regno) == 4)
 920     {
 921       union mips_register reg;
 922
 923       memcpy (&reg, buf, sizeof (reg));
 924       mips_supply_register (regcache, 0, regno, &reg);
 925     }
 926   else
 927     supply_register (regcache, regno, buf);
 928 }
 929
 930 static struct regset_info mips_regsets[] = {
 931 #ifdef HAVE_PTRACE_GETREGS
 932   { PTRACE_GETREGS, PTRACE_SETREGS, 0, 38 * 8, GENERAL_REGS,
 933     mips_fill_gregset, mips_store_gregset },
 934   { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, 33 * 8, FP_REGS,
 935     mips_fill_fpregset, mips_store_fpregset },
 936 #endif /* HAVE_PTRACE_GETREGS */
 937   NULL_REGSET
 938 };
 939
 940 static struct regsets_info mips_regsets_info =
 941   {
 942     mips_regsets, /* regsets */
 943     0, /* num_regsets */
 944     NULL, /* disabled_regsets */
 945   };
 946
 947 static struct usrregs_info mips_dsp_usrregs_info =
 948   {
 949     mips_dsp_num_regs,
 950     mips_dsp_regmap,
 951   };
 952
 953 static struct usrregs_info mips_usrregs_info =
 954   {
 955     mips_num_regs,
 956     mips_regmap,
 957   };
 958
 959 static struct regs_info dsp_regs_info =
 960   {
 961     mips_dsp_regset_bitmap,
 962     &mips_dsp_usrregs_info,
 963     &mips_regsets_info
 964   };
 965
 966 static struct regs_info myregs_info =
 967   {
 968     NULL, /* regset_bitmap */
 969     &mips_usrregs_info,
 970     &mips_regsets_info
 971   };
 972
 973 const regs_info *
 974 mips_target::get_regs_info ()
 975 {
 976   if (have_dsp)
 977     return &dsp_regs_info;
 978   else
 979     return &myregs_info;
 980 }
 981
 982 struct linux_target_ops the_low_target = {
 983   mips_collect_ptrace_register,
 984   mips_supply_ptrace_register,
 985   NULL, /* siginfo_fixup */
 986   mips_linux_new_process,
 987   mips_linux_delete_process,
 988   mips_linux_new_thread,
 989   mips_linux_delete_thread,
 990   mips_linux_new_fork,
 991   mips_linux_prepare_to_resume
 992 };
 993
 994 /* The linux target ops object.  */
 995
 996 linux_process_target *the_linux_target = &the_mips_target;
 997
 998 void
 999 initialize_low_arch (void)
1000 {
1001   /* Initialize the Linux target descriptions.  */
1002   init_registers_mips_linux ();
1003   init_registers_mips_dsp_linux ();
1004   init_registers_mips64_linux ();
1005   init_registers_mips64_dsp_linux ();
1006
1007   initialize_regsets_info (&mips_regsets_info);
1008 }