gdbserver/linux-mips-low.cc

   1 /* GNU/Linux/MIPS specific low level interface, for the remote server for GDB.
   2    Copyright (C) 1995-2020 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #include "server.h"
  20 #include "linux-low.h"
  21
  22 #include "nat/gdb_ptrace.h"
  23 #include <endian.h>
  24
  25 #include "nat/mips-linux-watch.h"
  26 #include "gdb_proc_service.h"
  27
  28 /* Linux target op definitions for the MIPS architecture.  */
  29
  30 class mips_target : public linux_process_target
  31 {
  32 public:
  33
  34   const regs_info *get_regs_info () override;
  35
  36   const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override;
  37
  38   bool supports_z_point_type (char z_type) override;
  39
  40 protected:
  41
  42   void low_arch_setup () override;
  43
  44   bool low_cannot_fetch_register (int regno) override;
  45
  46   bool low_cannot_store_register (int regno) override;
  47
  48   bool low_fetch_register (regcache *regcache, int regno) override;
  49
  50   bool low_supports_breakpoints () override;
  51
  52   CORE_ADDR low_get_pc (regcache *regcache) override;
  53
  54   void low_set_pc (regcache *regcache, CORE_ADDR newpc) override;
  55
  56   bool low_breakpoint_at (CORE_ADDR pc) override;
  57 };
  58
  59 /* The singleton target ops object.  */
  60
  61 static mips_target the_mips_target;
  62
  63 /* Defined in auto-generated file mips-linux.c.  */
  64 void init_registers_mips_linux (void);
  65 extern const struct target_desc *tdesc_mips_linux;
  66
  67 /* Defined in auto-generated file mips-dsp-linux.c.  */
  68 void init_registers_mips_dsp_linux (void);
  69 extern const struct target_desc *tdesc_mips_dsp_linux;
  70
  71 /* Defined in auto-generated file mips64-linux.c.  */
  72 void init_registers_mips64_linux (void);
  73 extern const struct target_desc *tdesc_mips64_linux;
  74
  75 /* Defined in auto-generated file mips64-dsp-linux.c.  */
  76 void init_registers_mips64_dsp_linux (void);
  77 extern const struct target_desc *tdesc_mips64_dsp_linux;
  78
  79 #ifdef __mips64
  80 #define tdesc_mips_linux tdesc_mips64_linux
  81 #define tdesc_mips_dsp_linux tdesc_mips64_dsp_linux
  82 #endif
  83
  84 #ifndef PTRACE_GET_THREAD_AREA
  85 #define PTRACE_GET_THREAD_AREA 25
  86 #endif
  87
  88 #ifdef HAVE_SYS_REG_H
  89 #include <sys/reg.h>
  90 #endif
  91
  92 #define mips_num_regs 73
  93 #define mips_dsp_num_regs 80
  94
  95 #include <asm/ptrace.h>
  96
  97 #ifndef DSP_BASE
  98 #define DSP_BASE 71
  99 #define DSP_CONTROL 77
 100 #endif
 101
 102 union mips_register
 103 {
 104   unsigned char buf[8];
 105
 106   /* Deliberately signed, for proper sign extension.  */
 107   int reg32;
 108   long long reg64;
 109 };
 110
 111 /* Return the ptrace ``address'' of register REGNO. */
 112
 113 #define mips_base_regs                                                  \
 114   -1,  1,  2,  3,  4,  5,  6,  7,                                       \
 115   8,  9,  10, 11, 12, 13, 14, 15,                                       \
 116   16, 17, 18, 19, 20, 21, 22, 23,                                       \
 117   24, 25, 26, 27, 28, 29, 30, 31,                                       \
 118                                                                         \
 119   -1, MMLO, MMHI, BADVADDR, CAUSE, PC,                                  \
 120                                                                         \
 121   FPR_BASE,      FPR_BASE + 1,  FPR_BASE + 2,  FPR_BASE + 3,            \
 122   FPR_BASE + 4,  FPR_BASE + 5,  FPR_BASE + 6,  FPR_BASE + 7,            \
 123   FPR_BASE + 8,  FPR_BASE + 9,  FPR_BASE + 10, FPR_BASE + 11,           \
 124   FPR_BASE + 12, FPR_BASE + 13, FPR_BASE + 14, FPR_BASE + 15,           \
 125   FPR_BASE + 16, FPR_BASE + 17, FPR_BASE + 18, FPR_BASE + 19,           \
 126   FPR_BASE + 20, FPR_BASE + 21, FPR_BASE + 22, FPR_BASE + 23,           \
 127   FPR_BASE + 24, FPR_BASE + 25, FPR_BASE + 26, FPR_BASE + 27,           \
 128   FPR_BASE + 28, FPR_BASE + 29, FPR_BASE + 30, FPR_BASE + 31,           \
 129   FPC_CSR, FPC_EIR
 130
 131 #define mips_dsp_regs                                                   \
 132   DSP_BASE,      DSP_BASE + 1,  DSP_BASE + 2,  DSP_BASE + 3,            \
 133   DSP_BASE + 4,  DSP_BASE + 5,                                          \
 134   DSP_CONTROL
 135
 136 static int mips_regmap[mips_num_regs] = {
 137   mips_base_regs,
 138   0
 139 };
 140
 141 static int mips_dsp_regmap[mips_dsp_num_regs] = {
 142   mips_base_regs,
 143   mips_dsp_regs,
 144   0
 145 };
 146
 147 /* DSP registers are not in any regset and can only be accessed
 148    individually.  */
 149
 150 static unsigned char mips_dsp_regset_bitmap[(mips_dsp_num_regs + 7) / 8] = {
 151   0xfe, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x80
 152 };
 153
 154 static int have_dsp = -1;
 155
 156 /* Try peeking at an arbitrarily chosen DSP register and pick the available
 157    user register set accordingly.  */
 158
 159 static const struct target_desc *
 160 mips_read_description (void)
 161 {
 162   if (have_dsp < 0)
 163     {
 164       int pid = lwpid_of (current_thread);
 165
 166       errno = 0;
 167       ptrace (PTRACE_PEEKUSER, pid, DSP_CONTROL, 0);
 168       switch (errno)
 169         {
 170         case 0:
 171           have_dsp = 1;
 172           break;
 173         case EIO:
 174           have_dsp = 0;
 175           break;
 176         default:
 177           perror_with_name ("ptrace");
 178           break;
 179         }
 180     }
 181
 182   return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux;
 183 }
 184
 185 void
 186 mips_target::low_arch_setup ()
 187 {
 188   current_process ()->tdesc = mips_read_description ();
 189 }
 190
 191 /* Per-process arch-specific data we want to keep.  */
 192
 193 struct arch_process_info
 194 {
 195   /* -1 if the kernel and/or CPU do not support watch registers.
 196       1 if watch_readback is valid and we can read style, num_valid
 197         and the masks.
 198       0 if we need to read the watch_readback.  */
 199
 200   int watch_readback_valid;
 201
 202   /* Cached watch register read values.  */
 203
 204   struct pt_watch_regs watch_readback;
 205
 206   /* Current watchpoint requests for this process.  */
 207
 208   struct mips_watchpoint *current_watches;
 209
 210   /* The current set of watch register values for writing the
 211      registers.  */
 212
 213   struct pt_watch_regs watch_mirror;
 214 };
 215
 216 /* Per-thread arch-specific data we want to keep.  */
 217
 218 struct arch_lwp_info
 219 {
 220   /* Non-zero if our copy differs from what's recorded in the thread.  */
 221   int watch_registers_changed;
 222 };
 223
 224 /* From mips-linux-nat.c.  */
 225
 226 /* Pseudo registers can not be read.  ptrace does not provide a way to
 227    read (or set) PS_REGNUM, and there's no point in reading or setting
 228    ZERO_REGNUM, it's always 0.  We also can not set BADVADDR, CAUSE,
 229    or FCRIR via ptrace().  */
 230
 231 bool
 232 mips_target::low_cannot_fetch_register (int regno)
 233 {
 234   const struct target_desc *tdesc;
 235
 236   if (get_regs_info ()->usrregs->regmap[regno] == -1)
 237     return true;
 238
 239   tdesc = current_process ()->tdesc;
 240
 241   /* On n32 we can't access 64-bit registers via PTRACE_PEEKUSR.  */
 242   if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE))
 243     return true;
 244
 245   if (find_regno (tdesc, "r0") == regno)
 246     return true;
 247
 248   return false;
 249 }
 250
 251 bool
 252 mips_target::low_cannot_store_register (int regno)
 253 {
 254   const struct target_desc *tdesc;
 255
 256   if (get_regs_info ()->usrregs->regmap[regno] == -1)
 257     return true;
 258
 259   tdesc = current_process ()->tdesc;
 260
 261   /* On n32 we can't access 64-bit registers via PTRACE_POKEUSR.  */
 262   if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE))
 263     return true;
 264
 265   if (find_regno (tdesc, "r0") == regno)
 266     return true;
 267
 268   if (find_regno (tdesc, "cause") == regno)
 269     return true;
 270
 271   if (find_regno (tdesc, "badvaddr") == regno)
 272     return true;
 273
 274   if (find_regno (tdesc, "fir") == regno)
 275     return true;
 276
 277   return false;
 278 }
 279
 280 bool
 281 mips_target::low_fetch_register (regcache *regcache, int regno)
 282 {
 283   const struct target_desc *tdesc = current_process ()->tdesc;
 284
 285   if (find_regno (tdesc, "r0") == regno)
 286     {
 287       supply_register_zeroed (regcache, regno);
 288       return true;
 289     }
 290
 291   return false;
 292 }
 293
 294 bool
 295 mips_target::low_supports_breakpoints ()
 296 {
 297   return true;
 298 }
 299
 300 CORE_ADDR
 301 mips_target::low_get_pc (regcache *regcache)
 302 {
 303   union mips_register pc;
 304   collect_register_by_name (regcache, "pc", pc.buf);
 305   return register_size (regcache->tdesc, 0) == 4 ? pc.reg32 : pc.reg64;
 306 }
 307
 308 void
 309 mips_target::low_set_pc (regcache *regcache, CORE_ADDR pc)
 310 {
 311   union mips_register newpc;
 312   if (register_size (regcache->tdesc, 0) == 4)
 313     newpc.reg32 = pc;
 314   else
 315     newpc.reg64 = pc;
 316
 317   supply_register_by_name (regcache, "pc", newpc.buf);
 318 }
 319
 320 /* Correct in either endianness.  */
 321 static const unsigned int mips_breakpoint = 0x0005000d;
 322 #define mips_breakpoint_len 4
 323
 324 /* Implementation of target ops method "sw_breakpoint_from_kind".  */
 325
 326 const gdb_byte *
 327 mips_target::sw_breakpoint_from_kind (int kind, int *size)
 328 {
 329   *size = mips_breakpoint_len;
 330   return (const gdb_byte *) &mips_breakpoint;
 331 }
 332
 333 bool
 334 mips_target::low_breakpoint_at (CORE_ADDR where)
 335 {
 336   unsigned int insn;
 337
 338   read_memory (where, (unsigned char *) &insn, 4);
 339   if (insn == mips_breakpoint)
 340     return true;
 341
 342   /* If necessary, recognize more trap instructions here.  GDB only uses the
 343      one.  */
 344   return false;
 345 }
 346
 347 /* Mark the watch registers of lwp, represented by ENTRY, as changed.  */
 348
 349 static void
 350 update_watch_registers_callback (thread_info *thread)
 351 {
 352   struct lwp_info *lwp = get_thread_lwp (thread);
 353
 354   /* The actual update is done later just before resuming the lwp,
 355      we just mark that the registers need updating.  */
 356   lwp->arch_private->watch_registers_changed = 1;
 357
 358   /* If the lwp isn't stopped, force it to momentarily pause, so
 359      we can update its watch registers.  */
 360   if (!lwp->stopped)
 361     linux_stop_lwp (lwp);
 362 }
 363
 364 /* This is the implementation of linux_target_ops method
 365    new_process.  */
 366
 367 static struct arch_process_info *
 368 mips_linux_new_process (void)
 369 {
 370   struct arch_process_info *info = XCNEW (struct arch_process_info);
 371
 372   return info;
 373 }
 374
 375 /* This is the implementation of linux_target_ops method
 376    delete_process.  */
 377
 378 static void
 379 mips_linux_delete_process (struct arch_process_info *info)
 380 {
 381   xfree (info);
 382 }
 383
 384 /* This is the implementation of linux_target_ops method new_thread.
 385    Mark the watch registers as changed, so the threads' copies will
 386    be updated.  */
 387
 388 static void
 389 mips_linux_new_thread (struct lwp_info *lwp)
 390 {
 391   struct arch_lwp_info *info = XCNEW (struct arch_lwp_info);
 392
 393   info->watch_registers_changed = 1;
 394
 395   lwp->arch_private = info;
 396 }
 397
 398 /* Function to call when a thread is being deleted.  */
 399
 400 static void
 401 mips_linux_delete_thread (struct arch_lwp_info *arch_lwp)
 402 {
 403   xfree (arch_lwp);
 404 }
 405
 406 /* Create a new mips_watchpoint and add it to the list.  */
 407
 408 static void
 409 mips_add_watchpoint (struct arch_process_info *priv, CORE_ADDR addr, int len,
 410                      enum target_hw_bp_type watch_type)
 411 {
 412   struct mips_watchpoint *new_watch;
 413   struct mips_watchpoint **pw;
 414
 415   new_watch = XNEW (struct mips_watchpoint);
 416   new_watch->addr = addr;
 417   new_watch->len = len;
 418   new_watch->type = watch_type;
 419   new_watch->next = NULL;
 420
 421   pw = &priv->current_watches;
 422   while (*pw != NULL)
 423     pw = &(*pw)->next;
 424   *pw = new_watch;
 425 }
 426
 427 /* Hook to call when a new fork is attached.  */
 428
 429 static void
 430 mips_linux_new_fork (struct process_info *parent,
 431                         struct process_info *child)
 432 {
 433   struct arch_process_info *parent_private;
 434   struct arch_process_info *child_private;
 435   struct mips_watchpoint *wp;
 436
 437   /* These are allocated by linux_add_process.  */
 438   gdb_assert (parent->priv != NULL
 439               && parent->priv->arch_private != NULL);
 440   gdb_assert (child->priv != NULL
 441               && child->priv->arch_private != NULL);
 442
 443   /* Linux kernel before 2.6.33 commit
 444      72f674d203cd230426437cdcf7dd6f681dad8b0d
 445      will inherit hardware debug registers from parent
 446      on fork/vfork/clone.  Newer Linux kernels create such tasks with
 447      zeroed debug registers.
 448
 449      GDB core assumes the child inherits the watchpoints/hw
 450      breakpoints of the parent, and will remove them all from the
 451      forked off process.  Copy the debug registers mirrors into the
 452      new process so that all breakpoints and watchpoints can be
 453      removed together.  The debug registers mirror will become zeroed
 454      in the end before detaching the forked off process, thus making
 455      this compatible with older Linux kernels too.  */
 456
 457   parent_private = parent->priv->arch_private;
 458   child_private = child->priv->arch_private;
 459
 460   child_private->watch_readback_valid = parent_private->watch_readback_valid;
 461   child_private->watch_readback = parent_private->watch_readback;
 462
 463   for (wp = parent_private->current_watches; wp != NULL; wp = wp->next)
 464     mips_add_watchpoint (child_private, wp->addr, wp->len, wp->type);
 465
 466   child_private->watch_mirror = parent_private->watch_mirror;
 467 }
 468 /* This is the implementation of linux_target_ops method
 469    prepare_to_resume.  If the watch regs have changed, update the
 470    thread's copies.  */
 471
 472 static void
 473 mips_linux_prepare_to_resume (struct lwp_info *lwp)
 474 {
 475   ptid_t ptid = ptid_of (get_lwp_thread (lwp));
 476   struct process_info *proc = find_process_pid (ptid.pid ());
 477   struct arch_process_info *priv = proc->priv->arch_private;
 478
 479   if (lwp->arch_private->watch_registers_changed)
 480     {
 481       /* Only update the watch registers if we have set or unset a
 482          watchpoint already.  */
 483       if (mips_linux_watch_get_num_valid (&priv->watch_mirror) > 0)
 484         {
 485           /* Write the mirrored watch register values.  */
 486           int tid = ptid.lwp ();
 487
 488           if (-1 == ptrace (PTRACE_SET_WATCH_REGS, tid,
 489                             &priv->watch_mirror, NULL))
 490             perror_with_name ("Couldn't write watch register");
 491         }
 492
 493       lwp->arch_private->watch_registers_changed = 0;
 494     }
 495 }
 496
 497 bool
 498 mips_target::supports_z_point_type (char z_type)
 499 {
 500   switch (z_type)
 501     {
 502     case Z_PACKET_WRITE_WP:
 503     case Z_PACKET_READ_WP:
 504     case Z_PACKET_ACCESS_WP:
 505       return true;
 506     default:
 507       return false;
 508     }
 509 }
 510
 511 /* This is the implementation of linux_target_ops method
 512    insert_point.  */
 513
 514 static int
 515 mips_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
 516                    int len, struct raw_breakpoint *bp)
 517 {
 518   struct process_info *proc = current_process ();
 519   struct arch_process_info *priv = proc->priv->arch_private;
 520   struct pt_watch_regs regs;
 521   long lwpid;
 522   enum target_hw_bp_type watch_type;
 523   uint32_t irw;
 524
 525   lwpid = lwpid_of (current_thread);
 526   if (!mips_linux_read_watch_registers (lwpid,
 527                                         &priv->watch_readback,
 528                                         &priv->watch_readback_valid,
 529                                         0))
 530     return -1;
 531
 532   if (len <= 0)
 533     return -1;
 534
 535   regs = priv->watch_readback;
 536   /* Add the current watches.  */
 537   mips_linux_watch_populate_regs (priv->current_watches, &regs);
 538
 539   /* Now try to add the new watch.  */
 540   watch_type = raw_bkpt_type_to_target_hw_bp_type (type);
 541   irw = mips_linux_watch_type_to_irw (watch_type);
 542   if (!mips_linux_watch_try_one_watch (&regs, addr, len, irw))
 543     return -1;
 544
 545   /* It fit.  Stick it on the end of the list.  */
 546   mips_add_watchpoint (priv, addr, len, watch_type);
 547
 548   priv->watch_mirror = regs;
 549
 550   /* Only update the threads of this process.  */
 551   for_each_thread (proc->pid, update_watch_registers_callback);
 552
 553   return 0;
 554 }
 555
 556 /* This is the implementation of linux_target_ops method
 557    remove_point.  */
 558
 559 static int
 560 mips_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
 561                    int len, struct raw_breakpoint *bp)
 562 {
 563   struct process_info *proc = current_process ();
 564   struct arch_process_info *priv = proc->priv->arch_private;
 565
 566   int deleted_one;
 567   enum target_hw_bp_type watch_type;
 568
 569   struct mips_watchpoint **pw;
 570   struct mips_watchpoint *w;
 571
 572   /* Search for a known watch that matches.  Then unlink and free it.  */
 573   watch_type = raw_bkpt_type_to_target_hw_bp_type (type);
 574   deleted_one = 0;
 575   pw = &priv->current_watches;
 576   while ((w = *pw))
 577     {
 578       if (w->addr == addr && w->len == len && w->type == watch_type)
 579         {
 580           *pw = w->next;
 581           free (w);
 582           deleted_one = 1;
 583           break;
 584         }
 585       pw = &(w->next);
 586     }
 587
 588   if (!deleted_one)
 589     return -1;  /* We don't know about it, fail doing nothing.  */
 590
 591   /* At this point watch_readback is known to be valid because we
 592      could not have added the watch without reading it.  */
 593   gdb_assert (priv->watch_readback_valid == 1);
 594
 595   priv->watch_mirror = priv->watch_readback;
 596   mips_linux_watch_populate_regs (priv->current_watches,
 597                                   &priv->watch_mirror);
 598
 599   /* Only update the threads of this process.  */
 600   for_each_thread (proc->pid, update_watch_registers_callback);
 601
 602   return 0;
 603 }
 604
 605 /* This is the implementation of linux_target_ops method
 606    stopped_by_watchpoint.  The watchhi R and W bits indicate
 607    the watch register triggered. */
 608
 609 static int
 610 mips_stopped_by_watchpoint (void)
 611 {
 612   struct process_info *proc = current_process ();
 613   struct arch_process_info *priv = proc->priv->arch_private;
 614   int n;
 615   int num_valid;
 616   long lwpid = lwpid_of (current_thread);
 617
 618   if (!mips_linux_read_watch_registers (lwpid,
 619                                         &priv->watch_readback,
 620                                         &priv->watch_readback_valid,
 621                                         1))
 622     return 0;
 623
 624   num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback);
 625
 626   for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
 627     if (mips_linux_watch_get_watchhi (&priv->watch_readback, n)
 628         & (R_MASK | W_MASK))
 629       return 1;
 630
 631   return 0;
 632 }
 633
 634 /* This is the implementation of linux_target_ops method
 635    stopped_data_address.  */
 636
 637 static CORE_ADDR
 638 mips_stopped_data_address (void)
 639 {
 640   struct process_info *proc = current_process ();
 641   struct arch_process_info *priv = proc->priv->arch_private;
 642   int n;
 643   int num_valid;
 644   long lwpid = lwpid_of (current_thread);
 645
 646   /* On MIPS we don't know the low order 3 bits of the data address.
 647      GDB does not support remote targets that can't report the
 648      watchpoint address.  So, make our best guess; return the starting
 649      address of a watchpoint request which overlaps the one that
 650      triggered.  */
 651
 652   if (!mips_linux_read_watch_registers (lwpid,
 653                                         &priv->watch_readback,
 654                                         &priv->watch_readback_valid,
 655                                         0))
 656     return 0;
 657
 658   num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback);
 659
 660   for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
 661     if (mips_linux_watch_get_watchhi (&priv->watch_readback, n)
 662         & (R_MASK | W_MASK))
 663       {
 664         CORE_ADDR t_low, t_hi;
 665         int t_irw;
 666         struct mips_watchpoint *watch;
 667
 668         t_low = mips_linux_watch_get_watchlo (&priv->watch_readback, n);
 669         t_irw = t_low & IRW_MASK;
 670         t_hi = (mips_linux_watch_get_watchhi (&priv->watch_readback, n)
 671                 | IRW_MASK);
 672         t_low &= ~(CORE_ADDR)t_hi;
 673
 674         for (watch = priv->current_watches;
 675              watch != NULL;
 676              watch = watch->next)
 677           {
 678             CORE_ADDR addr = watch->addr;
 679             CORE_ADDR last_byte = addr + watch->len - 1;
 680
 681             if ((t_irw & mips_linux_watch_type_to_irw (watch->type)) == 0)
 682               {
 683                 /* Different type.  */
 684                 continue;
 685               }
 686             /* Check for overlap of even a single byte.  */
 687             if (last_byte >= t_low && addr <= t_low + t_hi)
 688               return addr;
 689           }
 690       }
 691
 692   /* Shouldn't happen.  */
 693   return 0;
 694 }
 695
 696 /* Fetch the thread-local storage pointer for libthread_db.  */
 697
 698 ps_err_e
 699 ps_get_thread_area (struct ps_prochandle *ph,
 700                     lwpid_t lwpid, int idx, void **base)
 701 {
 702   if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
 703     return PS_ERR;
 704
 705   /* IDX is the bias from the thread pointer to the beginning of the
 706      thread descriptor.  It has to be subtracted due to implementation
 707      quirks in libthread_db.  */
 708   *base = (void *) ((char *)*base - idx);
 709
 710   return PS_OK;
 711 }
 712
 713 static void
 714 mips_collect_register (struct regcache *regcache,
 715                        int use_64bit, int regno, union mips_register *reg)
 716 {
 717   union mips_register tmp_reg;
 718
 719   if (use_64bit)
 720     {
 721       collect_register (regcache, regno, &tmp_reg.reg64);
 722       *reg = tmp_reg;
 723     }
 724   else
 725     {
 726       collect_register (regcache, regno, &tmp_reg.reg32);
 727       reg->reg64 = tmp_reg.reg32;
 728     }
 729 }
 730
 731 static void
 732 mips_supply_register (struct regcache *regcache,
 733                       int use_64bit, int regno, const union mips_register *reg)
 734 {
 735   int offset = 0;
 736
 737   /* For big-endian 32-bit targets, ignore the high four bytes of each
 738      eight-byte slot.  */
 739   if (__BYTE_ORDER == __BIG_ENDIAN && !use_64bit)
 740     offset = 4;
 741
 742   supply_register (regcache, regno, reg->buf + offset);
 743 }
 744
 745 #ifdef HAVE_PTRACE_GETREGS
 746
 747 static void
 748 mips_collect_register_32bit (struct regcache *regcache,
 749                              int use_64bit, int regno, unsigned char *buf)
 750 {
 751   union mips_register tmp_reg;
 752   int reg32;
 753
 754   mips_collect_register (regcache, use_64bit, regno, &tmp_reg);
 755   reg32 = tmp_reg.reg64;
 756   memcpy (buf, &reg32, 4);
 757 }
 758
 759 static void
 760 mips_supply_register_32bit (struct regcache *regcache,
 761                             int use_64bit, int regno, const unsigned char *buf)
 762 {
 763   union mips_register tmp_reg;
 764   int reg32;
 765
 766   memcpy (&reg32, buf, 4);
 767   tmp_reg.reg64 = reg32;
 768   mips_supply_register (regcache, use_64bit, regno, &tmp_reg);
 769 }
 770
 771 static void
 772 mips_fill_gregset (struct regcache *regcache, void *buf)
 773 {
 774   union mips_register *regset = (union mips_register *) buf;
 775   int i, use_64bit;
 776   const struct target_desc *tdesc = regcache->tdesc;
 777
 778   use_64bit = (register_size (tdesc, 0) == 8);
 779
 780   for (i = 1; i < 32; i++)
 781     mips_collect_register (regcache, use_64bit, i, regset + i);
 782
 783   mips_collect_register (regcache, use_64bit,
 784                          find_regno (tdesc, "lo"), regset + 32);
 785   mips_collect_register (regcache, use_64bit,
 786                          find_regno (tdesc, "hi"), regset + 33);
 787   mips_collect_register (regcache, use_64bit,
 788                          find_regno (tdesc, "pc"), regset + 34);
 789   mips_collect_register (regcache, use_64bit,
 790                          find_regno (tdesc, "badvaddr"), regset + 35);
 791   mips_collect_register (regcache, use_64bit,
 792                          find_regno (tdesc, "status"), regset + 36);
 793   mips_collect_register (regcache, use_64bit,
 794                          find_regno (tdesc, "cause"), regset + 37);
 795
 796   mips_collect_register (regcache, use_64bit,
 797                          find_regno (tdesc, "restart"), regset + 0);
 798 }
 799
 800 static void
 801 mips_store_gregset (struct regcache *regcache, const void *buf)
 802 {
 803   const union mips_register *regset = (const union mips_register *) buf;
 804   int i, use_64bit;
 805
 806   use_64bit = (register_size (regcache->tdesc, 0) == 8);
 807
 808   supply_register_by_name_zeroed (regcache, "r0");
 809
 810   for (i = 1; i < 32; i++)
 811     mips_supply_register (regcache, use_64bit, i, regset + i);
 812
 813   mips_supply_register (regcache, use_64bit,
 814                         find_regno (regcache->tdesc, "lo"), regset + 32);
 815   mips_supply_register (regcache, use_64bit,
 816                         find_regno (regcache->tdesc, "hi"), regset + 33);
 817   mips_supply_register (regcache, use_64bit,
 818                         find_regno (regcache->tdesc, "pc"), regset + 34);
 819   mips_supply_register (regcache, use_64bit,
 820                         find_regno (regcache->tdesc, "badvaddr"), regset + 35);
 821   mips_supply_register (regcache, use_64bit,
 822                         find_regno (regcache->tdesc, "status"), regset + 36);
 823   mips_supply_register (regcache, use_64bit,
 824                         find_regno (regcache->tdesc, "cause"), regset + 37);
 825
 826   mips_supply_register (regcache, use_64bit,
 827                         find_regno (regcache->tdesc, "restart"), regset + 0);
 828 }
 829
 830 static void
 831 mips_fill_fpregset (struct regcache *regcache, void *buf)
 832 {
 833   union mips_register *regset = (union mips_register *) buf;
 834   int i, use_64bit, first_fp, big_endian;
 835
 836   use_64bit = (register_size (regcache->tdesc, 0) == 8);
 837   first_fp = find_regno (regcache->tdesc, "f0");
 838   big_endian = (__BYTE_ORDER == __BIG_ENDIAN);
 839
 840   /* See GDB for a discussion of this peculiar layout.  */
 841   for (i = 0; i < 32; i++)
 842     if (use_64bit)
 843       collect_register (regcache, first_fp + i, regset[i].buf);
 844     else
 845       collect_register (regcache, first_fp + i,
 846                         regset[i & ~1].buf + 4 * (big_endian != (i & 1)));
 847
 848   mips_collect_register_32bit (regcache, use_64bit,
 849                                find_regno (regcache->tdesc, "fcsr"), regset[32].buf);
 850   mips_collect_register_32bit (regcache, use_64bit,
 851                                find_regno (regcache->tdesc, "fir"),
 852                                regset[32].buf + 4);
 853 }
 854
 855 static void
 856 mips_store_fpregset (struct regcache *regcache, const void *buf)
 857 {
 858   const union mips_register *regset = (const union mips_register *) buf;
 859   int i, use_64bit, first_fp, big_endian;
 860
 861   use_64bit = (register_size (regcache->tdesc, 0) == 8);
 862   first_fp = find_regno (regcache->tdesc, "f0");
 863   big_endian = (__BYTE_ORDER == __BIG_ENDIAN);
 864
 865   /* See GDB for a discussion of this peculiar layout.  */
 866   for (i = 0; i < 32; i++)
 867     if (use_64bit)
 868       supply_register (regcache, first_fp + i, regset[i].buf);
 869     else
 870       supply_register (regcache, first_fp + i,
 871                        regset[i & ~1].buf + 4 * (big_endian != (i & 1)));
 872
 873   mips_supply_register_32bit (regcache, use_64bit,
 874                               find_regno (regcache->tdesc, "fcsr"),
 875                               regset[32].buf);
 876   mips_supply_register_32bit (regcache, use_64bit,
 877                               find_regno (regcache->tdesc, "fir"),
 878                               regset[32].buf + 4);
 879 }
 880 #endif /* HAVE_PTRACE_GETREGS */
 881
 882 /* Take care of 32-bit registers with 64-bit ptrace, POKEUSER side.  */
 883
 884 static void
 885 mips_collect_ptrace_register (struct regcache *regcache,
 886                               int regno, char *buf)
 887 {
 888   int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8;
 889
 890   if (use_64bit && register_size (regcache->tdesc, regno) == 4)
 891     {
 892       union mips_register reg;
 893
 894       mips_collect_register (regcache, 0, regno, &reg);
 895       memcpy (buf, &reg, sizeof (reg));
 896     }
 897   else
 898     collect_register (regcache, regno, buf);
 899 }
 900
 901 /* Take care of 32-bit registers with 64-bit ptrace, PEEKUSER side.  */
 902
 903 static void
 904 mips_supply_ptrace_register (struct regcache *regcache,
 905                              int regno, const char *buf)
 906 {
 907   int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8;
 908
 909   if (use_64bit && register_size (regcache->tdesc, regno) == 4)
 910     {
 911       union mips_register reg;
 912
 913       memcpy (&reg, buf, sizeof (reg));
 914       mips_supply_register (regcache, 0, regno, &reg);
 915     }
 916   else
 917     supply_register (regcache, regno, buf);
 918 }
 919
 920 static struct regset_info mips_regsets[] = {
 921 #ifdef HAVE_PTRACE_GETREGS
 922   { PTRACE_GETREGS, PTRACE_SETREGS, 0, 38 * 8, GENERAL_REGS,
 923     mips_fill_gregset, mips_store_gregset },
 924   { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, 33 * 8, FP_REGS,
 925     mips_fill_fpregset, mips_store_fpregset },
 926 #endif /* HAVE_PTRACE_GETREGS */
 927   NULL_REGSET
 928 };
 929
 930 static struct regsets_info mips_regsets_info =
 931   {
 932     mips_regsets, /* regsets */
 933     0, /* num_regsets */
 934     NULL, /* disabled_regsets */
 935   };
 936
 937 static struct usrregs_info mips_dsp_usrregs_info =
 938   {
 939     mips_dsp_num_regs,
 940     mips_dsp_regmap,
 941   };
 942
 943 static struct usrregs_info mips_usrregs_info =
 944   {
 945     mips_num_regs,
 946     mips_regmap,
 947   };
 948
 949 static struct regs_info dsp_regs_info =
 950   {
 951     mips_dsp_regset_bitmap,
 952     &mips_dsp_usrregs_info,
 953     &mips_regsets_info
 954   };
 955
 956 static struct regs_info myregs_info =
 957   {
 958     NULL, /* regset_bitmap */
 959     &mips_usrregs_info,
 960     &mips_regsets_info
 961   };
 962
 963 const regs_info *
 964 mips_target::get_regs_info ()
 965 {
 966   if (have_dsp)
 967     return &dsp_regs_info;
 968   else
 969     return &myregs_info;
 970 }
 971
 972 struct linux_target_ops the_low_target = {
 973   mips_insert_point,
 974   mips_remove_point,
 975   mips_stopped_by_watchpoint,
 976   mips_stopped_data_address,
 977   mips_collect_ptrace_register,
 978   mips_supply_ptrace_register,
 979   NULL, /* siginfo_fixup */
 980   mips_linux_new_process,
 981   mips_linux_delete_process,
 982   mips_linux_new_thread,
 983   mips_linux_delete_thread,
 984   mips_linux_new_fork,
 985   mips_linux_prepare_to_resume
 986 };
 987
 988 /* The linux target ops object.  */
 989
 990 linux_process_target *the_linux_target = &the_mips_target;
 991
 992 void
 993 initialize_low_arch (void)
 994 {
 995   /* Initialize the Linux target descriptions.  */
 996   init_registers_mips_linux ();
 997   init_registers_mips_dsp_linux ();
 998   init_registers_mips64_linux ();
 999   init_registers_mips64_dsp_linux ();
1000
1001   initialize_regsets_info (&mips_regsets_info);
1002 }