gdbserver/linux-mips-low.cc

   1 /* GNU/Linux/MIPS specific low level interface, for the remote server for GDB.
   2    Copyright (C) 1995-2020 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #include "server.h"
  20 #include "linux-low.h"
  21
  22 #include "nat/gdb_ptrace.h"
  23 #include <endian.h>
  24
  25 #include "nat/mips-linux-watch.h"
  26 #include "gdb_proc_service.h"
  27
  28 /* Defined in auto-generated file mips-linux.c.  */
  29 void init_registers_mips_linux (void);
  30 extern const struct target_desc *tdesc_mips_linux;
  31
  32 /* Defined in auto-generated file mips-dsp-linux.c.  */
  33 void init_registers_mips_dsp_linux (void);
  34 extern const struct target_desc *tdesc_mips_dsp_linux;
  35
  36 /* Defined in auto-generated file mips64-linux.c.  */
  37 void init_registers_mips64_linux (void);
  38 extern const struct target_desc *tdesc_mips64_linux;
  39
  40 /* Defined in auto-generated file mips64-dsp-linux.c.  */
  41 void init_registers_mips64_dsp_linux (void);
  42 extern const struct target_desc *tdesc_mips64_dsp_linux;
  43
  44 #ifdef __mips64
  45 #define tdesc_mips_linux tdesc_mips64_linux
  46 #define tdesc_mips_dsp_linux tdesc_mips64_dsp_linux
  47 #endif
  48
  49 #ifndef PTRACE_GET_THREAD_AREA
  50 #define PTRACE_GET_THREAD_AREA 25
  51 #endif
  52
  53 #ifdef HAVE_SYS_REG_H
  54 #include <sys/reg.h>
  55 #endif
  56
  57 #define mips_num_regs 73
  58 #define mips_dsp_num_regs 80
  59
  60 #include <asm/ptrace.h>
  61
  62 #ifndef DSP_BASE
  63 #define DSP_BASE 71
  64 #define DSP_CONTROL 77
  65 #endif
  66
  67 union mips_register
  68 {
  69   unsigned char buf[8];
  70
  71   /* Deliberately signed, for proper sign extension.  */
  72   int reg32;
  73   long long reg64;
  74 };
  75
  76 /* Return the ptrace ``address'' of register REGNO. */
  77
  78 #define mips_base_regs                                                  \
  79   -1,  1,  2,  3,  4,  5,  6,  7,                                       \
  80   8,  9,  10, 11, 12, 13, 14, 15,                                       \
  81   16, 17, 18, 19, 20, 21, 22, 23,                                       \
  82   24, 25, 26, 27, 28, 29, 30, 31,                                       \
  83                                                                         \
  84   -1, MMLO, MMHI, BADVADDR, CAUSE, PC,                                  \
  85                                                                         \
  86   FPR_BASE,      FPR_BASE + 1,  FPR_BASE + 2,  FPR_BASE + 3,            \
  87   FPR_BASE + 4,  FPR_BASE + 5,  FPR_BASE + 6,  FPR_BASE + 7,            \
  88   FPR_BASE + 8,  FPR_BASE + 9,  FPR_BASE + 10, FPR_BASE + 11,           \
  89   FPR_BASE + 12, FPR_BASE + 13, FPR_BASE + 14, FPR_BASE + 15,           \
  90   FPR_BASE + 16, FPR_BASE + 17, FPR_BASE + 18, FPR_BASE + 19,           \
  91   FPR_BASE + 20, FPR_BASE + 21, FPR_BASE + 22, FPR_BASE + 23,           \
  92   FPR_BASE + 24, FPR_BASE + 25, FPR_BASE + 26, FPR_BASE + 27,           \
  93   FPR_BASE + 28, FPR_BASE + 29, FPR_BASE + 30, FPR_BASE + 31,           \
  94   FPC_CSR, FPC_EIR
  95
  96 #define mips_dsp_regs                                                   \
  97   DSP_BASE,      DSP_BASE + 1,  DSP_BASE + 2,  DSP_BASE + 3,            \
  98   DSP_BASE + 4,  DSP_BASE + 5,                                          \
  99   DSP_CONTROL
 100
 101 static int mips_regmap[mips_num_regs] = {
 102   mips_base_regs,
 103   0
 104 };
 105
 106 static int mips_dsp_regmap[mips_dsp_num_regs] = {
 107   mips_base_regs,
 108   mips_dsp_regs,
 109   0
 110 };
 111
 112 /* DSP registers are not in any regset and can only be accessed
 113    individually.  */
 114
 115 static unsigned char mips_dsp_regset_bitmap[(mips_dsp_num_regs + 7) / 8] = {
 116   0xfe, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x80
 117 };
 118
 119 static int have_dsp = -1;
 120
 121 /* Try peeking at an arbitrarily chosen DSP register and pick the available
 122    user register set accordingly.  */
 123
 124 static const struct target_desc *
 125 mips_read_description (void)
 126 {
 127   if (have_dsp < 0)
 128     {
 129       int pid = lwpid_of (current_thread);
 130
 131       errno = 0;
 132       ptrace (PTRACE_PEEKUSER, pid, DSP_CONTROL, 0);
 133       switch (errno)
 134         {
 135         case 0:
 136           have_dsp = 1;
 137           break;
 138         case EIO:
 139           have_dsp = 0;
 140           break;
 141         default:
 142           perror_with_name ("ptrace");
 143           break;
 144         }
 145     }
 146
 147   return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux;
 148 }
 149
 150 static void
 151 mips_arch_setup (void)
 152 {
 153   current_process ()->tdesc = mips_read_description ();
 154 }
 155
 156 static struct usrregs_info *
 157 get_usrregs_info (void)
 158 {
 159   const struct regs_info *regs_info = the_low_target.regs_info ();
 160
 161   return regs_info->usrregs;
 162 }
 163
 164 /* Per-process arch-specific data we want to keep.  */
 165
 166 struct arch_process_info
 167 {
 168   /* -1 if the kernel and/or CPU do not support watch registers.
 169       1 if watch_readback is valid and we can read style, num_valid
 170         and the masks.
 171       0 if we need to read the watch_readback.  */
 172
 173   int watch_readback_valid;
 174
 175   /* Cached watch register read values.  */
 176
 177   struct pt_watch_regs watch_readback;
 178
 179   /* Current watchpoint requests for this process.  */
 180
 181   struct mips_watchpoint *current_watches;
 182
 183   /* The current set of watch register values for writing the
 184      registers.  */
 185
 186   struct pt_watch_regs watch_mirror;
 187 };
 188
 189 /* Per-thread arch-specific data we want to keep.  */
 190
 191 struct arch_lwp_info
 192 {
 193   /* Non-zero if our copy differs from what's recorded in the thread.  */
 194   int watch_registers_changed;
 195 };
 196
 197 /* From mips-linux-nat.c.  */
 198
 199 /* Pseudo registers can not be read.  ptrace does not provide a way to
 200    read (or set) PS_REGNUM, and there's no point in reading or setting
 201    ZERO_REGNUM, it's always 0.  We also can not set BADVADDR, CAUSE,
 202    or FCRIR via ptrace().  */
 203
 204 static int
 205 mips_cannot_fetch_register (int regno)
 206 {
 207   const struct target_desc *tdesc;
 208
 209   if (get_usrregs_info ()->regmap[regno] == -1)
 210     return 1;
 211
 212   tdesc = current_process ()->tdesc;
 213
 214   /* On n32 we can't access 64-bit registers via PTRACE_PEEKUSR.  */
 215   if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE))
 216     return 1;
 217
 218   if (find_regno (tdesc, "r0") == regno)
 219     return 1;
 220
 221   return 0;
 222 }
 223
 224 static int
 225 mips_cannot_store_register (int regno)
 226 {
 227   const struct target_desc *tdesc;
 228
 229   if (get_usrregs_info ()->regmap[regno] == -1)
 230     return 1;
 231
 232   tdesc = current_process ()->tdesc;
 233
 234   /* On n32 we can't access 64-bit registers via PTRACE_POKEUSR.  */
 235   if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE))
 236     return 1;
 237
 238   if (find_regno (tdesc, "r0") == regno)
 239     return 1;
 240
 241   if (find_regno (tdesc, "cause") == regno)
 242     return 1;
 243
 244   if (find_regno (tdesc, "badvaddr") == regno)
 245     return 1;
 246
 247   if (find_regno (tdesc, "fir") == regno)
 248     return 1;
 249
 250   return 0;
 251 }
 252
 253 static int
 254 mips_fetch_register (struct regcache *regcache, int regno)
 255 {
 256   const struct target_desc *tdesc = current_process ()->tdesc;
 257
 258   if (find_regno (tdesc, "r0") == regno)
 259     {
 260       supply_register_zeroed (regcache, regno);
 261       return 1;
 262     }
 263
 264   return 0;
 265 }
 266
 267 static CORE_ADDR
 268 mips_get_pc (struct regcache *regcache)
 269 {
 270   union mips_register pc;
 271   collect_register_by_name (regcache, "pc", pc.buf);
 272   return register_size (regcache->tdesc, 0) == 4 ? pc.reg32 : pc.reg64;
 273 }
 274
 275 static void
 276 mips_set_pc (struct regcache *regcache, CORE_ADDR pc)
 277 {
 278   union mips_register newpc;
 279   if (register_size (regcache->tdesc, 0) == 4)
 280     newpc.reg32 = pc;
 281   else
 282     newpc.reg64 = pc;
 283
 284   supply_register_by_name (regcache, "pc", newpc.buf);
 285 }
 286
 287 /* Correct in either endianness.  */
 288 static const unsigned int mips_breakpoint = 0x0005000d;
 289 #define mips_breakpoint_len 4
 290
 291 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind".  */
 292
 293 static const gdb_byte *
 294 mips_sw_breakpoint_from_kind (int kind, int *size)
 295 {
 296   *size = mips_breakpoint_len;
 297   return (const gdb_byte *) &mips_breakpoint;
 298 }
 299
 300 static int
 301 mips_breakpoint_at (CORE_ADDR where)
 302 {
 303   unsigned int insn;
 304
 305   the_target->pt->read_memory (where, (unsigned char *) &insn, 4);
 306   if (insn == mips_breakpoint)
 307     return 1;
 308
 309   /* If necessary, recognize more trap instructions here.  GDB only uses the
 310      one.  */
 311   return 0;
 312 }
 313
 314 /* Mark the watch registers of lwp, represented by ENTRY, as changed.  */
 315
 316 static void
 317 update_watch_registers_callback (thread_info *thread)
 318 {
 319   struct lwp_info *lwp = get_thread_lwp (thread);
 320
 321   /* The actual update is done later just before resuming the lwp,
 322      we just mark that the registers need updating.  */
 323   lwp->arch_private->watch_registers_changed = 1;
 324
 325   /* If the lwp isn't stopped, force it to momentarily pause, so
 326      we can update its watch registers.  */
 327   if (!lwp->stopped)
 328     linux_stop_lwp (lwp);
 329 }
 330
 331 /* This is the implementation of linux_target_ops method
 332    new_process.  */
 333
 334 static struct arch_process_info *
 335 mips_linux_new_process (void)
 336 {
 337   struct arch_process_info *info = XCNEW (struct arch_process_info);
 338
 339   return info;
 340 }
 341
 342 /* This is the implementation of linux_target_ops method
 343    delete_process.  */
 344
 345 static void
 346 mips_linux_delete_process (struct arch_process_info *info)
 347 {
 348   xfree (info);
 349 }
 350
 351 /* This is the implementation of linux_target_ops method new_thread.
 352    Mark the watch registers as changed, so the threads' copies will
 353    be updated.  */
 354
 355 static void
 356 mips_linux_new_thread (struct lwp_info *lwp)
 357 {
 358   struct arch_lwp_info *info = XCNEW (struct arch_lwp_info);
 359
 360   info->watch_registers_changed = 1;
 361
 362   lwp->arch_private = info;
 363 }
 364
 365 /* Function to call when a thread is being deleted.  */
 366
 367 static void
 368 mips_linux_delete_thread (struct arch_lwp_info *arch_lwp)
 369 {
 370   xfree (arch_lwp);
 371 }
 372
 373 /* Create a new mips_watchpoint and add it to the list.  */
 374
 375 static void
 376 mips_add_watchpoint (struct arch_process_info *priv, CORE_ADDR addr, int len,
 377                      enum target_hw_bp_type watch_type)
 378 {
 379   struct mips_watchpoint *new_watch;
 380   struct mips_watchpoint **pw;
 381
 382   new_watch = XNEW (struct mips_watchpoint);
 383   new_watch->addr = addr;
 384   new_watch->len = len;
 385   new_watch->type = watch_type;
 386   new_watch->next = NULL;
 387
 388   pw = &priv->current_watches;
 389   while (*pw != NULL)
 390     pw = &(*pw)->next;
 391   *pw = new_watch;
 392 }
 393
 394 /* Hook to call when a new fork is attached.  */
 395
 396 static void
 397 mips_linux_new_fork (struct process_info *parent,
 398                         struct process_info *child)
 399 {
 400   struct arch_process_info *parent_private;
 401   struct arch_process_info *child_private;
 402   struct mips_watchpoint *wp;
 403
 404   /* These are allocated by linux_add_process.  */
 405   gdb_assert (parent->priv != NULL
 406               && parent->priv->arch_private != NULL);
 407   gdb_assert (child->priv != NULL
 408               && child->priv->arch_private != NULL);
 409
 410   /* Linux kernel before 2.6.33 commit
 411      72f674d203cd230426437cdcf7dd6f681dad8b0d
 412      will inherit hardware debug registers from parent
 413      on fork/vfork/clone.  Newer Linux kernels create such tasks with
 414      zeroed debug registers.
 415
 416      GDB core assumes the child inherits the watchpoints/hw
 417      breakpoints of the parent, and will remove them all from the
 418      forked off process.  Copy the debug registers mirrors into the
 419      new process so that all breakpoints and watchpoints can be
 420      removed together.  The debug registers mirror will become zeroed
 421      in the end before detaching the forked off process, thus making
 422      this compatible with older Linux kernels too.  */
 423
 424   parent_private = parent->priv->arch_private;
 425   child_private = child->priv->arch_private;
 426
 427   child_private->watch_readback_valid = parent_private->watch_readback_valid;
 428   child_private->watch_readback = parent_private->watch_readback;
 429
 430   for (wp = parent_private->current_watches; wp != NULL; wp = wp->next)
 431     mips_add_watchpoint (child_private, wp->addr, wp->len, wp->type);
 432
 433   child_private->watch_mirror = parent_private->watch_mirror;
 434 }
 435 /* This is the implementation of linux_target_ops method
 436    prepare_to_resume.  If the watch regs have changed, update the
 437    thread's copies.  */
 438
 439 static void
 440 mips_linux_prepare_to_resume (struct lwp_info *lwp)
 441 {
 442   ptid_t ptid = ptid_of (get_lwp_thread (lwp));
 443   struct process_info *proc = find_process_pid (ptid.pid ());
 444   struct arch_process_info *priv = proc->priv->arch_private;
 445
 446   if (lwp->arch_private->watch_registers_changed)
 447     {
 448       /* Only update the watch registers if we have set or unset a
 449          watchpoint already.  */
 450       if (mips_linux_watch_get_num_valid (&priv->watch_mirror) > 0)
 451         {
 452           /* Write the mirrored watch register values.  */
 453           int tid = ptid.lwp ();
 454
 455           if (-1 == ptrace (PTRACE_SET_WATCH_REGS, tid,
 456                             &priv->watch_mirror, NULL))
 457             perror_with_name ("Couldn't write watch register");
 458         }
 459
 460       lwp->arch_private->watch_registers_changed = 0;
 461     }
 462 }
 463
 464 static int
 465 mips_supports_z_point_type (char z_type)
 466 {
 467   switch (z_type)
 468     {
 469     case Z_PACKET_WRITE_WP:
 470     case Z_PACKET_READ_WP:
 471     case Z_PACKET_ACCESS_WP:
 472       return 1;
 473     default:
 474       return 0;
 475     }
 476 }
 477
 478 /* This is the implementation of linux_target_ops method
 479    insert_point.  */
 480
 481 static int
 482 mips_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
 483                    int len, struct raw_breakpoint *bp)
 484 {
 485   struct process_info *proc = current_process ();
 486   struct arch_process_info *priv = proc->priv->arch_private;
 487   struct pt_watch_regs regs;
 488   long lwpid;
 489   enum target_hw_bp_type watch_type;
 490   uint32_t irw;
 491
 492   lwpid = lwpid_of (current_thread);
 493   if (!mips_linux_read_watch_registers (lwpid,
 494                                         &priv->watch_readback,
 495                                         &priv->watch_readback_valid,
 496                                         0))
 497     return -1;
 498
 499   if (len <= 0)
 500     return -1;
 501
 502   regs = priv->watch_readback;
 503   /* Add the current watches.  */
 504   mips_linux_watch_populate_regs (priv->current_watches, &regs);
 505
 506   /* Now try to add the new watch.  */
 507   watch_type = raw_bkpt_type_to_target_hw_bp_type (type);
 508   irw = mips_linux_watch_type_to_irw (watch_type);
 509   if (!mips_linux_watch_try_one_watch (&regs, addr, len, irw))
 510     return -1;
 511
 512   /* It fit.  Stick it on the end of the list.  */
 513   mips_add_watchpoint (priv, addr, len, watch_type);
 514
 515   priv->watch_mirror = regs;
 516
 517   /* Only update the threads of this process.  */
 518   for_each_thread (proc->pid, update_watch_registers_callback);
 519
 520   return 0;
 521 }
 522
 523 /* This is the implementation of linux_target_ops method
 524    remove_point.  */
 525
 526 static int
 527 mips_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
 528                    int len, struct raw_breakpoint *bp)
 529 {
 530   struct process_info *proc = current_process ();
 531   struct arch_process_info *priv = proc->priv->arch_private;
 532
 533   int deleted_one;
 534   enum target_hw_bp_type watch_type;
 535
 536   struct mips_watchpoint **pw;
 537   struct mips_watchpoint *w;
 538
 539   /* Search for a known watch that matches.  Then unlink and free it.  */
 540   watch_type = raw_bkpt_type_to_target_hw_bp_type (type);
 541   deleted_one = 0;
 542   pw = &priv->current_watches;
 543   while ((w = *pw))
 544     {
 545       if (w->addr == addr && w->len == len && w->type == watch_type)
 546         {
 547           *pw = w->next;
 548           free (w);
 549           deleted_one = 1;
 550           break;
 551         }
 552       pw = &(w->next);
 553     }
 554
 555   if (!deleted_one)
 556     return -1;  /* We don't know about it, fail doing nothing.  */
 557
 558   /* At this point watch_readback is known to be valid because we
 559      could not have added the watch without reading it.  */
 560   gdb_assert (priv->watch_readback_valid == 1);
 561
 562   priv->watch_mirror = priv->watch_readback;
 563   mips_linux_watch_populate_regs (priv->current_watches,
 564                                   &priv->watch_mirror);
 565
 566   /* Only update the threads of this process.  */
 567   for_each_thread (proc->pid, update_watch_registers_callback);
 568
 569   return 0;
 570 }
 571
 572 /* This is the implementation of linux_target_ops method
 573    stopped_by_watchpoint.  The watchhi R and W bits indicate
 574    the watch register triggered. */
 575
 576 static int
 577 mips_stopped_by_watchpoint (void)
 578 {
 579   struct process_info *proc = current_process ();
 580   struct arch_process_info *priv = proc->priv->arch_private;
 581   int n;
 582   int num_valid;
 583   long lwpid = lwpid_of (current_thread);
 584
 585   if (!mips_linux_read_watch_registers (lwpid,
 586                                         &priv->watch_readback,
 587                                         &priv->watch_readback_valid,
 588                                         1))
 589     return 0;
 590
 591   num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback);
 592
 593   for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
 594     if (mips_linux_watch_get_watchhi (&priv->watch_readback, n)
 595         & (R_MASK | W_MASK))
 596       return 1;
 597
 598   return 0;
 599 }
 600
 601 /* This is the implementation of linux_target_ops method
 602    stopped_data_address.  */
 603
 604 static CORE_ADDR
 605 mips_stopped_data_address (void)
 606 {
 607   struct process_info *proc = current_process ();
 608   struct arch_process_info *priv = proc->priv->arch_private;
 609   int n;
 610   int num_valid;
 611   long lwpid = lwpid_of (current_thread);
 612
 613   /* On MIPS we don't know the low order 3 bits of the data address.
 614      GDB does not support remote targets that can't report the
 615      watchpoint address.  So, make our best guess; return the starting
 616      address of a watchpoint request which overlaps the one that
 617      triggered.  */
 618
 619   if (!mips_linux_read_watch_registers (lwpid,
 620                                         &priv->watch_readback,
 621                                         &priv->watch_readback_valid,
 622                                         0))
 623     return 0;
 624
 625   num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback);
 626
 627   for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
 628     if (mips_linux_watch_get_watchhi (&priv->watch_readback, n)
 629         & (R_MASK | W_MASK))
 630       {
 631         CORE_ADDR t_low, t_hi;
 632         int t_irw;
 633         struct mips_watchpoint *watch;
 634
 635         t_low = mips_linux_watch_get_watchlo (&priv->watch_readback, n);
 636         t_irw = t_low & IRW_MASK;
 637         t_hi = (mips_linux_watch_get_watchhi (&priv->watch_readback, n)
 638                 | IRW_MASK);
 639         t_low &= ~(CORE_ADDR)t_hi;
 640
 641         for (watch = priv->current_watches;
 642              watch != NULL;
 643              watch = watch->next)
 644           {
 645             CORE_ADDR addr = watch->addr;
 646             CORE_ADDR last_byte = addr + watch->len - 1;
 647
 648             if ((t_irw & mips_linux_watch_type_to_irw (watch->type)) == 0)
 649               {
 650                 /* Different type.  */
 651                 continue;
 652               }
 653             /* Check for overlap of even a single byte.  */
 654             if (last_byte >= t_low && addr <= t_low + t_hi)
 655               return addr;
 656           }
 657       }
 658
 659   /* Shouldn't happen.  */
 660   return 0;
 661 }
 662
 663 /* Fetch the thread-local storage pointer for libthread_db.  */
 664
 665 ps_err_e
 666 ps_get_thread_area (struct ps_prochandle *ph,
 667                     lwpid_t lwpid, int idx, void **base)
 668 {
 669   if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
 670     return PS_ERR;
 671
 672   /* IDX is the bias from the thread pointer to the beginning of the
 673      thread descriptor.  It has to be subtracted due to implementation
 674      quirks in libthread_db.  */
 675   *base = (void *) ((char *)*base - idx);
 676
 677   return PS_OK;
 678 }
 679
 680 static void
 681 mips_collect_register (struct regcache *regcache,
 682                        int use_64bit, int regno, union mips_register *reg)
 683 {
 684   union mips_register tmp_reg;
 685
 686   if (use_64bit)
 687     {
 688       collect_register (regcache, regno, &tmp_reg.reg64);
 689       *reg = tmp_reg;
 690     }
 691   else
 692     {
 693       collect_register (regcache, regno, &tmp_reg.reg32);
 694       reg->reg64 = tmp_reg.reg32;
 695     }
 696 }
 697
 698 static void
 699 mips_supply_register (struct regcache *regcache,
 700                       int use_64bit, int regno, const union mips_register *reg)
 701 {
 702   int offset = 0;
 703
 704   /* For big-endian 32-bit targets, ignore the high four bytes of each
 705      eight-byte slot.  */
 706   if (__BYTE_ORDER == __BIG_ENDIAN && !use_64bit)
 707     offset = 4;
 708
 709   supply_register (regcache, regno, reg->buf + offset);
 710 }
 711
 712 #ifdef HAVE_PTRACE_GETREGS
 713
 714 static void
 715 mips_collect_register_32bit (struct regcache *regcache,
 716                              int use_64bit, int regno, unsigned char *buf)
 717 {
 718   union mips_register tmp_reg;
 719   int reg32;
 720
 721   mips_collect_register (regcache, use_64bit, regno, &tmp_reg);
 722   reg32 = tmp_reg.reg64;
 723   memcpy (buf, &reg32, 4);
 724 }
 725
 726 static void
 727 mips_supply_register_32bit (struct regcache *regcache,
 728                             int use_64bit, int regno, const unsigned char *buf)
 729 {
 730   union mips_register tmp_reg;
 731   int reg32;
 732
 733   memcpy (&reg32, buf, 4);
 734   tmp_reg.reg64 = reg32;
 735   mips_supply_register (regcache, use_64bit, regno, &tmp_reg);
 736 }
 737
 738 static void
 739 mips_fill_gregset (struct regcache *regcache, void *buf)
 740 {
 741   union mips_register *regset = (union mips_register *) buf;
 742   int i, use_64bit;
 743   const struct target_desc *tdesc = regcache->tdesc;
 744
 745   use_64bit = (register_size (tdesc, 0) == 8);
 746
 747   for (i = 1; i < 32; i++)
 748     mips_collect_register (regcache, use_64bit, i, regset + i);
 749
 750   mips_collect_register (regcache, use_64bit,
 751                          find_regno (tdesc, "lo"), regset + 32);
 752   mips_collect_register (regcache, use_64bit,
 753                          find_regno (tdesc, "hi"), regset + 33);
 754   mips_collect_register (regcache, use_64bit,
 755                          find_regno (tdesc, "pc"), regset + 34);
 756   mips_collect_register (regcache, use_64bit,
 757                          find_regno (tdesc, "badvaddr"), regset + 35);
 758   mips_collect_register (regcache, use_64bit,
 759                          find_regno (tdesc, "status"), regset + 36);
 760   mips_collect_register (regcache, use_64bit,
 761                          find_regno (tdesc, "cause"), regset + 37);
 762
 763   mips_collect_register (regcache, use_64bit,
 764                          find_regno (tdesc, "restart"), regset + 0);
 765 }
 766
 767 static void
 768 mips_store_gregset (struct regcache *regcache, const void *buf)
 769 {
 770   const union mips_register *regset = (const union mips_register *) buf;
 771   int i, use_64bit;
 772
 773   use_64bit = (register_size (regcache->tdesc, 0) == 8);
 774
 775   supply_register_by_name_zeroed (regcache, "r0");
 776
 777   for (i = 1; i < 32; i++)
 778     mips_supply_register (regcache, use_64bit, i, regset + i);
 779
 780   mips_supply_register (regcache, use_64bit,
 781                         find_regno (regcache->tdesc, "lo"), regset + 32);
 782   mips_supply_register (regcache, use_64bit,
 783                         find_regno (regcache->tdesc, "hi"), regset + 33);
 784   mips_supply_register (regcache, use_64bit,
 785                         find_regno (regcache->tdesc, "pc"), regset + 34);
 786   mips_supply_register (regcache, use_64bit,
 787                         find_regno (regcache->tdesc, "badvaddr"), regset + 35);
 788   mips_supply_register (regcache, use_64bit,
 789                         find_regno (regcache->tdesc, "status"), regset + 36);
 790   mips_supply_register (regcache, use_64bit,
 791                         find_regno (regcache->tdesc, "cause"), regset + 37);
 792
 793   mips_supply_register (regcache, use_64bit,
 794                         find_regno (regcache->tdesc, "restart"), regset + 0);
 795 }
 796
 797 static void
 798 mips_fill_fpregset (struct regcache *regcache, void *buf)
 799 {
 800   union mips_register *regset = (union mips_register *) buf;
 801   int i, use_64bit, first_fp, big_endian;
 802
 803   use_64bit = (register_size (regcache->tdesc, 0) == 8);
 804   first_fp = find_regno (regcache->tdesc, "f0");
 805   big_endian = (__BYTE_ORDER == __BIG_ENDIAN);
 806
 807   /* See GDB for a discussion of this peculiar layout.  */
 808   for (i = 0; i < 32; i++)
 809     if (use_64bit)
 810       collect_register (regcache, first_fp + i, regset[i].buf);
 811     else
 812       collect_register (regcache, first_fp + i,
 813                         regset[i & ~1].buf + 4 * (big_endian != (i & 1)));
 814
 815   mips_collect_register_32bit (regcache, use_64bit,
 816                                find_regno (regcache->tdesc, "fcsr"), regset[32].buf);
 817   mips_collect_register_32bit (regcache, use_64bit,
 818                                find_regno (regcache->tdesc, "fir"),
 819                                regset[32].buf + 4);
 820 }
 821
 822 static void
 823 mips_store_fpregset (struct regcache *regcache, const void *buf)
 824 {
 825   const union mips_register *regset = (const union mips_register *) buf;
 826   int i, use_64bit, first_fp, big_endian;
 827
 828   use_64bit = (register_size (regcache->tdesc, 0) == 8);
 829   first_fp = find_regno (regcache->tdesc, "f0");
 830   big_endian = (__BYTE_ORDER == __BIG_ENDIAN);
 831
 832   /* See GDB for a discussion of this peculiar layout.  */
 833   for (i = 0; i < 32; i++)
 834     if (use_64bit)
 835       supply_register (regcache, first_fp + i, regset[i].buf);
 836     else
 837       supply_register (regcache, first_fp + i,
 838                        regset[i & ~1].buf + 4 * (big_endian != (i & 1)));
 839
 840   mips_supply_register_32bit (regcache, use_64bit,
 841                               find_regno (regcache->tdesc, "fcsr"),
 842                               regset[32].buf);
 843   mips_supply_register_32bit (regcache, use_64bit,
 844                               find_regno (regcache->tdesc, "fir"),
 845                               regset[32].buf + 4);
 846 }
 847 #endif /* HAVE_PTRACE_GETREGS */
 848
 849 /* Take care of 32-bit registers with 64-bit ptrace, POKEUSER side.  */
 850
 851 static void
 852 mips_collect_ptrace_register (struct regcache *regcache,
 853                               int regno, char *buf)
 854 {
 855   int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8;
 856
 857   if (use_64bit && register_size (regcache->tdesc, regno) == 4)
 858     {
 859       union mips_register reg;
 860
 861       mips_collect_register (regcache, 0, regno, &reg);
 862       memcpy (buf, &reg, sizeof (reg));
 863     }
 864   else
 865     collect_register (regcache, regno, buf);
 866 }
 867
 868 /* Take care of 32-bit registers with 64-bit ptrace, PEEKUSER side.  */
 869
 870 static void
 871 mips_supply_ptrace_register (struct regcache *regcache,
 872                              int regno, const char *buf)
 873 {
 874   int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8;
 875
 876   if (use_64bit && register_size (regcache->tdesc, regno) == 4)
 877     {
 878       union mips_register reg;
 879
 880       memcpy (&reg, buf, sizeof (reg));
 881       mips_supply_register (regcache, 0, regno, &reg);
 882     }
 883   else
 884     supply_register (regcache, regno, buf);
 885 }
 886
 887 static struct regset_info mips_regsets[] = {
 888 #ifdef HAVE_PTRACE_GETREGS
 889   { PTRACE_GETREGS, PTRACE_SETREGS, 0, 38 * 8, GENERAL_REGS,
 890     mips_fill_gregset, mips_store_gregset },
 891   { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, 33 * 8, FP_REGS,
 892     mips_fill_fpregset, mips_store_fpregset },
 893 #endif /* HAVE_PTRACE_GETREGS */
 894   NULL_REGSET
 895 };
 896
 897 static struct regsets_info mips_regsets_info =
 898   {
 899     mips_regsets, /* regsets */
 900     0, /* num_regsets */
 901     NULL, /* disabled_regsets */
 902   };
 903
 904 static struct usrregs_info mips_dsp_usrregs_info =
 905   {
 906     mips_dsp_num_regs,
 907     mips_dsp_regmap,
 908   };
 909
 910 static struct usrregs_info mips_usrregs_info =
 911   {
 912     mips_num_regs,
 913     mips_regmap,
 914   };
 915
 916 static struct regs_info dsp_regs_info =
 917   {
 918     mips_dsp_regset_bitmap,
 919     &mips_dsp_usrregs_info,
 920     &mips_regsets_info
 921   };
 922
 923 static struct regs_info regs_info =
 924   {
 925     NULL, /* regset_bitmap */
 926     &mips_usrregs_info,
 927     &mips_regsets_info
 928   };
 929
 930 static const struct regs_info *
 931 mips_regs_info (void)
 932 {
 933   if (have_dsp)
 934     return &dsp_regs_info;
 935   else
 936     return &regs_info;
 937 }
 938
 939 struct linux_target_ops the_low_target = {
 940   mips_arch_setup,
 941   mips_regs_info,
 942   mips_cannot_fetch_register,
 943   mips_cannot_store_register,
 944   mips_fetch_register,
 945   mips_get_pc,
 946   mips_set_pc,
 947   NULL, /* breakpoint_kind_from_pc */
 948   mips_sw_breakpoint_from_kind,
 949   NULL, /* get_next_pcs */
 950   0,
 951   mips_breakpoint_at,
 952   mips_supports_z_point_type,
 953   mips_insert_point,
 954   mips_remove_point,
 955   mips_stopped_by_watchpoint,
 956   mips_stopped_data_address,
 957   mips_collect_ptrace_register,
 958   mips_supply_ptrace_register,
 959   NULL, /* siginfo_fixup */
 960   mips_linux_new_process,
 961   mips_linux_delete_process,
 962   mips_linux_new_thread,
 963   mips_linux_delete_thread,
 964   mips_linux_new_fork,
 965   mips_linux_prepare_to_resume
 966 };
 967
 968 void
 969 initialize_low_arch (void)
 970 {
 971   /* Initialize the Linux target descriptions.  */
 972   init_registers_mips_linux ();
 973   init_registers_mips_dsp_linux ();
 974   init_registers_mips64_linux ();
 975   init_registers_mips64_dsp_linux ();
 976
 977   initialize_regsets_info (&mips_regsets_info);
 978 }