gdbserver/linux-mips-low.cc

   1 /* GNU/Linux/MIPS specific low level interface, for the remote server for GDB.
   2    Copyright (C) 1995-2020 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #include "server.h"
  20 #include "linux-low.h"
  21
  22 #include "nat/gdb_ptrace.h"
  23 #include <endian.h>
  24
  25 #include "nat/mips-linux-watch.h"
  26 #include "gdb_proc_service.h"
  27
  28 /* Linux target op definitions for the MIPS architecture.  */
  29
  30 class mips_target : public linux_process_target
  31 {
  32 public:
  33
  34   const regs_info *get_regs_info () override;
  35
  36 protected:
  37
  38   void low_arch_setup () override;
  39
  40   bool low_cannot_fetch_register (int regno) override;
  41
  42   bool low_cannot_store_register (int regno) override;
  43
  44   bool low_fetch_register (regcache *regcache, int regno) override;
  45
  46   bool low_supports_breakpoints () override;
  47
  48   CORE_ADDR low_get_pc (regcache *regcache) override;
  49
  50   void low_set_pc (regcache *regcache, CORE_ADDR newpc) override;
  51 };
  52
  53 /* The singleton target ops object.  */
  54
  55 static mips_target the_mips_target;
  56
  57 /* Defined in auto-generated file mips-linux.c.  */
  58 void init_registers_mips_linux (void);
  59 extern const struct target_desc *tdesc_mips_linux;
  60
  61 /* Defined in auto-generated file mips-dsp-linux.c.  */
  62 void init_registers_mips_dsp_linux (void);
  63 extern const struct target_desc *tdesc_mips_dsp_linux;
  64
  65 /* Defined in auto-generated file mips64-linux.c.  */
  66 void init_registers_mips64_linux (void);
  67 extern const struct target_desc *tdesc_mips64_linux;
  68
  69 /* Defined in auto-generated file mips64-dsp-linux.c.  */
  70 void init_registers_mips64_dsp_linux (void);
  71 extern const struct target_desc *tdesc_mips64_dsp_linux;
  72
  73 #ifdef __mips64
  74 #define tdesc_mips_linux tdesc_mips64_linux
  75 #define tdesc_mips_dsp_linux tdesc_mips64_dsp_linux
  76 #endif
  77
  78 #ifndef PTRACE_GET_THREAD_AREA
  79 #define PTRACE_GET_THREAD_AREA 25
  80 #endif
  81
  82 #ifdef HAVE_SYS_REG_H
  83 #include <sys/reg.h>
  84 #endif
  85
  86 #define mips_num_regs 73
  87 #define mips_dsp_num_regs 80
  88
  89 #include <asm/ptrace.h>
  90
  91 #ifndef DSP_BASE
  92 #define DSP_BASE 71
  93 #define DSP_CONTROL 77
  94 #endif
  95
  96 union mips_register
  97 {
  98   unsigned char buf[8];
  99
 100   /* Deliberately signed, for proper sign extension.  */
 101   int reg32;
 102   long long reg64;
 103 };
 104
 105 /* Return the ptrace ``address'' of register REGNO. */
 106
 107 #define mips_base_regs                                                  \
 108   -1,  1,  2,  3,  4,  5,  6,  7,                                       \
 109   8,  9,  10, 11, 12, 13, 14, 15,                                       \
 110   16, 17, 18, 19, 20, 21, 22, 23,                                       \
 111   24, 25, 26, 27, 28, 29, 30, 31,                                       \
 112                                                                         \
 113   -1, MMLO, MMHI, BADVADDR, CAUSE, PC,                                  \
 114                                                                         \
 115   FPR_BASE,      FPR_BASE + 1,  FPR_BASE + 2,  FPR_BASE + 3,            \
 116   FPR_BASE + 4,  FPR_BASE + 5,  FPR_BASE + 6,  FPR_BASE + 7,            \
 117   FPR_BASE + 8,  FPR_BASE + 9,  FPR_BASE + 10, FPR_BASE + 11,           \
 118   FPR_BASE + 12, FPR_BASE + 13, FPR_BASE + 14, FPR_BASE + 15,           \
 119   FPR_BASE + 16, FPR_BASE + 17, FPR_BASE + 18, FPR_BASE + 19,           \
 120   FPR_BASE + 20, FPR_BASE + 21, FPR_BASE + 22, FPR_BASE + 23,           \
 121   FPR_BASE + 24, FPR_BASE + 25, FPR_BASE + 26, FPR_BASE + 27,           \
 122   FPR_BASE + 28, FPR_BASE + 29, FPR_BASE + 30, FPR_BASE + 31,           \
 123   FPC_CSR, FPC_EIR
 124
 125 #define mips_dsp_regs                                                   \
 126   DSP_BASE,      DSP_BASE + 1,  DSP_BASE + 2,  DSP_BASE + 3,            \
 127   DSP_BASE + 4,  DSP_BASE + 5,                                          \
 128   DSP_CONTROL
 129
 130 static int mips_regmap[mips_num_regs] = {
 131   mips_base_regs,
 132   0
 133 };
 134
 135 static int mips_dsp_regmap[mips_dsp_num_regs] = {
 136   mips_base_regs,
 137   mips_dsp_regs,
 138   0
 139 };
 140
 141 /* DSP registers are not in any regset and can only be accessed
 142    individually.  */
 143
 144 static unsigned char mips_dsp_regset_bitmap[(mips_dsp_num_regs + 7) / 8] = {
 145   0xfe, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x80
 146 };
 147
 148 static int have_dsp = -1;
 149
 150 /* Try peeking at an arbitrarily chosen DSP register and pick the available
 151    user register set accordingly.  */
 152
 153 static const struct target_desc *
 154 mips_read_description (void)
 155 {
 156   if (have_dsp < 0)
 157     {
 158       int pid = lwpid_of (current_thread);
 159
 160       errno = 0;
 161       ptrace (PTRACE_PEEKUSER, pid, DSP_CONTROL, 0);
 162       switch (errno)
 163         {
 164         case 0:
 165           have_dsp = 1;
 166           break;
 167         case EIO:
 168           have_dsp = 0;
 169           break;
 170         default:
 171           perror_with_name ("ptrace");
 172           break;
 173         }
 174     }
 175
 176   return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux;
 177 }
 178
 179 void
 180 mips_target::low_arch_setup ()
 181 {
 182   current_process ()->tdesc = mips_read_description ();
 183 }
 184
 185 /* Per-process arch-specific data we want to keep.  */
 186
 187 struct arch_process_info
 188 {
 189   /* -1 if the kernel and/or CPU do not support watch registers.
 190       1 if watch_readback is valid and we can read style, num_valid
 191         and the masks.
 192       0 if we need to read the watch_readback.  */
 193
 194   int watch_readback_valid;
 195
 196   /* Cached watch register read values.  */
 197
 198   struct pt_watch_regs watch_readback;
 199
 200   /* Current watchpoint requests for this process.  */
 201
 202   struct mips_watchpoint *current_watches;
 203
 204   /* The current set of watch register values for writing the
 205      registers.  */
 206
 207   struct pt_watch_regs watch_mirror;
 208 };
 209
 210 /* Per-thread arch-specific data we want to keep.  */
 211
 212 struct arch_lwp_info
 213 {
 214   /* Non-zero if our copy differs from what's recorded in the thread.  */
 215   int watch_registers_changed;
 216 };
 217
 218 /* From mips-linux-nat.c.  */
 219
 220 /* Pseudo registers can not be read.  ptrace does not provide a way to
 221    read (or set) PS_REGNUM, and there's no point in reading or setting
 222    ZERO_REGNUM, it's always 0.  We also can not set BADVADDR, CAUSE,
 223    or FCRIR via ptrace().  */
 224
 225 bool
 226 mips_target::low_cannot_fetch_register (int regno)
 227 {
 228   const struct target_desc *tdesc;
 229
 230   if (get_regs_info ()->usrregs->regmap[regno] == -1)
 231     return true;
 232
 233   tdesc = current_process ()->tdesc;
 234
 235   /* On n32 we can't access 64-bit registers via PTRACE_PEEKUSR.  */
 236   if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE))
 237     return true;
 238
 239   if (find_regno (tdesc, "r0") == regno)
 240     return true;
 241
 242   return false;
 243 }
 244
 245 bool
 246 mips_target::low_cannot_store_register (int regno)
 247 {
 248   const struct target_desc *tdesc;
 249
 250   if (get_regs_info ()->usrregs->regmap[regno] == -1)
 251     return true;
 252
 253   tdesc = current_process ()->tdesc;
 254
 255   /* On n32 we can't access 64-bit registers via PTRACE_POKEUSR.  */
 256   if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE))
 257     return true;
 258
 259   if (find_regno (tdesc, "r0") == regno)
 260     return true;
 261
 262   if (find_regno (tdesc, "cause") == regno)
 263     return true;
 264
 265   if (find_regno (tdesc, "badvaddr") == regno)
 266     return true;
 267
 268   if (find_regno (tdesc, "fir") == regno)
 269     return true;
 270
 271   return false;
 272 }
 273
 274 bool
 275 mips_target::low_fetch_register (regcache *regcache, int regno)
 276 {
 277   const struct target_desc *tdesc = current_process ()->tdesc;
 278
 279   if (find_regno (tdesc, "r0") == regno)
 280     {
 281       supply_register_zeroed (regcache, regno);
 282       return true;
 283     }
 284
 285   return false;
 286 }
 287
 288 bool
 289 mips_target::low_supports_breakpoints ()
 290 {
 291   return true;
 292 }
 293
 294 CORE_ADDR
 295 mips_target::low_get_pc (regcache *regcache)
 296 {
 297   union mips_register pc;
 298   collect_register_by_name (regcache, "pc", pc.buf);
 299   return register_size (regcache->tdesc, 0) == 4 ? pc.reg32 : pc.reg64;
 300 }
 301
 302 void
 303 mips_target::low_set_pc (regcache *regcache, CORE_ADDR pc)
 304 {
 305   union mips_register newpc;
 306   if (register_size (regcache->tdesc, 0) == 4)
 307     newpc.reg32 = pc;
 308   else
 309     newpc.reg64 = pc;
 310
 311   supply_register_by_name (regcache, "pc", newpc.buf);
 312 }
 313
 314 /* Correct in either endianness.  */
 315 static const unsigned int mips_breakpoint = 0x0005000d;
 316 #define mips_breakpoint_len 4
 317
 318 /* Implementation of linux_target_ops method "sw_breakpoint_from_kind".  */
 319
 320 static const gdb_byte *
 321 mips_sw_breakpoint_from_kind (int kind, int *size)
 322 {
 323   *size = mips_breakpoint_len;
 324   return (const gdb_byte *) &mips_breakpoint;
 325 }
 326
 327 static int
 328 mips_breakpoint_at (CORE_ADDR where)
 329 {
 330   unsigned int insn;
 331
 332   the_target->read_memory (where, (unsigned char *) &insn, 4);
 333   if (insn == mips_breakpoint)
 334     return 1;
 335
 336   /* If necessary, recognize more trap instructions here.  GDB only uses the
 337      one.  */
 338   return 0;
 339 }
 340
 341 /* Mark the watch registers of lwp, represented by ENTRY, as changed.  */
 342
 343 static void
 344 update_watch_registers_callback (thread_info *thread)
 345 {
 346   struct lwp_info *lwp = get_thread_lwp (thread);
 347
 348   /* The actual update is done later just before resuming the lwp,
 349      we just mark that the registers need updating.  */
 350   lwp->arch_private->watch_registers_changed = 1;
 351
 352   /* If the lwp isn't stopped, force it to momentarily pause, so
 353      we can update its watch registers.  */
 354   if (!lwp->stopped)
 355     linux_stop_lwp (lwp);
 356 }
 357
 358 /* This is the implementation of linux_target_ops method
 359    new_process.  */
 360
 361 static struct arch_process_info *
 362 mips_linux_new_process (void)
 363 {
 364   struct arch_process_info *info = XCNEW (struct arch_process_info);
 365
 366   return info;
 367 }
 368
 369 /* This is the implementation of linux_target_ops method
 370    delete_process.  */
 371
 372 static void
 373 mips_linux_delete_process (struct arch_process_info *info)
 374 {
 375   xfree (info);
 376 }
 377
 378 /* This is the implementation of linux_target_ops method new_thread.
 379    Mark the watch registers as changed, so the threads' copies will
 380    be updated.  */
 381
 382 static void
 383 mips_linux_new_thread (struct lwp_info *lwp)
 384 {
 385   struct arch_lwp_info *info = XCNEW (struct arch_lwp_info);
 386
 387   info->watch_registers_changed = 1;
 388
 389   lwp->arch_private = info;
 390 }
 391
 392 /* Function to call when a thread is being deleted.  */
 393
 394 static void
 395 mips_linux_delete_thread (struct arch_lwp_info *arch_lwp)
 396 {
 397   xfree (arch_lwp);
 398 }
 399
 400 /* Create a new mips_watchpoint and add it to the list.  */
 401
 402 static void
 403 mips_add_watchpoint (struct arch_process_info *priv, CORE_ADDR addr, int len,
 404                      enum target_hw_bp_type watch_type)
 405 {
 406   struct mips_watchpoint *new_watch;
 407   struct mips_watchpoint **pw;
 408
 409   new_watch = XNEW (struct mips_watchpoint);
 410   new_watch->addr = addr;
 411   new_watch->len = len;
 412   new_watch->type = watch_type;
 413   new_watch->next = NULL;
 414
 415   pw = &priv->current_watches;
 416   while (*pw != NULL)
 417     pw = &(*pw)->next;
 418   *pw = new_watch;
 419 }
 420
 421 /* Hook to call when a new fork is attached.  */
 422
 423 static void
 424 mips_linux_new_fork (struct process_info *parent,
 425                         struct process_info *child)
 426 {
 427   struct arch_process_info *parent_private;
 428   struct arch_process_info *child_private;
 429   struct mips_watchpoint *wp;
 430
 431   /* These are allocated by linux_add_process.  */
 432   gdb_assert (parent->priv != NULL
 433               && parent->priv->arch_private != NULL);
 434   gdb_assert (child->priv != NULL
 435               && child->priv->arch_private != NULL);
 436
 437   /* Linux kernel before 2.6.33 commit
 438      72f674d203cd230426437cdcf7dd6f681dad8b0d
 439      will inherit hardware debug registers from parent
 440      on fork/vfork/clone.  Newer Linux kernels create such tasks with
 441      zeroed debug registers.
 442
 443      GDB core assumes the child inherits the watchpoints/hw
 444      breakpoints of the parent, and will remove them all from the
 445      forked off process.  Copy the debug registers mirrors into the
 446      new process so that all breakpoints and watchpoints can be
 447      removed together.  The debug registers mirror will become zeroed
 448      in the end before detaching the forked off process, thus making
 449      this compatible with older Linux kernels too.  */
 450
 451   parent_private = parent->priv->arch_private;
 452   child_private = child->priv->arch_private;
 453
 454   child_private->watch_readback_valid = parent_private->watch_readback_valid;
 455   child_private->watch_readback = parent_private->watch_readback;
 456
 457   for (wp = parent_private->current_watches; wp != NULL; wp = wp->next)
 458     mips_add_watchpoint (child_private, wp->addr, wp->len, wp->type);
 459
 460   child_private->watch_mirror = parent_private->watch_mirror;
 461 }
 462 /* This is the implementation of linux_target_ops method
 463    prepare_to_resume.  If the watch regs have changed, update the
 464    thread's copies.  */
 465
 466 static void
 467 mips_linux_prepare_to_resume (struct lwp_info *lwp)
 468 {
 469   ptid_t ptid = ptid_of (get_lwp_thread (lwp));
 470   struct process_info *proc = find_process_pid (ptid.pid ());
 471   struct arch_process_info *priv = proc->priv->arch_private;
 472
 473   if (lwp->arch_private->watch_registers_changed)
 474     {
 475       /* Only update the watch registers if we have set or unset a
 476          watchpoint already.  */
 477       if (mips_linux_watch_get_num_valid (&priv->watch_mirror) > 0)
 478         {
 479           /* Write the mirrored watch register values.  */
 480           int tid = ptid.lwp ();
 481
 482           if (-1 == ptrace (PTRACE_SET_WATCH_REGS, tid,
 483                             &priv->watch_mirror, NULL))
 484             perror_with_name ("Couldn't write watch register");
 485         }
 486
 487       lwp->arch_private->watch_registers_changed = 0;
 488     }
 489 }
 490
 491 static int
 492 mips_supports_z_point_type (char z_type)
 493 {
 494   switch (z_type)
 495     {
 496     case Z_PACKET_WRITE_WP:
 497     case Z_PACKET_READ_WP:
 498     case Z_PACKET_ACCESS_WP:
 499       return 1;
 500     default:
 501       return 0;
 502     }
 503 }
 504
 505 /* This is the implementation of linux_target_ops method
 506    insert_point.  */
 507
 508 static int
 509 mips_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
 510                    int len, struct raw_breakpoint *bp)
 511 {
 512   struct process_info *proc = current_process ();
 513   struct arch_process_info *priv = proc->priv->arch_private;
 514   struct pt_watch_regs regs;
 515   long lwpid;
 516   enum target_hw_bp_type watch_type;
 517   uint32_t irw;
 518
 519   lwpid = lwpid_of (current_thread);
 520   if (!mips_linux_read_watch_registers (lwpid,
 521                                         &priv->watch_readback,
 522                                         &priv->watch_readback_valid,
 523                                         0))
 524     return -1;
 525
 526   if (len <= 0)
 527     return -1;
 528
 529   regs = priv->watch_readback;
 530   /* Add the current watches.  */
 531   mips_linux_watch_populate_regs (priv->current_watches, &regs);
 532
 533   /* Now try to add the new watch.  */
 534   watch_type = raw_bkpt_type_to_target_hw_bp_type (type);
 535   irw = mips_linux_watch_type_to_irw (watch_type);
 536   if (!mips_linux_watch_try_one_watch (&regs, addr, len, irw))
 537     return -1;
 538
 539   /* It fit.  Stick it on the end of the list.  */
 540   mips_add_watchpoint (priv, addr, len, watch_type);
 541
 542   priv->watch_mirror = regs;
 543
 544   /* Only update the threads of this process.  */
 545   for_each_thread (proc->pid, update_watch_registers_callback);
 546
 547   return 0;
 548 }
 549
 550 /* This is the implementation of linux_target_ops method
 551    remove_point.  */
 552
 553 static int
 554 mips_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
 555                    int len, struct raw_breakpoint *bp)
 556 {
 557   struct process_info *proc = current_process ();
 558   struct arch_process_info *priv = proc->priv->arch_private;
 559
 560   int deleted_one;
 561   enum target_hw_bp_type watch_type;
 562
 563   struct mips_watchpoint **pw;
 564   struct mips_watchpoint *w;
 565
 566   /* Search for a known watch that matches.  Then unlink and free it.  */
 567   watch_type = raw_bkpt_type_to_target_hw_bp_type (type);
 568   deleted_one = 0;
 569   pw = &priv->current_watches;
 570   while ((w = *pw))
 571     {
 572       if (w->addr == addr && w->len == len && w->type == watch_type)
 573         {
 574           *pw = w->next;
 575           free (w);
 576           deleted_one = 1;
 577           break;
 578         }
 579       pw = &(w->next);
 580     }
 581
 582   if (!deleted_one)
 583     return -1;  /* We don't know about it, fail doing nothing.  */
 584
 585   /* At this point watch_readback is known to be valid because we
 586      could not have added the watch without reading it.  */
 587   gdb_assert (priv->watch_readback_valid == 1);
 588
 589   priv->watch_mirror = priv->watch_readback;
 590   mips_linux_watch_populate_regs (priv->current_watches,
 591                                   &priv->watch_mirror);
 592
 593   /* Only update the threads of this process.  */
 594   for_each_thread (proc->pid, update_watch_registers_callback);
 595
 596   return 0;
 597 }
 598
 599 /* This is the implementation of linux_target_ops method
 600    stopped_by_watchpoint.  The watchhi R and W bits indicate
 601    the watch register triggered. */
 602
 603 static int
 604 mips_stopped_by_watchpoint (void)
 605 {
 606   struct process_info *proc = current_process ();
 607   struct arch_process_info *priv = proc->priv->arch_private;
 608   int n;
 609   int num_valid;
 610   long lwpid = lwpid_of (current_thread);
 611
 612   if (!mips_linux_read_watch_registers (lwpid,
 613                                         &priv->watch_readback,
 614                                         &priv->watch_readback_valid,
 615                                         1))
 616     return 0;
 617
 618   num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback);
 619
 620   for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
 621     if (mips_linux_watch_get_watchhi (&priv->watch_readback, n)
 622         & (R_MASK | W_MASK))
 623       return 1;
 624
 625   return 0;
 626 }
 627
 628 /* This is the implementation of linux_target_ops method
 629    stopped_data_address.  */
 630
 631 static CORE_ADDR
 632 mips_stopped_data_address (void)
 633 {
 634   struct process_info *proc = current_process ();
 635   struct arch_process_info *priv = proc->priv->arch_private;
 636   int n;
 637   int num_valid;
 638   long lwpid = lwpid_of (current_thread);
 639
 640   /* On MIPS we don't know the low order 3 bits of the data address.
 641      GDB does not support remote targets that can't report the
 642      watchpoint address.  So, make our best guess; return the starting
 643      address of a watchpoint request which overlaps the one that
 644      triggered.  */
 645
 646   if (!mips_linux_read_watch_registers (lwpid,
 647                                         &priv->watch_readback,
 648                                         &priv->watch_readback_valid,
 649                                         0))
 650     return 0;
 651
 652   num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback);
 653
 654   for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
 655     if (mips_linux_watch_get_watchhi (&priv->watch_readback, n)
 656         & (R_MASK | W_MASK))
 657       {
 658         CORE_ADDR t_low, t_hi;
 659         int t_irw;
 660         struct mips_watchpoint *watch;
 661
 662         t_low = mips_linux_watch_get_watchlo (&priv->watch_readback, n);
 663         t_irw = t_low & IRW_MASK;
 664         t_hi = (mips_linux_watch_get_watchhi (&priv->watch_readback, n)
 665                 | IRW_MASK);
 666         t_low &= ~(CORE_ADDR)t_hi;
 667
 668         for (watch = priv->current_watches;
 669              watch != NULL;
 670              watch = watch->next)
 671           {
 672             CORE_ADDR addr = watch->addr;
 673             CORE_ADDR last_byte = addr + watch->len - 1;
 674
 675             if ((t_irw & mips_linux_watch_type_to_irw (watch->type)) == 0)
 676               {
 677                 /* Different type.  */
 678                 continue;
 679               }
 680             /* Check for overlap of even a single byte.  */
 681             if (last_byte >= t_low && addr <= t_low + t_hi)
 682               return addr;
 683           }
 684       }
 685
 686   /* Shouldn't happen.  */
 687   return 0;
 688 }
 689
 690 /* Fetch the thread-local storage pointer for libthread_db.  */
 691
 692 ps_err_e
 693 ps_get_thread_area (struct ps_prochandle *ph,
 694                     lwpid_t lwpid, int idx, void **base)
 695 {
 696   if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
 697     return PS_ERR;
 698
 699   /* IDX is the bias from the thread pointer to the beginning of the
 700      thread descriptor.  It has to be subtracted due to implementation
 701      quirks in libthread_db.  */
 702   *base = (void *) ((char *)*base - idx);
 703
 704   return PS_OK;
 705 }
 706
 707 static void
 708 mips_collect_register (struct regcache *regcache,
 709                        int use_64bit, int regno, union mips_register *reg)
 710 {
 711   union mips_register tmp_reg;
 712
 713   if (use_64bit)
 714     {
 715       collect_register (regcache, regno, &tmp_reg.reg64);
 716       *reg = tmp_reg;
 717     }
 718   else
 719     {
 720       collect_register (regcache, regno, &tmp_reg.reg32);
 721       reg->reg64 = tmp_reg.reg32;
 722     }
 723 }
 724
 725 static void
 726 mips_supply_register (struct regcache *regcache,
 727                       int use_64bit, int regno, const union mips_register *reg)
 728 {
 729   int offset = 0;
 730
 731   /* For big-endian 32-bit targets, ignore the high four bytes of each
 732      eight-byte slot.  */
 733   if (__BYTE_ORDER == __BIG_ENDIAN && !use_64bit)
 734     offset = 4;
 735
 736   supply_register (regcache, regno, reg->buf + offset);
 737 }
 738
 739 #ifdef HAVE_PTRACE_GETREGS
 740
 741 static void
 742 mips_collect_register_32bit (struct regcache *regcache,
 743                              int use_64bit, int regno, unsigned char *buf)
 744 {
 745   union mips_register tmp_reg;
 746   int reg32;
 747
 748   mips_collect_register (regcache, use_64bit, regno, &tmp_reg);
 749   reg32 = tmp_reg.reg64;
 750   memcpy (buf, &reg32, 4);
 751 }
 752
 753 static void
 754 mips_supply_register_32bit (struct regcache *regcache,
 755                             int use_64bit, int regno, const unsigned char *buf)
 756 {
 757   union mips_register tmp_reg;
 758   int reg32;
 759
 760   memcpy (&reg32, buf, 4);
 761   tmp_reg.reg64 = reg32;
 762   mips_supply_register (regcache, use_64bit, regno, &tmp_reg);
 763 }
 764
 765 static void
 766 mips_fill_gregset (struct regcache *regcache, void *buf)
 767 {
 768   union mips_register *regset = (union mips_register *) buf;
 769   int i, use_64bit;
 770   const struct target_desc *tdesc = regcache->tdesc;
 771
 772   use_64bit = (register_size (tdesc, 0) == 8);
 773
 774   for (i = 1; i < 32; i++)
 775     mips_collect_register (regcache, use_64bit, i, regset + i);
 776
 777   mips_collect_register (regcache, use_64bit,
 778                          find_regno (tdesc, "lo"), regset + 32);
 779   mips_collect_register (regcache, use_64bit,
 780                          find_regno (tdesc, "hi"), regset + 33);
 781   mips_collect_register (regcache, use_64bit,
 782                          find_regno (tdesc, "pc"), regset + 34);
 783   mips_collect_register (regcache, use_64bit,
 784                          find_regno (tdesc, "badvaddr"), regset + 35);
 785   mips_collect_register (regcache, use_64bit,
 786                          find_regno (tdesc, "status"), regset + 36);
 787   mips_collect_register (regcache, use_64bit,
 788                          find_regno (tdesc, "cause"), regset + 37);
 789
 790   mips_collect_register (regcache, use_64bit,
 791                          find_regno (tdesc, "restart"), regset + 0);
 792 }
 793
 794 static void
 795 mips_store_gregset (struct regcache *regcache, const void *buf)
 796 {
 797   const union mips_register *regset = (const union mips_register *) buf;
 798   int i, use_64bit;
 799
 800   use_64bit = (register_size (regcache->tdesc, 0) == 8);
 801
 802   supply_register_by_name_zeroed (regcache, "r0");
 803
 804   for (i = 1; i < 32; i++)
 805     mips_supply_register (regcache, use_64bit, i, regset + i);
 806
 807   mips_supply_register (regcache, use_64bit,
 808                         find_regno (regcache->tdesc, "lo"), regset + 32);
 809   mips_supply_register (regcache, use_64bit,
 810                         find_regno (regcache->tdesc, "hi"), regset + 33);
 811   mips_supply_register (regcache, use_64bit,
 812                         find_regno (regcache->tdesc, "pc"), regset + 34);
 813   mips_supply_register (regcache, use_64bit,
 814                         find_regno (regcache->tdesc, "badvaddr"), regset + 35);
 815   mips_supply_register (regcache, use_64bit,
 816                         find_regno (regcache->tdesc, "status"), regset + 36);
 817   mips_supply_register (regcache, use_64bit,
 818                         find_regno (regcache->tdesc, "cause"), regset + 37);
 819
 820   mips_supply_register (regcache, use_64bit,
 821                         find_regno (regcache->tdesc, "restart"), regset + 0);
 822 }
 823
 824 static void
 825 mips_fill_fpregset (struct regcache *regcache, void *buf)
 826 {
 827   union mips_register *regset = (union mips_register *) buf;
 828   int i, use_64bit, first_fp, big_endian;
 829
 830   use_64bit = (register_size (regcache->tdesc, 0) == 8);
 831   first_fp = find_regno (regcache->tdesc, "f0");
 832   big_endian = (__BYTE_ORDER == __BIG_ENDIAN);
 833
 834   /* See GDB for a discussion of this peculiar layout.  */
 835   for (i = 0; i < 32; i++)
 836     if (use_64bit)
 837       collect_register (regcache, first_fp + i, regset[i].buf);
 838     else
 839       collect_register (regcache, first_fp + i,
 840                         regset[i & ~1].buf + 4 * (big_endian != (i & 1)));
 841
 842   mips_collect_register_32bit (regcache, use_64bit,
 843                                find_regno (regcache->tdesc, "fcsr"), regset[32].buf);
 844   mips_collect_register_32bit (regcache, use_64bit,
 845                                find_regno (regcache->tdesc, "fir"),
 846                                regset[32].buf + 4);
 847 }
 848
 849 static void
 850 mips_store_fpregset (struct regcache *regcache, const void *buf)
 851 {
 852   const union mips_register *regset = (const union mips_register *) buf;
 853   int i, use_64bit, first_fp, big_endian;
 854
 855   use_64bit = (register_size (regcache->tdesc, 0) == 8);
 856   first_fp = find_regno (regcache->tdesc, "f0");
 857   big_endian = (__BYTE_ORDER == __BIG_ENDIAN);
 858
 859   /* See GDB for a discussion of this peculiar layout.  */
 860   for (i = 0; i < 32; i++)
 861     if (use_64bit)
 862       supply_register (regcache, first_fp + i, regset[i].buf);
 863     else
 864       supply_register (regcache, first_fp + i,
 865                        regset[i & ~1].buf + 4 * (big_endian != (i & 1)));
 866
 867   mips_supply_register_32bit (regcache, use_64bit,
 868                               find_regno (regcache->tdesc, "fcsr"),
 869                               regset[32].buf);
 870   mips_supply_register_32bit (regcache, use_64bit,
 871                               find_regno (regcache->tdesc, "fir"),
 872                               regset[32].buf + 4);
 873 }
 874 #endif /* HAVE_PTRACE_GETREGS */
 875
 876 /* Take care of 32-bit registers with 64-bit ptrace, POKEUSER side.  */
 877
 878 static void
 879 mips_collect_ptrace_register (struct regcache *regcache,
 880                               int regno, char *buf)
 881 {
 882   int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8;
 883
 884   if (use_64bit && register_size (regcache->tdesc, regno) == 4)
 885     {
 886       union mips_register reg;
 887
 888       mips_collect_register (regcache, 0, regno, &reg);
 889       memcpy (buf, &reg, sizeof (reg));
 890     }
 891   else
 892     collect_register (regcache, regno, buf);
 893 }
 894
 895 /* Take care of 32-bit registers with 64-bit ptrace, PEEKUSER side.  */
 896
 897 static void
 898 mips_supply_ptrace_register (struct regcache *regcache,
 899                              int regno, const char *buf)
 900 {
 901   int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8;
 902
 903   if (use_64bit && register_size (regcache->tdesc, regno) == 4)
 904     {
 905       union mips_register reg;
 906
 907       memcpy (&reg, buf, sizeof (reg));
 908       mips_supply_register (regcache, 0, regno, &reg);
 909     }
 910   else
 911     supply_register (regcache, regno, buf);
 912 }
 913
 914 static struct regset_info mips_regsets[] = {
 915 #ifdef HAVE_PTRACE_GETREGS
 916   { PTRACE_GETREGS, PTRACE_SETREGS, 0, 38 * 8, GENERAL_REGS,
 917     mips_fill_gregset, mips_store_gregset },
 918   { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, 33 * 8, FP_REGS,
 919     mips_fill_fpregset, mips_store_fpregset },
 920 #endif /* HAVE_PTRACE_GETREGS */
 921   NULL_REGSET
 922 };
 923
 924 static struct regsets_info mips_regsets_info =
 925   {
 926     mips_regsets, /* regsets */
 927     0, /* num_regsets */
 928     NULL, /* disabled_regsets */
 929   };
 930
 931 static struct usrregs_info mips_dsp_usrregs_info =
 932   {
 933     mips_dsp_num_regs,
 934     mips_dsp_regmap,
 935   };
 936
 937 static struct usrregs_info mips_usrregs_info =
 938   {
 939     mips_num_regs,
 940     mips_regmap,
 941   };
 942
 943 static struct regs_info dsp_regs_info =
 944   {
 945     mips_dsp_regset_bitmap,
 946     &mips_dsp_usrregs_info,
 947     &mips_regsets_info
 948   };
 949
 950 static struct regs_info myregs_info =
 951   {
 952     NULL, /* regset_bitmap */
 953     &mips_usrregs_info,
 954     &mips_regsets_info
 955   };
 956
 957 const regs_info *
 958 mips_target::get_regs_info ()
 959 {
 960   if (have_dsp)
 961     return &dsp_regs_info;
 962   else
 963     return &myregs_info;
 964 }
 965
 966 struct linux_target_ops the_low_target = {
 967   mips_sw_breakpoint_from_kind,
 968   NULL, /* get_next_pcs */
 969   0,
 970   mips_breakpoint_at,
 971   mips_supports_z_point_type,
 972   mips_insert_point,
 973   mips_remove_point,
 974   mips_stopped_by_watchpoint,
 975   mips_stopped_data_address,
 976   mips_collect_ptrace_register,
 977   mips_supply_ptrace_register,
 978   NULL, /* siginfo_fixup */
 979   mips_linux_new_process,
 980   mips_linux_delete_process,
 981   mips_linux_new_thread,
 982   mips_linux_delete_thread,
 983   mips_linux_new_fork,
 984   mips_linux_prepare_to_resume
 985 };
 986
 987 /* The linux target ops object.  */
 988
 989 linux_process_target *the_linux_target = &the_mips_target;
 990
 991 void
 992 initialize_low_arch (void)
 993 {
 994   /* Initialize the Linux target descriptions.  */
 995   init_registers_mips_linux ();
 996   init_registers_mips_dsp_linux ();
 997   init_registers_mips64_linux ();
 998   init_registers_mips64_dsp_linux ();
 999
1000   initialize_regsets_info (&mips_regsets_info);
1001 }