gdbserver/linux-mips-low.cc

   1 /* GNU/Linux/MIPS specific low level interface, for the remote server for GDB.
   2    Copyright (C) 1995-2020 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #include "server.h"
  20 #include "linux-low.h"
  21
  22 #include "nat/gdb_ptrace.h"
  23 #include <endian.h>
  24
  25 #include "nat/mips-linux-watch.h"
  26 #include "gdb_proc_service.h"
  27
  28 /* Linux target op definitions for the MIPS architecture.  */
  29
  30 class mips_target : public linux_process_target
  31 {
  32 public:
  33
  34   const regs_info *get_regs_info () override;
  35
  36   const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override;
  37
  38 protected:
  39
  40   void low_arch_setup () override;
  41
  42   bool low_cannot_fetch_register (int regno) override;
  43
  44   bool low_cannot_store_register (int regno) override;
  45
  46   bool low_fetch_register (regcache *regcache, int regno) override;
  47
  48   bool low_supports_breakpoints () override;
  49
  50   CORE_ADDR low_get_pc (regcache *regcache) override;
  51
  52   void low_set_pc (regcache *regcache, CORE_ADDR newpc) override;
  53 };
  54
  55 /* The singleton target ops object.  */
  56
  57 static mips_target the_mips_target;
  58
  59 /* Defined in auto-generated file mips-linux.c.  */
  60 void init_registers_mips_linux (void);
  61 extern const struct target_desc *tdesc_mips_linux;
  62
  63 /* Defined in auto-generated file mips-dsp-linux.c.  */
  64 void init_registers_mips_dsp_linux (void);
  65 extern const struct target_desc *tdesc_mips_dsp_linux;
  66
  67 /* Defined in auto-generated file mips64-linux.c.  */
  68 void init_registers_mips64_linux (void);
  69 extern const struct target_desc *tdesc_mips64_linux;
  70
  71 /* Defined in auto-generated file mips64-dsp-linux.c.  */
  72 void init_registers_mips64_dsp_linux (void);
  73 extern const struct target_desc *tdesc_mips64_dsp_linux;
  74
  75 #ifdef __mips64
  76 #define tdesc_mips_linux tdesc_mips64_linux
  77 #define tdesc_mips_dsp_linux tdesc_mips64_dsp_linux
  78 #endif
  79
  80 #ifndef PTRACE_GET_THREAD_AREA
  81 #define PTRACE_GET_THREAD_AREA 25
  82 #endif
  83
  84 #ifdef HAVE_SYS_REG_H
  85 #include <sys/reg.h>
  86 #endif
  87
  88 #define mips_num_regs 73
  89 #define mips_dsp_num_regs 80
  90
  91 #include <asm/ptrace.h>
  92
  93 #ifndef DSP_BASE
  94 #define DSP_BASE 71
  95 #define DSP_CONTROL 77
  96 #endif
  97
  98 union mips_register
  99 {
 100   unsigned char buf[8];
 101
 102   /* Deliberately signed, for proper sign extension.  */
 103   int reg32;
 104   long long reg64;
 105 };
 106
 107 /* Return the ptrace ``address'' of register REGNO. */
 108
 109 #define mips_base_regs                                                  \
 110   -1,  1,  2,  3,  4,  5,  6,  7,                                       \
 111   8,  9,  10, 11, 12, 13, 14, 15,                                       \
 112   16, 17, 18, 19, 20, 21, 22, 23,                                       \
 113   24, 25, 26, 27, 28, 29, 30, 31,                                       \
 114                                                                         \
 115   -1, MMLO, MMHI, BADVADDR, CAUSE, PC,                                  \
 116                                                                         \
 117   FPR_BASE,      FPR_BASE + 1,  FPR_BASE + 2,  FPR_BASE + 3,            \
 118   FPR_BASE + 4,  FPR_BASE + 5,  FPR_BASE + 6,  FPR_BASE + 7,            \
 119   FPR_BASE + 8,  FPR_BASE + 9,  FPR_BASE + 10, FPR_BASE + 11,           \
 120   FPR_BASE + 12, FPR_BASE + 13, FPR_BASE + 14, FPR_BASE + 15,           \
 121   FPR_BASE + 16, FPR_BASE + 17, FPR_BASE + 18, FPR_BASE + 19,           \
 122   FPR_BASE + 20, FPR_BASE + 21, FPR_BASE + 22, FPR_BASE + 23,           \
 123   FPR_BASE + 24, FPR_BASE + 25, FPR_BASE + 26, FPR_BASE + 27,           \
 124   FPR_BASE + 28, FPR_BASE + 29, FPR_BASE + 30, FPR_BASE + 31,           \
 125   FPC_CSR, FPC_EIR
 126
 127 #define mips_dsp_regs                                                   \
 128   DSP_BASE,      DSP_BASE + 1,  DSP_BASE + 2,  DSP_BASE + 3,            \
 129   DSP_BASE + 4,  DSP_BASE + 5,                                          \
 130   DSP_CONTROL
 131
 132 static int mips_regmap[mips_num_regs] = {
 133   mips_base_regs,
 134   0
 135 };
 136
 137 static int mips_dsp_regmap[mips_dsp_num_regs] = {
 138   mips_base_regs,
 139   mips_dsp_regs,
 140   0
 141 };
 142
 143 /* DSP registers are not in any regset and can only be accessed
 144    individually.  */
 145
 146 static unsigned char mips_dsp_regset_bitmap[(mips_dsp_num_regs + 7) / 8] = {
 147   0xfe, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x80
 148 };
 149
 150 static int have_dsp = -1;
 151
 152 /* Try peeking at an arbitrarily chosen DSP register and pick the available
 153    user register set accordingly.  */
 154
 155 static const struct target_desc *
 156 mips_read_description (void)
 157 {
 158   if (have_dsp < 0)
 159     {
 160       int pid = lwpid_of (current_thread);
 161
 162       errno = 0;
 163       ptrace (PTRACE_PEEKUSER, pid, DSP_CONTROL, 0);
 164       switch (errno)
 165         {
 166         case 0:
 167           have_dsp = 1;
 168           break;
 169         case EIO:
 170           have_dsp = 0;
 171           break;
 172         default:
 173           perror_with_name ("ptrace");
 174           break;
 175         }
 176     }
 177
 178   return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux;
 179 }
 180
 181 void
 182 mips_target::low_arch_setup ()
 183 {
 184   current_process ()->tdesc = mips_read_description ();
 185 }
 186
 187 /* Per-process arch-specific data we want to keep.  */
 188
 189 struct arch_process_info
 190 {
 191   /* -1 if the kernel and/or CPU do not support watch registers.
 192       1 if watch_readback is valid and we can read style, num_valid
 193         and the masks.
 194       0 if we need to read the watch_readback.  */
 195
 196   int watch_readback_valid;
 197
 198   /* Cached watch register read values.  */
 199
 200   struct pt_watch_regs watch_readback;
 201
 202   /* Current watchpoint requests for this process.  */
 203
 204   struct mips_watchpoint *current_watches;
 205
 206   /* The current set of watch register values for writing the
 207      registers.  */
 208
 209   struct pt_watch_regs watch_mirror;
 210 };
 211
 212 /* Per-thread arch-specific data we want to keep.  */
 213
 214 struct arch_lwp_info
 215 {
 216   /* Non-zero if our copy differs from what's recorded in the thread.  */
 217   int watch_registers_changed;
 218 };
 219
 220 /* From mips-linux-nat.c.  */
 221
 222 /* Pseudo registers can not be read.  ptrace does not provide a way to
 223    read (or set) PS_REGNUM, and there's no point in reading or setting
 224    ZERO_REGNUM, it's always 0.  We also can not set BADVADDR, CAUSE,
 225    or FCRIR via ptrace().  */
 226
 227 bool
 228 mips_target::low_cannot_fetch_register (int regno)
 229 {
 230   const struct target_desc *tdesc;
 231
 232   if (get_regs_info ()->usrregs->regmap[regno] == -1)
 233     return true;
 234
 235   tdesc = current_process ()->tdesc;
 236
 237   /* On n32 we can't access 64-bit registers via PTRACE_PEEKUSR.  */
 238   if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE))
 239     return true;
 240
 241   if (find_regno (tdesc, "r0") == regno)
 242     return true;
 243
 244   return false;
 245 }
 246
 247 bool
 248 mips_target::low_cannot_store_register (int regno)
 249 {
 250   const struct target_desc *tdesc;
 251
 252   if (get_regs_info ()->usrregs->regmap[regno] == -1)
 253     return true;
 254
 255   tdesc = current_process ()->tdesc;
 256
 257   /* On n32 we can't access 64-bit registers via PTRACE_POKEUSR.  */
 258   if (register_size (tdesc, regno) > sizeof (PTRACE_XFER_TYPE))
 259     return true;
 260
 261   if (find_regno (tdesc, "r0") == regno)
 262     return true;
 263
 264   if (find_regno (tdesc, "cause") == regno)
 265     return true;
 266
 267   if (find_regno (tdesc, "badvaddr") == regno)
 268     return true;
 269
 270   if (find_regno (tdesc, "fir") == regno)
 271     return true;
 272
 273   return false;
 274 }
 275
 276 bool
 277 mips_target::low_fetch_register (regcache *regcache, int regno)
 278 {
 279   const struct target_desc *tdesc = current_process ()->tdesc;
 280
 281   if (find_regno (tdesc, "r0") == regno)
 282     {
 283       supply_register_zeroed (regcache, regno);
 284       return true;
 285     }
 286
 287   return false;
 288 }
 289
 290 bool
 291 mips_target::low_supports_breakpoints ()
 292 {
 293   return true;
 294 }
 295
 296 CORE_ADDR
 297 mips_target::low_get_pc (regcache *regcache)
 298 {
 299   union mips_register pc;
 300   collect_register_by_name (regcache, "pc", pc.buf);
 301   return register_size (regcache->tdesc, 0) == 4 ? pc.reg32 : pc.reg64;
 302 }
 303
 304 void
 305 mips_target::low_set_pc (regcache *regcache, CORE_ADDR pc)
 306 {
 307   union mips_register newpc;
 308   if (register_size (regcache->tdesc, 0) == 4)
 309     newpc.reg32 = pc;
 310   else
 311     newpc.reg64 = pc;
 312
 313   supply_register_by_name (regcache, "pc", newpc.buf);
 314 }
 315
 316 /* Correct in either endianness.  */
 317 static const unsigned int mips_breakpoint = 0x0005000d;
 318 #define mips_breakpoint_len 4
 319
 320 /* Implementation of target ops method "sw_breakpoint_from_kind".  */
 321
 322 const gdb_byte *
 323 mips_target::sw_breakpoint_from_kind (int kind, int *size)
 324 {
 325   *size = mips_breakpoint_len;
 326   return (const gdb_byte *) &mips_breakpoint;
 327 }
 328
 329 static int
 330 mips_breakpoint_at (CORE_ADDR where)
 331 {
 332   unsigned int insn;
 333
 334   the_target->read_memory (where, (unsigned char *) &insn, 4);
 335   if (insn == mips_breakpoint)
 336     return 1;
 337
 338   /* If necessary, recognize more trap instructions here.  GDB only uses the
 339      one.  */
 340   return 0;
 341 }
 342
 343 /* Mark the watch registers of lwp, represented by ENTRY, as changed.  */
 344
 345 static void
 346 update_watch_registers_callback (thread_info *thread)
 347 {
 348   struct lwp_info *lwp = get_thread_lwp (thread);
 349
 350   /* The actual update is done later just before resuming the lwp,
 351      we just mark that the registers need updating.  */
 352   lwp->arch_private->watch_registers_changed = 1;
 353
 354   /* If the lwp isn't stopped, force it to momentarily pause, so
 355      we can update its watch registers.  */
 356   if (!lwp->stopped)
 357     linux_stop_lwp (lwp);
 358 }
 359
 360 /* This is the implementation of linux_target_ops method
 361    new_process.  */
 362
 363 static struct arch_process_info *
 364 mips_linux_new_process (void)
 365 {
 366   struct arch_process_info *info = XCNEW (struct arch_process_info);
 367
 368   return info;
 369 }
 370
 371 /* This is the implementation of linux_target_ops method
 372    delete_process.  */
 373
 374 static void
 375 mips_linux_delete_process (struct arch_process_info *info)
 376 {
 377   xfree (info);
 378 }
 379
 380 /* This is the implementation of linux_target_ops method new_thread.
 381    Mark the watch registers as changed, so the threads' copies will
 382    be updated.  */
 383
 384 static void
 385 mips_linux_new_thread (struct lwp_info *lwp)
 386 {
 387   struct arch_lwp_info *info = XCNEW (struct arch_lwp_info);
 388
 389   info->watch_registers_changed = 1;
 390
 391   lwp->arch_private = info;
 392 }
 393
 394 /* Function to call when a thread is being deleted.  */
 395
 396 static void
 397 mips_linux_delete_thread (struct arch_lwp_info *arch_lwp)
 398 {
 399   xfree (arch_lwp);
 400 }
 401
 402 /* Create a new mips_watchpoint and add it to the list.  */
 403
 404 static void
 405 mips_add_watchpoint (struct arch_process_info *priv, CORE_ADDR addr, int len,
 406                      enum target_hw_bp_type watch_type)
 407 {
 408   struct mips_watchpoint *new_watch;
 409   struct mips_watchpoint **pw;
 410
 411   new_watch = XNEW (struct mips_watchpoint);
 412   new_watch->addr = addr;
 413   new_watch->len = len;
 414   new_watch->type = watch_type;
 415   new_watch->next = NULL;
 416
 417   pw = &priv->current_watches;
 418   while (*pw != NULL)
 419     pw = &(*pw)->next;
 420   *pw = new_watch;
 421 }
 422
 423 /* Hook to call when a new fork is attached.  */
 424
 425 static void
 426 mips_linux_new_fork (struct process_info *parent,
 427                         struct process_info *child)
 428 {
 429   struct arch_process_info *parent_private;
 430   struct arch_process_info *child_private;
 431   struct mips_watchpoint *wp;
 432
 433   /* These are allocated by linux_add_process.  */
 434   gdb_assert (parent->priv != NULL
 435               && parent->priv->arch_private != NULL);
 436   gdb_assert (child->priv != NULL
 437               && child->priv->arch_private != NULL);
 438
 439   /* Linux kernel before 2.6.33 commit
 440      72f674d203cd230426437cdcf7dd6f681dad8b0d
 441      will inherit hardware debug registers from parent
 442      on fork/vfork/clone.  Newer Linux kernels create such tasks with
 443      zeroed debug registers.
 444
 445      GDB core assumes the child inherits the watchpoints/hw
 446      breakpoints of the parent, and will remove them all from the
 447      forked off process.  Copy the debug registers mirrors into the
 448      new process so that all breakpoints and watchpoints can be
 449      removed together.  The debug registers mirror will become zeroed
 450      in the end before detaching the forked off process, thus making
 451      this compatible with older Linux kernels too.  */
 452
 453   parent_private = parent->priv->arch_private;
 454   child_private = child->priv->arch_private;
 455
 456   child_private->watch_readback_valid = parent_private->watch_readback_valid;
 457   child_private->watch_readback = parent_private->watch_readback;
 458
 459   for (wp = parent_private->current_watches; wp != NULL; wp = wp->next)
 460     mips_add_watchpoint (child_private, wp->addr, wp->len, wp->type);
 461
 462   child_private->watch_mirror = parent_private->watch_mirror;
 463 }
 464 /* This is the implementation of linux_target_ops method
 465    prepare_to_resume.  If the watch regs have changed, update the
 466    thread's copies.  */
 467
 468 static void
 469 mips_linux_prepare_to_resume (struct lwp_info *lwp)
 470 {
 471   ptid_t ptid = ptid_of (get_lwp_thread (lwp));
 472   struct process_info *proc = find_process_pid (ptid.pid ());
 473   struct arch_process_info *priv = proc->priv->arch_private;
 474
 475   if (lwp->arch_private->watch_registers_changed)
 476     {
 477       /* Only update the watch registers if we have set or unset a
 478          watchpoint already.  */
 479       if (mips_linux_watch_get_num_valid (&priv->watch_mirror) > 0)
 480         {
 481           /* Write the mirrored watch register values.  */
 482           int tid = ptid.lwp ();
 483
 484           if (-1 == ptrace (PTRACE_SET_WATCH_REGS, tid,
 485                             &priv->watch_mirror, NULL))
 486             perror_with_name ("Couldn't write watch register");
 487         }
 488
 489       lwp->arch_private->watch_registers_changed = 0;
 490     }
 491 }
 492
 493 static int
 494 mips_supports_z_point_type (char z_type)
 495 {
 496   switch (z_type)
 497     {
 498     case Z_PACKET_WRITE_WP:
 499     case Z_PACKET_READ_WP:
 500     case Z_PACKET_ACCESS_WP:
 501       return 1;
 502     default:
 503       return 0;
 504     }
 505 }
 506
 507 /* This is the implementation of linux_target_ops method
 508    insert_point.  */
 509
 510 static int
 511 mips_insert_point (enum raw_bkpt_type type, CORE_ADDR addr,
 512                    int len, struct raw_breakpoint *bp)
 513 {
 514   struct process_info *proc = current_process ();
 515   struct arch_process_info *priv = proc->priv->arch_private;
 516   struct pt_watch_regs regs;
 517   long lwpid;
 518   enum target_hw_bp_type watch_type;
 519   uint32_t irw;
 520
 521   lwpid = lwpid_of (current_thread);
 522   if (!mips_linux_read_watch_registers (lwpid,
 523                                         &priv->watch_readback,
 524                                         &priv->watch_readback_valid,
 525                                         0))
 526     return -1;
 527
 528   if (len <= 0)
 529     return -1;
 530
 531   regs = priv->watch_readback;
 532   /* Add the current watches.  */
 533   mips_linux_watch_populate_regs (priv->current_watches, &regs);
 534
 535   /* Now try to add the new watch.  */
 536   watch_type = raw_bkpt_type_to_target_hw_bp_type (type);
 537   irw = mips_linux_watch_type_to_irw (watch_type);
 538   if (!mips_linux_watch_try_one_watch (&regs, addr, len, irw))
 539     return -1;
 540
 541   /* It fit.  Stick it on the end of the list.  */
 542   mips_add_watchpoint (priv, addr, len, watch_type);
 543
 544   priv->watch_mirror = regs;
 545
 546   /* Only update the threads of this process.  */
 547   for_each_thread (proc->pid, update_watch_registers_callback);
 548
 549   return 0;
 550 }
 551
 552 /* This is the implementation of linux_target_ops method
 553    remove_point.  */
 554
 555 static int
 556 mips_remove_point (enum raw_bkpt_type type, CORE_ADDR addr,
 557                    int len, struct raw_breakpoint *bp)
 558 {
 559   struct process_info *proc = current_process ();
 560   struct arch_process_info *priv = proc->priv->arch_private;
 561
 562   int deleted_one;
 563   enum target_hw_bp_type watch_type;
 564
 565   struct mips_watchpoint **pw;
 566   struct mips_watchpoint *w;
 567
 568   /* Search for a known watch that matches.  Then unlink and free it.  */
 569   watch_type = raw_bkpt_type_to_target_hw_bp_type (type);
 570   deleted_one = 0;
 571   pw = &priv->current_watches;
 572   while ((w = *pw))
 573     {
 574       if (w->addr == addr && w->len == len && w->type == watch_type)
 575         {
 576           *pw = w->next;
 577           free (w);
 578           deleted_one = 1;
 579           break;
 580         }
 581       pw = &(w->next);
 582     }
 583
 584   if (!deleted_one)
 585     return -1;  /* We don't know about it, fail doing nothing.  */
 586
 587   /* At this point watch_readback is known to be valid because we
 588      could not have added the watch without reading it.  */
 589   gdb_assert (priv->watch_readback_valid == 1);
 590
 591   priv->watch_mirror = priv->watch_readback;
 592   mips_linux_watch_populate_regs (priv->current_watches,
 593                                   &priv->watch_mirror);
 594
 595   /* Only update the threads of this process.  */
 596   for_each_thread (proc->pid, update_watch_registers_callback);
 597
 598   return 0;
 599 }
 600
 601 /* This is the implementation of linux_target_ops method
 602    stopped_by_watchpoint.  The watchhi R and W bits indicate
 603    the watch register triggered. */
 604
 605 static int
 606 mips_stopped_by_watchpoint (void)
 607 {
 608   struct process_info *proc = current_process ();
 609   struct arch_process_info *priv = proc->priv->arch_private;
 610   int n;
 611   int num_valid;
 612   long lwpid = lwpid_of (current_thread);
 613
 614   if (!mips_linux_read_watch_registers (lwpid,
 615                                         &priv->watch_readback,
 616                                         &priv->watch_readback_valid,
 617                                         1))
 618     return 0;
 619
 620   num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback);
 621
 622   for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
 623     if (mips_linux_watch_get_watchhi (&priv->watch_readback, n)
 624         & (R_MASK | W_MASK))
 625       return 1;
 626
 627   return 0;
 628 }
 629
 630 /* This is the implementation of linux_target_ops method
 631    stopped_data_address.  */
 632
 633 static CORE_ADDR
 634 mips_stopped_data_address (void)
 635 {
 636   struct process_info *proc = current_process ();
 637   struct arch_process_info *priv = proc->priv->arch_private;
 638   int n;
 639   int num_valid;
 640   long lwpid = lwpid_of (current_thread);
 641
 642   /* On MIPS we don't know the low order 3 bits of the data address.
 643      GDB does not support remote targets that can't report the
 644      watchpoint address.  So, make our best guess; return the starting
 645      address of a watchpoint request which overlaps the one that
 646      triggered.  */
 647
 648   if (!mips_linux_read_watch_registers (lwpid,
 649                                         &priv->watch_readback,
 650                                         &priv->watch_readback_valid,
 651                                         0))
 652     return 0;
 653
 654   num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback);
 655
 656   for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
 657     if (mips_linux_watch_get_watchhi (&priv->watch_readback, n)
 658         & (R_MASK | W_MASK))
 659       {
 660         CORE_ADDR t_low, t_hi;
 661         int t_irw;
 662         struct mips_watchpoint *watch;
 663
 664         t_low = mips_linux_watch_get_watchlo (&priv->watch_readback, n);
 665         t_irw = t_low & IRW_MASK;
 666         t_hi = (mips_linux_watch_get_watchhi (&priv->watch_readback, n)
 667                 | IRW_MASK);
 668         t_low &= ~(CORE_ADDR)t_hi;
 669
 670         for (watch = priv->current_watches;
 671              watch != NULL;
 672              watch = watch->next)
 673           {
 674             CORE_ADDR addr = watch->addr;
 675             CORE_ADDR last_byte = addr + watch->len - 1;
 676
 677             if ((t_irw & mips_linux_watch_type_to_irw (watch->type)) == 0)
 678               {
 679                 /* Different type.  */
 680                 continue;
 681               }
 682             /* Check for overlap of even a single byte.  */
 683             if (last_byte >= t_low && addr <= t_low + t_hi)
 684               return addr;
 685           }
 686       }
 687
 688   /* Shouldn't happen.  */
 689   return 0;
 690 }
 691
 692 /* Fetch the thread-local storage pointer for libthread_db.  */
 693
 694 ps_err_e
 695 ps_get_thread_area (struct ps_prochandle *ph,
 696                     lwpid_t lwpid, int idx, void **base)
 697 {
 698   if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
 699     return PS_ERR;
 700
 701   /* IDX is the bias from the thread pointer to the beginning of the
 702      thread descriptor.  It has to be subtracted due to implementation
 703      quirks in libthread_db.  */
 704   *base = (void *) ((char *)*base - idx);
 705
 706   return PS_OK;
 707 }
 708
 709 static void
 710 mips_collect_register (struct regcache *regcache,
 711                        int use_64bit, int regno, union mips_register *reg)
 712 {
 713   union mips_register tmp_reg;
 714
 715   if (use_64bit)
 716     {
 717       collect_register (regcache, regno, &tmp_reg.reg64);
 718       *reg = tmp_reg;
 719     }
 720   else
 721     {
 722       collect_register (regcache, regno, &tmp_reg.reg32);
 723       reg->reg64 = tmp_reg.reg32;
 724     }
 725 }
 726
 727 static void
 728 mips_supply_register (struct regcache *regcache,
 729                       int use_64bit, int regno, const union mips_register *reg)
 730 {
 731   int offset = 0;
 732
 733   /* For big-endian 32-bit targets, ignore the high four bytes of each
 734      eight-byte slot.  */
 735   if (__BYTE_ORDER == __BIG_ENDIAN && !use_64bit)
 736     offset = 4;
 737
 738   supply_register (regcache, regno, reg->buf + offset);
 739 }
 740
 741 #ifdef HAVE_PTRACE_GETREGS
 742
 743 static void
 744 mips_collect_register_32bit (struct regcache *regcache,
 745                              int use_64bit, int regno, unsigned char *buf)
 746 {
 747   union mips_register tmp_reg;
 748   int reg32;
 749
 750   mips_collect_register (regcache, use_64bit, regno, &tmp_reg);
 751   reg32 = tmp_reg.reg64;
 752   memcpy (buf, &reg32, 4);
 753 }
 754
 755 static void
 756 mips_supply_register_32bit (struct regcache *regcache,
 757                             int use_64bit, int regno, const unsigned char *buf)
 758 {
 759   union mips_register tmp_reg;
 760   int reg32;
 761
 762   memcpy (&reg32, buf, 4);
 763   tmp_reg.reg64 = reg32;
 764   mips_supply_register (regcache, use_64bit, regno, &tmp_reg);
 765 }
 766
 767 static void
 768 mips_fill_gregset (struct regcache *regcache, void *buf)
 769 {
 770   union mips_register *regset = (union mips_register *) buf;
 771   int i, use_64bit;
 772   const struct target_desc *tdesc = regcache->tdesc;
 773
 774   use_64bit = (register_size (tdesc, 0) == 8);
 775
 776   for (i = 1; i < 32; i++)
 777     mips_collect_register (regcache, use_64bit, i, regset + i);
 778
 779   mips_collect_register (regcache, use_64bit,
 780                          find_regno (tdesc, "lo"), regset + 32);
 781   mips_collect_register (regcache, use_64bit,
 782                          find_regno (tdesc, "hi"), regset + 33);
 783   mips_collect_register (regcache, use_64bit,
 784                          find_regno (tdesc, "pc"), regset + 34);
 785   mips_collect_register (regcache, use_64bit,
 786                          find_regno (tdesc, "badvaddr"), regset + 35);
 787   mips_collect_register (regcache, use_64bit,
 788                          find_regno (tdesc, "status"), regset + 36);
 789   mips_collect_register (regcache, use_64bit,
 790                          find_regno (tdesc, "cause"), regset + 37);
 791
 792   mips_collect_register (regcache, use_64bit,
 793                          find_regno (tdesc, "restart"), regset + 0);
 794 }
 795
 796 static void
 797 mips_store_gregset (struct regcache *regcache, const void *buf)
 798 {
 799   const union mips_register *regset = (const union mips_register *) buf;
 800   int i, use_64bit;
 801
 802   use_64bit = (register_size (regcache->tdesc, 0) == 8);
 803
 804   supply_register_by_name_zeroed (regcache, "r0");
 805
 806   for (i = 1; i < 32; i++)
 807     mips_supply_register (regcache, use_64bit, i, regset + i);
 808
 809   mips_supply_register (regcache, use_64bit,
 810                         find_regno (regcache->tdesc, "lo"), regset + 32);
 811   mips_supply_register (regcache, use_64bit,
 812                         find_regno (regcache->tdesc, "hi"), regset + 33);
 813   mips_supply_register (regcache, use_64bit,
 814                         find_regno (regcache->tdesc, "pc"), regset + 34);
 815   mips_supply_register (regcache, use_64bit,
 816                         find_regno (regcache->tdesc, "badvaddr"), regset + 35);
 817   mips_supply_register (regcache, use_64bit,
 818                         find_regno (regcache->tdesc, "status"), regset + 36);
 819   mips_supply_register (regcache, use_64bit,
 820                         find_regno (regcache->tdesc, "cause"), regset + 37);
 821
 822   mips_supply_register (regcache, use_64bit,
 823                         find_regno (regcache->tdesc, "restart"), regset + 0);
 824 }
 825
 826 static void
 827 mips_fill_fpregset (struct regcache *regcache, void *buf)
 828 {
 829   union mips_register *regset = (union mips_register *) buf;
 830   int i, use_64bit, first_fp, big_endian;
 831
 832   use_64bit = (register_size (regcache->tdesc, 0) == 8);
 833   first_fp = find_regno (regcache->tdesc, "f0");
 834   big_endian = (__BYTE_ORDER == __BIG_ENDIAN);
 835
 836   /* See GDB for a discussion of this peculiar layout.  */
 837   for (i = 0; i < 32; i++)
 838     if (use_64bit)
 839       collect_register (regcache, first_fp + i, regset[i].buf);
 840     else
 841       collect_register (regcache, first_fp + i,
 842                         regset[i & ~1].buf + 4 * (big_endian != (i & 1)));
 843
 844   mips_collect_register_32bit (regcache, use_64bit,
 845                                find_regno (regcache->tdesc, "fcsr"), regset[32].buf);
 846   mips_collect_register_32bit (regcache, use_64bit,
 847                                find_regno (regcache->tdesc, "fir"),
 848                                regset[32].buf + 4);
 849 }
 850
 851 static void
 852 mips_store_fpregset (struct regcache *regcache, const void *buf)
 853 {
 854   const union mips_register *regset = (const union mips_register *) buf;
 855   int i, use_64bit, first_fp, big_endian;
 856
 857   use_64bit = (register_size (regcache->tdesc, 0) == 8);
 858   first_fp = find_regno (regcache->tdesc, "f0");
 859   big_endian = (__BYTE_ORDER == __BIG_ENDIAN);
 860
 861   /* See GDB for a discussion of this peculiar layout.  */
 862   for (i = 0; i < 32; i++)
 863     if (use_64bit)
 864       supply_register (regcache, first_fp + i, regset[i].buf);
 865     else
 866       supply_register (regcache, first_fp + i,
 867                        regset[i & ~1].buf + 4 * (big_endian != (i & 1)));
 868
 869   mips_supply_register_32bit (regcache, use_64bit,
 870                               find_regno (regcache->tdesc, "fcsr"),
 871                               regset[32].buf);
 872   mips_supply_register_32bit (regcache, use_64bit,
 873                               find_regno (regcache->tdesc, "fir"),
 874                               regset[32].buf + 4);
 875 }
 876 #endif /* HAVE_PTRACE_GETREGS */
 877
 878 /* Take care of 32-bit registers with 64-bit ptrace, POKEUSER side.  */
 879
 880 static void
 881 mips_collect_ptrace_register (struct regcache *regcache,
 882                               int regno, char *buf)
 883 {
 884   int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8;
 885
 886   if (use_64bit && register_size (regcache->tdesc, regno) == 4)
 887     {
 888       union mips_register reg;
 889
 890       mips_collect_register (regcache, 0, regno, &reg);
 891       memcpy (buf, &reg, sizeof (reg));
 892     }
 893   else
 894     collect_register (regcache, regno, buf);
 895 }
 896
 897 /* Take care of 32-bit registers with 64-bit ptrace, PEEKUSER side.  */
 898
 899 static void
 900 mips_supply_ptrace_register (struct regcache *regcache,
 901                              int regno, const char *buf)
 902 {
 903   int use_64bit = sizeof (PTRACE_XFER_TYPE) == 8;
 904
 905   if (use_64bit && register_size (regcache->tdesc, regno) == 4)
 906     {
 907       union mips_register reg;
 908
 909       memcpy (&reg, buf, sizeof (reg));
 910       mips_supply_register (regcache, 0, regno, &reg);
 911     }
 912   else
 913     supply_register (regcache, regno, buf);
 914 }
 915
 916 static struct regset_info mips_regsets[] = {
 917 #ifdef HAVE_PTRACE_GETREGS
 918   { PTRACE_GETREGS, PTRACE_SETREGS, 0, 38 * 8, GENERAL_REGS,
 919     mips_fill_gregset, mips_store_gregset },
 920   { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, 33 * 8, FP_REGS,
 921     mips_fill_fpregset, mips_store_fpregset },
 922 #endif /* HAVE_PTRACE_GETREGS */
 923   NULL_REGSET
 924 };
 925
 926 static struct regsets_info mips_regsets_info =
 927   {
 928     mips_regsets, /* regsets */
 929     0, /* num_regsets */
 930     NULL, /* disabled_regsets */
 931   };
 932
 933 static struct usrregs_info mips_dsp_usrregs_info =
 934   {
 935     mips_dsp_num_regs,
 936     mips_dsp_regmap,
 937   };
 938
 939 static struct usrregs_info mips_usrregs_info =
 940   {
 941     mips_num_regs,
 942     mips_regmap,
 943   };
 944
 945 static struct regs_info dsp_regs_info =
 946   {
 947     mips_dsp_regset_bitmap,
 948     &mips_dsp_usrregs_info,
 949     &mips_regsets_info
 950   };
 951
 952 static struct regs_info myregs_info =
 953   {
 954     NULL, /* regset_bitmap */
 955     &mips_usrregs_info,
 956     &mips_regsets_info
 957   };
 958
 959 const regs_info *
 960 mips_target::get_regs_info ()
 961 {
 962   if (have_dsp)
 963     return &dsp_regs_info;
 964   else
 965     return &myregs_info;
 966 }
 967
 968 struct linux_target_ops the_low_target = {
 969   NULL, /* get_next_pcs */
 970   0,
 971   mips_breakpoint_at,
 972   mips_supports_z_point_type,
 973   mips_insert_point,
 974   mips_remove_point,
 975   mips_stopped_by_watchpoint,
 976   mips_stopped_data_address,
 977   mips_collect_ptrace_register,
 978   mips_supply_ptrace_register,
 979   NULL, /* siginfo_fixup */
 980   mips_linux_new_process,
 981   mips_linux_delete_process,
 982   mips_linux_new_thread,
 983   mips_linux_delete_thread,
 984   mips_linux_new_fork,
 985   mips_linux_prepare_to_resume
 986 };
 987
 988 /* The linux target ops object.  */
 989
 990 linux_process_target *the_linux_target = &the_mips_target;
 991
 992 void
 993 initialize_low_arch (void)
 994 {
 995   /* Initialize the Linux target descriptions.  */
 996   init_registers_mips_linux ();
 997   init_registers_mips_dsp_linux ();
 998   init_registers_mips64_linux ();
 999   init_registers_mips64_dsp_linux ();
1000
1001   initialize_regsets_info (&mips_regsets_info);
1002 }