1 /* GNU/Linux/PowerPC specific low level interface, for the remote server for
3 Copyright (C) 1995-2020 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "linux-low.h"
23 #include "elf/common.h"
26 #include <asm/ptrace.h>
28 #include "arch/ppc-linux-common.h"
29 #include "arch/ppc-linux-tdesc.h"
30 #include "nat/ppc-linux.h"
31 #include "nat/linux-ptrace.h"
32 #include "linux-ppc-tdesc-init.h"
34 #include "tracepoint.h"
36 #define PPC_FIELD(value, from, len) \
37 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
38 #define PPC_SEXT(v, bs) \
39 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
40 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
41 - ((CORE_ADDR) 1 << ((bs) - 1)))
42 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
43 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
44 #define PPC_LI(insn) (PPC_SEXT (PPC_FIELD (insn, 6, 24), 24) << 2)
45 #define PPC_BD(insn) (PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) << 2)
47 /* Linux target op definitions for the PowerPC architecture. */
49 class ppc_target
: public linux_process_target
53 const regs_info
*get_regs_info () override
;
55 const gdb_byte
*sw_breakpoint_from_kind (int kind
, int *size
) override
;
57 bool supports_z_point_type (char z_type
) override
;
60 void low_collect_ptrace_register (regcache
*regcache
, int regno
,
63 void low_supply_ptrace_register (regcache
*regcache
, int regno
,
64 const char *buf
) override
;
66 bool supports_tracepoints () override
;
68 bool supports_fast_tracepoints () override
;
70 int install_fast_tracepoint_jump_pad
71 (CORE_ADDR tpoint
, CORE_ADDR tpaddr
, CORE_ADDR collector
,
72 CORE_ADDR lockaddr
, ULONGEST orig_size
, CORE_ADDR
*jump_entry
,
73 CORE_ADDR
*trampoline
, ULONGEST
*trampoline_size
,
74 unsigned char *jjump_pad_insn
, ULONGEST
*jjump_pad_insn_size
,
75 CORE_ADDR
*adjusted_insn_addr
, CORE_ADDR
*adjusted_insn_addr_end
,
78 int get_min_fast_tracepoint_insn_len () override
;
80 struct emit_ops
*emit_ops () override
;
84 void low_arch_setup () override
;
86 bool low_cannot_fetch_register (int regno
) override
;
88 bool low_cannot_store_register (int regno
) override
;
90 bool low_supports_breakpoints () override
;
92 CORE_ADDR
low_get_pc (regcache
*regcache
) override
;
94 void low_set_pc (regcache
*regcache
, CORE_ADDR newpc
) override
;
96 bool low_breakpoint_at (CORE_ADDR pc
) override
;
98 int low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
99 int size
, raw_breakpoint
*bp
) override
;
101 int low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
102 int size
, raw_breakpoint
*bp
) override
;
104 int low_get_thread_area (int lwpid
, CORE_ADDR
*addrp
) override
;
107 /* The singleton target ops object. */
109 static ppc_target the_ppc_target
;
111 /* Holds the AT_HWCAP auxv entry. */
113 static unsigned long ppc_hwcap
;
115 /* Holds the AT_HWCAP2 auxv entry. */
117 static unsigned long ppc_hwcap2
;
120 #define ppc_num_regs 73
123 /* We use a constant for FPSCR instead of PT_FPSCR, because
124 many shipped PPC64 kernels had the wrong value in ptrace.h. */
125 static int ppc_regmap
[] =
126 {PT_R0
* 8, PT_R1
* 8, PT_R2
* 8, PT_R3
* 8,
127 PT_R4
* 8, PT_R5
* 8, PT_R6
* 8, PT_R7
* 8,
128 PT_R8
* 8, PT_R9
* 8, PT_R10
* 8, PT_R11
* 8,
129 PT_R12
* 8, PT_R13
* 8, PT_R14
* 8, PT_R15
* 8,
130 PT_R16
* 8, PT_R17
* 8, PT_R18
* 8, PT_R19
* 8,
131 PT_R20
* 8, PT_R21
* 8, PT_R22
* 8, PT_R23
* 8,
132 PT_R24
* 8, PT_R25
* 8, PT_R26
* 8, PT_R27
* 8,
133 PT_R28
* 8, PT_R29
* 8, PT_R30
* 8, PT_R31
* 8,
134 PT_FPR0
*8, PT_FPR0
*8 + 8, PT_FPR0
*8+16, PT_FPR0
*8+24,
135 PT_FPR0
*8+32, PT_FPR0
*8+40, PT_FPR0
*8+48, PT_FPR0
*8+56,
136 PT_FPR0
*8+64, PT_FPR0
*8+72, PT_FPR0
*8+80, PT_FPR0
*8+88,
137 PT_FPR0
*8+96, PT_FPR0
*8+104, PT_FPR0
*8+112, PT_FPR0
*8+120,
138 PT_FPR0
*8+128, PT_FPR0
*8+136, PT_FPR0
*8+144, PT_FPR0
*8+152,
139 PT_FPR0
*8+160, PT_FPR0
*8+168, PT_FPR0
*8+176, PT_FPR0
*8+184,
140 PT_FPR0
*8+192, PT_FPR0
*8+200, PT_FPR0
*8+208, PT_FPR0
*8+216,
141 PT_FPR0
*8+224, PT_FPR0
*8+232, PT_FPR0
*8+240, PT_FPR0
*8+248,
142 PT_NIP
* 8, PT_MSR
* 8, PT_CCR
* 8, PT_LNK
* 8,
143 PT_CTR
* 8, PT_XER
* 8, PT_FPR0
*8 + 256,
144 PT_ORIG_R3
* 8, PT_TRAP
* 8 };
146 /* Currently, don't check/send MQ. */
147 static int ppc_regmap
[] =
148 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
149 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
150 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
151 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
152 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
153 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
154 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
155 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
156 PT_FPR0
*4, PT_FPR0
*4 + 8, PT_FPR0
*4+16, PT_FPR0
*4+24,
157 PT_FPR0
*4+32, PT_FPR0
*4+40, PT_FPR0
*4+48, PT_FPR0
*4+56,
158 PT_FPR0
*4+64, PT_FPR0
*4+72, PT_FPR0
*4+80, PT_FPR0
*4+88,
159 PT_FPR0
*4+96, PT_FPR0
*4+104, PT_FPR0
*4+112, PT_FPR0
*4+120,
160 PT_FPR0
*4+128, PT_FPR0
*4+136, PT_FPR0
*4+144, PT_FPR0
*4+152,
161 PT_FPR0
*4+160, PT_FPR0
*4+168, PT_FPR0
*4+176, PT_FPR0
*4+184,
162 PT_FPR0
*4+192, PT_FPR0
*4+200, PT_FPR0
*4+208, PT_FPR0
*4+216,
163 PT_FPR0
*4+224, PT_FPR0
*4+232, PT_FPR0
*4+240, PT_FPR0
*4+248,
164 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
165 PT_CTR
* 4, PT_XER
* 4, PT_FPSCR
* 4,
166 PT_ORIG_R3
* 4, PT_TRAP
* 4
169 static int ppc_regmap_e500
[] =
170 {PT_R0
* 4, PT_R1
* 4, PT_R2
* 4, PT_R3
* 4,
171 PT_R4
* 4, PT_R5
* 4, PT_R6
* 4, PT_R7
* 4,
172 PT_R8
* 4, PT_R9
* 4, PT_R10
* 4, PT_R11
* 4,
173 PT_R12
* 4, PT_R13
* 4, PT_R14
* 4, PT_R15
* 4,
174 PT_R16
* 4, PT_R17
* 4, PT_R18
* 4, PT_R19
* 4,
175 PT_R20
* 4, PT_R21
* 4, PT_R22
* 4, PT_R23
* 4,
176 PT_R24
* 4, PT_R25
* 4, PT_R26
* 4, PT_R27
* 4,
177 PT_R28
* 4, PT_R29
* 4, PT_R30
* 4, PT_R31
* 4,
186 PT_NIP
* 4, PT_MSR
* 4, PT_CCR
* 4, PT_LNK
* 4,
187 PT_CTR
* 4, PT_XER
* 4, -1,
188 PT_ORIG_R3
* 4, PT_TRAP
* 4
192 /* Check whether the kernel provides a register set with number
193 REGSET_ID of size REGSETSIZE for process/thread TID. */
196 ppc_check_regset (int tid
, int regset_id
, int regsetsize
)
198 void *buf
= alloca (regsetsize
);
202 iov
.iov_len
= regsetsize
;
204 if (ptrace (PTRACE_GETREGSET
, tid
, regset_id
, &iov
) >= 0
211 ppc_target::low_cannot_store_register (int regno
)
213 const struct target_desc
*tdesc
= current_process ()->tdesc
;
215 #ifndef __powerpc64__
216 /* Some kernels do not allow us to store fpscr. */
217 if (!(ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
218 && regno
== find_regno (tdesc
, "fpscr"))
222 /* Some kernels do not allow us to store orig_r3 or trap. */
223 if (regno
== find_regno (tdesc
, "orig_r3")
224 || regno
== find_regno (tdesc
, "trap"))
231 ppc_target::low_cannot_fetch_register (int regno
)
237 ppc_target::low_collect_ptrace_register (regcache
*regcache
, int regno
,
240 memset (buf
, 0, sizeof (long));
242 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
244 /* Little-endian values always sit at the left end of the buffer. */
245 collect_register (regcache
, regno
, buf
);
247 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
249 /* Big-endian values sit at the right end of the buffer. In case of
250 registers whose sizes are smaller than sizeof (long), we must use a
251 padding to access them correctly. */
252 int size
= register_size (regcache
->tdesc
, regno
);
254 if (size
< sizeof (long))
255 collect_register (regcache
, regno
, buf
+ sizeof (long) - size
);
257 collect_register (regcache
, regno
, buf
);
260 perror_with_name ("Unexpected byte order");
264 ppc_target::low_supply_ptrace_register (regcache
*regcache
, int regno
,
267 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
269 /* Little-endian values always sit at the left end of the buffer. */
270 supply_register (regcache
, regno
, buf
);
272 else if (__BYTE_ORDER
== __BIG_ENDIAN
)
274 /* Big-endian values sit at the right end of the buffer. In case of
275 registers whose sizes are smaller than sizeof (long), we must use a
276 padding to access them correctly. */
277 int size
= register_size (regcache
->tdesc
, regno
);
279 if (size
< sizeof (long))
280 supply_register (regcache
, regno
, buf
+ sizeof (long) - size
);
282 supply_register (regcache
, regno
, buf
);
285 perror_with_name ("Unexpected byte order");
289 ppc_target::low_supports_breakpoints ()
295 ppc_target::low_get_pc (regcache
*regcache
)
297 if (register_size (regcache
->tdesc
, 0) == 4)
300 collect_register_by_name (regcache
, "pc", &pc
);
301 return (CORE_ADDR
) pc
;
306 collect_register_by_name (regcache
, "pc", &pc
);
307 return (CORE_ADDR
) pc
;
312 ppc_target::low_set_pc (regcache
*regcache
, CORE_ADDR pc
)
314 if (register_size (regcache
->tdesc
, 0) == 4)
316 unsigned int newpc
= pc
;
317 supply_register_by_name (regcache
, "pc", &newpc
);
321 unsigned long newpc
= pc
;
322 supply_register_by_name (regcache
, "pc", &newpc
);
326 #ifndef __powerpc64__
327 static int ppc_regmap_adjusted
;
331 /* Correct in either endianness.
332 This instruction is "twge r2, r2", which GDB uses as a software
334 static const unsigned int ppc_breakpoint
= 0x7d821008;
335 #define ppc_breakpoint_len 4
337 /* Implementation of target ops method "sw_breakpoint_from_kind". */
340 ppc_target::sw_breakpoint_from_kind (int kind
, int *size
)
342 *size
= ppc_breakpoint_len
;
343 return (const gdb_byte
*) &ppc_breakpoint
;
347 ppc_target::low_breakpoint_at (CORE_ADDR where
)
351 read_memory (where
, (unsigned char *) &insn
, 4);
352 if (insn
== ppc_breakpoint
)
354 /* If necessary, recognize more trap instructions here. GDB only uses
360 /* Implement supports_z_point_type target-ops.
361 Returns true if type Z_TYPE breakpoint is supported.
363 Handling software breakpoint at server side, so tracepoints
364 and breakpoints can be inserted at the same location. */
367 ppc_target::supports_z_point_type (char z_type
)
374 case Z_PACKET_WRITE_WP
:
375 case Z_PACKET_ACCESS_WP
:
381 /* Implement the low_insert_point linux target op.
382 Returns 0 on success, -1 on failure and 1 on unsupported. */
385 ppc_target::low_insert_point (raw_bkpt_type type
, CORE_ADDR addr
,
386 int size
, raw_breakpoint
*bp
)
390 case raw_bkpt_type_sw
:
391 return insert_memory_breakpoint (bp
);
393 case raw_bkpt_type_hw
:
394 case raw_bkpt_type_write_wp
:
395 case raw_bkpt_type_access_wp
:
402 /* Implement the low_remove_point linux target op.
403 Returns 0 on success, -1 on failure and 1 on unsupported. */
406 ppc_target::low_remove_point (raw_bkpt_type type
, CORE_ADDR addr
,
407 int size
, raw_breakpoint
*bp
)
411 case raw_bkpt_type_sw
:
412 return remove_memory_breakpoint (bp
);
414 case raw_bkpt_type_hw
:
415 case raw_bkpt_type_write_wp
:
416 case raw_bkpt_type_access_wp
:
423 /* Provide only a fill function for the general register set. ps_lgetregs
424 will use this for NPTL support. */
426 static void ppc_fill_gregset (struct regcache
*regcache
, void *buf
)
430 ppc_target
*my_ppc_target
= (ppc_target
*) the_linux_target
;
432 for (i
= 0; i
< 32; i
++)
433 my_ppc_target
->low_collect_ptrace_register (regcache
, i
,
434 (char *) buf
+ ppc_regmap
[i
]);
436 for (i
= 64; i
< 70; i
++)
437 my_ppc_target
->low_collect_ptrace_register (regcache
, i
,
438 (char *) buf
+ ppc_regmap
[i
]);
440 for (i
= 71; i
< 73; i
++)
441 my_ppc_target
->low_collect_ptrace_register (regcache
, i
,
442 (char *) buf
+ ppc_regmap
[i
]);
445 /* Program Priority Register regset fill function. */
448 ppc_fill_pprregset (struct regcache
*regcache
, void *buf
)
450 char *ppr
= (char *) buf
;
452 collect_register_by_name (regcache
, "ppr", ppr
);
455 /* Program Priority Register regset store function. */
458 ppc_store_pprregset (struct regcache
*regcache
, const void *buf
)
460 const char *ppr
= (const char *) buf
;
462 supply_register_by_name (regcache
, "ppr", ppr
);
465 /* Data Stream Control Register regset fill function. */
468 ppc_fill_dscrregset (struct regcache
*regcache
, void *buf
)
470 char *dscr
= (char *) buf
;
472 collect_register_by_name (regcache
, "dscr", dscr
);
475 /* Data Stream Control Register regset store function. */
478 ppc_store_dscrregset (struct regcache
*regcache
, const void *buf
)
480 const char *dscr
= (const char *) buf
;
482 supply_register_by_name (regcache
, "dscr", dscr
);
485 /* Target Address Register regset fill function. */
488 ppc_fill_tarregset (struct regcache
*regcache
, void *buf
)
490 char *tar
= (char *) buf
;
492 collect_register_by_name (regcache
, "tar", tar
);
495 /* Target Address Register regset store function. */
498 ppc_store_tarregset (struct regcache
*regcache
, const void *buf
)
500 const char *tar
= (const char *) buf
;
502 supply_register_by_name (regcache
, "tar", tar
);
505 /* Event-Based Branching regset store function. Unless the inferior
506 has a perf event open, ptrace can return in error when reading and
507 writing to the regset, with ENODATA. For reading, the registers
508 will correctly show as unavailable. For writing, gdbserver
509 currently only caches any register writes from P and G packets and
510 the stub always tries to write all the regsets when resuming the
511 inferior, which would result in frequent warnings. For this
512 reason, we don't define a fill function. This also means that the
513 client-side regcache will be dirty if the user tries to write to
514 the EBB registers. G packets that the client sends to write to
515 unrelated registers will also include data for EBB registers, even
516 if they are unavailable. */
519 ppc_store_ebbregset (struct regcache
*regcache
, const void *buf
)
521 const char *regset
= (const char *) buf
;
523 /* The order in the kernel regset is: EBBRR, EBBHR, BESCR. In the
524 .dat file is BESCR, EBBHR, EBBRR. */
525 supply_register_by_name (regcache
, "ebbrr", ®set
[0]);
526 supply_register_by_name (regcache
, "ebbhr", ®set
[8]);
527 supply_register_by_name (regcache
, "bescr", ®set
[16]);
530 /* Performance Monitoring Unit regset fill function. */
533 ppc_fill_pmuregset (struct regcache
*regcache
, void *buf
)
535 char *regset
= (char *) buf
;
537 /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0.
538 In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */
539 collect_register_by_name (regcache
, "siar", ®set
[0]);
540 collect_register_by_name (regcache
, "sdar", ®set
[8]);
541 collect_register_by_name (regcache
, "sier", ®set
[16]);
542 collect_register_by_name (regcache
, "mmcr2", ®set
[24]);
543 collect_register_by_name (regcache
, "mmcr0", ®set
[32]);
546 /* Performance Monitoring Unit regset store function. */
549 ppc_store_pmuregset (struct regcache
*regcache
, const void *buf
)
551 const char *regset
= (const char *) buf
;
553 supply_register_by_name (regcache
, "siar", ®set
[0]);
554 supply_register_by_name (regcache
, "sdar", ®set
[8]);
555 supply_register_by_name (regcache
, "sier", ®set
[16]);
556 supply_register_by_name (regcache
, "mmcr2", ®set
[24]);
557 supply_register_by_name (regcache
, "mmcr0", ®set
[32]);
560 /* Hardware Transactional Memory special-purpose register regset fill
564 ppc_fill_tm_sprregset (struct regcache
*regcache
, void *buf
)
567 char *regset
= (char *) buf
;
569 base
= find_regno (regcache
->tdesc
, "tfhar");
570 for (i
= 0; i
< 3; i
++)
571 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
574 /* Hardware Transactional Memory special-purpose register regset store
578 ppc_store_tm_sprregset (struct regcache
*regcache
, const void *buf
)
581 const char *regset
= (const char *) buf
;
583 base
= find_regno (regcache
->tdesc
, "tfhar");
584 for (i
= 0; i
< 3; i
++)
585 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
588 /* For the same reasons as the EBB regset, none of the HTM
589 checkpointed regsets have a fill function. These registers are
590 only available if the inferior is in a transaction. */
592 /* Hardware Transactional Memory checkpointed general-purpose regset
596 ppc_store_tm_cgprregset (struct regcache
*regcache
, const void *buf
)
598 int i
, base
, size
, endian_offset
;
599 const char *regset
= (const char *) buf
;
601 base
= find_regno (regcache
->tdesc
, "cr0");
602 size
= register_size (regcache
->tdesc
, base
);
604 gdb_assert (size
== 4 || size
== 8);
606 for (i
= 0; i
< 32; i
++)
607 supply_register (regcache
, base
+ i
, ®set
[i
* size
]);
611 if ((size
== 8) && (__BYTE_ORDER
== __BIG_ENDIAN
))
614 supply_register_by_name (regcache
, "ccr",
615 ®set
[PT_CCR
* size
+ endian_offset
]);
617 supply_register_by_name (regcache
, "cxer",
618 ®set
[PT_XER
* size
+ endian_offset
]);
620 supply_register_by_name (regcache
, "clr", ®set
[PT_LNK
* size
]);
621 supply_register_by_name (regcache
, "cctr", ®set
[PT_CTR
* size
]);
624 /* Hardware Transactional Memory checkpointed floating-point regset
628 ppc_store_tm_cfprregset (struct regcache
*regcache
, const void *buf
)
631 const char *regset
= (const char *) buf
;
633 base
= find_regno (regcache
->tdesc
, "cf0");
635 for (i
= 0; i
< 32; i
++)
636 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
638 supply_register_by_name (regcache
, "cfpscr", ®set
[32 * 8]);
641 /* Hardware Transactional Memory checkpointed vector regset store
645 ppc_store_tm_cvrregset (struct regcache
*regcache
, const void *buf
)
648 const char *regset
= (const char *) buf
;
651 base
= find_regno (regcache
->tdesc
, "cvr0");
653 for (i
= 0; i
< 32; i
++)
654 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
656 if (__BYTE_ORDER
== __BIG_ENDIAN
)
659 supply_register_by_name (regcache
, "cvscr",
660 ®set
[32 * 16 + vscr_offset
]);
662 supply_register_by_name (regcache
, "cvrsave", ®set
[33 * 16]);
665 /* Hardware Transactional Memory checkpointed vector-scalar regset
669 ppc_store_tm_cvsxregset (struct regcache
*regcache
, const void *buf
)
672 const char *regset
= (const char *) buf
;
674 base
= find_regno (regcache
->tdesc
, "cvs0h");
675 for (i
= 0; i
< 32; i
++)
676 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
679 /* Hardware Transactional Memory checkpointed Program Priority
680 Register regset store function. */
683 ppc_store_tm_cpprregset (struct regcache
*regcache
, const void *buf
)
685 const char *cppr
= (const char *) buf
;
687 supply_register_by_name (regcache
, "cppr", cppr
);
690 /* Hardware Transactional Memory checkpointed Data Stream Control
691 Register regset store function. */
694 ppc_store_tm_cdscrregset (struct regcache
*regcache
, const void *buf
)
696 const char *cdscr
= (const char *) buf
;
698 supply_register_by_name (regcache
, "cdscr", cdscr
);
701 /* Hardware Transactional Memory checkpointed Target Address Register
702 regset store function. */
705 ppc_store_tm_ctarregset (struct regcache
*regcache
, const void *buf
)
707 const char *ctar
= (const char *) buf
;
709 supply_register_by_name (regcache
, "ctar", ctar
);
713 ppc_fill_vsxregset (struct regcache
*regcache
, void *buf
)
716 char *regset
= (char *) buf
;
718 base
= find_regno (regcache
->tdesc
, "vs0h");
719 for (i
= 0; i
< 32; i
++)
720 collect_register (regcache
, base
+ i
, ®set
[i
* 8]);
724 ppc_store_vsxregset (struct regcache
*regcache
, const void *buf
)
727 const char *regset
= (const char *) buf
;
729 base
= find_regno (regcache
->tdesc
, "vs0h");
730 for (i
= 0; i
< 32; i
++)
731 supply_register (regcache
, base
+ i
, ®set
[i
* 8]);
735 ppc_fill_vrregset (struct regcache
*regcache
, void *buf
)
738 char *regset
= (char *) buf
;
741 base
= find_regno (regcache
->tdesc
, "vr0");
742 for (i
= 0; i
< 32; i
++)
743 collect_register (regcache
, base
+ i
, ®set
[i
* 16]);
745 if (__BYTE_ORDER
== __BIG_ENDIAN
)
748 collect_register_by_name (regcache
, "vscr",
749 ®set
[32 * 16 + vscr_offset
]);
751 collect_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
755 ppc_store_vrregset (struct regcache
*regcache
, const void *buf
)
758 const char *regset
= (const char *) buf
;
761 base
= find_regno (regcache
->tdesc
, "vr0");
762 for (i
= 0; i
< 32; i
++)
763 supply_register (regcache
, base
+ i
, ®set
[i
* 16]);
765 if (__BYTE_ORDER
== __BIG_ENDIAN
)
768 supply_register_by_name (regcache
, "vscr",
769 ®set
[32 * 16 + vscr_offset
]);
770 supply_register_by_name (regcache
, "vrsave", ®set
[33 * 16]);
773 struct gdb_evrregset_t
775 unsigned long evr
[32];
776 unsigned long long acc
;
777 unsigned long spefscr
;
781 ppc_fill_evrregset (struct regcache
*regcache
, void *buf
)
784 struct gdb_evrregset_t
*regset
= (struct gdb_evrregset_t
*) buf
;
786 ev0
= find_regno (regcache
->tdesc
, "ev0h");
787 for (i
= 0; i
< 32; i
++)
788 collect_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
790 collect_register_by_name (regcache
, "acc", ®set
->acc
);
791 collect_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
795 ppc_store_evrregset (struct regcache
*regcache
, const void *buf
)
798 const struct gdb_evrregset_t
*regset
= (const struct gdb_evrregset_t
*) buf
;
800 ev0
= find_regno (regcache
->tdesc
, "ev0h");
801 for (i
= 0; i
< 32; i
++)
802 supply_register (regcache
, ev0
+ i
, ®set
->evr
[i
]);
804 supply_register_by_name (regcache
, "acc", ®set
->acc
);
805 supply_register_by_name (regcache
, "spefscr", ®set
->spefscr
);
808 static struct regset_info ppc_regsets
[] = {
809 /* List the extra register sets before GENERAL_REGS. That way we will
810 fetch them every time, but still fall back to PTRACE_PEEKUSER for the
811 general registers. Some kernels support these, but not the newer
812 PPC_PTRACE_GETREGS. */
813 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CTAR
, 0, EXTENDED_REGS
,
814 NULL
, ppc_store_tm_ctarregset
},
815 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CDSCR
, 0, EXTENDED_REGS
,
816 NULL
, ppc_store_tm_cdscrregset
},
817 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CPPR
, 0, EXTENDED_REGS
,
818 NULL
, ppc_store_tm_cpprregset
},
819 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CVSX
, 0, EXTENDED_REGS
,
820 NULL
, ppc_store_tm_cvsxregset
},
821 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CVMX
, 0, EXTENDED_REGS
,
822 NULL
, ppc_store_tm_cvrregset
},
823 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CFPR
, 0, EXTENDED_REGS
,
824 NULL
, ppc_store_tm_cfprregset
},
825 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_CGPR
, 0, EXTENDED_REGS
,
826 NULL
, ppc_store_tm_cgprregset
},
827 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TM_SPR
, 0, EXTENDED_REGS
,
828 ppc_fill_tm_sprregset
, ppc_store_tm_sprregset
},
829 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_EBB
, 0, EXTENDED_REGS
,
830 NULL
, ppc_store_ebbregset
},
831 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PMU
, 0, EXTENDED_REGS
,
832 ppc_fill_pmuregset
, ppc_store_pmuregset
},
833 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_TAR
, 0, EXTENDED_REGS
,
834 ppc_fill_tarregset
, ppc_store_tarregset
},
835 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_PPR
, 0, EXTENDED_REGS
,
836 ppc_fill_pprregset
, ppc_store_pprregset
},
837 { PTRACE_GETREGSET
, PTRACE_SETREGSET
, NT_PPC_DSCR
, 0, EXTENDED_REGS
,
838 ppc_fill_dscrregset
, ppc_store_dscrregset
},
839 { PTRACE_GETVSXREGS
, PTRACE_SETVSXREGS
, 0, 0, EXTENDED_REGS
,
840 ppc_fill_vsxregset
, ppc_store_vsxregset
},
841 { PTRACE_GETVRREGS
, PTRACE_SETVRREGS
, 0, 0, EXTENDED_REGS
,
842 ppc_fill_vrregset
, ppc_store_vrregset
},
843 { PTRACE_GETEVRREGS
, PTRACE_SETEVRREGS
, 0, 0, EXTENDED_REGS
,
844 ppc_fill_evrregset
, ppc_store_evrregset
},
845 { 0, 0, 0, 0, GENERAL_REGS
, ppc_fill_gregset
, NULL
},
849 static struct usrregs_info ppc_usrregs_info
=
855 static struct regsets_info ppc_regsets_info
=
857 ppc_regsets
, /* regsets */
859 NULL
, /* disabled_regsets */
862 static struct regs_info myregs_info
=
864 NULL
, /* regset_bitmap */
870 ppc_target::get_regs_info ()
876 ppc_target::low_arch_setup ()
878 const struct target_desc
*tdesc
;
879 struct regset_info
*regset
;
880 struct ppc_linux_features features
= ppc_linux_no_features
;
882 int tid
= lwpid_of (current_thread
);
884 features
.wordsize
= ppc_linux_target_wordsize (tid
);
886 if (features
.wordsize
== 4)
887 tdesc
= tdesc_powerpc_32l
;
889 tdesc
= tdesc_powerpc_64l
;
891 current_process ()->tdesc
= tdesc
;
893 /* The value of current_process ()->tdesc needs to be set for this
895 ppc_hwcap
= linux_get_hwcap (features
.wordsize
);
896 ppc_hwcap2
= linux_get_hwcap2 (features
.wordsize
);
898 features
.isa205
= ppc_linux_has_isa205 (ppc_hwcap
);
900 if (ppc_hwcap
& PPC_FEATURE_HAS_VSX
)
903 if (ppc_hwcap
& PPC_FEATURE_HAS_ALTIVEC
)
904 features
.altivec
= true;
906 if ((ppc_hwcap2
& PPC_FEATURE2_DSCR
)
907 && ppc_check_regset (tid
, NT_PPC_DSCR
, PPC_LINUX_SIZEOF_DSCRREGSET
)
908 && ppc_check_regset (tid
, NT_PPC_PPR
, PPC_LINUX_SIZEOF_PPRREGSET
))
910 features
.ppr_dscr
= true;
911 if ((ppc_hwcap2
& PPC_FEATURE2_ARCH_2_07
)
912 && (ppc_hwcap2
& PPC_FEATURE2_TAR
)
913 && (ppc_hwcap2
& PPC_FEATURE2_EBB
)
914 && ppc_check_regset (tid
, NT_PPC_TAR
,
915 PPC_LINUX_SIZEOF_TARREGSET
)
916 && ppc_check_regset (tid
, NT_PPC_EBB
,
917 PPC_LINUX_SIZEOF_EBBREGSET
)
918 && ppc_check_regset (tid
, NT_PPC_PMU
,
919 PPC_LINUX_SIZEOF_PMUREGSET
))
921 features
.isa207
= true;
922 if ((ppc_hwcap2
& PPC_FEATURE2_HTM
)
923 && ppc_check_regset (tid
, NT_PPC_TM_SPR
,
924 PPC_LINUX_SIZEOF_TM_SPRREGSET
))
929 tdesc
= ppc_linux_match_description (features
);
931 /* On 32-bit machines, check for SPE registers.
932 Set the low target's regmap field as appropriately. */
933 #ifndef __powerpc64__
934 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
935 tdesc
= tdesc_powerpc_e500l
;
937 if (!ppc_regmap_adjusted
)
939 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
940 ppc_usrregs_info
.regmap
= ppc_regmap_e500
;
942 /* If the FPSCR is 64-bit wide, we need to fetch the whole
943 64-bit slot and not just its second word. The PT_FPSCR
944 supplied in a 32-bit GDB compilation doesn't reflect
946 if (register_size (tdesc
, 70) == 8)
947 ppc_regmap
[70] = (48 + 2*32) * sizeof (long);
949 ppc_regmap_adjusted
= 1;
953 current_process ()->tdesc
= tdesc
;
955 for (regset
= ppc_regsets
; regset
->size
>= 0; regset
++)
956 switch (regset
->get_request
)
958 case PTRACE_GETVRREGS
:
959 regset
->size
= features
.altivec
? PPC_LINUX_SIZEOF_VRREGSET
: 0;
961 case PTRACE_GETVSXREGS
:
962 regset
->size
= features
.vsx
? PPC_LINUX_SIZEOF_VSXREGSET
: 0;
964 case PTRACE_GETEVRREGS
:
965 if (ppc_hwcap
& PPC_FEATURE_HAS_SPE
)
966 regset
->size
= 32 * 4 + 8 + 4;
970 case PTRACE_GETREGSET
:
971 switch (regset
->nt_type
)
974 regset
->size
= (features
.ppr_dscr
?
975 PPC_LINUX_SIZEOF_PPRREGSET
: 0);
978 regset
->size
= (features
.ppr_dscr
?
979 PPC_LINUX_SIZEOF_DSCRREGSET
: 0);
982 regset
->size
= (features
.isa207
?
983 PPC_LINUX_SIZEOF_TARREGSET
: 0);
986 regset
->size
= (features
.isa207
?
987 PPC_LINUX_SIZEOF_EBBREGSET
: 0);
990 regset
->size
= (features
.isa207
?
991 PPC_LINUX_SIZEOF_PMUREGSET
: 0);
994 regset
->size
= (features
.htm
?
995 PPC_LINUX_SIZEOF_TM_SPRREGSET
: 0);
998 if (features
.wordsize
== 4)
999 regset
->size
= (features
.htm
?
1000 PPC32_LINUX_SIZEOF_CGPRREGSET
: 0);
1002 regset
->size
= (features
.htm
?
1003 PPC64_LINUX_SIZEOF_CGPRREGSET
: 0);
1005 case NT_PPC_TM_CFPR
:
1006 regset
->size
= (features
.htm
?
1007 PPC_LINUX_SIZEOF_CFPRREGSET
: 0);
1009 case NT_PPC_TM_CVMX
:
1010 regset
->size
= (features
.htm
?
1011 PPC_LINUX_SIZEOF_CVMXREGSET
: 0);
1013 case NT_PPC_TM_CVSX
:
1014 regset
->size
= (features
.htm
?
1015 PPC_LINUX_SIZEOF_CVSXREGSET
: 0);
1017 case NT_PPC_TM_CPPR
:
1018 regset
->size
= (features
.htm
?
1019 PPC_LINUX_SIZEOF_CPPRREGSET
: 0);
1021 case NT_PPC_TM_CDSCR
:
1022 regset
->size
= (features
.htm
?
1023 PPC_LINUX_SIZEOF_CDSCRREGSET
: 0);
1025 case NT_PPC_TM_CTAR
:
1026 regset
->size
= (features
.htm
?
1027 PPC_LINUX_SIZEOF_CTARREGSET
: 0);
1038 /* Implementation of target ops method "supports_tracepoints". */
1041 ppc_target::supports_tracepoints ()
1046 /* Get the thread area address. This is used to recognize which
1047 thread is which when tracing with the in-process agent library. We
1048 don't read anything from the address, and treat it as opaque; it's
1049 the address itself that we assume is unique per-thread. */
1052 ppc_target::low_get_thread_area (int lwpid
, CORE_ADDR
*addr
)
1054 struct lwp_info
*lwp
= find_lwp_pid (ptid_t (lwpid
));
1055 struct thread_info
*thr
= get_lwp_thread (lwp
);
1056 struct regcache
*regcache
= get_thread_regcache (thr
, 1);
1059 #ifdef __powerpc64__
1060 if (register_size (regcache
->tdesc
, 0) == 8)
1061 collect_register_by_name (regcache
, "r13", &tp
);
1064 collect_register_by_name (regcache
, "r2", &tp
);
1071 #ifdef __powerpc64__
1073 /* Older glibc doesn't provide this. */
1075 #ifndef EF_PPC64_ABI
1076 #define EF_PPC64_ABI 3
1079 /* Returns 1 if inferior is using ELFv2 ABI. Undefined for 32-bit
1083 is_elfv2_inferior (void)
1085 /* To be used as fallback if we're unable to determine the right result -
1086 assume inferior uses the same ABI as gdbserver. */
1088 const int def_res
= 1;
1090 const int def_res
= 0;
1095 const struct target_desc
*tdesc
= current_process ()->tdesc
;
1096 int wordsize
= register_size (tdesc
, 0);
1098 if (!linux_get_auxv (wordsize
, AT_PHDR
, &phdr
))
1101 /* Assume ELF header is at the beginning of the page where program headers
1102 are located. If it doesn't look like one, bail. */
1104 read_inferior_memory (phdr
& ~0xfff, (unsigned char *) &ehdr
, sizeof ehdr
);
1105 if (memcmp(ehdr
.e_ident
, ELFMAG
, SELFMAG
))
1108 return (ehdr
.e_flags
& EF_PPC64_ABI
) == 2;
1113 /* Generate a ds-form instruction in BUF and return the number of bytes written
1116 | OPCD | RST | RA | DS |XO| */
1118 __attribute__((unused
)) /* Maybe unused due to conditional compilation. */
1120 gen_ds_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int ds
, int xo
)
1124 gdb_assert ((opcd
& ~0x3f) == 0);
1125 gdb_assert ((rst
& ~0x1f) == 0);
1126 gdb_assert ((ra
& ~0x1f) == 0);
1127 gdb_assert ((xo
& ~0x3) == 0);
1129 insn
= (rst
<< 21) | (ra
<< 16) | (ds
& 0xfffc) | (xo
& 0x3);
1130 *buf
= (opcd
<< 26) | insn
;
1134 /* Followings are frequently used ds-form instructions. */
1136 #define GEN_STD(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 0)
1137 #define GEN_STDU(buf, rs, ra, offset) gen_ds_form (buf, 62, rs, ra, offset, 1)
1138 #define GEN_LD(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 0)
1139 #define GEN_LDU(buf, rt, ra, offset) gen_ds_form (buf, 58, rt, ra, offset, 1)
1141 /* Generate a d-form instruction in BUF.
1144 | OPCD | RST | RA | D | */
1147 gen_d_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int si
)
1151 gdb_assert ((opcd
& ~0x3f) == 0);
1152 gdb_assert ((rst
& ~0x1f) == 0);
1153 gdb_assert ((ra
& ~0x1f) == 0);
1155 insn
= (rst
<< 21) | (ra
<< 16) | (si
& 0xffff);
1156 *buf
= (opcd
<< 26) | insn
;
1160 /* Followings are frequently used d-form instructions. */
1162 #define GEN_ADDI(buf, rt, ra, si) gen_d_form (buf, 14, rt, ra, si)
1163 #define GEN_ADDIS(buf, rt, ra, si) gen_d_form (buf, 15, rt, ra, si)
1164 #define GEN_LI(buf, rt, si) GEN_ADDI (buf, rt, 0, si)
1165 #define GEN_LIS(buf, rt, si) GEN_ADDIS (buf, rt, 0, si)
1166 #define GEN_ORI(buf, rt, ra, si) gen_d_form (buf, 24, rt, ra, si)
1167 #define GEN_ORIS(buf, rt, ra, si) gen_d_form (buf, 25, rt, ra, si)
1168 #define GEN_LWZ(buf, rt, ra, si) gen_d_form (buf, 32, rt, ra, si)
1169 #define GEN_STW(buf, rt, ra, si) gen_d_form (buf, 36, rt, ra, si)
1170 #define GEN_STWU(buf, rt, ra, si) gen_d_form (buf, 37, rt, ra, si)
1172 /* Generate a xfx-form instruction in BUF and return the number of bytes
1176 | OPCD | RST | RI | XO |/| */
1179 gen_xfx_form (uint32_t *buf
, int opcd
, int rst
, int ri
, int xo
)
1182 unsigned int n
= ((ri
& 0x1f) << 5) | ((ri
>> 5) & 0x1f);
1184 gdb_assert ((opcd
& ~0x3f) == 0);
1185 gdb_assert ((rst
& ~0x1f) == 0);
1186 gdb_assert ((xo
& ~0x3ff) == 0);
1188 insn
= (rst
<< 21) | (n
<< 11) | (xo
<< 1);
1189 *buf
= (opcd
<< 26) | insn
;
1193 /* Followings are frequently used xfx-form instructions. */
1195 #define GEN_MFSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 339)
1196 #define GEN_MTSPR(buf, rt, spr) gen_xfx_form (buf, 31, rt, spr, 467)
1197 #define GEN_MFCR(buf, rt) gen_xfx_form (buf, 31, rt, 0, 19)
1198 #define GEN_MTCR(buf, rt) gen_xfx_form (buf, 31, rt, 0x3cf, 144)
1199 #define GEN_SYNC(buf, L, E) gen_xfx_form (buf, 31, L & 0x3, \
1201 #define GEN_LWSYNC(buf) GEN_SYNC (buf, 1, 0)
1204 /* Generate a x-form instruction in BUF and return the number of bytes written.
1207 | OPCD | RST | RA | RB | XO |RC| */
1210 gen_x_form (uint32_t *buf
, int opcd
, int rst
, int ra
, int rb
, int xo
, int rc
)
1214 gdb_assert ((opcd
& ~0x3f) == 0);
1215 gdb_assert ((rst
& ~0x1f) == 0);
1216 gdb_assert ((ra
& ~0x1f) == 0);
1217 gdb_assert ((rb
& ~0x1f) == 0);
1218 gdb_assert ((xo
& ~0x3ff) == 0);
1219 gdb_assert ((rc
& ~1) == 0);
1221 insn
= (rst
<< 21) | (ra
<< 16) | (rb
<< 11) | (xo
<< 1) | rc
;
1222 *buf
= (opcd
<< 26) | insn
;
1226 /* Followings are frequently used x-form instructions. */
1228 #define GEN_OR(buf, ra, rs, rb) gen_x_form (buf, 31, rs, ra, rb, 444, 0)
1229 #define GEN_MR(buf, ra, rs) GEN_OR (buf, ra, rs, rs)
1230 #define GEN_LWARX(buf, rt, ra, rb) gen_x_form (buf, 31, rt, ra, rb, 20, 0)
1231 #define GEN_STWCX(buf, rs, ra, rb) gen_x_form (buf, 31, rs, ra, rb, 150, 1)
1232 /* Assume bf = cr7. */
1233 #define GEN_CMPW(buf, ra, rb) gen_x_form (buf, 31, 28, ra, rb, 0, 0)
1236 /* Generate a md-form instruction in BUF and return the number of bytes written.
1238 0 6 11 16 21 27 30 31 32
1239 | OPCD | RS | RA | sh | mb | XO |sh|Rc| */
1242 gen_md_form (uint32_t *buf
, int opcd
, int rs
, int ra
, int sh
, int mb
,
1246 unsigned int n
= ((mb
& 0x1f) << 1) | ((mb
>> 5) & 0x1);
1247 unsigned int sh0_4
= sh
& 0x1f;
1248 unsigned int sh5
= (sh
>> 5) & 1;
1250 gdb_assert ((opcd
& ~0x3f) == 0);
1251 gdb_assert ((rs
& ~0x1f) == 0);
1252 gdb_assert ((ra
& ~0x1f) == 0);
1253 gdb_assert ((sh
& ~0x3f) == 0);
1254 gdb_assert ((mb
& ~0x3f) == 0);
1255 gdb_assert ((xo
& ~0x7) == 0);
1256 gdb_assert ((rc
& ~0x1) == 0);
1258 insn
= (rs
<< 21) | (ra
<< 16) | (sh0_4
<< 11) | (n
<< 5)
1259 | (sh5
<< 1) | (xo
<< 2) | (rc
& 1);
1260 *buf
= (opcd
<< 26) | insn
;
1264 /* The following are frequently used md-form instructions. */
1266 #define GEN_RLDICL(buf, ra, rs ,sh, mb) \
1267 gen_md_form (buf, 30, rs, ra, sh, mb, 0, 0)
1268 #define GEN_RLDICR(buf, ra, rs ,sh, mb) \
1269 gen_md_form (buf, 30, rs, ra, sh, mb, 1, 0)
1271 /* Generate a i-form instruction in BUF and return the number of bytes written.
1274 | OPCD | LI |AA|LK| */
1277 gen_i_form (uint32_t *buf
, int opcd
, int li
, int aa
, int lk
)
1281 gdb_assert ((opcd
& ~0x3f) == 0);
1283 insn
= (li
& 0x3fffffc) | (aa
& 1) | (lk
& 1);
1284 *buf
= (opcd
<< 26) | insn
;
1288 /* The following are frequently used i-form instructions. */
1290 #define GEN_B(buf, li) gen_i_form (buf, 18, li, 0, 0)
1291 #define GEN_BL(buf, li) gen_i_form (buf, 18, li, 0, 1)
1293 /* Generate a b-form instruction in BUF and return the number of bytes written.
1296 | OPCD | BO | BI | BD |AA|LK| */
1299 gen_b_form (uint32_t *buf
, int opcd
, int bo
, int bi
, int bd
,
1304 gdb_assert ((opcd
& ~0x3f) == 0);
1305 gdb_assert ((bo
& ~0x1f) == 0);
1306 gdb_assert ((bi
& ~0x1f) == 0);
1308 insn
= (bo
<< 21) | (bi
<< 16) | (bd
& 0xfffc) | (aa
& 1) | (lk
& 1);
1309 *buf
= (opcd
<< 26) | insn
;
1313 /* The following are frequently used b-form instructions. */
1314 /* Assume bi = cr7. */
1315 #define GEN_BNE(buf, bd) gen_b_form (buf, 16, 0x4, (7 << 2) | 2, bd, 0 ,0)
1317 /* GEN_LOAD and GEN_STORE generate 64- or 32-bit load/store for ppc64 or ppc32
1318 respectively. They are primary used for save/restore GPRs in jump-pad,
1319 not used for bytecode compiling. */
1321 #ifdef __powerpc64__
1322 #define GEN_LOAD(buf, rt, ra, si, is_64) (is_64 ? \
1323 GEN_LD (buf, rt, ra, si) : \
1324 GEN_LWZ (buf, rt, ra, si))
1325 #define GEN_STORE(buf, rt, ra, si, is_64) (is_64 ? \
1326 GEN_STD (buf, rt, ra, si) : \
1327 GEN_STW (buf, rt, ra, si))
1329 #define GEN_LOAD(buf, rt, ra, si, is_64) GEN_LWZ (buf, rt, ra, si)
1330 #define GEN_STORE(buf, rt, ra, si, is_64) GEN_STW (buf, rt, ra, si)
1333 /* Generate a sequence of instructions to load IMM in the register REG.
1334 Write the instructions in BUF and return the number of bytes written. */
1337 gen_limm (uint32_t *buf
, int reg
, uint64_t imm
, int is_64
)
1341 if ((imm
+ 32768) < 65536)
1343 /* li reg, imm[15:0] */
1344 p
+= GEN_LI (p
, reg
, imm
);
1346 else if ((imm
>> 32) == 0)
1348 /* lis reg, imm[31:16]
1349 ori reg, reg, imm[15:0]
1350 rldicl reg, reg, 0, 32 */
1351 p
+= GEN_LIS (p
, reg
, (imm
>> 16) & 0xffff);
1352 if ((imm
& 0xffff) != 0)
1353 p
+= GEN_ORI (p
, reg
, reg
, imm
& 0xffff);
1354 /* Clear upper 32-bit if sign-bit is set. */
1355 if (imm
& (1u << 31) && is_64
)
1356 p
+= GEN_RLDICL (p
, reg
, reg
, 0, 32);
1361 /* lis reg, <imm[63:48]>
1362 ori reg, reg, <imm[48:32]>
1363 rldicr reg, reg, 32, 31
1364 oris reg, reg, <imm[31:16]>
1365 ori reg, reg, <imm[15:0]> */
1366 p
+= GEN_LIS (p
, reg
, ((imm
>> 48) & 0xffff));
1367 if (((imm
>> 32) & 0xffff) != 0)
1368 p
+= GEN_ORI (p
, reg
, reg
, ((imm
>> 32) & 0xffff));
1369 p
+= GEN_RLDICR (p
, reg
, reg
, 32, 31);
1370 if (((imm
>> 16) & 0xffff) != 0)
1371 p
+= GEN_ORIS (p
, reg
, reg
, ((imm
>> 16) & 0xffff));
1372 if ((imm
& 0xffff) != 0)
1373 p
+= GEN_ORI (p
, reg
, reg
, (imm
& 0xffff));
1379 /* Generate a sequence for atomically exchange at location LOCK.
1380 This code sequence clobbers r6, r7, r8. LOCK is the location for
1381 the atomic-xchg, OLD_VALUE is expected old value stored in the
1382 location, and R_NEW is a register for the new value. */
1385 gen_atomic_xchg (uint32_t *buf
, CORE_ADDR lock
, int old_value
, int r_new
,
1388 const int r_lock
= 6;
1389 const int r_old
= 7;
1390 const int r_tmp
= 8;
1394 1: lwarx TMP, 0, LOCK
1400 p
+= gen_limm (p
, r_lock
, lock
, is_64
);
1401 p
+= gen_limm (p
, r_old
, old_value
, is_64
);
1403 p
+= GEN_LWARX (p
, r_tmp
, 0, r_lock
);
1404 p
+= GEN_CMPW (p
, r_tmp
, r_old
);
1405 p
+= GEN_BNE (p
, -8);
1406 p
+= GEN_STWCX (p
, r_new
, 0, r_lock
);
1407 p
+= GEN_BNE (p
, -16);
1412 /* Generate a sequence of instructions for calling a function
1413 at address of FN. Return the number of bytes are written in BUF. */
1416 gen_call (uint32_t *buf
, CORE_ADDR fn
, int is_64
, int is_opd
)
1420 /* Must be called by r12 for caller to calculate TOC address. */
1421 p
+= gen_limm (p
, 12, fn
, is_64
);
1424 p
+= GEN_LOAD (p
, 11, 12, 16, is_64
);
1425 p
+= GEN_LOAD (p
, 2, 12, 8, is_64
);
1426 p
+= GEN_LOAD (p
, 12, 12, 0, is_64
);
1428 p
+= GEN_MTSPR (p
, 12, 9); /* mtctr r12 */
1429 *p
++ = 0x4e800421; /* bctrl */
1434 /* Copy the instruction from OLDLOC to *TO, and update *TO to *TO + size
1435 of instruction. This function is used to adjust pc-relative instructions
1439 ppc_relocate_instruction (CORE_ADDR
*to
, CORE_ADDR oldloc
)
1444 read_inferior_memory (oldloc
, (unsigned char *) &insn
, 4);
1445 op6
= PPC_OP6 (insn
);
1447 if (op6
== 18 && (insn
& 2) == 0)
1449 /* branch && AA = 0 */
1450 rel
= PPC_LI (insn
);
1451 newrel
= (oldloc
- *to
) + rel
;
1453 /* Out of range. Cannot relocate instruction. */
1454 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1457 insn
= (insn
& ~0x3fffffc) | (newrel
& 0x3fffffc);
1459 else if (op6
== 16 && (insn
& 2) == 0)
1461 /* conditional branch && AA = 0 */
1463 /* If the new relocation is too big for even a 26-bit unconditional
1464 branch, there is nothing we can do. Just abort.
1466 Otherwise, if it can be fit in 16-bit conditional branch, just
1467 copy the instruction and relocate the address.
1469 If the it's big for conditional-branch (16-bit), try to invert the
1470 condition and jump with 26-bit branch. For example,
1481 After this transform, we are actually jump from *TO+4 instead of *TO,
1482 so check the relocation again because it will be 1-insn farther then
1483 before if *TO is after OLDLOC.
1486 For BDNZT (or so) is transformed from
1498 See also "BO field encodings". */
1500 rel
= PPC_BD (insn
);
1501 newrel
= (oldloc
- *to
) + rel
;
1503 if (newrel
< (1 << 15) && newrel
>= -(1 << 15))
1504 insn
= (insn
& ~0xfffc) | (newrel
& 0xfffc);
1505 else if ((PPC_BO (insn
) & 0x14) == 0x4 || (PPC_BO (insn
) & 0x14) == 0x10)
1509 /* Out of range. Cannot relocate instruction. */
1510 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1513 if ((PPC_BO (insn
) & 0x14) == 0x4)
1515 else if ((PPC_BO (insn
) & 0x14) == 0x10)
1518 /* Jump over the unconditional branch. */
1519 insn
= (insn
& ~0xfffc) | 0x8;
1520 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1523 /* Build a unconditional branch and copy LK bit. */
1524 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1525 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1530 else if ((PPC_BO (insn
) & 0x14) == 0)
1532 uint32_t bdnz_insn
= (16 << 26) | (0x10 << 21) | 12;
1533 uint32_t bf_insn
= (16 << 26) | (0x4 << 21) | 8;
1537 /* Out of range. Cannot relocate instruction. */
1538 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1541 /* Copy BI field. */
1542 bf_insn
|= (insn
& 0x1f0000);
1544 /* Invert condition. */
1545 bdnz_insn
|= (insn
^ (1 << 22)) & (1 << 22);
1546 bf_insn
|= (insn
^ (1 << 24)) & (1 << 24);
1548 target_write_memory (*to
, (unsigned char *) &bdnz_insn
, 4);
1550 target_write_memory (*to
, (unsigned char *) &bf_insn
, 4);
1553 /* Build a unconditional branch and copy LK bit. */
1554 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1555 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1560 else /* (BO & 0x14) == 0x14, branch always. */
1562 /* Out of range. Cannot relocate instruction. */
1563 if (newrel
>= (1 << 25) || newrel
< -(1 << 25))
1566 /* Build a unconditional branch and copy LK bit. */
1567 insn
= (18 << 26) | (0x3fffffc & newrel
) | (insn
& 0x3);
1568 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1575 target_write_memory (*to
, (unsigned char *) &insn
, 4);
1580 ppc_target::supports_fast_tracepoints ()
1585 /* Implement install_fast_tracepoint_jump_pad of target_ops.
1586 See target.h for details. */
1589 ppc_target::install_fast_tracepoint_jump_pad (CORE_ADDR tpoint
,
1591 CORE_ADDR collector
,
1594 CORE_ADDR
*jump_entry
,
1595 CORE_ADDR
*trampoline
,
1596 ULONGEST
*trampoline_size
,
1597 unsigned char *jjump_pad_insn
,
1598 ULONGEST
*jjump_pad_insn_size
,
1599 CORE_ADDR
*adjusted_insn_addr
,
1600 CORE_ADDR
*adjusted_insn_addr_end
,
1606 CORE_ADDR buildaddr
= *jump_entry
;
1607 const CORE_ADDR entryaddr
= *jump_entry
;
1608 int rsz
, min_frame
, frame_size
, tp_reg
;
1609 #ifdef __powerpc64__
1610 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
1611 int is_64
= register_size (regcache
->tdesc
, 0) == 8;
1612 int is_opd
= is_64
&& !is_elfv2_inferior ();
1614 int is_64
= 0, is_opd
= 0;
1617 #ifdef __powerpc64__
1620 /* Minimum frame size is 32 bytes for ELFv2, and 112 bytes for ELFv1. */
1623 frame_size
= (40 * rsz
) + min_frame
;
1631 frame_size
= (40 * rsz
) + min_frame
;
1633 #ifdef __powerpc64__
1637 /* Stack frame layout for this jump pad,
1639 High thread_area (r13/r2) |
1640 tpoint - collecting_t obj
1650 R0 - collected registers
1656 The code flow of this jump pad,
1661 4. Call gdb_collector
1662 5. Restore GPR and SPR
1664 7. Build a jump for back to the program
1665 8. Copy/relocate original instruction
1666 9. Build a jump for replacing original instruction. */
1668 /* Adjust stack pointer. */
1670 p
+= GEN_STDU (p
, 1, 1, -frame_size
); /* stdu r1,-frame_size(r1) */
1672 p
+= GEN_STWU (p
, 1, 1, -frame_size
); /* stwu r1,-frame_size(r1) */
1674 /* Store GPRs. Save R1 later, because it had just been modified, but
1675 we want the original value. */
1676 for (j
= 2; j
< 32; j
++)
1677 p
+= GEN_STORE (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1678 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1679 /* Set r0 to the original value of r1 before adjusting stack frame,
1680 and then save it. */
1681 p
+= GEN_ADDI (p
, 0, 1, frame_size
);
1682 p
+= GEN_STORE (p
, 0, 1, min_frame
+ 1 * rsz
, is_64
);
1684 /* Save CR, XER, LR, and CTR. */
1685 p
+= GEN_MFCR (p
, 3); /* mfcr r3 */
1686 p
+= GEN_MFSPR (p
, 4, 1); /* mfxer r4 */
1687 p
+= GEN_MFSPR (p
, 5, 8); /* mflr r5 */
1688 p
+= GEN_MFSPR (p
, 6, 9); /* mfctr r6 */
1689 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
);/* std r3, 32(r1) */
1690 p
+= GEN_STORE (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
);/* std r4, 33(r1) */
1691 p
+= GEN_STORE (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
);/* std r5, 34(r1) */
1692 p
+= GEN_STORE (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
);/* std r6, 35(r1) */
1694 /* Save PC<tpaddr> */
1695 p
+= gen_limm (p
, 3, tpaddr
, is_64
);
1696 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 36 * rsz
, is_64
);
1699 /* Setup arguments to collector. */
1700 /* Set r4 to collected registers. */
1701 p
+= GEN_ADDI (p
, 4, 1, min_frame
);
1702 /* Set r3 to TPOINT. */
1703 p
+= gen_limm (p
, 3, tpoint
, is_64
);
1705 /* Prepare collecting_t object for lock. */
1706 p
+= GEN_STORE (p
, 3, 1, min_frame
+ 37 * rsz
, is_64
);
1707 p
+= GEN_STORE (p
, tp_reg
, 1, min_frame
+ 38 * rsz
, is_64
);
1708 /* Set R5 to collecting object. */
1709 p
+= GEN_ADDI (p
, 5, 1, 37 * rsz
);
1711 p
+= GEN_LWSYNC (p
);
1712 p
+= gen_atomic_xchg (p
, lockaddr
, 0, 5, is_64
);
1713 p
+= GEN_LWSYNC (p
);
1715 /* Call to collector. */
1716 p
+= gen_call (p
, collector
, is_64
, is_opd
);
1718 /* Simply write 0 to release the lock. */
1719 p
+= gen_limm (p
, 3, lockaddr
, is_64
);
1720 p
+= gen_limm (p
, 4, 0, is_64
);
1721 p
+= GEN_LWSYNC (p
);
1722 p
+= GEN_STORE (p
, 4, 3, 0, is_64
);
1724 /* Restore stack and registers. */
1725 p
+= GEN_LOAD (p
, 3, 1, min_frame
+ 32 * rsz
, is_64
); /* ld r3, 32(r1) */
1726 p
+= GEN_LOAD (p
, 4, 1, min_frame
+ 33 * rsz
, is_64
); /* ld r4, 33(r1) */
1727 p
+= GEN_LOAD (p
, 5, 1, min_frame
+ 34 * rsz
, is_64
); /* ld r5, 34(r1) */
1728 p
+= GEN_LOAD (p
, 6, 1, min_frame
+ 35 * rsz
, is_64
); /* ld r6, 35(r1) */
1729 p
+= GEN_MTCR (p
, 3); /* mtcr r3 */
1730 p
+= GEN_MTSPR (p
, 4, 1); /* mtxer r4 */
1731 p
+= GEN_MTSPR (p
, 5, 8); /* mtlr r5 */
1732 p
+= GEN_MTSPR (p
, 6, 9); /* mtctr r6 */
1735 for (j
= 2; j
< 32; j
++)
1736 p
+= GEN_LOAD (p
, j
, 1, min_frame
+ j
* rsz
, is_64
);
1737 p
+= GEN_LOAD (p
, 0, 1, min_frame
+ 0 * rsz
, is_64
);
1739 p
+= GEN_ADDI (p
, 1, 1, frame_size
);
1741 /* Flush instructions to inferior memory. */
1742 target_write_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1744 /* Now, insert the original instruction to execute in the jump pad. */
1745 *adjusted_insn_addr
= buildaddr
+ (p
- buf
) * 4;
1746 *adjusted_insn_addr_end
= *adjusted_insn_addr
;
1747 ppc_relocate_instruction (adjusted_insn_addr_end
, tpaddr
);
1749 /* Verify the relocation size. If should be 4 for normal copy,
1750 8 or 12 for some conditional branch. */
1751 if ((*adjusted_insn_addr_end
- *adjusted_insn_addr
== 0)
1752 || (*adjusted_insn_addr_end
- *adjusted_insn_addr
> 12))
1754 sprintf (err
, "E.Unexpected instruction length = %d"
1755 "when relocate instruction.",
1756 (int) (*adjusted_insn_addr_end
- *adjusted_insn_addr
));
1760 buildaddr
= *adjusted_insn_addr_end
;
1762 /* Finally, write a jump back to the program. */
1763 offset
= (tpaddr
+ 4) - buildaddr
;
1764 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1766 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1767 "(offset 0x%x > 26-bit).", offset
);
1771 p
+= GEN_B (p
, offset
);
1772 target_write_memory (buildaddr
, (unsigned char *) buf
, (p
- buf
) * 4);
1773 *jump_entry
= buildaddr
+ (p
- buf
) * 4;
1775 /* The jump pad is now built. Wire in a jump to our jump pad. This
1776 is always done last (by our caller actually), so that we can
1777 install fast tracepoints with threads running. This relies on
1778 the agent's atomic write support. */
1779 offset
= entryaddr
- tpaddr
;
1780 if (offset
>= (1 << 25) || offset
< -(1 << 25))
1782 sprintf (err
, "E.Jump back from jump pad too far from tracepoint "
1783 "(offset 0x%x > 26-bit).", offset
);
1787 GEN_B ((uint32_t *) jjump_pad_insn
, offset
);
1788 *jjump_pad_insn_size
= 4;
1793 /* Returns the minimum instruction length for installing a tracepoint. */
1796 ppc_target::get_min_fast_tracepoint_insn_len ()
1801 /* Emits a given buffer into the target at current_insn_ptr. Length
1802 is in units of 32-bit words. */
1805 emit_insns (uint32_t *buf
, int n
)
1807 n
= n
* sizeof (uint32_t);
1808 target_write_memory (current_insn_ptr
, (unsigned char *) buf
, n
);
1809 current_insn_ptr
+= n
;
1812 #define __EMIT_ASM(NAME, INSNS) \
1815 extern uint32_t start_bcax_ ## NAME []; \
1816 extern uint32_t end_bcax_ ## NAME []; \
1817 emit_insns (start_bcax_ ## NAME, \
1818 end_bcax_ ## NAME - start_bcax_ ## NAME); \
1819 __asm__ (".section .text.__ppcbcax\n\t" \
1820 "start_bcax_" #NAME ":\n\t" \
1822 "end_bcax_" #NAME ":\n\t" \
1826 #define _EMIT_ASM(NAME, INSNS) __EMIT_ASM (NAME, INSNS)
1827 #define EMIT_ASM(INSNS) _EMIT_ASM (__LINE__, INSNS)
1831 Bytecode execution stack frame - 32-bit
1833 | LR save area (SP + 4)
1834 SP' -> +- Back chain (SP + 0)
1835 | Save r31 for access saved arguments
1836 | Save r30 for bytecode stack pointer
1837 | Save r4 for incoming argument *value
1838 | Save r3 for incoming argument regs
1839 r30 -> +- Bytecode execution stack
1841 | 64-byte (8 doublewords) at initial.
1842 | Expand stack as needed.
1845 | Some padding for minimum stack frame and 16-byte alignment.
1847 SP +- Back-chain (SP')
1853 r30 is the stack-pointer for bytecode machine.
1854 It should point to next-empty, so we can use LDU for pop.
1855 r3 is used for cache of the high part of TOP value.
1856 It was the first argument, pointer to regs.
1857 r4 is used for cache of the low part of TOP value.
1858 It was the second argument, pointer to the result.
1859 We should set *result = TOP after leaving this function.
1862 * To restore stack at epilogue
1864 * To check stack is big enough for bytecode execution.
1866 * To return execution result.
1871 /* Regardless of endian, register 3 is always high part, 4 is low part.
1872 These defines are used when the register pair is stored/loaded.
1873 Likewise, to simplify code, have a similiar define for 5:6. */
1875 #if __BYTE_ORDER == __LITTLE_ENDIAN
1876 #define TOP_FIRST "4"
1877 #define TOP_SECOND "3"
1878 #define TMP_FIRST "6"
1879 #define TMP_SECOND "5"
1881 #define TOP_FIRST "3"
1882 #define TOP_SECOND "4"
1883 #define TMP_FIRST "5"
1884 #define TMP_SECOND "6"
1887 /* Emit prologue in inferior memory. See above comments. */
1890 ppc_emit_prologue (void)
1892 EMIT_ASM (/* Save return address. */
1895 /* Adjust SP. 96 is the initial frame size. */
1897 /* Save r30 and incoming arguments. */
1898 "stw 31, 96-4(1) \n"
1899 "stw 30, 96-8(1) \n"
1900 "stw 4, 96-12(1) \n"
1901 "stw 3, 96-16(1) \n"
1902 /* Point r31 to original r1 for access arguments. */
1904 /* Set r30 to pointing stack-top. */
1906 /* Initial r3/TOP to 0. */
1911 /* Emit epilogue in inferior memory. See above comments. */
1914 ppc_emit_epilogue (void)
1916 EMIT_ASM (/* *result = TOP */
1918 "stw " TOP_FIRST
", 0(5) \n"
1919 "stw " TOP_SECOND
", 4(5) \n"
1920 /* Restore registers. */
1927 /* Return 0 for no-error. */
1933 /* TOP = stack[--sp] + TOP */
1938 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1939 "lwz " TMP_SECOND
", 4(30)\n"
1944 /* TOP = stack[--sp] - TOP */
1949 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1950 "lwz " TMP_SECOND
", 4(30) \n"
1952 "subfe 3, 3, 5 \n");
1955 /* TOP = stack[--sp] * TOP */
1960 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1961 "lwz " TMP_SECOND
", 4(30) \n"
1970 /* TOP = stack[--sp] << TOP */
1975 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1976 "lwz " TMP_SECOND
", 4(30) \n"
1977 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
1978 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1979 "slw 5, 5, 4\n" /* Shift high part left */
1980 "slw 4, 6, 4\n" /* Shift low part left */
1981 "srw 3, 6, 3\n" /* Shift low to high if shift < 32 */
1982 "slw 7, 6, 7\n" /* Shift low to high if shift >= 32 */
1984 "or 3, 7, 3\n"); /* Assemble high part */
1987 /* Top = stack[--sp] >> TOP
1988 (Arithmetic shift right) */
1991 ppc_emit_rsh_signed (void)
1993 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
1994 "lwz " TMP_SECOND
", 4(30) \n"
1995 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
1996 "sraw 3, 5, 4\n" /* Shift high part right */
1998 "blt 0, 1f\n" /* If shift <= 32, goto 1: */
1999 "sraw 4, 5, 7\n" /* Shift high to low */
2002 "subfic 7, 4, 32\n" /* r7 = 32 - TOP */
2003 "srw 4, 6, 4\n" /* Shift low part right */
2004 "slw 5, 5, 7\n" /* Shift high to low */
2005 "or 4, 4, 5\n" /* Assemble low part */
2009 /* Top = stack[--sp] >> TOP
2010 (Logical shift right) */
2013 ppc_emit_rsh_unsigned (void)
2015 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2016 "lwz " TMP_SECOND
", 4(30) \n"
2017 "subfic 3, 4, 32\n" /* r3 = 32 - TOP */
2018 "addi 7, 4, -32\n" /* r7 = TOP - 32 */
2019 "srw 6, 6, 4\n" /* Shift low part right */
2020 "slw 3, 5, 3\n" /* Shift high to low if shift < 32 */
2021 "srw 7, 5, 7\n" /* Shift high to low if shift >= 32 */
2023 "srw 3, 5, 4\n" /* Shift high part right */
2024 "or 4, 6, 7\n"); /* Assemble low part */
2027 /* Emit code for signed-extension specified by ARG. */
2030 ppc_emit_ext (int arg
)
2035 EMIT_ASM ("extsb 4, 4\n"
2039 EMIT_ASM ("extsh 4, 4\n"
2043 EMIT_ASM ("srawi 3, 4, 31");
2050 /* Emit code for zero-extension specified by ARG. */
2053 ppc_emit_zero_ext (int arg
)
2058 EMIT_ASM ("clrlwi 4,4,24\n"
2062 EMIT_ASM ("clrlwi 4,4,16\n"
2066 EMIT_ASM ("li 3, 0");
2074 i.e., TOP = (TOP == 0) ? 1 : 0; */
2077 ppc_emit_log_not (void)
2079 EMIT_ASM ("or 4, 3, 4 \n"
2085 /* TOP = stack[--sp] & TOP */
2088 ppc_emit_bit_and (void)
2090 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2091 "lwz " TMP_SECOND
", 4(30) \n"
2096 /* TOP = stack[--sp] | TOP */
2099 ppc_emit_bit_or (void)
2101 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2102 "lwz " TMP_SECOND
", 4(30) \n"
2107 /* TOP = stack[--sp] ^ TOP */
2110 ppc_emit_bit_xor (void)
2112 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2113 "lwz " TMP_SECOND
", 4(30) \n"
2119 i.e., TOP = ~(TOP | TOP) */
2122 ppc_emit_bit_not (void)
2124 EMIT_ASM ("nor 3, 3, 3 \n"
2128 /* TOP = stack[--sp] == TOP */
2131 ppc_emit_equal (void)
2133 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2134 "lwz " TMP_SECOND
", 4(30) \n"
2143 /* TOP = stack[--sp] < TOP
2144 (Signed comparison) */
2147 ppc_emit_less_signed (void)
2149 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2150 "lwz " TMP_SECOND
", 4(30) \n"
2153 /* CR6 bit 0 = low less and high equal */
2154 "crand 6*4+0, 6*4+0, 7*4+2\n"
2155 /* CR7 bit 0 = (low less and high equal) or high less */
2156 "cror 7*4+0, 7*4+0, 6*4+0\n"
2158 "rlwinm 4, 4, 29, 31, 31 \n"
2162 /* TOP = stack[--sp] < TOP
2163 (Unsigned comparison) */
2166 ppc_emit_less_unsigned (void)
2168 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2169 "lwz " TMP_SECOND
", 4(30) \n"
2172 /* CR6 bit 0 = low less and high equal */
2173 "crand 6*4+0, 6*4+0, 7*4+2\n"
2174 /* CR7 bit 0 = (low less and high equal) or high less */
2175 "cror 7*4+0, 7*4+0, 6*4+0\n"
2177 "rlwinm 4, 4, 29, 31, 31 \n"
2181 /* Access the memory address in TOP in size of SIZE.
2182 Zero-extend the read value. */
2185 ppc_emit_ref (int size
)
2190 EMIT_ASM ("lbz 4, 0(4)\n"
2194 EMIT_ASM ("lhz 4, 0(4)\n"
2198 EMIT_ASM ("lwz 4, 0(4)\n"
2202 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2203 EMIT_ASM ("lwz 3, 4(4)\n"
2206 EMIT_ASM ("lwz 3, 0(4)\n"
2215 ppc_emit_const (LONGEST num
)
2220 p
+= gen_limm (p
, 3, num
>> 32 & 0xffffffff, 0);
2221 p
+= gen_limm (p
, 4, num
& 0xffffffff, 0);
2223 emit_insns (buf
, p
- buf
);
2224 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2227 /* Set TOP to the value of register REG by calling get_raw_reg function
2228 with two argument, collected buffer and register number. */
2231 ppc_emit_reg (int reg
)
2236 /* fctx->regs is passed in r3 and then saved in -16(31). */
2237 p
+= GEN_LWZ (p
, 3, 31, -16);
2238 p
+= GEN_LI (p
, 4, reg
); /* li r4, reg */
2239 p
+= gen_call (p
, get_raw_reg_func_addr (), 0, 0);
2241 emit_insns (buf
, p
- buf
);
2242 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2244 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2246 EMIT_ASM ("mr 5, 4\n"
2252 /* TOP = stack[--sp] */
2257 EMIT_ASM ("lwzu " TOP_FIRST
", 8(30) \n"
2258 "lwz " TOP_SECOND
", 4(30) \n");
2261 /* stack[sp++] = TOP
2263 Because we may use up bytecode stack, expand 8 doublewords more
2267 ppc_emit_stack_flush (void)
2269 /* Make sure bytecode stack is big enough before push.
2270 Otherwise, expand 64-byte more. */
2272 EMIT_ASM (" stw " TOP_FIRST
", 0(30) \n"
2273 " stw " TOP_SECOND
", 4(30)\n"
2274 " addi 5, 30, -(8 + 8) \n"
2277 " stwu 31, -64(1) \n"
2278 "1:addi 30, 30, -8 \n");
2281 /* Swap TOP and stack[sp-1] */
2284 ppc_emit_swap (void)
2286 EMIT_ASM ("lwz " TMP_FIRST
", 8(30) \n"
2287 "lwz " TMP_SECOND
", 12(30) \n"
2288 "stw " TOP_FIRST
", 8(30) \n"
2289 "stw " TOP_SECOND
", 12(30) \n"
2294 /* Discard N elements in the stack. Also used for ppc64. */
2297 ppc_emit_stack_adjust (int n
)
2309 p
+= GEN_ADDI (p
, 30, 30, n
);
2311 emit_insns (buf
, p
- buf
);
2312 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2315 /* Call function FN. */
2318 ppc_emit_call (CORE_ADDR fn
)
2323 p
+= gen_call (p
, fn
, 0, 0);
2325 emit_insns (buf
, p
- buf
);
2326 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2329 /* FN's prototype is `LONGEST(*fn)(int)'.
2334 ppc_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
2339 /* Setup argument. arg1 is a 16-bit value. */
2340 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2341 p
+= gen_call (p
, fn
, 0, 0);
2343 emit_insns (buf
, p
- buf
);
2344 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2346 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2348 EMIT_ASM ("mr 5, 4\n"
2354 /* FN's prototype is `void(*fn)(int,LONGEST)'.
2357 TOP should be preserved/restored before/after the call. */
2360 ppc_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
2365 /* Save TOP. 0(30) is next-empty. */
2366 p
+= GEN_STW (p
, 3, 30, 0);
2367 p
+= GEN_STW (p
, 4, 30, 4);
2369 /* Setup argument. arg1 is a 16-bit value. */
2370 if (__BYTE_ORDER
== __LITTLE_ENDIAN
)
2372 p
+= GEN_MR (p
, 5, 4);
2373 p
+= GEN_MR (p
, 6, 3);
2377 p
+= GEN_MR (p
, 5, 3);
2378 p
+= GEN_MR (p
, 6, 4);
2380 p
+= gen_limm (p
, 3, (uint32_t) arg1
, 0);
2381 p
+= gen_call (p
, fn
, 0, 0);
2384 p
+= GEN_LWZ (p
, 3, 30, 0);
2385 p
+= GEN_LWZ (p
, 4, 30, 4);
2387 emit_insns (buf
, p
- buf
);
2388 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2391 /* Note in the following goto ops:
2393 When emitting goto, the target address is later relocated by
2394 write_goto_address. OFFSET_P is the offset of the branch instruction
2395 in the code sequence, and SIZE_P is how to relocate the instruction,
2396 recognized by ppc_write_goto_address. In current implementation,
2397 SIZE can be either 24 or 14 for branch of conditional-branch instruction.
2400 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
2403 ppc_emit_if_goto (int *offset_p
, int *size_p
)
2405 EMIT_ASM ("or. 3, 3, 4 \n"
2406 "lwzu " TOP_FIRST
", 8(30) \n"
2407 "lwz " TOP_SECOND
", 4(30) \n"
2416 /* Unconditional goto. Also used for ppc64. */
2419 ppc_emit_goto (int *offset_p
, int *size_p
)
2421 EMIT_ASM ("1:b 1b");
2429 /* Goto if stack[--sp] == TOP */
2432 ppc_emit_eq_goto (int *offset_p
, int *size_p
)
2434 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2435 "lwz " TMP_SECOND
", 4(30) \n"
2439 "lwzu " TOP_FIRST
", 8(30) \n"
2440 "lwz " TOP_SECOND
", 4(30) \n"
2449 /* Goto if stack[--sp] != TOP */
2452 ppc_emit_ne_goto (int *offset_p
, int *size_p
)
2454 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2455 "lwz " TMP_SECOND
", 4(30) \n"
2459 "lwzu " TOP_FIRST
", 8(30) \n"
2460 "lwz " TOP_SECOND
", 4(30) \n"
2469 /* Goto if stack[--sp] < TOP */
2472 ppc_emit_lt_goto (int *offset_p
, int *size_p
)
2474 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2475 "lwz " TMP_SECOND
", 4(30) \n"
2478 /* CR6 bit 0 = low less and high equal */
2479 "crand 6*4+0, 6*4+0, 7*4+2\n"
2480 /* CR7 bit 0 = (low less and high equal) or high less */
2481 "cror 7*4+0, 7*4+0, 6*4+0\n"
2482 "lwzu " TOP_FIRST
", 8(30) \n"
2483 "lwz " TOP_SECOND
", 4(30)\n"
2492 /* Goto if stack[--sp] <= TOP */
2495 ppc_emit_le_goto (int *offset_p
, int *size_p
)
2497 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2498 "lwz " TMP_SECOND
", 4(30) \n"
2501 /* CR6 bit 0 = low less/equal and high equal */
2502 "crandc 6*4+0, 7*4+2, 6*4+1\n"
2503 /* CR7 bit 0 = (low less/eq and high equal) or high less */
2504 "cror 7*4+0, 7*4+0, 6*4+0\n"
2505 "lwzu " TOP_FIRST
", 8(30) \n"
2506 "lwz " TOP_SECOND
", 4(30)\n"
2515 /* Goto if stack[--sp] > TOP */
2518 ppc_emit_gt_goto (int *offset_p
, int *size_p
)
2520 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2521 "lwz " TMP_SECOND
", 4(30) \n"
2524 /* CR6 bit 0 = low greater and high equal */
2525 "crand 6*4+0, 6*4+1, 7*4+2\n"
2526 /* CR7 bit 0 = (low greater and high equal) or high greater */
2527 "cror 7*4+0, 7*4+1, 6*4+0\n"
2528 "lwzu " TOP_FIRST
", 8(30) \n"
2529 "lwz " TOP_SECOND
", 4(30)\n"
2538 /* Goto if stack[--sp] >= TOP */
2541 ppc_emit_ge_goto (int *offset_p
, int *size_p
)
2543 EMIT_ASM ("lwzu " TMP_FIRST
", 8(30) \n"
2544 "lwz " TMP_SECOND
", 4(30) \n"
2547 /* CR6 bit 0 = low ge and high equal */
2548 "crandc 6*4+0, 7*4+2, 6*4+0\n"
2549 /* CR7 bit 0 = (low ge and high equal) or high greater */
2550 "cror 7*4+0, 7*4+1, 6*4+0\n"
2551 "lwzu " TOP_FIRST
", 8(30)\n"
2552 "lwz " TOP_SECOND
", 4(30)\n"
2561 /* Relocate previous emitted branch instruction. FROM is the address
2562 of the branch instruction, TO is the goto target address, and SIZE
2563 if the value we set by *SIZE_P before. Currently, it is either
2564 24 or 14 of branch and conditional-branch instruction.
2565 Also used for ppc64. */
2568 ppc_write_goto_address (CORE_ADDR from
, CORE_ADDR to
, int size
)
2570 long rel
= to
- from
;
2574 read_inferior_memory (from
, (unsigned char *) &insn
, 4);
2575 opcd
= (insn
>> 26) & 0x3f;
2581 || (rel
>= (1 << 15) || rel
< -(1 << 15)))
2583 insn
= (insn
& ~0xfffc) | (rel
& 0xfffc);
2587 || (rel
>= (1 << 25) || rel
< -(1 << 25)))
2589 insn
= (insn
& ~0x3fffffc) | (rel
& 0x3fffffc);
2596 target_write_memory (from
, (unsigned char *) &insn
, 4);
2599 /* Table of emit ops for 32-bit. */
2601 static struct emit_ops ppc_emit_ops_impl
=
2609 ppc_emit_rsh_signed
,
2610 ppc_emit_rsh_unsigned
,
2618 ppc_emit_less_signed
,
2619 ppc_emit_less_unsigned
,
2623 ppc_write_goto_address
,
2628 ppc_emit_stack_flush
,
2631 ppc_emit_stack_adjust
,
2632 ppc_emit_int_call_1
,
2633 ppc_emit_void_call_2
,
2642 #ifdef __powerpc64__
2646 Bytecode execution stack frame - 64-bit
2648 | LR save area (SP + 16)
2649 | CR save area (SP + 8)
2650 SP' -> +- Back chain (SP + 0)
2651 | Save r31 for access saved arguments
2652 | Save r30 for bytecode stack pointer
2653 | Save r4 for incoming argument *value
2654 | Save r3 for incoming argument regs
2655 r30 -> +- Bytecode execution stack
2657 | 64-byte (8 doublewords) at initial.
2658 | Expand stack as needed.
2661 | Some padding for minimum stack frame.
2663 SP +- Back-chain (SP')
2666 = 112 + (4 * 8) + 64
2669 r30 is the stack-pointer for bytecode machine.
2670 It should point to next-empty, so we can use LDU for pop.
2671 r3 is used for cache of TOP value.
2672 It was the first argument, pointer to regs.
2673 r4 is the second argument, pointer to the result.
2674 We should set *result = TOP after leaving this function.
2677 * To restore stack at epilogue
2679 * To check stack is big enough for bytecode execution.
2680 => r30 - 8 > SP + 112
2681 * To return execution result.
2686 /* Emit prologue in inferior memory. See above comments. */
2689 ppc64v1_emit_prologue (void)
2691 /* On ELFv1, function pointers really point to function descriptor,
2692 so emit one here. We don't care about contents of words 1 and 2,
2693 so let them just overlap out code. */
2694 uint64_t opd
= current_insn_ptr
+ 8;
2697 /* Mind the strict aliasing rules. */
2698 memcpy (buf
, &opd
, sizeof buf
);
2700 EMIT_ASM (/* Save return address. */
2703 /* Save r30 and incoming arguments. */
2708 /* Point r31 to current r1 for access arguments. */
2710 /* Adjust SP. 208 is the initial frame size. */
2711 "stdu 1, -208(1) \n"
2712 /* Set r30 to pointing stack-top. */
2713 "addi 30, 1, 168 \n"
2714 /* Initial r3/TOP to 0. */
2718 /* Emit prologue in inferior memory. See above comments. */
2721 ppc64v2_emit_prologue (void)
2723 EMIT_ASM (/* Save return address. */
2726 /* Save r30 and incoming arguments. */
2731 /* Point r31 to current r1 for access arguments. */
2733 /* Adjust SP. 208 is the initial frame size. */
2734 "stdu 1, -208(1) \n"
2735 /* Set r30 to pointing stack-top. */
2736 "addi 30, 1, 168 \n"
2737 /* Initial r3/TOP to 0. */
2741 /* Emit epilogue in inferior memory. See above comments. */
2744 ppc64_emit_epilogue (void)
2746 EMIT_ASM (/* Restore SP. */
2751 /* Restore registers. */
2756 /* Return 0 for no-error. */
2762 /* TOP = stack[--sp] + TOP */
2765 ppc64_emit_add (void)
2767 EMIT_ASM ("ldu 4, 8(30) \n"
2771 /* TOP = stack[--sp] - TOP */
2774 ppc64_emit_sub (void)
2776 EMIT_ASM ("ldu 4, 8(30) \n"
2780 /* TOP = stack[--sp] * TOP */
2783 ppc64_emit_mul (void)
2785 EMIT_ASM ("ldu 4, 8(30) \n"
2786 "mulld 3, 4, 3 \n");
2789 /* TOP = stack[--sp] << TOP */
2792 ppc64_emit_lsh (void)
2794 EMIT_ASM ("ldu 4, 8(30) \n"
2798 /* Top = stack[--sp] >> TOP
2799 (Arithmetic shift right) */
2802 ppc64_emit_rsh_signed (void)
2804 EMIT_ASM ("ldu 4, 8(30) \n"
2808 /* Top = stack[--sp] >> TOP
2809 (Logical shift right) */
2812 ppc64_emit_rsh_unsigned (void)
2814 EMIT_ASM ("ldu 4, 8(30) \n"
2818 /* Emit code for signed-extension specified by ARG. */
2821 ppc64_emit_ext (int arg
)
2826 EMIT_ASM ("extsb 3, 3");
2829 EMIT_ASM ("extsh 3, 3");
2832 EMIT_ASM ("extsw 3, 3");
2839 /* Emit code for zero-extension specified by ARG. */
2842 ppc64_emit_zero_ext (int arg
)
2847 EMIT_ASM ("rldicl 3,3,0,56");
2850 EMIT_ASM ("rldicl 3,3,0,48");
2853 EMIT_ASM ("rldicl 3,3,0,32");
2861 i.e., TOP = (TOP == 0) ? 1 : 0; */
2864 ppc64_emit_log_not (void)
2866 EMIT_ASM ("cntlzd 3, 3 \n"
2870 /* TOP = stack[--sp] & TOP */
2873 ppc64_emit_bit_and (void)
2875 EMIT_ASM ("ldu 4, 8(30) \n"
2879 /* TOP = stack[--sp] | TOP */
2882 ppc64_emit_bit_or (void)
2884 EMIT_ASM ("ldu 4, 8(30) \n"
2888 /* TOP = stack[--sp] ^ TOP */
2891 ppc64_emit_bit_xor (void)
2893 EMIT_ASM ("ldu 4, 8(30) \n"
2898 i.e., TOP = ~(TOP | TOP) */
2901 ppc64_emit_bit_not (void)
2903 EMIT_ASM ("nor 3, 3, 3 \n");
2906 /* TOP = stack[--sp] == TOP */
2909 ppc64_emit_equal (void)
2911 EMIT_ASM ("ldu 4, 8(30) \n"
2917 /* TOP = stack[--sp] < TOP
2918 (Signed comparison) */
2921 ppc64_emit_less_signed (void)
2923 EMIT_ASM ("ldu 4, 8(30) \n"
2926 "rlwinm 3, 3, 29, 31, 31 \n");
2929 /* TOP = stack[--sp] < TOP
2930 (Unsigned comparison) */
2933 ppc64_emit_less_unsigned (void)
2935 EMIT_ASM ("ldu 4, 8(30) \n"
2938 "rlwinm 3, 3, 29, 31, 31 \n");
2941 /* Access the memory address in TOP in size of SIZE.
2942 Zero-extend the read value. */
2945 ppc64_emit_ref (int size
)
2950 EMIT_ASM ("lbz 3, 0(3)");
2953 EMIT_ASM ("lhz 3, 0(3)");
2956 EMIT_ASM ("lwz 3, 0(3)");
2959 EMIT_ASM ("ld 3, 0(3)");
2967 ppc64_emit_const (LONGEST num
)
2972 p
+= gen_limm (p
, 3, num
, 1);
2974 emit_insns (buf
, p
- buf
);
2975 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2978 /* Set TOP to the value of register REG by calling get_raw_reg function
2979 with two argument, collected buffer and register number. */
2982 ppc64v1_emit_reg (int reg
)
2987 /* fctx->regs is passed in r3 and then saved in 176(1). */
2988 p
+= GEN_LD (p
, 3, 31, -32);
2989 p
+= GEN_LI (p
, 4, reg
);
2990 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
2991 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 1);
2992 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
2994 emit_insns (buf
, p
- buf
);
2995 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
2998 /* Likewise, for ELFv2. */
3001 ppc64v2_emit_reg (int reg
)
3006 /* fctx->regs is passed in r3 and then saved in 176(1). */
3007 p
+= GEN_LD (p
, 3, 31, -32);
3008 p
+= GEN_LI (p
, 4, reg
);
3009 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3010 p
+= gen_call (p
, get_raw_reg_func_addr (), 1, 0);
3011 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3013 emit_insns (buf
, p
- buf
);
3014 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3017 /* TOP = stack[--sp] */
3020 ppc64_emit_pop (void)
3022 EMIT_ASM ("ldu 3, 8(30)");
3025 /* stack[sp++] = TOP
3027 Because we may use up bytecode stack, expand 8 doublewords more
3031 ppc64_emit_stack_flush (void)
3033 /* Make sure bytecode stack is big enough before push.
3034 Otherwise, expand 64-byte more. */
3036 EMIT_ASM (" std 3, 0(30) \n"
3037 " addi 4, 30, -(112 + 8) \n"
3040 " stdu 31, -64(1) \n"
3041 "1:addi 30, 30, -8 \n");
3044 /* Swap TOP and stack[sp-1] */
3047 ppc64_emit_swap (void)
3049 EMIT_ASM ("ld 4, 8(30) \n"
3054 /* Call function FN - ELFv1. */
3057 ppc64v1_emit_call (CORE_ADDR fn
)
3062 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3063 p
+= gen_call (p
, fn
, 1, 1);
3064 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3066 emit_insns (buf
, p
- buf
);
3067 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3070 /* Call function FN - ELFv2. */
3073 ppc64v2_emit_call (CORE_ADDR fn
)
3078 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3079 p
+= gen_call (p
, fn
, 1, 0);
3080 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3082 emit_insns (buf
, p
- buf
);
3083 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3086 /* FN's prototype is `LONGEST(*fn)(int)'.
3091 ppc64v1_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3096 /* Setup argument. arg1 is a 16-bit value. */
3097 p
+= gen_limm (p
, 3, arg1
, 1);
3098 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3099 p
+= gen_call (p
, fn
, 1, 1);
3100 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3102 emit_insns (buf
, p
- buf
);
3103 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3106 /* Likewise for ELFv2. */
3109 ppc64v2_emit_int_call_1 (CORE_ADDR fn
, int arg1
)
3114 /* Setup argument. arg1 is a 16-bit value. */
3115 p
+= gen_limm (p
, 3, arg1
, 1);
3116 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3117 p
+= gen_call (p
, fn
, 1, 0);
3118 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3120 emit_insns (buf
, p
- buf
);
3121 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3124 /* FN's prototype is `void(*fn)(int,LONGEST)'.
3127 TOP should be preserved/restored before/after the call. */
3130 ppc64v1_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3135 /* Save TOP. 0(30) is next-empty. */
3136 p
+= GEN_STD (p
, 3, 30, 0);
3138 /* Setup argument. arg1 is a 16-bit value. */
3139 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
3140 p
+= gen_limm (p
, 3, arg1
, 1);
3141 p
+= GEN_STD (p
, 2, 1, 40); /* Save TOC. */
3142 p
+= gen_call (p
, fn
, 1, 1);
3143 p
+= GEN_LD (p
, 2, 1, 40); /* Restore TOC. */
3146 p
+= GEN_LD (p
, 3, 30, 0);
3148 emit_insns (buf
, p
- buf
);
3149 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3152 /* Likewise for ELFv2. */
3155 ppc64v2_emit_void_call_2 (CORE_ADDR fn
, int arg1
)
3160 /* Save TOP. 0(30) is next-empty. */
3161 p
+= GEN_STD (p
, 3, 30, 0);
3163 /* Setup argument. arg1 is a 16-bit value. */
3164 p
+= GEN_MR (p
, 4, 3); /* mr r4, r3 */
3165 p
+= gen_limm (p
, 3, arg1
, 1);
3166 p
+= GEN_STD (p
, 2, 1, 24); /* Save TOC. */
3167 p
+= gen_call (p
, fn
, 1, 0);
3168 p
+= GEN_LD (p
, 2, 1, 24); /* Restore TOC. */
3171 p
+= GEN_LD (p
, 3, 30, 0);
3173 emit_insns (buf
, p
- buf
);
3174 gdb_assert ((p
- buf
) <= (sizeof (buf
) / sizeof (*buf
)));
3177 /* If TOP is true, goto somewhere. Otherwise, just fall-through. */
3180 ppc64_emit_if_goto (int *offset_p
, int *size_p
)
3182 EMIT_ASM ("cmpdi 7, 3, 0 \n"
3192 /* Goto if stack[--sp] == TOP */
3195 ppc64_emit_eq_goto (int *offset_p
, int *size_p
)
3197 EMIT_ASM ("ldu 4, 8(30) \n"
3208 /* Goto if stack[--sp] != TOP */
3211 ppc64_emit_ne_goto (int *offset_p
, int *size_p
)
3213 EMIT_ASM ("ldu 4, 8(30) \n"
3224 /* Goto if stack[--sp] < TOP */
3227 ppc64_emit_lt_goto (int *offset_p
, int *size_p
)
3229 EMIT_ASM ("ldu 4, 8(30) \n"
3240 /* Goto if stack[--sp] <= TOP */
3243 ppc64_emit_le_goto (int *offset_p
, int *size_p
)
3245 EMIT_ASM ("ldu 4, 8(30) \n"
3256 /* Goto if stack[--sp] > TOP */
3259 ppc64_emit_gt_goto (int *offset_p
, int *size_p
)
3261 EMIT_ASM ("ldu 4, 8(30) \n"
3272 /* Goto if stack[--sp] >= TOP */
3275 ppc64_emit_ge_goto (int *offset_p
, int *size_p
)
3277 EMIT_ASM ("ldu 4, 8(30) \n"
3288 /* Table of emit ops for 64-bit ELFv1. */
3290 static struct emit_ops ppc64v1_emit_ops_impl
=
3292 ppc64v1_emit_prologue
,
3293 ppc64_emit_epilogue
,
3298 ppc64_emit_rsh_signed
,
3299 ppc64_emit_rsh_unsigned
,
3307 ppc64_emit_less_signed
,
3308 ppc64_emit_less_unsigned
,
3312 ppc_write_goto_address
,
3317 ppc64_emit_stack_flush
,
3318 ppc64_emit_zero_ext
,
3320 ppc_emit_stack_adjust
,
3321 ppc64v1_emit_int_call_1
,
3322 ppc64v1_emit_void_call_2
,
3331 /* Table of emit ops for 64-bit ELFv2. */
3333 static struct emit_ops ppc64v2_emit_ops_impl
=
3335 ppc64v2_emit_prologue
,
3336 ppc64_emit_epilogue
,
3341 ppc64_emit_rsh_signed
,
3342 ppc64_emit_rsh_unsigned
,
3350 ppc64_emit_less_signed
,
3351 ppc64_emit_less_unsigned
,
3355 ppc_write_goto_address
,
3360 ppc64_emit_stack_flush
,
3361 ppc64_emit_zero_ext
,
3363 ppc_emit_stack_adjust
,
3364 ppc64v2_emit_int_call_1
,
3365 ppc64v2_emit_void_call_2
,
3376 /* Implementation of target ops method "emit_ops". */
3379 ppc_target::emit_ops ()
3381 #ifdef __powerpc64__
3382 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3384 if (register_size (regcache
->tdesc
, 0) == 8)
3386 if (is_elfv2_inferior ())
3387 return &ppc64v2_emit_ops_impl
;
3389 return &ppc64v1_emit_ops_impl
;
3392 return &ppc_emit_ops_impl
;
3395 /* Implementation of linux_target_ops method "get_ipa_tdesc_idx". */
3398 ppc_get_ipa_tdesc_idx (void)
3400 struct regcache
*regcache
= get_thread_regcache (current_thread
, 0);
3401 const struct target_desc
*tdesc
= regcache
->tdesc
;
3403 #ifdef __powerpc64__
3404 if (tdesc
== tdesc_powerpc_64l
)
3405 return PPC_TDESC_BASE
;
3406 if (tdesc
== tdesc_powerpc_altivec64l
)
3407 return PPC_TDESC_ALTIVEC
;
3408 if (tdesc
== tdesc_powerpc_vsx64l
)
3409 return PPC_TDESC_VSX
;
3410 if (tdesc
== tdesc_powerpc_isa205_64l
)
3411 return PPC_TDESC_ISA205
;
3412 if (tdesc
== tdesc_powerpc_isa205_altivec64l
)
3413 return PPC_TDESC_ISA205_ALTIVEC
;
3414 if (tdesc
== tdesc_powerpc_isa205_vsx64l
)
3415 return PPC_TDESC_ISA205_VSX
;
3416 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx64l
)
3417 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3418 if (tdesc
== tdesc_powerpc_isa207_vsx64l
)
3419 return PPC_TDESC_ISA207_VSX
;
3420 if (tdesc
== tdesc_powerpc_isa207_htm_vsx64l
)
3421 return PPC_TDESC_ISA207_HTM_VSX
;
3424 if (tdesc
== tdesc_powerpc_32l
)
3425 return PPC_TDESC_BASE
;
3426 if (tdesc
== tdesc_powerpc_altivec32l
)
3427 return PPC_TDESC_ALTIVEC
;
3428 if (tdesc
== tdesc_powerpc_vsx32l
)
3429 return PPC_TDESC_VSX
;
3430 if (tdesc
== tdesc_powerpc_isa205_32l
)
3431 return PPC_TDESC_ISA205
;
3432 if (tdesc
== tdesc_powerpc_isa205_altivec32l
)
3433 return PPC_TDESC_ISA205_ALTIVEC
;
3434 if (tdesc
== tdesc_powerpc_isa205_vsx32l
)
3435 return PPC_TDESC_ISA205_VSX
;
3436 if (tdesc
== tdesc_powerpc_isa205_ppr_dscr_vsx32l
)
3437 return PPC_TDESC_ISA205_PPR_DSCR_VSX
;
3438 if (tdesc
== tdesc_powerpc_isa207_vsx32l
)
3439 return PPC_TDESC_ISA207_VSX
;
3440 if (tdesc
== tdesc_powerpc_isa207_htm_vsx32l
)
3441 return PPC_TDESC_ISA207_HTM_VSX
;
3442 if (tdesc
== tdesc_powerpc_e500l
)
3443 return PPC_TDESC_E500
;
3448 struct linux_target_ops the_low_target
= {
3449 ppc_get_ipa_tdesc_idx
,
3452 /* The linux target ops object. */
3454 linux_process_target
*the_linux_target
= &the_ppc_target
;
3457 initialize_low_arch (void)
3459 /* Initialize the Linux target descriptions. */
3461 init_registers_powerpc_32l ();
3462 init_registers_powerpc_altivec32l ();
3463 init_registers_powerpc_vsx32l ();
3464 init_registers_powerpc_isa205_32l ();
3465 init_registers_powerpc_isa205_altivec32l ();
3466 init_registers_powerpc_isa205_vsx32l ();
3467 init_registers_powerpc_isa205_ppr_dscr_vsx32l ();
3468 init_registers_powerpc_isa207_vsx32l ();
3469 init_registers_powerpc_isa207_htm_vsx32l ();
3470 init_registers_powerpc_e500l ();
3472 init_registers_powerpc_64l ();
3473 init_registers_powerpc_altivec64l ();
3474 init_registers_powerpc_vsx64l ();
3475 init_registers_powerpc_isa205_64l ();
3476 init_registers_powerpc_isa205_altivec64l ();
3477 init_registers_powerpc_isa205_vsx64l ();
3478 init_registers_powerpc_isa205_ppr_dscr_vsx64l ();
3479 init_registers_powerpc_isa207_vsx64l ();
3480 init_registers_powerpc_isa207_htm_vsx64l ();
3483 initialize_regsets_info (&ppc_regsets_info
);