fb: adv7393: off by one in probe function
[deliverable/linux.git] / include / dt-bindings / clock / rk3399-cru.h
1 /*
2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
3 * Author: Xing Zheng <zhengxing@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3399_H
18
19 /* core clocks */
20 #define PLL_APLLL 1
21 #define PLL_APLLB 2
22 #define PLL_DPLL 3
23 #define PLL_CPLL 4
24 #define PLL_GPLL 5
25 #define PLL_NPLL 6
26 #define PLL_VPLL 7
27 #define ARMCLKL 8
28 #define ARMCLKB 9
29
30 /* sclk gates (special clocks) */
31 #define SCLK_I2C1 65
32 #define SCLK_I2C2 66
33 #define SCLK_I2C3 67
34 #define SCLK_I2C5 68
35 #define SCLK_I2C6 69
36 #define SCLK_I2C7 70
37 #define SCLK_SPI0 71
38 #define SCLK_SPI1 72
39 #define SCLK_SPI2 73
40 #define SCLK_SPI4 74
41 #define SCLK_SPI5 75
42 #define SCLK_SDMMC 76
43 #define SCLK_SDIO 77
44 #define SCLK_EMMC 78
45 #define SCLK_TSADC 79
46 #define SCLK_SARADC 80
47 #define SCLK_UART0 81
48 #define SCLK_UART1 82
49 #define SCLK_UART2 83
50 #define SCLK_UART3 84
51 #define SCLK_SPDIF_8CH 85
52 #define SCLK_I2S0_8CH 86
53 #define SCLK_I2S1_8CH 87
54 #define SCLK_I2S2_8CH 88
55 #define SCLK_I2S_8CH_OUT 89
56 #define SCLK_TIMER00 90
57 #define SCLK_TIMER01 91
58 #define SCLK_TIMER02 92
59 #define SCLK_TIMER03 93
60 #define SCLK_TIMER04 94
61 #define SCLK_TIMER05 95
62 #define SCLK_TIMER06 96
63 #define SCLK_TIMER07 97
64 #define SCLK_TIMER08 98
65 #define SCLK_TIMER09 99
66 #define SCLK_TIMER10 100
67 #define SCLK_TIMER11 101
68 #define SCLK_MACREF 102
69 #define SCLK_MAC_RX 103
70 #define SCLK_MAC_TX 104
71 #define SCLK_MAC 105
72 #define SCLK_MACREF_OUT 106
73 #define SCLK_VOP0_PWM 107
74 #define SCLK_VOP1_PWM 108
75 #define SCLK_RGA_CORE 109
76 #define SCLK_ISP0 110
77 #define SCLK_ISP1 111
78 #define SCLK_HDMI_CEC 112
79 #define SCLK_HDMI_SFR 113
80 #define SCLK_DP_CORE 114
81 #define SCLK_PVTM_CORE_L 115
82 #define SCLK_PVTM_CORE_B 116
83 #define SCLK_PVTM_GPU 117
84 #define SCLK_PVTM_DDR 118
85 #define SCLK_MIPIDPHY_REF 119
86 #define SCLK_MIPIDPHY_CFG 120
87 #define SCLK_HSICPHY 121
88 #define SCLK_USBPHY480M 122
89 #define SCLK_USB2PHY0_REF 123
90 #define SCLK_USB2PHY1_REF 124
91 #define SCLK_UPHY0_TCPDPHY_REF 125
92 #define SCLK_UPHY0_TCPDCORE 126
93 #define SCLK_UPHY1_TCPDPHY_REF 127
94 #define SCLK_UPHY1_TCPDCORE 128
95 #define SCLK_USB3OTG0_REF 129
96 #define SCLK_USB3OTG1_REF 130
97 #define SCLK_USB3OTG0_SUSPEND 131
98 #define SCLK_USB3OTG1_SUSPEND 132
99 #define SCLK_CRYPTO0 133
100 #define SCLK_CRYPTO1 134
101 #define SCLK_CCI_TRACE 135
102 #define SCLK_CS 136
103 #define SCLK_CIF_OUT 137
104 #define SCLK_PCIEPHY_REF 138
105 #define SCLK_PCIE_CORE 139
106 #define SCLK_M0_PERILP 140
107 #define SCLK_M0_PERILP_DEC 141
108 #define SCLK_CM0S 142
109 #define SCLK_DBG_NOC 143
110 #define SCLK_DBG_PD_CORE_B 144
111 #define SCLK_DBG_PD_CORE_L 145
112 #define SCLK_DFIMON0_TIMER 146
113 #define SCLK_DFIMON1_TIMER 147
114 #define SCLK_INTMEM0 148
115 #define SCLK_INTMEM1 149
116 #define SCLK_INTMEM2 150
117 #define SCLK_INTMEM3 151
118 #define SCLK_INTMEM4 152
119 #define SCLK_INTMEM5 153
120 #define SCLK_SDMMC_DRV 154
121 #define SCLK_SDMMC_SAMPLE 155
122 #define SCLK_SDIO_DRV 156
123 #define SCLK_SDIO_SAMPLE 157
124 #define SCLK_VDU_CORE 158
125 #define SCLK_VDU_CA 159
126 #define SCLK_PCIE_PM 160
127 #define SCLK_SPDIF_REC_DPTX 161
128 #define SCLK_DPHY_PLL 162
129 #define SCLK_DPHY_TX0_CFG 163
130 #define SCLK_DPHY_TX1RX1_CFG 164
131 #define SCLK_DPHY_RX0_CFG 165
132 #define SCLK_RMII_SRC 166
133 #define SCLK_PCIEPHY_REF100M 167
134
135 #define DCLK_VOP0 180
136 #define DCLK_VOP1 181
137 #define DCLK_VOP0_DIV 182
138 #define DCLK_VOP1_DIV 183
139 #define DCLK_M0_PERILP 184
140
141 #define FCLK_CM0S 190
142
143 /* aclk gates */
144 #define ACLK_PERIHP 192
145 #define ACLK_PERIHP_NOC 193
146 #define ACLK_PERILP0 194
147 #define ACLK_PERILP0_NOC 195
148 #define ACLK_PERF_PCIE 196
149 #define ACLK_PCIE 197
150 #define ACLK_INTMEM 198
151 #define ACLK_TZMA 199
152 #define ACLK_DCF 200
153 #define ACLK_CCI 201
154 #define ACLK_CCI_NOC0 202
155 #define ACLK_CCI_NOC1 203
156 #define ACLK_CCI_GRF 204
157 #define ACLK_CENTER 205
158 #define ACLK_CENTER_MAIN_NOC 206
159 #define ACLK_CENTER_PERI_NOC 207
160 #define ACLK_GPU 208
161 #define ACLK_PERF_GPU 209
162 #define ACLK_GPU_GRF 210
163 #define ACLK_DMAC0_PERILP 211
164 #define ACLK_DMAC1_PERILP 212
165 #define ACLK_GMAC 213
166 #define ACLK_GMAC_NOC 214
167 #define ACLK_PERF_GMAC 215
168 #define ACLK_VOP0_NOC 216
169 #define ACLK_VOP0 217
170 #define ACLK_VOP1_NOC 218
171 #define ACLK_VOP1 219
172 #define ACLK_RGA 220
173 #define ACLK_RGA_NOC 221
174 #define ACLK_HDCP 222
175 #define ACLK_HDCP_NOC 223
176 #define ACLK_HDCP22 224
177 #define ACLK_IEP 225
178 #define ACLK_IEP_NOC 226
179 #define ACLK_VIO 227
180 #define ACLK_VIO_NOC 228
181 #define ACLK_ISP0 229
182 #define ACLK_ISP1 230
183 #define ACLK_ISP0_NOC 231
184 #define ACLK_ISP1_NOC 232
185 #define ACLK_ISP0_WRAPPER 233
186 #define ACLK_ISP1_WRAPPER 234
187 #define ACLK_VCODEC 235
188 #define ACLK_VCODEC_NOC 236
189 #define ACLK_VDU 237
190 #define ACLK_VDU_NOC 238
191 #define ACLK_PERI 239
192 #define ACLK_EMMC 240
193 #define ACLK_EMMC_CORE 241
194 #define ACLK_EMMC_NOC 242
195 #define ACLK_EMMC_GRF 243
196 #define ACLK_USB3 244
197 #define ACLK_USB3_NOC 245
198 #define ACLK_USB3OTG0 246
199 #define ACLK_USB3OTG1 247
200 #define ACLK_USB3_RKSOC_AXI_PERF 248
201 #define ACLK_USB3_GRF 249
202 #define ACLK_GIC 250
203 #define ACLK_GIC_NOC 251
204 #define ACLK_GIC_ADB400_CORE_L_2_GIC 252
205 #define ACLK_GIC_ADB400_CORE_B_2_GIC 253
206 #define ACLK_GIC_ADB400_GIC_2_CORE_L 254
207 #define ACLK_GIC_ADB400_GIC_2_CORE_B 255
208 #define ACLK_CORE_ADB400_CORE_L_2_CCI500 256
209 #define ACLK_CORE_ADB400_CORE_B_2_CCI500 257
210 #define ACLK_ADB400M_PD_CORE_L 258
211 #define ACLK_ADB400M_PD_CORE_B 259
212 #define ACLK_PERF_CORE_L 260
213 #define ACLK_PERF_CORE_B 261
214 #define ACLK_GIC_PRE 262
215 #define ACLK_VOP0_PRE 263
216 #define ACLK_VOP1_PRE 264
217
218 /* pclk gates */
219 #define PCLK_PERIHP 320
220 #define PCLK_PERIHP_NOC 321
221 #define PCLK_PERILP0 322
222 #define PCLK_PERILP1 323
223 #define PCLK_PERILP1_NOC 324
224 #define PCLK_PERILP_SGRF 325
225 #define PCLK_PERIHP_GRF 326
226 #define PCLK_PCIE 327
227 #define PCLK_SGRF 328
228 #define PCLK_INTR_ARB 329
229 #define PCLK_CENTER_MAIN_NOC 330
230 #define PCLK_CIC 331
231 #define PCLK_COREDBG_B 332
232 #define PCLK_COREDBG_L 333
233 #define PCLK_DBG_CXCS_PD_CORE_B 334
234 #define PCLK_DCF 335
235 #define PCLK_GPIO2 336
236 #define PCLK_GPIO3 337
237 #define PCLK_GPIO4 338
238 #define PCLK_GRF 339
239 #define PCLK_HSICPHY 340
240 #define PCLK_I2C1 341
241 #define PCLK_I2C2 342
242 #define PCLK_I2C3 343
243 #define PCLK_I2C5 344
244 #define PCLK_I2C6 345
245 #define PCLK_I2C7 346
246 #define PCLK_SPI0 347
247 #define PCLK_SPI1 348
248 #define PCLK_SPI2 349
249 #define PCLK_SPI4 350
250 #define PCLK_SPI5 351
251 #define PCLK_UART0 352
252 #define PCLK_UART1 353
253 #define PCLK_UART2 354
254 #define PCLK_UART3 355
255 #define PCLK_TSADC 356
256 #define PCLK_SARADC 357
257 #define PCLK_GMAC 358
258 #define PCLK_GMAC_NOC 359
259 #define PCLK_TIMER0 360
260 #define PCLK_TIMER1 361
261 #define PCLK_EDP 362
262 #define PCLK_EDP_NOC 363
263 #define PCLK_EDP_CTRL 364
264 #define PCLK_VIO 365
265 #define PCLK_VIO_NOC 366
266 #define PCLK_VIO_GRF 367
267 #define PCLK_MIPI_DSI0 368
268 #define PCLK_MIPI_DSI1 369
269 #define PCLK_HDCP 370
270 #define PCLK_HDCP_NOC 371
271 #define PCLK_HDMI_CTRL 372
272 #define PCLK_DP_CTRL 373
273 #define PCLK_HDCP22 374
274 #define PCLK_GASKET 375
275 #define PCLK_DDR 376
276 #define PCLK_DDR_MON 377
277 #define PCLK_DDR_SGRF 378
278 #define PCLK_ISP1_WRAPPER 379
279 #define PCLK_WDT 380
280 #define PCLK_EFUSE1024NS 381
281 #define PCLK_EFUSE1024S 382
282 #define PCLK_PMU_INTR_ARB 383
283 #define PCLK_MAILBOX0 384
284 #define PCLK_USBPHY_MUX_G 385
285 #define PCLK_UPHY0_TCPHY_G 386
286 #define PCLK_UPHY0_TCPD_G 387
287 #define PCLK_UPHY1_TCPHY_G 388
288 #define PCLK_UPHY1_TCPD_G 389
289 #define PCLK_ALIVE 390
290
291 /* hclk gates */
292 #define HCLK_PERIHP 448
293 #define HCLK_PERILP0 449
294 #define HCLK_PERILP1 450
295 #define HCLK_PERILP0_NOC 451
296 #define HCLK_PERILP1_NOC 452
297 #define HCLK_M0_PERILP 453
298 #define HCLK_M0_PERILP_NOC 454
299 #define HCLK_AHB1TOM 455
300 #define HCLK_HOST0 456
301 #define HCLK_HOST0_ARB 457
302 #define HCLK_HOST1 458
303 #define HCLK_HOST1_ARB 459
304 #define HCLK_HSIC 460
305 #define HCLK_SD 461
306 #define HCLK_SDMMC 462
307 #define HCLK_SDMMC_NOC 463
308 #define HCLK_M_CRYPTO0 464
309 #define HCLK_M_CRYPTO1 465
310 #define HCLK_S_CRYPTO0 466
311 #define HCLK_S_CRYPTO1 467
312 #define HCLK_I2S0_8CH 468
313 #define HCLK_I2S1_8CH 469
314 #define HCLK_I2S2_8CH 470
315 #define HCLK_SPDIF 471
316 #define HCLK_VOP0_NOC 472
317 #define HCLK_VOP0 473
318 #define HCLK_VOP1_NOC 474
319 #define HCLK_VOP1 475
320 #define HCLK_ROM 476
321 #define HCLK_IEP 477
322 #define HCLK_IEP_NOC 478
323 #define HCLK_ISP0 479
324 #define HCLK_ISP1 480
325 #define HCLK_ISP0_NOC 481
326 #define HCLK_ISP1_NOC 482
327 #define HCLK_ISP0_WRAPPER 483
328 #define HCLK_ISP1_WRAPPER 484
329 #define HCLK_RGA 485
330 #define HCLK_RGA_NOC 486
331 #define HCLK_HDCP 487
332 #define HCLK_HDCP_NOC 488
333 #define HCLK_HDCP22 489
334 #define HCLK_VCODEC 490
335 #define HCLK_VCODEC_NOC 491
336 #define HCLK_VDU 492
337 #define HCLK_VDU_NOC 493
338 #define HCLK_SDIO 494
339 #define HCLK_SDIO_NOC 495
340 #define HCLK_SDIOAUDIO_NOC 496
341
342 #define CLK_NR_CLKS (HCLK_SDIOAUDIO_NOC + 1)
343
344 /* pmu-clocks indices */
345
346 #define PLL_PPLL 1
347
348 #define SCLK_32K_SUSPEND_PMU 2
349 #define SCLK_SPI3_PMU 3
350 #define SCLK_TIMER12_PMU 4
351 #define SCLK_TIMER13_PMU 5
352 #define SCLK_UART4_PMU 6
353 #define SCLK_PVTM_PMU 7
354 #define SCLK_WIFI_PMU 8
355 #define SCLK_I2C0_PMU 9
356 #define SCLK_I2C4_PMU 10
357 #define SCLK_I2C8_PMU 11
358
359 #define PCLK_SRC_PMU 19
360 #define PCLK_PMU 20
361 #define PCLK_PMUGRF_PMU 21
362 #define PCLK_INTMEM1_PMU 22
363 #define PCLK_GPIO0_PMU 23
364 #define PCLK_GPIO1_PMU 24
365 #define PCLK_SGRF_PMU 25
366 #define PCLK_NOC_PMU 26
367 #define PCLK_I2C0_PMU 27
368 #define PCLK_I2C4_PMU 28
369 #define PCLK_I2C8_PMU 29
370 #define PCLK_RKPWM_PMU 30
371 #define PCLK_SPI3_PMU 31
372 #define PCLK_TIMER_PMU 32
373 #define PCLK_MAILBOX_PMU 33
374 #define PCLK_UART4_PMU 34
375 #define PCLK_WDT_M0_PMU 35
376
377 #define FCLK_CM0S_SRC_PMU 44
378 #define FCLK_CM0S_PMU 45
379 #define SCLK_CM0S_PMU 46
380 #define HCLK_CM0S_PMU 47
381 #define DCLK_CM0S_PMU 48
382 #define PCLK_INTR_ARB_PMU 49
383 #define HCLK_NOC_PMU 50
384
385 #define CLKPMU_NR_CLKS (HCLK_NOC_PMU + 1)
386
387 /* soft-reset indices */
388
389 /* cru_softrst_con0 */
390 #define SRST_CORE_L0 0
391 #define SRST_CORE_B0 1
392 #define SRST_CORE_PO_L0 2
393 #define SRST_CORE_PO_B0 3
394 #define SRST_L2_L 4
395 #define SRST_L2_B 5
396 #define SRST_ADB_L 6
397 #define SRST_ADB_B 7
398 #define SRST_A_CCI 8
399 #define SRST_A_CCIM0_NOC 9
400 #define SRST_A_CCIM1_NOC 10
401 #define SRST_DBG_NOC 11
402
403 /* cru_softrst_con1 */
404 #define SRST_CORE_L0_T 16
405 #define SRST_CORE_L1 17
406 #define SRST_CORE_L2 18
407 #define SRST_CORE_L3 19
408 #define SRST_CORE_PO_L0_T 20
409 #define SRST_CORE_PO_L1 21
410 #define SRST_CORE_PO_L2 22
411 #define SRST_CORE_PO_L3 23
412 #define SRST_A_ADB400_GIC2COREL 24
413 #define SRST_A_ADB400_COREL2GIC 25
414 #define SRST_P_DBG_L 26
415 #define SRST_L2_L_T 28
416 #define SRST_ADB_L_T 29
417 #define SRST_A_RKPERF_L 30
418 #define SRST_PVTM_CORE_L 31
419
420 /* cru_softrst_con2 */
421 #define SRST_CORE_B0_T 32
422 #define SRST_CORE_B1 33
423 #define SRST_CORE_PO_B0_T 36
424 #define SRST_CORE_PO_B1 37
425 #define SRST_A_ADB400_GIC2COREB 40
426 #define SRST_A_ADB400_COREB2GIC 41
427 #define SRST_P_DBG_B 42
428 #define SRST_L2_B_T 43
429 #define SRST_ADB_B_T 45
430 #define SRST_A_RKPERF_B 46
431 #define SRST_PVTM_CORE_B 47
432
433 /* cru_softrst_con3 */
434 #define SRST_A_CCI_T 50
435 #define SRST_A_CCIM0_NOC_T 51
436 #define SRST_A_CCIM1_NOC_T 52
437 #define SRST_A_ADB400M_PD_CORE_B_T 53
438 #define SRST_A_ADB400M_PD_CORE_L_T 54
439 #define SRST_DBG_NOC_T 55
440 #define SRST_DBG_CXCS 56
441 #define SRST_CCI_TRACE 57
442 #define SRST_P_CCI_GRF 58
443
444 /* cru_softrst_con4 */
445 #define SRST_A_CENTER_MAIN_NOC 64
446 #define SRST_A_CENTER_PERI_NOC 65
447 #define SRST_P_CENTER_MAIN 66
448 #define SRST_P_DDRMON 67
449 #define SRST_P_CIC 68
450 #define SRST_P_CENTER_SGRF 69
451 #define SRST_DDR0_MSCH 70
452 #define SRST_DDRCFG0_MSCH 71
453 #define SRST_DDR0 72
454 #define SRST_DDRPHY0 73
455 #define SRST_DDR1_MSCH 74
456 #define SRST_DDRCFG1_MSCH 75
457 #define SRST_DDR1 76
458 #define SRST_DDRPHY1 77
459 #define SRST_DDR_CIC 78
460 #define SRST_PVTM_DDR 79
461
462 /* cru_softrst_con5 */
463 #define SRST_A_VCODEC_NOC 80
464 #define SRST_A_VCODEC 81
465 #define SRST_H_VCODEC_NOC 82
466 #define SRST_H_VCODEC 83
467 #define SRST_A_VDU_NOC 88
468 #define SRST_A_VDU 89
469 #define SRST_H_VDU_NOC 90
470 #define SRST_H_VDU 91
471 #define SRST_VDU_CORE 92
472 #define SRST_VDU_CA 93
473
474 /* cru_softrst_con6 */
475 #define SRST_A_IEP_NOC 96
476 #define SRST_A_VOP_IEP 97
477 #define SRST_A_IEP 98
478 #define SRST_H_IEP_NOC 99
479 #define SRST_H_IEP 100
480 #define SRST_A_RGA_NOC 102
481 #define SRST_A_RGA 103
482 #define SRST_H_RGA_NOC 104
483 #define SRST_H_RGA 105
484 #define SRST_RGA_CORE 106
485 #define SRST_EMMC_NOC 108
486 #define SRST_EMMC 109
487 #define SRST_EMMC_GRF 110
488
489 /* cru_softrst_con7 */
490 #define SRST_A_PERIHP_NOC 112
491 #define SRST_P_PERIHP_GRF 113
492 #define SRST_H_PERIHP_NOC 114
493 #define SRST_USBHOST0 115
494 #define SRST_HOSTC0_AUX 116
495 #define SRST_HOST0_ARB 117
496 #define SRST_USBHOST1 118
497 #define SRST_HOSTC1_AUX 119
498 #define SRST_HOST1_ARB 120
499 #define SRST_SDIO0 121
500 #define SRST_SDMMC 122
501 #define SRST_HSIC 123
502 #define SRST_HSIC_AUX 124
503 #define SRST_AHB1TOM 125
504 #define SRST_P_PERIHP_NOC 126
505 #define SRST_HSICPHY 127
506
507 /* cru_softrst_con8 */
508 #define SRST_A_PCIE 128
509 #define SRST_P_PCIE 129
510 #define SRST_PCIE_CORE 130
511 #define SRST_PCIE_MGMT 131
512 #define SRST_PCIE_MGMT_STICKY 132
513 #define SRST_PCIE_PIPE 133
514 #define SRST_PCIE_PM 134
515 #define SRST_PCIEPHY 135
516 #define SRST_A_GMAC_NOC 136
517 #define SRST_A_GMAC 137
518 #define SRST_P_GMAC_NOC 138
519 #define SRST_P_GMAC_GRF 140
520 #define SRST_HSICPHY_POR 142
521 #define SRST_HSICPHY_UTMI 143
522
523 /* cru_softrst_con9 */
524 #define SRST_USB2PHY0_POR 144
525 #define SRST_USB2PHY0_UTMI_PORT0 145
526 #define SRST_USB2PHY0_UTMI_PORT1 146
527 #define SRST_USB2PHY0_EHCIPHY 147
528 #define SRST_UPHY0_PIPE_L00 148
529 #define SRST_UPHY0 149
530 #define SRST_UPHY0_TCPDPWRUP 150
531 #define SRST_USB2PHY1_POR 152
532 #define SRST_USB2PHY1_UTMI_PORT0 153
533 #define SRST_USB2PHY1_UTMI_PORT1 154
534 #define SRST_USB2PHY1_EHCIPHY 155
535 #define SRST_UPHY1_PIPE_L00 156
536 #define SRST_UPHY1 157
537 #define SRST_UPHY1_TCPDPWRUP 158
538
539 /* cru_softrst_con10 */
540 #define SRST_A_PERILP0_NOC 160
541 #define SRST_A_DCF 161
542 #define SRST_GIC500 162
543 #define SRST_DMAC0_PERILP0 163
544 #define SRST_DMAC1_PERILP0 164
545 #define SRST_TZMA 165
546 #define SRST_INTMEM 166
547 #define SRST_ADB400_MST0 167
548 #define SRST_ADB400_MST1 168
549 #define SRST_ADB400_SLV0 169
550 #define SRST_ADB400_SLV1 170
551 #define SRST_H_PERILP0 171
552 #define SRST_H_PERILP0_NOC 172
553 #define SRST_ROM 173
554 #define SRST_CRYPTO_S 174
555 #define SRST_CRYPTO_M 175
556
557 /* cru_softrst_con11 */
558 #define SRST_P_DCF 176
559 #define SRST_CM0S_NOC 177
560 #define SRST_CM0S 178
561 #define SRST_CM0S_DBG 179
562 #define SRST_CM0S_PO 180
563 #define SRST_CRYPTO 181
564 #define SRST_P_PERILP1_SGRF 182
565 #define SRST_P_PERILP1_GRF 183
566 #define SRST_CRYPTO1_S 184
567 #define SRST_CRYPTO1_M 185
568 #define SRST_CRYPTO1 186
569 #define SRST_GIC_NOC 188
570 #define SRST_SD_NOC 189
571 #define SRST_SDIOAUDIO_BRG 190
572
573 /* cru_softrst_con12 */
574 #define SRST_H_PERILP1 192
575 #define SRST_H_PERILP1_NOC 193
576 #define SRST_H_I2S0_8CH 194
577 #define SRST_H_I2S1_8CH 195
578 #define SRST_H_I2S2_8CH 196
579 #define SRST_H_SPDIF_8CH 197
580 #define SRST_P_PERILP1_NOC 198
581 #define SRST_P_EFUSE_1024 199
582 #define SRST_P_EFUSE_1024S 200
583 #define SRST_P_I2C0 201
584 #define SRST_P_I2C1 202
585 #define SRST_P_I2C2 203
586 #define SRST_P_I2C3 204
587 #define SRST_P_I2C4 205
588 #define SRST_P_I2C5 206
589 #define SRST_P_MAILBOX0 207
590
591 /* cru_softrst_con13 */
592 #define SRST_P_UART0 208
593 #define SRST_P_UART1 209
594 #define SRST_P_UART2 210
595 #define SRST_P_UART3 211
596 #define SRST_P_SARADC 212
597 #define SRST_P_TSADC 213
598 #define SRST_P_SPI0 214
599 #define SRST_P_SPI1 215
600 #define SRST_P_SPI2 216
601 #define SRST_P_SPI3 217
602 #define SRST_P_SPI4 218
603 #define SRST_SPI0 219
604 #define SRST_SPI1 220
605 #define SRST_SPI2 221
606 #define SRST_SPI3 222
607 #define SRST_SPI4 223
608
609 /* cru_softrst_con14 */
610 #define SRST_I2S0_8CH 224
611 #define SRST_I2S1_8CH 225
612 #define SRST_I2S2_8CH 226
613 #define SRST_SPDIF_8CH 227
614 #define SRST_UART0 228
615 #define SRST_UART1 229
616 #define SRST_UART2 230
617 #define SRST_UART3 231
618 #define SRST_TSADC 232
619 #define SRST_I2C0 233
620 #define SRST_I2C1 234
621 #define SRST_I2C2 235
622 #define SRST_I2C3 236
623 #define SRST_I2C4 237
624 #define SRST_I2C5 238
625 #define SRST_SDIOAUDIO_NOC 239
626
627 /* cru_softrst_con15 */
628 #define SRST_A_VIO_NOC 240
629 #define SRST_A_HDCP_NOC 241
630 #define SRST_A_HDCP 242
631 #define SRST_H_HDCP_NOC 243
632 #define SRST_H_HDCP 244
633 #define SRST_P_HDCP_NOC 245
634 #define SRST_P_HDCP 246
635 #define SRST_P_HDMI_CTRL 247
636 #define SRST_P_DP_CTRL 248
637 #define SRST_S_DP_CTRL 249
638 #define SRST_C_DP_CTRL 250
639 #define SRST_P_MIPI_DSI0 251
640 #define SRST_P_MIPI_DSI1 252
641 #define SRST_DP_CORE 253
642 #define SRST_DP_I2S 254
643
644 /* cru_softrst_con16 */
645 #define SRST_GASKET 256
646 #define SRST_VIO_GRF 258
647 #define SRST_DPTX_SPDIF_REC 259
648 #define SRST_HDMI_CTRL 260
649 #define SRST_HDCP_CTRL 261
650 #define SRST_A_ISP0_NOC 262
651 #define SRST_A_ISP1_NOC 263
652 #define SRST_H_ISP0_NOC 266
653 #define SRST_H_ISP1_NOC 267
654 #define SRST_H_ISP0 268
655 #define SRST_H_ISP1 269
656 #define SRST_ISP0 270
657 #define SRST_ISP1 271
658
659 /* cru_softrst_con17 */
660 #define SRST_A_VOP0_NOC 272
661 #define SRST_A_VOP1_NOC 273
662 #define SRST_A_VOP0 274
663 #define SRST_A_VOP1 275
664 #define SRST_H_VOP0_NOC 276
665 #define SRST_H_VOP1_NOC 277
666 #define SRST_H_VOP0 278
667 #define SRST_H_VOP1 279
668 #define SRST_D_VOP0 280
669 #define SRST_D_VOP1 281
670 #define SRST_VOP0_PWM 282
671 #define SRST_VOP1_PWM 283
672 #define SRST_P_EDP_NOC 284
673 #define SRST_P_EDP_CTRL 285
674
675 /* cru_softrst_con18 */
676 #define SRST_A_GPU 288
677 #define SRST_A_GPU_NOC 289
678 #define SRST_A_GPU_GRF 290
679 #define SRST_PVTM_GPU 291
680 #define SRST_A_USB3_NOC 292
681 #define SRST_A_USB3_OTG0 293
682 #define SRST_A_USB3_OTG1 294
683 #define SRST_A_USB3_GRF 295
684 #define SRST_PMU 296
685
686 /* cru_softrst_con19 */
687 #define SRST_P_TIMER0_5 304
688 #define SRST_TIMER0 305
689 #define SRST_TIMER1 306
690 #define SRST_TIMER2 307
691 #define SRST_TIMER3 308
692 #define SRST_TIMER4 309
693 #define SRST_TIMER5 310
694 #define SRST_P_TIMER6_11 311
695 #define SRST_TIMER6 312
696 #define SRST_TIMER7 313
697 #define SRST_TIMER8 314
698 #define SRST_TIMER9 315
699 #define SRST_TIMER10 316
700 #define SRST_TIMER11 317
701 #define SRST_P_INTR_ARB_PMU 318
702 #define SRST_P_ALIVE_SGRF 319
703
704 /* cru_softrst_con20 */
705 #define SRST_P_GPIO2 320
706 #define SRST_P_GPIO3 321
707 #define SRST_P_GPIO4 322
708 #define SRST_P_GRF 323
709 #define SRST_P_ALIVE_NOC 324
710 #define SRST_P_WDT0 325
711 #define SRST_P_WDT1 326
712 #define SRST_P_INTR_ARB 327
713 #define SRST_P_UPHY0_DPTX 328
714 #define SRST_P_UPHY0_APB 330
715 #define SRST_P_UPHY0_TCPHY 332
716 #define SRST_P_UPHY1_TCPHY 333
717 #define SRST_P_UPHY0_TCPDCTRL 334
718 #define SRST_P_UPHY1_TCPDCTRL 335
719
720 /* pmu soft-reset indices */
721
722 /* pmu_cru_softrst_con0 */
723 #define SRST_P_NOC 0
724 #define SRST_P_INTMEM 1
725 #define SRST_H_CM0S 2
726 #define SRST_H_CM0S_NOC 3
727 #define SRST_DBG_CM0S 4
728 #define SRST_PO_CM0S 5
729 #define SRST_P_SPI6 6
730 #define SRST_SPI6 7
731 #define SRST_P_TIMER_0_1 8
732 #define SRST_P_TIMER_0 9
733 #define SRST_P_TIMER_1 10
734 #define SRST_P_UART4 11
735 #define SRST_UART4 12
736 #define SRST_P_WDT 13
737
738 /* pmu_cru_softrst_con1 */
739 #define SRST_P_I2C6 16
740 #define SRST_P_I2C7 17
741 #define SRST_P_I2C8 18
742 #define SRST_P_MAILBOX 19
743 #define SRST_P_RKPWM 20
744 #define SRST_P_PMUGRF 21
745 #define SRST_P_SGRF 22
746 #define SRST_P_GPIO0 23
747 #define SRST_P_GPIO1 24
748 #define SRST_P_CRU 25
749 #define SRST_P_INTR 26
750 #define SRST_PVTM 27
751 #define SRST_I2C6 28
752 #define SRST_I2C7 29
753 #define SRST_I2C8 30
754
755 #endif
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