include/gdb/sim-riscv.h

   1 /* This file defines the interface between the RISC-V simulator and GDB.
   2
   3    Copyright (C) 2005-2022 Free Software Foundation, Inc.
   4    Contributed by Mike Frysinger.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 /* Order has to match gdb riscv-tdep list.  */
  22 enum sim_riscv_regnum {
  23   SIM_RISCV_ZERO_REGNUM = 0,
  24   SIM_RISCV_RA_REGNUM,
  25   SIM_RISCV_SP_REGNUM,
  26   SIM_RISCV_GP_REGNUM,
  27   SIM_RISCV_TP_REGNUM,
  28   SIM_RISCV_T0_REGNUM,
  29   SIM_RISCV_T1_REGNUM,
  30   SIM_RISCV_T2_REGNUM,
  31   SIM_RISCV_S0_REGNUM,
  32 #define SIM_RISCV_FP_REGNUM SIM_RISCV_S0_REGNUM
  33   SIM_RISCV_S1_REGNUM,
  34   SIM_RISCV_A0_REGNUM,
  35   SIM_RISCV_A1_REGNUM,
  36   SIM_RISCV_A2_REGNUM,
  37   SIM_RISCV_A3_REGNUM,
  38   SIM_RISCV_A4_REGNUM,
  39   SIM_RISCV_A5_REGNUM,
  40   SIM_RISCV_A6_REGNUM,
  41   SIM_RISCV_A7_REGNUM,
  42   SIM_RISCV_S2_REGNUM,
  43   SIM_RISCV_S3_REGNUM,
  44   SIM_RISCV_S4_REGNUM,
  45   SIM_RISCV_S5_REGNUM,
  46   SIM_RISCV_S6_REGNUM,
  47   SIM_RISCV_S7_REGNUM,
  48   SIM_RISCV_S8_REGNUM,
  49   SIM_RISCV_S9_REGNUM,
  50   SIM_RISCV_S10_REGNUM,
  51   SIM_RISCV_S11_REGNUM,
  52   SIM_RISCV_T3_REGNUM,
  53   SIM_RISCV_T4_REGNUM,
  54   SIM_RISCV_T5_REGNUM,
  55   SIM_RISCV_T6_REGNUM,
  56   SIM_RISCV_PC_REGNUM,
  57   SIM_RISCV_FT0_REGNUM,
  58 #define SIM_RISCV_FIRST_FP_REGNUM SIM_RISCV_FT0_REGNUM
  59   SIM_RISCV_FT1_REGNUM,
  60   SIM_RISCV_FT2_REGNUM,
  61   SIM_RISCV_FT3_REGNUM,
  62   SIM_RISCV_FT4_REGNUM,
  63   SIM_RISCV_FT5_REGNUM,
  64   SIM_RISCV_FT6_REGNUM,
  65   SIM_RISCV_FT7_REGNUM,
  66   SIM_RISCV_FS0_REGNUM,
  67   SIM_RISCV_FS1_REGNUM,
  68   SIM_RISCV_FA0_REGNUM,
  69   SIM_RISCV_FA1_REGNUM,
  70   SIM_RISCV_FA2_REGNUM,
  71   SIM_RISCV_FA3_REGNUM,
  72   SIM_RISCV_FA4_REGNUM,
  73   SIM_RISCV_FA5_REGNUM,
  74   SIM_RISCV_FA6_REGNUM,
  75   SIM_RISCV_FA7_REGNUM,
  76   SIM_RISCV_FS2_REGNUM,
  77   SIM_RISCV_FS3_REGNUM,
  78   SIM_RISCV_FS4_REGNUM,
  79   SIM_RISCV_FS5_REGNUM,
  80   SIM_RISCV_FS6_REGNUM,
  81   SIM_RISCV_FS7_REGNUM,
  82   SIM_RISCV_FS8_REGNUM,
  83   SIM_RISCV_FS9_REGNUM,
  84   SIM_RISCV_FS10_REGNUM,
  85   SIM_RISCV_FS11_REGNUM,
  86   SIM_RISCV_FT8_REGNUM,
  87   SIM_RISCV_FT9_REGNUM,
  88   SIM_RISCV_FT10_REGNUM,
  89   SIM_RISCV_FT11_REGNUM,
  90 #define SIM_RISCV_LAST_FP_REGNUM SIM_RISCV_FT11_REGNUM
  91
  92 #define SIM_RISCV_FIRST_CSR_REGNUM SIM_RISCV_LAST_FP_REGNUM + 1
  93 #define DECLARE_CSR(name, num, ...) SIM_RISCV_ ## num ## _REGNUM,
  94 #include "opcode/riscv-opc.h"
  95 #undef DECLARE_CSR
  96 #define SIM_RISCV_LAST_CSR_REGNUM SIM_RISCV_LAST_REGNUM - 1
  97
  98   SIM_RISCV_LAST_REGNUM
  99 };