2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/types.h>
37 #include <rdma/ib_verbs.h>
38 #include <linux/mlx5/mlx5_ifc.h>
40 #if defined(__LITTLE_ENDIAN)
41 #define MLX5_SET_HOST_ENDIANNESS 0
42 #elif defined(__BIG_ENDIAN)
43 #define MLX5_SET_HOST_ENDIANNESS 0x80
45 #error Host endianness not defined
49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
52 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
53 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
59 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
60 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
61 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
62 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
63 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
64 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
65 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
67 /* insert a value to a struct */
68 #define MLX5_SET(typ, p, fld, v) do { \
69 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
70 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
71 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
72 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
73 << __mlx5_dw_bit_off(typ, fld))); \
76 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
77 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
78 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
79 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
80 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
81 << __mlx5_dw_bit_off(typ, fld))); \
84 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
85 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
86 __mlx5_mask(typ, fld))
88 #define MLX5_GET_PR(typ, p, fld) ({ \
89 u32 ___t = MLX5_GET(typ, p, fld); \
90 pr_debug(#fld " = 0x%x\n", ___t); \
94 #define MLX5_SET64(typ, p, fld, v) do { \
95 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
96 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
97 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
100 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
103 MLX5_MAX_COMMANDS
= 32,
104 MLX5_CMD_DATA_BLOCK_SIZE
= 512,
105 MLX5_PCI_CMD_XPORT
= 7,
106 MLX5_MKEY_BSF_OCTO_SIZE
= 4,
111 MLX5_EXTENDED_UD_AV
= 0x80000000,
115 MLX5_CQ_STATE_ARMED
= 9,
116 MLX5_CQ_STATE_ALWAYS_ARMED
= 0xb,
117 MLX5_CQ_STATE_FIRED
= 0xa,
121 MLX5_STAT_RATE_OFFSET
= 5,
125 MLX5_INLINE_SEG
= 0x80000000,
129 MLX5_MIN_PKEY_TABLE_SIZE
= 128,
130 MLX5_MAX_LOG_PKEY_TABLE
= 5,
134 MLX5_MKEY_INBOX_PG_ACCESS
= 1 << 31
138 MLX5_PFAULT_SUBTYPE_WQE
= 0,
139 MLX5_PFAULT_SUBTYPE_RDMA
= 1,
143 MLX5_PERM_LOCAL_READ
= 1 << 2,
144 MLX5_PERM_LOCAL_WRITE
= 1 << 3,
145 MLX5_PERM_REMOTE_READ
= 1 << 4,
146 MLX5_PERM_REMOTE_WRITE
= 1 << 5,
147 MLX5_PERM_ATOMIC
= 1 << 6,
148 MLX5_PERM_UMR_EN
= 1 << 7,
152 MLX5_PCIE_CTRL_SMALL_FENCE
= 1 << 0,
153 MLX5_PCIE_CTRL_RELAXED_ORDERING
= 1 << 2,
154 MLX5_PCIE_CTRL_NO_SNOOP
= 1 << 3,
155 MLX5_PCIE_CTRL_TLP_PROCE_EN
= 1 << 6,
156 MLX5_PCIE_CTRL_TPH_MASK
= 3 << 4,
160 MLX5_ACCESS_MODE_PA
= 0,
161 MLX5_ACCESS_MODE_MTT
= 1,
162 MLX5_ACCESS_MODE_KLM
= 2
166 MLX5_MKEY_REMOTE_INVAL
= 1 << 24,
167 MLX5_MKEY_FLAG_SYNC_UMR
= 1 << 29,
168 MLX5_MKEY_BSF_EN
= 1 << 30,
169 MLX5_MKEY_LEN64
= 1 << 31,
178 MLX5_BF_REGS_PER_PAGE
= 4,
179 MLX5_MAX_UAR_PAGES
= 1 << 8,
180 MLX5_NON_FP_BF_REGS_PER_PAGE
= 2,
181 MLX5_MAX_UUARS
= MLX5_MAX_UAR_PAGES
* MLX5_NON_FP_BF_REGS_PER_PAGE
,
185 MLX5_MKEY_MASK_LEN
= 1ull << 0,
186 MLX5_MKEY_MASK_PAGE_SIZE
= 1ull << 1,
187 MLX5_MKEY_MASK_START_ADDR
= 1ull << 6,
188 MLX5_MKEY_MASK_PD
= 1ull << 7,
189 MLX5_MKEY_MASK_EN_RINVAL
= 1ull << 8,
190 MLX5_MKEY_MASK_EN_SIGERR
= 1ull << 9,
191 MLX5_MKEY_MASK_BSF_EN
= 1ull << 12,
192 MLX5_MKEY_MASK_KEY
= 1ull << 13,
193 MLX5_MKEY_MASK_QPN
= 1ull << 14,
194 MLX5_MKEY_MASK_LR
= 1ull << 17,
195 MLX5_MKEY_MASK_LW
= 1ull << 18,
196 MLX5_MKEY_MASK_RR
= 1ull << 19,
197 MLX5_MKEY_MASK_RW
= 1ull << 20,
198 MLX5_MKEY_MASK_A
= 1ull << 21,
199 MLX5_MKEY_MASK_SMALL_FENCE
= 1ull << 23,
200 MLX5_MKEY_MASK_FREE
= 1ull << 29,
204 MLX5_UMR_TRANSLATION_OFFSET_EN
= (1 << 4),
206 MLX5_UMR_CHECK_NOT_FREE
= (1 << 5),
207 MLX5_UMR_CHECK_FREE
= (2 << 5),
209 MLX5_UMR_INLINE
= (1 << 7),
212 #define MLX5_UMR_MTT_ALIGNMENT 0x40
213 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
214 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
217 MLX5_EVENT_TYPE_COMP
= 0x0,
219 MLX5_EVENT_TYPE_PATH_MIG
= 0x01,
220 MLX5_EVENT_TYPE_COMM_EST
= 0x02,
221 MLX5_EVENT_TYPE_SQ_DRAINED
= 0x03,
222 MLX5_EVENT_TYPE_SRQ_LAST_WQE
= 0x13,
223 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT
= 0x14,
225 MLX5_EVENT_TYPE_CQ_ERROR
= 0x04,
226 MLX5_EVENT_TYPE_WQ_CATAS_ERROR
= 0x05,
227 MLX5_EVENT_TYPE_PATH_MIG_FAILED
= 0x07,
228 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR
= 0x10,
229 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR
= 0x11,
230 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR
= 0x12,
232 MLX5_EVENT_TYPE_INTERNAL_ERROR
= 0x08,
233 MLX5_EVENT_TYPE_PORT_CHANGE
= 0x09,
234 MLX5_EVENT_TYPE_GPIO_EVENT
= 0x15,
235 MLX5_EVENT_TYPE_REMOTE_CONFIG
= 0x19,
237 MLX5_EVENT_TYPE_DB_BF_CONGESTION
= 0x1a,
238 MLX5_EVENT_TYPE_STALL_EVENT
= 0x1b,
240 MLX5_EVENT_TYPE_CMD
= 0x0a,
241 MLX5_EVENT_TYPE_PAGE_REQUEST
= 0xb,
243 MLX5_EVENT_TYPE_PAGE_FAULT
= 0xc,
247 MLX5_PORT_CHANGE_SUBTYPE_DOWN
= 1,
248 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE
= 4,
249 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED
= 5,
250 MLX5_PORT_CHANGE_SUBTYPE_LID
= 6,
251 MLX5_PORT_CHANGE_SUBTYPE_PKEY
= 7,
252 MLX5_PORT_CHANGE_SUBTYPE_GUID
= 8,
253 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG
= 9,
257 MLX5_DEV_CAP_FLAG_XRC
= 1LL << 3,
258 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR
= 1LL << 8,
259 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR
= 1LL << 9,
260 MLX5_DEV_CAP_FLAG_APM
= 1LL << 17,
261 MLX5_DEV_CAP_FLAG_ATOMIC
= 1LL << 18,
262 MLX5_DEV_CAP_FLAG_BLOCK_MCAST
= 1LL << 23,
263 MLX5_DEV_CAP_FLAG_ON_DMND_PG
= 1LL << 24,
264 MLX5_DEV_CAP_FLAG_CQ_MODER
= 1LL << 29,
265 MLX5_DEV_CAP_FLAG_RESIZE_CQ
= 1LL << 30,
266 MLX5_DEV_CAP_FLAG_DCT
= 1LL << 37,
267 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER
= 1LL << 40,
268 MLX5_DEV_CAP_FLAG_CMDIF_CSUM
= 3LL << 46,
272 MLX5_OPCODE_NOP
= 0x00,
273 MLX5_OPCODE_SEND_INVAL
= 0x01,
274 MLX5_OPCODE_RDMA_WRITE
= 0x08,
275 MLX5_OPCODE_RDMA_WRITE_IMM
= 0x09,
276 MLX5_OPCODE_SEND
= 0x0a,
277 MLX5_OPCODE_SEND_IMM
= 0x0b,
278 MLX5_OPCODE_LSO
= 0x0e,
279 MLX5_OPCODE_RDMA_READ
= 0x10,
280 MLX5_OPCODE_ATOMIC_CS
= 0x11,
281 MLX5_OPCODE_ATOMIC_FA
= 0x12,
282 MLX5_OPCODE_ATOMIC_MASKED_CS
= 0x14,
283 MLX5_OPCODE_ATOMIC_MASKED_FA
= 0x15,
284 MLX5_OPCODE_BIND_MW
= 0x18,
285 MLX5_OPCODE_CONFIG_CMD
= 0x1f,
287 MLX5_RECV_OPCODE_RDMA_WRITE_IMM
= 0x00,
288 MLX5_RECV_OPCODE_SEND
= 0x01,
289 MLX5_RECV_OPCODE_SEND_IMM
= 0x02,
290 MLX5_RECV_OPCODE_SEND_INVAL
= 0x03,
292 MLX5_CQE_OPCODE_ERROR
= 0x1e,
293 MLX5_CQE_OPCODE_RESIZE
= 0x16,
295 MLX5_OPCODE_SET_PSV
= 0x20,
296 MLX5_OPCODE_GET_PSV
= 0x21,
297 MLX5_OPCODE_CHECK_PSV
= 0x22,
298 MLX5_OPCODE_RGET_PSV
= 0x26,
299 MLX5_OPCODE_RCHECK_PSV
= 0x27,
301 MLX5_OPCODE_UMR
= 0x25,
306 MLX5_SET_PORT_RESET_QKEY
= 0,
307 MLX5_SET_PORT_GUID0
= 16,
308 MLX5_SET_PORT_NODE_GUID
= 17,
309 MLX5_SET_PORT_SYS_GUID
= 18,
310 MLX5_SET_PORT_GID_TABLE
= 19,
311 MLX5_SET_PORT_PKEY_TABLE
= 20,
315 MLX5_MAX_PAGE_SHIFT
= 31
319 MLX5_ADAPTER_PAGE_SHIFT
= 12,
320 MLX5_ADAPTER_PAGE_SIZE
= 1 << MLX5_ADAPTER_PAGE_SHIFT
,
324 MLX5_CAP_OFF_CMDIF_CSUM
= 46,
327 struct mlx5_inbox_hdr
{
333 struct mlx5_outbox_hdr
{
339 struct mlx5_cmd_query_adapter_mbox_in
{
340 struct mlx5_inbox_hdr hdr
;
344 struct mlx5_cmd_query_adapter_mbox_out
{
345 struct mlx5_outbox_hdr hdr
;
349 __be16 vsd_vendor_id
;
354 enum mlx5_odp_transport_cap_bits
{
355 MLX5_ODP_SUPPORT_SEND
= 1 << 31,
356 MLX5_ODP_SUPPORT_RECV
= 1 << 30,
357 MLX5_ODP_SUPPORT_WRITE
= 1 << 29,
358 MLX5_ODP_SUPPORT_READ
= 1 << 28,
361 struct mlx5_odp_caps
{
367 } per_transport_caps
;
368 char reserved2
[0xe4];
371 struct mlx5_cmd_init_hca_mbox_in
{
372 struct mlx5_inbox_hdr hdr
;
378 struct mlx5_cmd_init_hca_mbox_out
{
379 struct mlx5_outbox_hdr hdr
;
383 struct mlx5_cmd_teardown_hca_mbox_in
{
384 struct mlx5_inbox_hdr hdr
;
390 struct mlx5_cmd_teardown_hca_mbox_out
{
391 struct mlx5_outbox_hdr hdr
;
395 struct mlx5_cmd_layout
{
411 struct health_buffer
{
412 __be32 assert_var
[5];
414 __be32 assert_exit_ptr
;
415 __be32 assert_callra
;
425 struct mlx5_init_seg
{
427 __be32 cmdif_rev_fw_sub
;
430 __be32 cmdq_addr_l_sz
;
433 struct health_buffer health
;
435 __be32 health_counter
;
438 __be32 ieee1588_clk_type
;
442 struct mlx5_eqe_comp
{
447 struct mlx5_eqe_qp_srq
{
452 struct mlx5_eqe_cq_err
{
458 struct mlx5_eqe_port_state
{
463 struct mlx5_eqe_gpio
{
468 struct mlx5_eqe_congestion
{
474 struct mlx5_eqe_stall_vl
{
479 struct mlx5_eqe_cmd
{
484 struct mlx5_eqe_page_req
{
491 struct mlx5_eqe_page_fault
{
492 __be32 bytes_committed
;
498 __be16 packet_length
;
504 __be16 packet_length
;
514 struct mlx5_eqe_cmd cmd
;
515 struct mlx5_eqe_comp comp
;
516 struct mlx5_eqe_qp_srq qp_srq
;
517 struct mlx5_eqe_cq_err cq_err
;
518 struct mlx5_eqe_port_state port
;
519 struct mlx5_eqe_gpio gpio
;
520 struct mlx5_eqe_congestion cong
;
521 struct mlx5_eqe_stall_vl stall_vl
;
522 struct mlx5_eqe_page_req req_pages
;
523 struct mlx5_eqe_page_fault page_fault
;
538 struct mlx5_cmd_prot_block
{
539 u8 data
[MLX5_CMD_DATA_BLOCK_SIZE
];
550 MLX5_CQE_SYND_FLUSHED_IN_ERROR
= 5,
553 struct mlx5_err_cqe
{
559 __be32 s_wqe_opcode_qpn
;
567 u8 lro_tcppsh_abort_dupack
;
570 __be32 lro_ack_seq_num
;
571 __be32 rss_hash_result
;
581 __be32 srqn
; /* [31:24]: lro_num_seg, [23:0]: srqn */
582 __be32 imm_inval_pkey
;
592 static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64
*cqe
)
594 return (cqe
->lro_tcppsh_abort_dupack
>> 6) & 1;
597 static inline u8
get_cqe_l4_hdr_type(struct mlx5_cqe64
*cqe
)
599 return (cqe
->l4_hdr_type_etc
>> 4) & 0x7;
602 static inline int cqe_has_vlan(struct mlx5_cqe64
*cqe
)
604 return !!(cqe
->l4_hdr_type_etc
& 0x1);
608 CQE_L4_HDR_TYPE_NONE
= 0x0,
609 CQE_L4_HDR_TYPE_TCP_NO_ACK
= 0x1,
610 CQE_L4_HDR_TYPE_UDP
= 0x2,
611 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA
= 0x3,
612 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA
= 0x4,
616 CQE_RSS_HTYPE_IP
= 0x3 << 6,
617 CQE_RSS_HTYPE_L4
= 0x3 << 2,
626 struct mlx5_sig_err_cqe
{
628 __be32 expected_trans_sig
;
629 __be32 actual_trans_sig
;
630 __be32 expected_reftag
;
631 __be32 actual_reftag
;
643 struct mlx5_wqe_srq_next_seg
{
645 __be16 next_wqe_index
;
656 union mlx5_ext_cqe inl_grh
;
657 struct mlx5_cqe64 cqe64
;
660 struct mlx5_srq_ctx
{
675 struct mlx5_create_srq_mbox_in
{
676 struct mlx5_inbox_hdr hdr
;
679 struct mlx5_srq_ctx ctx
;
684 struct mlx5_create_srq_mbox_out
{
685 struct mlx5_outbox_hdr hdr
;
690 struct mlx5_destroy_srq_mbox_in
{
691 struct mlx5_inbox_hdr hdr
;
696 struct mlx5_destroy_srq_mbox_out
{
697 struct mlx5_outbox_hdr hdr
;
701 struct mlx5_query_srq_mbox_in
{
702 struct mlx5_inbox_hdr hdr
;
707 struct mlx5_query_srq_mbox_out
{
708 struct mlx5_outbox_hdr hdr
;
710 struct mlx5_srq_ctx ctx
;
715 struct mlx5_arm_srq_mbox_in
{
716 struct mlx5_inbox_hdr hdr
;
722 struct mlx5_arm_srq_mbox_out
{
723 struct mlx5_outbox_hdr hdr
;
727 struct mlx5_cq_context
{
734 __be32 log_sz_usr_page
;
741 __be32 last_notified_index
;
742 __be32 solicit_producer_index
;
743 __be32 consumer_counter
;
744 __be32 producer_counter
;
746 __be64 db_record_addr
;
749 struct mlx5_create_cq_mbox_in
{
750 struct mlx5_inbox_hdr hdr
;
753 struct mlx5_cq_context ctx
;
758 struct mlx5_create_cq_mbox_out
{
759 struct mlx5_outbox_hdr hdr
;
764 struct mlx5_destroy_cq_mbox_in
{
765 struct mlx5_inbox_hdr hdr
;
770 struct mlx5_destroy_cq_mbox_out
{
771 struct mlx5_outbox_hdr hdr
;
775 struct mlx5_query_cq_mbox_in
{
776 struct mlx5_inbox_hdr hdr
;
781 struct mlx5_query_cq_mbox_out
{
782 struct mlx5_outbox_hdr hdr
;
784 struct mlx5_cq_context ctx
;
789 struct mlx5_modify_cq_mbox_in
{
790 struct mlx5_inbox_hdr hdr
;
793 struct mlx5_cq_context ctx
;
798 struct mlx5_modify_cq_mbox_out
{
799 struct mlx5_outbox_hdr hdr
;
803 struct mlx5_enable_hca_mbox_in
{
804 struct mlx5_inbox_hdr hdr
;
808 struct mlx5_enable_hca_mbox_out
{
809 struct mlx5_outbox_hdr hdr
;
813 struct mlx5_disable_hca_mbox_in
{
814 struct mlx5_inbox_hdr hdr
;
818 struct mlx5_disable_hca_mbox_out
{
819 struct mlx5_outbox_hdr hdr
;
823 struct mlx5_eq_context
{
829 __be32 log_sz_usr_page
;
834 __be32 consumer_counter
;
835 __be32 produser_counter
;
839 struct mlx5_create_eq_mbox_in
{
840 struct mlx5_inbox_hdr hdr
;
844 struct mlx5_eq_context ctx
;
851 struct mlx5_create_eq_mbox_out
{
852 struct mlx5_outbox_hdr hdr
;
858 struct mlx5_destroy_eq_mbox_in
{
859 struct mlx5_inbox_hdr hdr
;
865 struct mlx5_destroy_eq_mbox_out
{
866 struct mlx5_outbox_hdr hdr
;
870 struct mlx5_map_eq_mbox_in
{
871 struct mlx5_inbox_hdr hdr
;
879 struct mlx5_map_eq_mbox_out
{
880 struct mlx5_outbox_hdr hdr
;
884 struct mlx5_query_eq_mbox_in
{
885 struct mlx5_inbox_hdr hdr
;
891 struct mlx5_query_eq_mbox_out
{
892 struct mlx5_outbox_hdr hdr
;
894 struct mlx5_eq_context ctx
;
898 MLX5_MKEY_STATUS_FREE
= 1 << 6,
901 struct mlx5_mkey_seg
{
902 /* This is a two bit field occupying bits 31-30.
903 * bit 31 is always 0,
904 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
915 __be32 bsfs_octo_size
;
923 struct mlx5_query_special_ctxs_mbox_in
{
924 struct mlx5_inbox_hdr hdr
;
928 struct mlx5_query_special_ctxs_mbox_out
{
929 struct mlx5_outbox_hdr hdr
;
930 __be32 dump_fill_mkey
;
931 __be32 reserved_lkey
;
934 struct mlx5_create_mkey_mbox_in
{
935 struct mlx5_inbox_hdr hdr
;
936 __be32 input_mkey_index
;
938 struct mlx5_mkey_seg seg
;
940 __be32 xlat_oct_act_size
;
946 struct mlx5_create_mkey_mbox_out
{
947 struct mlx5_outbox_hdr hdr
;
952 struct mlx5_destroy_mkey_mbox_in
{
953 struct mlx5_inbox_hdr hdr
;
958 struct mlx5_destroy_mkey_mbox_out
{
959 struct mlx5_outbox_hdr hdr
;
963 struct mlx5_query_mkey_mbox_in
{
964 struct mlx5_inbox_hdr hdr
;
968 struct mlx5_query_mkey_mbox_out
{
969 struct mlx5_outbox_hdr hdr
;
973 struct mlx5_modify_mkey_mbox_in
{
974 struct mlx5_inbox_hdr hdr
;
979 struct mlx5_modify_mkey_mbox_out
{
980 struct mlx5_outbox_hdr hdr
;
984 struct mlx5_dump_mkey_mbox_in
{
985 struct mlx5_inbox_hdr hdr
;
988 struct mlx5_dump_mkey_mbox_out
{
989 struct mlx5_outbox_hdr hdr
;
993 struct mlx5_mad_ifc_mbox_in
{
994 struct mlx5_inbox_hdr hdr
;
1002 struct mlx5_mad_ifc_mbox_out
{
1003 struct mlx5_outbox_hdr hdr
;
1008 struct mlx5_access_reg_mbox_in
{
1009 struct mlx5_inbox_hdr hdr
;
1016 struct mlx5_access_reg_mbox_out
{
1017 struct mlx5_outbox_hdr hdr
;
1022 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
1025 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO
= 1 << 0
1028 struct mlx5_allocate_psv_in
{
1029 struct mlx5_inbox_hdr hdr
;
1034 struct mlx5_allocate_psv_out
{
1035 struct mlx5_outbox_hdr hdr
;
1040 struct mlx5_destroy_psv_in
{
1041 struct mlx5_inbox_hdr hdr
;
1046 struct mlx5_destroy_psv_out
{
1047 struct mlx5_outbox_hdr hdr
;
1051 #define MLX5_CMD_OP_MAX 0x920
1054 VPORT_STATE_DOWN
= 0x0,
1055 VPORT_STATE_UP
= 0x1,
1059 MLX5_L3_PROT_TYPE_IPV4
= 0,
1060 MLX5_L3_PROT_TYPE_IPV6
= 1,
1064 MLX5_L4_PROT_TYPE_TCP
= 0,
1065 MLX5_L4_PROT_TYPE_UDP
= 1,
1069 MLX5_HASH_FIELD_SEL_SRC_IP
= 1 << 0,
1070 MLX5_HASH_FIELD_SEL_DST_IP
= 1 << 1,
1071 MLX5_HASH_FIELD_SEL_L4_SPORT
= 1 << 2,
1072 MLX5_HASH_FIELD_SEL_L4_DPORT
= 1 << 3,
1073 MLX5_HASH_FIELD_SEL_IPSEC_SPI
= 1 << 4,
1077 MLX5_MATCH_OUTER_HEADERS
= 1 << 0,
1078 MLX5_MATCH_MISC_PARAMETERS
= 1 << 1,
1079 MLX5_MATCH_INNER_HEADERS
= 1 << 2,
1084 MLX5_FLOW_TABLE_TYPE_NIC_RCV
= 0,
1085 MLX5_FLOW_TABLE_TYPE_ESWITCH
= 4,
1089 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT
= 0,
1090 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE
= 1,
1091 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR
= 2,
1095 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE
= 0x0,
1096 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM
= 0x1,
1102 enum mlx5_cap_mode
{
1103 HCA_CAP_OPMOD_GET_MAX
= 0,
1104 HCA_CAP_OPMOD_GET_CUR
= 1,
1107 enum mlx5_cap_type
{
1108 MLX5_CAP_GENERAL
= 0,
1109 MLX5_CAP_ETHERNET_OFFLOADS
,
1113 MLX5_CAP_IPOIB_OFFLOADS
,
1114 MLX5_CAP_EOIB_OFFLOADS
,
1115 MLX5_CAP_FLOW_TABLE
,
1116 /* NUM OF CAP Types */
1120 /* GET Dev Caps macros */
1121 #define MLX5_CAP_GEN(mdev, cap) \
1122 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1124 #define MLX5_CAP_GEN_MAX(mdev, cap) \
1125 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
1127 #define MLX5_CAP_ETH(mdev, cap) \
1128 MLX5_GET(per_protocol_networking_offload_caps,\
1129 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1131 #define MLX5_CAP_ETH_MAX(mdev, cap) \
1132 MLX5_GET(per_protocol_networking_offload_caps,\
1133 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1135 #define MLX5_CAP_ROCE(mdev, cap) \
1136 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1138 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
1139 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1141 #define MLX5_CAP_ATOMIC(mdev, cap) \
1142 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1144 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1145 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1147 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
1148 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1150 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1151 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1153 #define MLX5_CAP_ODP(mdev, cap)\
1154 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1157 MLX5_CMD_STAT_OK
= 0x0,
1158 MLX5_CMD_STAT_INT_ERR
= 0x1,
1159 MLX5_CMD_STAT_BAD_OP_ERR
= 0x2,
1160 MLX5_CMD_STAT_BAD_PARAM_ERR
= 0x3,
1161 MLX5_CMD_STAT_BAD_SYS_STATE_ERR
= 0x4,
1162 MLX5_CMD_STAT_BAD_RES_ERR
= 0x5,
1163 MLX5_CMD_STAT_RES_BUSY
= 0x6,
1164 MLX5_CMD_STAT_LIM_ERR
= 0x8,
1165 MLX5_CMD_STAT_BAD_RES_STATE_ERR
= 0x9,
1166 MLX5_CMD_STAT_IX_ERR
= 0xa,
1167 MLX5_CMD_STAT_NO_RES_ERR
= 0xf,
1168 MLX5_CMD_STAT_BAD_INP_LEN_ERR
= 0x50,
1169 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR
= 0x51,
1170 MLX5_CMD_STAT_BAD_QP_STATE_ERR
= 0x10,
1171 MLX5_CMD_STAT_BAD_PKT_ERR
= 0x30,
1172 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR
= 0x40,
1175 #endif /* MLX5_DEVICE_H */