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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[deliverable/linux.git] / include / linux / mlx5 / mlx5_ifc.h
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34
35 enum {
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
60 };
61
62 enum {
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
67 };
68
69 enum {
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
72 };
73
74 enum {
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
86 MLX5_CMD_OP_CREATE_MKEY = 0x200,
87 MLX5_CMD_OP_QUERY_MKEY = 0x201,
88 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
89 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
90 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
91 MLX5_CMD_OP_CREATE_EQ = 0x301,
92 MLX5_CMD_OP_DESTROY_EQ = 0x302,
93 MLX5_CMD_OP_QUERY_EQ = 0x303,
94 MLX5_CMD_OP_GEN_EQE = 0x304,
95 MLX5_CMD_OP_CREATE_CQ = 0x400,
96 MLX5_CMD_OP_DESTROY_CQ = 0x401,
97 MLX5_CMD_OP_QUERY_CQ = 0x402,
98 MLX5_CMD_OP_MODIFY_CQ = 0x403,
99 MLX5_CMD_OP_CREATE_QP = 0x500,
100 MLX5_CMD_OP_DESTROY_QP = 0x501,
101 MLX5_CMD_OP_RST2INIT_QP = 0x502,
102 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
103 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
104 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
105 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
106 MLX5_CMD_OP_2ERR_QP = 0x507,
107 MLX5_CMD_OP_2RST_QP = 0x50a,
108 MLX5_CMD_OP_QUERY_QP = 0x50b,
109 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
110 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
111 MLX5_CMD_OP_CREATE_PSV = 0x600,
112 MLX5_CMD_OP_DESTROY_PSV = 0x601,
113 MLX5_CMD_OP_CREATE_SRQ = 0x700,
114 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
115 MLX5_CMD_OP_QUERY_SRQ = 0x702,
116 MLX5_CMD_OP_ARM_RQ = 0x703,
117 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
118 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
119 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
120 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
121 MLX5_CMD_OP_CREATE_DCT = 0x710,
122 MLX5_CMD_OP_DESTROY_DCT = 0x711,
123 MLX5_CMD_OP_DRAIN_DCT = 0x712,
124 MLX5_CMD_OP_QUERY_DCT = 0x713,
125 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
126 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
127 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
128 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
129 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
130 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
131 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
132 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
133 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
134 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
135 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
136 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
137 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
138 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
139 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
140 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
141 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
142 MLX5_CMD_OP_ALLOC_PD = 0x800,
143 MLX5_CMD_OP_DEALLOC_PD = 0x801,
144 MLX5_CMD_OP_ALLOC_UAR = 0x802,
145 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
146 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
147 MLX5_CMD_OP_ACCESS_REG = 0x805,
148 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
149 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807,
150 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
151 MLX5_CMD_OP_MAD_IFC = 0x50d,
152 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
153 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
154 MLX5_CMD_OP_NOP = 0x80d,
155 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
156 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
157 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
158 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
159 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
160 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
161 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
162 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
163 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
164 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
165 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
166 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
167 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
168 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
169 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
170 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
171 MLX5_CMD_OP_CREATE_TIR = 0x900,
172 MLX5_CMD_OP_MODIFY_TIR = 0x901,
173 MLX5_CMD_OP_DESTROY_TIR = 0x902,
174 MLX5_CMD_OP_QUERY_TIR = 0x903,
175 MLX5_CMD_OP_CREATE_SQ = 0x904,
176 MLX5_CMD_OP_MODIFY_SQ = 0x905,
177 MLX5_CMD_OP_DESTROY_SQ = 0x906,
178 MLX5_CMD_OP_QUERY_SQ = 0x907,
179 MLX5_CMD_OP_CREATE_RQ = 0x908,
180 MLX5_CMD_OP_MODIFY_RQ = 0x909,
181 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
182 MLX5_CMD_OP_QUERY_RQ = 0x90b,
183 MLX5_CMD_OP_CREATE_RMP = 0x90c,
184 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
185 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
186 MLX5_CMD_OP_QUERY_RMP = 0x90f,
187 MLX5_CMD_OP_CREATE_TIS = 0x912,
188 MLX5_CMD_OP_MODIFY_TIS = 0x913,
189 MLX5_CMD_OP_DESTROY_TIS = 0x914,
190 MLX5_CMD_OP_QUERY_TIS = 0x915,
191 MLX5_CMD_OP_CREATE_RQT = 0x916,
192 MLX5_CMD_OP_MODIFY_RQT = 0x917,
193 MLX5_CMD_OP_DESTROY_RQT = 0x918,
194 MLX5_CMD_OP_QUERY_RQT = 0x919,
195 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
196 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
197 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
198 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
199 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
200 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
201 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
202 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
203 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
204 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
205 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c
206 };
207
208 struct mlx5_ifc_flow_table_fields_supported_bits {
209 u8 outer_dmac[0x1];
210 u8 outer_smac[0x1];
211 u8 outer_ether_type[0x1];
212 u8 reserved_at_3[0x1];
213 u8 outer_first_prio[0x1];
214 u8 outer_first_cfi[0x1];
215 u8 outer_first_vid[0x1];
216 u8 reserved_at_7[0x1];
217 u8 outer_second_prio[0x1];
218 u8 outer_second_cfi[0x1];
219 u8 outer_second_vid[0x1];
220 u8 reserved_at_b[0x1];
221 u8 outer_sip[0x1];
222 u8 outer_dip[0x1];
223 u8 outer_frag[0x1];
224 u8 outer_ip_protocol[0x1];
225 u8 outer_ip_ecn[0x1];
226 u8 outer_ip_dscp[0x1];
227 u8 outer_udp_sport[0x1];
228 u8 outer_udp_dport[0x1];
229 u8 outer_tcp_sport[0x1];
230 u8 outer_tcp_dport[0x1];
231 u8 outer_tcp_flags[0x1];
232 u8 outer_gre_protocol[0x1];
233 u8 outer_gre_key[0x1];
234 u8 outer_vxlan_vni[0x1];
235 u8 reserved_at_1a[0x5];
236 u8 source_eswitch_port[0x1];
237
238 u8 inner_dmac[0x1];
239 u8 inner_smac[0x1];
240 u8 inner_ether_type[0x1];
241 u8 reserved_at_23[0x1];
242 u8 inner_first_prio[0x1];
243 u8 inner_first_cfi[0x1];
244 u8 inner_first_vid[0x1];
245 u8 reserved_at_27[0x1];
246 u8 inner_second_prio[0x1];
247 u8 inner_second_cfi[0x1];
248 u8 inner_second_vid[0x1];
249 u8 reserved_at_2b[0x1];
250 u8 inner_sip[0x1];
251 u8 inner_dip[0x1];
252 u8 inner_frag[0x1];
253 u8 inner_ip_protocol[0x1];
254 u8 inner_ip_ecn[0x1];
255 u8 inner_ip_dscp[0x1];
256 u8 inner_udp_sport[0x1];
257 u8 inner_udp_dport[0x1];
258 u8 inner_tcp_sport[0x1];
259 u8 inner_tcp_dport[0x1];
260 u8 inner_tcp_flags[0x1];
261 u8 reserved_at_37[0x9];
262
263 u8 reserved_at_40[0x40];
264 };
265
266 struct mlx5_ifc_flow_table_prop_layout_bits {
267 u8 ft_support[0x1];
268 u8 reserved_at_1[0x2];
269 u8 flow_modify_en[0x1];
270 u8 modify_root[0x1];
271 u8 identified_miss_table_mode[0x1];
272 u8 flow_table_modify[0x1];
273 u8 reserved_at_7[0x19];
274
275 u8 reserved_at_20[0x2];
276 u8 log_max_ft_size[0x6];
277 u8 reserved_at_28[0x10];
278 u8 max_ft_level[0x8];
279
280 u8 reserved_at_40[0x20];
281
282 u8 reserved_at_60[0x18];
283 u8 log_max_ft_num[0x8];
284
285 u8 reserved_at_80[0x18];
286 u8 log_max_destination[0x8];
287
288 u8 reserved_at_a0[0x18];
289 u8 log_max_flow[0x8];
290
291 u8 reserved_at_c0[0x40];
292
293 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
294
295 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
296 };
297
298 struct mlx5_ifc_odp_per_transport_service_cap_bits {
299 u8 send[0x1];
300 u8 receive[0x1];
301 u8 write[0x1];
302 u8 read[0x1];
303 u8 reserved_at_4[0x1];
304 u8 srq_receive[0x1];
305 u8 reserved_at_6[0x1a];
306 };
307
308 struct mlx5_ifc_ipv4_layout_bits {
309 u8 reserved_at_0[0x60];
310
311 u8 ipv4[0x20];
312 };
313
314 struct mlx5_ifc_ipv6_layout_bits {
315 u8 ipv6[16][0x8];
316 };
317
318 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
319 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
320 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
321 u8 reserved_at_0[0x80];
322 };
323
324 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
325 u8 smac_47_16[0x20];
326
327 u8 smac_15_0[0x10];
328 u8 ethertype[0x10];
329
330 u8 dmac_47_16[0x20];
331
332 u8 dmac_15_0[0x10];
333 u8 first_prio[0x3];
334 u8 first_cfi[0x1];
335 u8 first_vid[0xc];
336
337 u8 ip_protocol[0x8];
338 u8 ip_dscp[0x6];
339 u8 ip_ecn[0x2];
340 u8 vlan_tag[0x1];
341 u8 reserved_at_91[0x1];
342 u8 frag[0x1];
343 u8 reserved_at_93[0x4];
344 u8 tcp_flags[0x9];
345
346 u8 tcp_sport[0x10];
347 u8 tcp_dport[0x10];
348
349 u8 reserved_at_c0[0x20];
350
351 u8 udp_sport[0x10];
352 u8 udp_dport[0x10];
353
354 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
355
356 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
357 };
358
359 struct mlx5_ifc_fte_match_set_misc_bits {
360 u8 reserved_at_0[0x20];
361
362 u8 reserved_at_20[0x10];
363 u8 source_port[0x10];
364
365 u8 outer_second_prio[0x3];
366 u8 outer_second_cfi[0x1];
367 u8 outer_second_vid[0xc];
368 u8 inner_second_prio[0x3];
369 u8 inner_second_cfi[0x1];
370 u8 inner_second_vid[0xc];
371
372 u8 outer_second_vlan_tag[0x1];
373 u8 inner_second_vlan_tag[0x1];
374 u8 reserved_at_62[0xe];
375 u8 gre_protocol[0x10];
376
377 u8 gre_key_h[0x18];
378 u8 gre_key_l[0x8];
379
380 u8 vxlan_vni[0x18];
381 u8 reserved_at_b8[0x8];
382
383 u8 reserved_at_c0[0x20];
384
385 u8 reserved_at_e0[0xc];
386 u8 outer_ipv6_flow_label[0x14];
387
388 u8 reserved_at_100[0xc];
389 u8 inner_ipv6_flow_label[0x14];
390
391 u8 reserved_at_120[0xe0];
392 };
393
394 struct mlx5_ifc_cmd_pas_bits {
395 u8 pa_h[0x20];
396
397 u8 pa_l[0x14];
398 u8 reserved_at_34[0xc];
399 };
400
401 struct mlx5_ifc_uint64_bits {
402 u8 hi[0x20];
403
404 u8 lo[0x20];
405 };
406
407 enum {
408 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
409 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
410 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
411 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
412 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
413 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
414 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
415 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
416 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
417 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
418 };
419
420 struct mlx5_ifc_ads_bits {
421 u8 fl[0x1];
422 u8 free_ar[0x1];
423 u8 reserved_at_2[0xe];
424 u8 pkey_index[0x10];
425
426 u8 reserved_at_20[0x8];
427 u8 grh[0x1];
428 u8 mlid[0x7];
429 u8 rlid[0x10];
430
431 u8 ack_timeout[0x5];
432 u8 reserved_at_45[0x3];
433 u8 src_addr_index[0x8];
434 u8 reserved_at_50[0x4];
435 u8 stat_rate[0x4];
436 u8 hop_limit[0x8];
437
438 u8 reserved_at_60[0x4];
439 u8 tclass[0x8];
440 u8 flow_label[0x14];
441
442 u8 rgid_rip[16][0x8];
443
444 u8 reserved_at_100[0x4];
445 u8 f_dscp[0x1];
446 u8 f_ecn[0x1];
447 u8 reserved_at_106[0x1];
448 u8 f_eth_prio[0x1];
449 u8 ecn[0x2];
450 u8 dscp[0x6];
451 u8 udp_sport[0x10];
452
453 u8 dei_cfi[0x1];
454 u8 eth_prio[0x3];
455 u8 sl[0x4];
456 u8 port[0x8];
457 u8 rmac_47_32[0x10];
458
459 u8 rmac_31_0[0x20];
460 };
461
462 struct mlx5_ifc_flow_table_nic_cap_bits {
463 u8 reserved_at_0[0x200];
464
465 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
466
467 u8 reserved_at_400[0x200];
468
469 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
470
471 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
472
473 u8 reserved_at_a00[0x200];
474
475 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
476
477 u8 reserved_at_e00[0x7200];
478 };
479
480 struct mlx5_ifc_flow_table_eswitch_cap_bits {
481 u8 reserved_at_0[0x200];
482
483 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
484
485 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
486
487 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
488
489 u8 reserved_at_800[0x7800];
490 };
491
492 struct mlx5_ifc_e_switch_cap_bits {
493 u8 vport_svlan_strip[0x1];
494 u8 vport_cvlan_strip[0x1];
495 u8 vport_svlan_insert[0x1];
496 u8 vport_cvlan_insert_if_not_exist[0x1];
497 u8 vport_cvlan_insert_overwrite[0x1];
498 u8 reserved_at_5[0x1b];
499
500 u8 reserved_at_20[0x7e0];
501 };
502
503 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
504 u8 csum_cap[0x1];
505 u8 vlan_cap[0x1];
506 u8 lro_cap[0x1];
507 u8 lro_psh_flag[0x1];
508 u8 lro_time_stamp[0x1];
509 u8 reserved_at_5[0x3];
510 u8 self_lb_en_modifiable[0x1];
511 u8 reserved_at_9[0x2];
512 u8 max_lso_cap[0x5];
513 u8 reserved_at_10[0x4];
514 u8 rss_ind_tbl_cap[0x4];
515 u8 reserved_at_18[0x3];
516 u8 tunnel_lso_const_out_ip_id[0x1];
517 u8 reserved_at_1c[0x2];
518 u8 tunnel_statless_gre[0x1];
519 u8 tunnel_stateless_vxlan[0x1];
520
521 u8 reserved_at_20[0x20];
522
523 u8 reserved_at_40[0x10];
524 u8 lro_min_mss_size[0x10];
525
526 u8 reserved_at_60[0x120];
527
528 u8 lro_timer_supported_periods[4][0x20];
529
530 u8 reserved_at_200[0x600];
531 };
532
533 struct mlx5_ifc_roce_cap_bits {
534 u8 roce_apm[0x1];
535 u8 reserved_at_1[0x1f];
536
537 u8 reserved_at_20[0x60];
538
539 u8 reserved_at_80[0xc];
540 u8 l3_type[0x4];
541 u8 reserved_at_90[0x8];
542 u8 roce_version[0x8];
543
544 u8 reserved_at_a0[0x10];
545 u8 r_roce_dest_udp_port[0x10];
546
547 u8 r_roce_max_src_udp_port[0x10];
548 u8 r_roce_min_src_udp_port[0x10];
549
550 u8 reserved_at_e0[0x10];
551 u8 roce_address_table_size[0x10];
552
553 u8 reserved_at_100[0x700];
554 };
555
556 enum {
557 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
558 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
559 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
560 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
561 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
562 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
563 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
564 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
565 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
566 };
567
568 enum {
569 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
570 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
571 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
572 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
573 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
574 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
575 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
576 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
577 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
578 };
579
580 struct mlx5_ifc_atomic_caps_bits {
581 u8 reserved_at_0[0x40];
582
583 u8 atomic_req_8B_endianess_mode[0x2];
584 u8 reserved_at_42[0x4];
585 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
586
587 u8 reserved_at_47[0x19];
588
589 u8 reserved_at_60[0x20];
590
591 u8 reserved_at_80[0x10];
592 u8 atomic_operations[0x10];
593
594 u8 reserved_at_a0[0x10];
595 u8 atomic_size_qp[0x10];
596
597 u8 reserved_at_c0[0x10];
598 u8 atomic_size_dc[0x10];
599
600 u8 reserved_at_e0[0x720];
601 };
602
603 struct mlx5_ifc_odp_cap_bits {
604 u8 reserved_at_0[0x40];
605
606 u8 sig[0x1];
607 u8 reserved_at_41[0x1f];
608
609 u8 reserved_at_60[0x20];
610
611 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
612
613 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
614
615 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
616
617 u8 reserved_at_e0[0x720];
618 };
619
620 enum {
621 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
622 MLX5_WQ_TYPE_CYCLIC = 0x1,
623 MLX5_WQ_TYPE_STRQ = 0x2,
624 };
625
626 enum {
627 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
628 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
629 };
630
631 enum {
632 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
633 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
634 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
635 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
636 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
637 };
638
639 enum {
640 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
641 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
642 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
643 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
644 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
645 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
646 };
647
648 enum {
649 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
650 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
651 };
652
653 enum {
654 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
655 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
656 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
657 };
658
659 enum {
660 MLX5_CAP_PORT_TYPE_IB = 0x0,
661 MLX5_CAP_PORT_TYPE_ETH = 0x1,
662 };
663
664 struct mlx5_ifc_cmd_hca_cap_bits {
665 u8 reserved_at_0[0x80];
666
667 u8 log_max_srq_sz[0x8];
668 u8 log_max_qp_sz[0x8];
669 u8 reserved_at_90[0xb];
670 u8 log_max_qp[0x5];
671
672 u8 reserved_at_a0[0xb];
673 u8 log_max_srq[0x5];
674 u8 reserved_at_b0[0x10];
675
676 u8 reserved_at_c0[0x8];
677 u8 log_max_cq_sz[0x8];
678 u8 reserved_at_d0[0xb];
679 u8 log_max_cq[0x5];
680
681 u8 log_max_eq_sz[0x8];
682 u8 reserved_at_e8[0x2];
683 u8 log_max_mkey[0x6];
684 u8 reserved_at_f0[0xc];
685 u8 log_max_eq[0x4];
686
687 u8 max_indirection[0x8];
688 u8 reserved_at_108[0x1];
689 u8 log_max_mrw_sz[0x7];
690 u8 reserved_at_110[0x2];
691 u8 log_max_bsf_list_size[0x6];
692 u8 reserved_at_118[0x2];
693 u8 log_max_klm_list_size[0x6];
694
695 u8 reserved_at_120[0xa];
696 u8 log_max_ra_req_dc[0x6];
697 u8 reserved_at_130[0xa];
698 u8 log_max_ra_res_dc[0x6];
699
700 u8 reserved_at_140[0xa];
701 u8 log_max_ra_req_qp[0x6];
702 u8 reserved_at_150[0xa];
703 u8 log_max_ra_res_qp[0x6];
704
705 u8 pad_cap[0x1];
706 u8 cc_query_allowed[0x1];
707 u8 cc_modify_allowed[0x1];
708 u8 reserved_at_163[0xd];
709 u8 gid_table_size[0x10];
710
711 u8 out_of_seq_cnt[0x1];
712 u8 vport_counters[0x1];
713 u8 reserved_at_182[0x4];
714 u8 max_qp_cnt[0xa];
715 u8 pkey_table_size[0x10];
716
717 u8 vport_group_manager[0x1];
718 u8 vhca_group_manager[0x1];
719 u8 ib_virt[0x1];
720 u8 eth_virt[0x1];
721 u8 reserved_at_1a4[0x1];
722 u8 ets[0x1];
723 u8 nic_flow_table[0x1];
724 u8 eswitch_flow_table[0x1];
725 u8 early_vf_enable;
726 u8 reserved_at_1a8[0x2];
727 u8 local_ca_ack_delay[0x5];
728 u8 reserved_at_1af[0x6];
729 u8 port_type[0x2];
730 u8 num_ports[0x8];
731
732 u8 reserved_at_1bf[0x3];
733 u8 log_max_msg[0x5];
734 u8 reserved_at_1c7[0x4];
735 u8 max_tc[0x4];
736 u8 reserved_at_1cf[0x6];
737 u8 rol_s[0x1];
738 u8 rol_g[0x1];
739 u8 reserved_at_1d7[0x1];
740 u8 wol_s[0x1];
741 u8 wol_g[0x1];
742 u8 wol_a[0x1];
743 u8 wol_b[0x1];
744 u8 wol_m[0x1];
745 u8 wol_u[0x1];
746 u8 wol_p[0x1];
747
748 u8 stat_rate_support[0x10];
749 u8 reserved_at_1ef[0xc];
750 u8 cqe_version[0x4];
751
752 u8 compact_address_vector[0x1];
753 u8 reserved_at_200[0xe];
754 u8 drain_sigerr[0x1];
755 u8 cmdif_checksum[0x2];
756 u8 sigerr_cqe[0x1];
757 u8 reserved_at_212[0x1];
758 u8 wq_signature[0x1];
759 u8 sctr_data_cqe[0x1];
760 u8 reserved_at_215[0x1];
761 u8 sho[0x1];
762 u8 tph[0x1];
763 u8 rf[0x1];
764 u8 dct[0x1];
765 u8 reserved_at_21a[0x1];
766 u8 eth_net_offloads[0x1];
767 u8 roce[0x1];
768 u8 atomic[0x1];
769 u8 reserved_at_21e[0x1];
770
771 u8 cq_oi[0x1];
772 u8 cq_resize[0x1];
773 u8 cq_moderation[0x1];
774 u8 reserved_at_222[0x3];
775 u8 cq_eq_remap[0x1];
776 u8 pg[0x1];
777 u8 block_lb_mc[0x1];
778 u8 reserved_at_228[0x1];
779 u8 scqe_break_moderation[0x1];
780 u8 reserved_at_22a[0x1];
781 u8 cd[0x1];
782 u8 reserved_at_22c[0x1];
783 u8 apm[0x1];
784 u8 reserved_at_22e[0x7];
785 u8 qkv[0x1];
786 u8 pkv[0x1];
787 u8 reserved_at_237[0x4];
788 u8 xrc[0x1];
789 u8 ud[0x1];
790 u8 uc[0x1];
791 u8 rc[0x1];
792
793 u8 reserved_at_23f[0xa];
794 u8 uar_sz[0x6];
795 u8 reserved_at_24f[0x8];
796 u8 log_pg_sz[0x8];
797
798 u8 bf[0x1];
799 u8 reserved_at_260[0x1];
800 u8 pad_tx_eth_packet[0x1];
801 u8 reserved_at_262[0x8];
802 u8 log_bf_reg_size[0x5];
803 u8 reserved_at_26f[0x10];
804
805 u8 reserved_at_27f[0x10];
806 u8 max_wqe_sz_sq[0x10];
807
808 u8 reserved_at_29f[0x10];
809 u8 max_wqe_sz_rq[0x10];
810
811 u8 reserved_at_2bf[0x10];
812 u8 max_wqe_sz_sq_dc[0x10];
813
814 u8 reserved_at_2df[0x7];
815 u8 max_qp_mcg[0x19];
816
817 u8 reserved_at_2ff[0x18];
818 u8 log_max_mcg[0x8];
819
820 u8 reserved_at_31f[0x3];
821 u8 log_max_transport_domain[0x5];
822 u8 reserved_at_327[0x3];
823 u8 log_max_pd[0x5];
824 u8 reserved_at_32f[0xb];
825 u8 log_max_xrcd[0x5];
826
827 u8 reserved_at_33f[0x20];
828
829 u8 reserved_at_35f[0x3];
830 u8 log_max_rq[0x5];
831 u8 reserved_at_367[0x3];
832 u8 log_max_sq[0x5];
833 u8 reserved_at_36f[0x3];
834 u8 log_max_tir[0x5];
835 u8 reserved_at_377[0x3];
836 u8 log_max_tis[0x5];
837
838 u8 basic_cyclic_rcv_wqe[0x1];
839 u8 reserved_at_380[0x2];
840 u8 log_max_rmp[0x5];
841 u8 reserved_at_387[0x3];
842 u8 log_max_rqt[0x5];
843 u8 reserved_at_38f[0x3];
844 u8 log_max_rqt_size[0x5];
845 u8 reserved_at_397[0x3];
846 u8 log_max_tis_per_sq[0x5];
847
848 u8 reserved_at_39f[0x3];
849 u8 log_max_stride_sz_rq[0x5];
850 u8 reserved_at_3a7[0x3];
851 u8 log_min_stride_sz_rq[0x5];
852 u8 reserved_at_3af[0x3];
853 u8 log_max_stride_sz_sq[0x5];
854 u8 reserved_at_3b7[0x3];
855 u8 log_min_stride_sz_sq[0x5];
856
857 u8 reserved_at_3bf[0x1b];
858 u8 log_max_wq_sz[0x5];
859
860 u8 nic_vport_change_event[0x1];
861 u8 reserved_at_3e0[0xa];
862 u8 log_max_vlan_list[0x5];
863 u8 reserved_at_3ef[0x3];
864 u8 log_max_current_mc_list[0x5];
865 u8 reserved_at_3f7[0x3];
866 u8 log_max_current_uc_list[0x5];
867
868 u8 reserved_at_3ff[0x80];
869
870 u8 reserved_at_47f[0x3];
871 u8 log_max_l2_table[0x5];
872 u8 reserved_at_487[0x8];
873 u8 log_uar_page_sz[0x10];
874
875 u8 reserved_at_49f[0x20];
876 u8 device_frequency_mhz[0x20];
877 u8 device_frequency_khz[0x20];
878 u8 reserved_at_4ff[0x5f];
879 u8 cqe_zip[0x1];
880
881 u8 cqe_zip_timeout[0x10];
882 u8 cqe_zip_max_num[0x10];
883
884 u8 reserved_at_57f[0x220];
885 };
886
887 enum mlx5_flow_destination_type {
888 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
889 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
890 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
891 };
892
893 struct mlx5_ifc_dest_format_struct_bits {
894 u8 destination_type[0x8];
895 u8 destination_id[0x18];
896
897 u8 reserved_at_20[0x20];
898 };
899
900 struct mlx5_ifc_fte_match_param_bits {
901 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
902
903 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
904
905 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
906
907 u8 reserved_at_600[0xa00];
908 };
909
910 enum {
911 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
912 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
913 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
914 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
915 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
916 };
917
918 struct mlx5_ifc_rx_hash_field_select_bits {
919 u8 l3_prot_type[0x1];
920 u8 l4_prot_type[0x1];
921 u8 selected_fields[0x1e];
922 };
923
924 enum {
925 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
926 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
927 };
928
929 enum {
930 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
931 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
932 };
933
934 struct mlx5_ifc_wq_bits {
935 u8 wq_type[0x4];
936 u8 wq_signature[0x1];
937 u8 end_padding_mode[0x2];
938 u8 cd_slave[0x1];
939 u8 reserved_at_8[0x18];
940
941 u8 hds_skip_first_sge[0x1];
942 u8 log2_hds_buf_size[0x3];
943 u8 reserved_at_24[0x7];
944 u8 page_offset[0x5];
945 u8 lwm[0x10];
946
947 u8 reserved_at_40[0x8];
948 u8 pd[0x18];
949
950 u8 reserved_at_60[0x8];
951 u8 uar_page[0x18];
952
953 u8 dbr_addr[0x40];
954
955 u8 hw_counter[0x20];
956
957 u8 sw_counter[0x20];
958
959 u8 reserved_at_100[0xc];
960 u8 log_wq_stride[0x4];
961 u8 reserved_at_110[0x3];
962 u8 log_wq_pg_sz[0x5];
963 u8 reserved_at_118[0x3];
964 u8 log_wq_sz[0x5];
965
966 u8 reserved_at_120[0x4e0];
967
968 struct mlx5_ifc_cmd_pas_bits pas[0];
969 };
970
971 struct mlx5_ifc_rq_num_bits {
972 u8 reserved_at_0[0x8];
973 u8 rq_num[0x18];
974 };
975
976 struct mlx5_ifc_mac_address_layout_bits {
977 u8 reserved_at_0[0x10];
978 u8 mac_addr_47_32[0x10];
979
980 u8 mac_addr_31_0[0x20];
981 };
982
983 struct mlx5_ifc_vlan_layout_bits {
984 u8 reserved_at_0[0x14];
985 u8 vlan[0x0c];
986
987 u8 reserved_at_20[0x20];
988 };
989
990 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
991 u8 reserved_at_0[0xa0];
992
993 u8 min_time_between_cnps[0x20];
994
995 u8 reserved_at_c0[0x12];
996 u8 cnp_dscp[0x6];
997 u8 reserved_at_d8[0x5];
998 u8 cnp_802p_prio[0x3];
999
1000 u8 reserved_at_e0[0x720];
1001 };
1002
1003 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1004 u8 reserved_at_0[0x60];
1005
1006 u8 reserved_at_60[0x4];
1007 u8 clamp_tgt_rate[0x1];
1008 u8 reserved_at_65[0x3];
1009 u8 clamp_tgt_rate_after_time_inc[0x1];
1010 u8 reserved_at_69[0x17];
1011
1012 u8 reserved_at_80[0x20];
1013
1014 u8 rpg_time_reset[0x20];
1015
1016 u8 rpg_byte_reset[0x20];
1017
1018 u8 rpg_threshold[0x20];
1019
1020 u8 rpg_max_rate[0x20];
1021
1022 u8 rpg_ai_rate[0x20];
1023
1024 u8 rpg_hai_rate[0x20];
1025
1026 u8 rpg_gd[0x20];
1027
1028 u8 rpg_min_dec_fac[0x20];
1029
1030 u8 rpg_min_rate[0x20];
1031
1032 u8 reserved_at_1c0[0xe0];
1033
1034 u8 rate_to_set_on_first_cnp[0x20];
1035
1036 u8 dce_tcp_g[0x20];
1037
1038 u8 dce_tcp_rtt[0x20];
1039
1040 u8 rate_reduce_monitor_period[0x20];
1041
1042 u8 reserved_at_320[0x20];
1043
1044 u8 initial_alpha_value[0x20];
1045
1046 u8 reserved_at_360[0x4a0];
1047 };
1048
1049 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1050 u8 reserved_at_0[0x80];
1051
1052 u8 rppp_max_rps[0x20];
1053
1054 u8 rpg_time_reset[0x20];
1055
1056 u8 rpg_byte_reset[0x20];
1057
1058 u8 rpg_threshold[0x20];
1059
1060 u8 rpg_max_rate[0x20];
1061
1062 u8 rpg_ai_rate[0x20];
1063
1064 u8 rpg_hai_rate[0x20];
1065
1066 u8 rpg_gd[0x20];
1067
1068 u8 rpg_min_dec_fac[0x20];
1069
1070 u8 rpg_min_rate[0x20];
1071
1072 u8 reserved_at_1c0[0x640];
1073 };
1074
1075 enum {
1076 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1077 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1078 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1079 };
1080
1081 struct mlx5_ifc_resize_field_select_bits {
1082 u8 resize_field_select[0x20];
1083 };
1084
1085 enum {
1086 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1087 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1088 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1089 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1090 };
1091
1092 struct mlx5_ifc_modify_field_select_bits {
1093 u8 modify_field_select[0x20];
1094 };
1095
1096 struct mlx5_ifc_field_select_r_roce_np_bits {
1097 u8 field_select_r_roce_np[0x20];
1098 };
1099
1100 struct mlx5_ifc_field_select_r_roce_rp_bits {
1101 u8 field_select_r_roce_rp[0x20];
1102 };
1103
1104 enum {
1105 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1106 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1107 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1108 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1109 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1110 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1111 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1112 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1113 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1114 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1115 };
1116
1117 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1118 u8 field_select_8021qaurp[0x20];
1119 };
1120
1121 struct mlx5_ifc_phys_layer_cntrs_bits {
1122 u8 time_since_last_clear_high[0x20];
1123
1124 u8 time_since_last_clear_low[0x20];
1125
1126 u8 symbol_errors_high[0x20];
1127
1128 u8 symbol_errors_low[0x20];
1129
1130 u8 sync_headers_errors_high[0x20];
1131
1132 u8 sync_headers_errors_low[0x20];
1133
1134 u8 edpl_bip_errors_lane0_high[0x20];
1135
1136 u8 edpl_bip_errors_lane0_low[0x20];
1137
1138 u8 edpl_bip_errors_lane1_high[0x20];
1139
1140 u8 edpl_bip_errors_lane1_low[0x20];
1141
1142 u8 edpl_bip_errors_lane2_high[0x20];
1143
1144 u8 edpl_bip_errors_lane2_low[0x20];
1145
1146 u8 edpl_bip_errors_lane3_high[0x20];
1147
1148 u8 edpl_bip_errors_lane3_low[0x20];
1149
1150 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1151
1152 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1153
1154 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1155
1156 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1157
1158 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1159
1160 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1161
1162 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1163
1164 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1165
1166 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1167
1168 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1169
1170 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1171
1172 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1173
1174 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1175
1176 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1177
1178 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1179
1180 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1181
1182 u8 rs_fec_corrected_blocks_high[0x20];
1183
1184 u8 rs_fec_corrected_blocks_low[0x20];
1185
1186 u8 rs_fec_uncorrectable_blocks_high[0x20];
1187
1188 u8 rs_fec_uncorrectable_blocks_low[0x20];
1189
1190 u8 rs_fec_no_errors_blocks_high[0x20];
1191
1192 u8 rs_fec_no_errors_blocks_low[0x20];
1193
1194 u8 rs_fec_single_error_blocks_high[0x20];
1195
1196 u8 rs_fec_single_error_blocks_low[0x20];
1197
1198 u8 rs_fec_corrected_symbols_total_high[0x20];
1199
1200 u8 rs_fec_corrected_symbols_total_low[0x20];
1201
1202 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1203
1204 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1205
1206 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1207
1208 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1209
1210 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1211
1212 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1213
1214 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1215
1216 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1217
1218 u8 link_down_events[0x20];
1219
1220 u8 successful_recovery_events[0x20];
1221
1222 u8 reserved_at_640[0x180];
1223 };
1224
1225 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1226 u8 transmit_queue_high[0x20];
1227
1228 u8 transmit_queue_low[0x20];
1229
1230 u8 reserved_at_40[0x780];
1231 };
1232
1233 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1234 u8 rx_octets_high[0x20];
1235
1236 u8 rx_octets_low[0x20];
1237
1238 u8 reserved_at_40[0xc0];
1239
1240 u8 rx_frames_high[0x20];
1241
1242 u8 rx_frames_low[0x20];
1243
1244 u8 tx_octets_high[0x20];
1245
1246 u8 tx_octets_low[0x20];
1247
1248 u8 reserved_at_180[0xc0];
1249
1250 u8 tx_frames_high[0x20];
1251
1252 u8 tx_frames_low[0x20];
1253
1254 u8 rx_pause_high[0x20];
1255
1256 u8 rx_pause_low[0x20];
1257
1258 u8 rx_pause_duration_high[0x20];
1259
1260 u8 rx_pause_duration_low[0x20];
1261
1262 u8 tx_pause_high[0x20];
1263
1264 u8 tx_pause_low[0x20];
1265
1266 u8 tx_pause_duration_high[0x20];
1267
1268 u8 tx_pause_duration_low[0x20];
1269
1270 u8 rx_pause_transition_high[0x20];
1271
1272 u8 rx_pause_transition_low[0x20];
1273
1274 u8 reserved_at_3c0[0x400];
1275 };
1276
1277 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1278 u8 port_transmit_wait_high[0x20];
1279
1280 u8 port_transmit_wait_low[0x20];
1281
1282 u8 reserved_at_40[0x780];
1283 };
1284
1285 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1286 u8 dot3stats_alignment_errors_high[0x20];
1287
1288 u8 dot3stats_alignment_errors_low[0x20];
1289
1290 u8 dot3stats_fcs_errors_high[0x20];
1291
1292 u8 dot3stats_fcs_errors_low[0x20];
1293
1294 u8 dot3stats_single_collision_frames_high[0x20];
1295
1296 u8 dot3stats_single_collision_frames_low[0x20];
1297
1298 u8 dot3stats_multiple_collision_frames_high[0x20];
1299
1300 u8 dot3stats_multiple_collision_frames_low[0x20];
1301
1302 u8 dot3stats_sqe_test_errors_high[0x20];
1303
1304 u8 dot3stats_sqe_test_errors_low[0x20];
1305
1306 u8 dot3stats_deferred_transmissions_high[0x20];
1307
1308 u8 dot3stats_deferred_transmissions_low[0x20];
1309
1310 u8 dot3stats_late_collisions_high[0x20];
1311
1312 u8 dot3stats_late_collisions_low[0x20];
1313
1314 u8 dot3stats_excessive_collisions_high[0x20];
1315
1316 u8 dot3stats_excessive_collisions_low[0x20];
1317
1318 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1319
1320 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1321
1322 u8 dot3stats_carrier_sense_errors_high[0x20];
1323
1324 u8 dot3stats_carrier_sense_errors_low[0x20];
1325
1326 u8 dot3stats_frame_too_longs_high[0x20];
1327
1328 u8 dot3stats_frame_too_longs_low[0x20];
1329
1330 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1331
1332 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1333
1334 u8 dot3stats_symbol_errors_high[0x20];
1335
1336 u8 dot3stats_symbol_errors_low[0x20];
1337
1338 u8 dot3control_in_unknown_opcodes_high[0x20];
1339
1340 u8 dot3control_in_unknown_opcodes_low[0x20];
1341
1342 u8 dot3in_pause_frames_high[0x20];
1343
1344 u8 dot3in_pause_frames_low[0x20];
1345
1346 u8 dot3out_pause_frames_high[0x20];
1347
1348 u8 dot3out_pause_frames_low[0x20];
1349
1350 u8 reserved_at_400[0x3c0];
1351 };
1352
1353 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1354 u8 ether_stats_drop_events_high[0x20];
1355
1356 u8 ether_stats_drop_events_low[0x20];
1357
1358 u8 ether_stats_octets_high[0x20];
1359
1360 u8 ether_stats_octets_low[0x20];
1361
1362 u8 ether_stats_pkts_high[0x20];
1363
1364 u8 ether_stats_pkts_low[0x20];
1365
1366 u8 ether_stats_broadcast_pkts_high[0x20];
1367
1368 u8 ether_stats_broadcast_pkts_low[0x20];
1369
1370 u8 ether_stats_multicast_pkts_high[0x20];
1371
1372 u8 ether_stats_multicast_pkts_low[0x20];
1373
1374 u8 ether_stats_crc_align_errors_high[0x20];
1375
1376 u8 ether_stats_crc_align_errors_low[0x20];
1377
1378 u8 ether_stats_undersize_pkts_high[0x20];
1379
1380 u8 ether_stats_undersize_pkts_low[0x20];
1381
1382 u8 ether_stats_oversize_pkts_high[0x20];
1383
1384 u8 ether_stats_oversize_pkts_low[0x20];
1385
1386 u8 ether_stats_fragments_high[0x20];
1387
1388 u8 ether_stats_fragments_low[0x20];
1389
1390 u8 ether_stats_jabbers_high[0x20];
1391
1392 u8 ether_stats_jabbers_low[0x20];
1393
1394 u8 ether_stats_collisions_high[0x20];
1395
1396 u8 ether_stats_collisions_low[0x20];
1397
1398 u8 ether_stats_pkts64octets_high[0x20];
1399
1400 u8 ether_stats_pkts64octets_low[0x20];
1401
1402 u8 ether_stats_pkts65to127octets_high[0x20];
1403
1404 u8 ether_stats_pkts65to127octets_low[0x20];
1405
1406 u8 ether_stats_pkts128to255octets_high[0x20];
1407
1408 u8 ether_stats_pkts128to255octets_low[0x20];
1409
1410 u8 ether_stats_pkts256to511octets_high[0x20];
1411
1412 u8 ether_stats_pkts256to511octets_low[0x20];
1413
1414 u8 ether_stats_pkts512to1023octets_high[0x20];
1415
1416 u8 ether_stats_pkts512to1023octets_low[0x20];
1417
1418 u8 ether_stats_pkts1024to1518octets_high[0x20];
1419
1420 u8 ether_stats_pkts1024to1518octets_low[0x20];
1421
1422 u8 ether_stats_pkts1519to2047octets_high[0x20];
1423
1424 u8 ether_stats_pkts1519to2047octets_low[0x20];
1425
1426 u8 ether_stats_pkts2048to4095octets_high[0x20];
1427
1428 u8 ether_stats_pkts2048to4095octets_low[0x20];
1429
1430 u8 ether_stats_pkts4096to8191octets_high[0x20];
1431
1432 u8 ether_stats_pkts4096to8191octets_low[0x20];
1433
1434 u8 ether_stats_pkts8192to10239octets_high[0x20];
1435
1436 u8 ether_stats_pkts8192to10239octets_low[0x20];
1437
1438 u8 reserved_at_540[0x280];
1439 };
1440
1441 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1442 u8 if_in_octets_high[0x20];
1443
1444 u8 if_in_octets_low[0x20];
1445
1446 u8 if_in_ucast_pkts_high[0x20];
1447
1448 u8 if_in_ucast_pkts_low[0x20];
1449
1450 u8 if_in_discards_high[0x20];
1451
1452 u8 if_in_discards_low[0x20];
1453
1454 u8 if_in_errors_high[0x20];
1455
1456 u8 if_in_errors_low[0x20];
1457
1458 u8 if_in_unknown_protos_high[0x20];
1459
1460 u8 if_in_unknown_protos_low[0x20];
1461
1462 u8 if_out_octets_high[0x20];
1463
1464 u8 if_out_octets_low[0x20];
1465
1466 u8 if_out_ucast_pkts_high[0x20];
1467
1468 u8 if_out_ucast_pkts_low[0x20];
1469
1470 u8 if_out_discards_high[0x20];
1471
1472 u8 if_out_discards_low[0x20];
1473
1474 u8 if_out_errors_high[0x20];
1475
1476 u8 if_out_errors_low[0x20];
1477
1478 u8 if_in_multicast_pkts_high[0x20];
1479
1480 u8 if_in_multicast_pkts_low[0x20];
1481
1482 u8 if_in_broadcast_pkts_high[0x20];
1483
1484 u8 if_in_broadcast_pkts_low[0x20];
1485
1486 u8 if_out_multicast_pkts_high[0x20];
1487
1488 u8 if_out_multicast_pkts_low[0x20];
1489
1490 u8 if_out_broadcast_pkts_high[0x20];
1491
1492 u8 if_out_broadcast_pkts_low[0x20];
1493
1494 u8 reserved_at_340[0x480];
1495 };
1496
1497 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1498 u8 a_frames_transmitted_ok_high[0x20];
1499
1500 u8 a_frames_transmitted_ok_low[0x20];
1501
1502 u8 a_frames_received_ok_high[0x20];
1503
1504 u8 a_frames_received_ok_low[0x20];
1505
1506 u8 a_frame_check_sequence_errors_high[0x20];
1507
1508 u8 a_frame_check_sequence_errors_low[0x20];
1509
1510 u8 a_alignment_errors_high[0x20];
1511
1512 u8 a_alignment_errors_low[0x20];
1513
1514 u8 a_octets_transmitted_ok_high[0x20];
1515
1516 u8 a_octets_transmitted_ok_low[0x20];
1517
1518 u8 a_octets_received_ok_high[0x20];
1519
1520 u8 a_octets_received_ok_low[0x20];
1521
1522 u8 a_multicast_frames_xmitted_ok_high[0x20];
1523
1524 u8 a_multicast_frames_xmitted_ok_low[0x20];
1525
1526 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1527
1528 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1529
1530 u8 a_multicast_frames_received_ok_high[0x20];
1531
1532 u8 a_multicast_frames_received_ok_low[0x20];
1533
1534 u8 a_broadcast_frames_received_ok_high[0x20];
1535
1536 u8 a_broadcast_frames_received_ok_low[0x20];
1537
1538 u8 a_in_range_length_errors_high[0x20];
1539
1540 u8 a_in_range_length_errors_low[0x20];
1541
1542 u8 a_out_of_range_length_field_high[0x20];
1543
1544 u8 a_out_of_range_length_field_low[0x20];
1545
1546 u8 a_frame_too_long_errors_high[0x20];
1547
1548 u8 a_frame_too_long_errors_low[0x20];
1549
1550 u8 a_symbol_error_during_carrier_high[0x20];
1551
1552 u8 a_symbol_error_during_carrier_low[0x20];
1553
1554 u8 a_mac_control_frames_transmitted_high[0x20];
1555
1556 u8 a_mac_control_frames_transmitted_low[0x20];
1557
1558 u8 a_mac_control_frames_received_high[0x20];
1559
1560 u8 a_mac_control_frames_received_low[0x20];
1561
1562 u8 a_unsupported_opcodes_received_high[0x20];
1563
1564 u8 a_unsupported_opcodes_received_low[0x20];
1565
1566 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1567
1568 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1569
1570 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1571
1572 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1573
1574 u8 reserved_at_4c0[0x300];
1575 };
1576
1577 struct mlx5_ifc_cmd_inter_comp_event_bits {
1578 u8 command_completion_vector[0x20];
1579
1580 u8 reserved_at_20[0xc0];
1581 };
1582
1583 struct mlx5_ifc_stall_vl_event_bits {
1584 u8 reserved_at_0[0x18];
1585 u8 port_num[0x1];
1586 u8 reserved_at_19[0x3];
1587 u8 vl[0x4];
1588
1589 u8 reserved_at_20[0xa0];
1590 };
1591
1592 struct mlx5_ifc_db_bf_congestion_event_bits {
1593 u8 event_subtype[0x8];
1594 u8 reserved_at_8[0x8];
1595 u8 congestion_level[0x8];
1596 u8 reserved_at_18[0x8];
1597
1598 u8 reserved_at_20[0xa0];
1599 };
1600
1601 struct mlx5_ifc_gpio_event_bits {
1602 u8 reserved_at_0[0x60];
1603
1604 u8 gpio_event_hi[0x20];
1605
1606 u8 gpio_event_lo[0x20];
1607
1608 u8 reserved_at_a0[0x40];
1609 };
1610
1611 struct mlx5_ifc_port_state_change_event_bits {
1612 u8 reserved_at_0[0x40];
1613
1614 u8 port_num[0x4];
1615 u8 reserved_at_44[0x1c];
1616
1617 u8 reserved_at_60[0x80];
1618 };
1619
1620 struct mlx5_ifc_dropped_packet_logged_bits {
1621 u8 reserved_at_0[0xe0];
1622 };
1623
1624 enum {
1625 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1626 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1627 };
1628
1629 struct mlx5_ifc_cq_error_bits {
1630 u8 reserved_at_0[0x8];
1631 u8 cqn[0x18];
1632
1633 u8 reserved_at_20[0x20];
1634
1635 u8 reserved_at_40[0x18];
1636 u8 syndrome[0x8];
1637
1638 u8 reserved_at_60[0x80];
1639 };
1640
1641 struct mlx5_ifc_rdma_page_fault_event_bits {
1642 u8 bytes_committed[0x20];
1643
1644 u8 r_key[0x20];
1645
1646 u8 reserved_at_40[0x10];
1647 u8 packet_len[0x10];
1648
1649 u8 rdma_op_len[0x20];
1650
1651 u8 rdma_va[0x40];
1652
1653 u8 reserved_at_c0[0x5];
1654 u8 rdma[0x1];
1655 u8 write[0x1];
1656 u8 requestor[0x1];
1657 u8 qp_number[0x18];
1658 };
1659
1660 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1661 u8 bytes_committed[0x20];
1662
1663 u8 reserved_at_20[0x10];
1664 u8 wqe_index[0x10];
1665
1666 u8 reserved_at_40[0x10];
1667 u8 len[0x10];
1668
1669 u8 reserved_at_60[0x60];
1670
1671 u8 reserved_at_c0[0x5];
1672 u8 rdma[0x1];
1673 u8 write_read[0x1];
1674 u8 requestor[0x1];
1675 u8 qpn[0x18];
1676 };
1677
1678 struct mlx5_ifc_qp_events_bits {
1679 u8 reserved_at_0[0xa0];
1680
1681 u8 type[0x8];
1682 u8 reserved_at_a8[0x18];
1683
1684 u8 reserved_at_c0[0x8];
1685 u8 qpn_rqn_sqn[0x18];
1686 };
1687
1688 struct mlx5_ifc_dct_events_bits {
1689 u8 reserved_at_0[0xc0];
1690
1691 u8 reserved_at_c0[0x8];
1692 u8 dct_number[0x18];
1693 };
1694
1695 struct mlx5_ifc_comp_event_bits {
1696 u8 reserved_at_0[0xc0];
1697
1698 u8 reserved_at_c0[0x8];
1699 u8 cq_number[0x18];
1700 };
1701
1702 enum {
1703 MLX5_QPC_STATE_RST = 0x0,
1704 MLX5_QPC_STATE_INIT = 0x1,
1705 MLX5_QPC_STATE_RTR = 0x2,
1706 MLX5_QPC_STATE_RTS = 0x3,
1707 MLX5_QPC_STATE_SQER = 0x4,
1708 MLX5_QPC_STATE_ERR = 0x6,
1709 MLX5_QPC_STATE_SQD = 0x7,
1710 MLX5_QPC_STATE_SUSPENDED = 0x9,
1711 };
1712
1713 enum {
1714 MLX5_QPC_ST_RC = 0x0,
1715 MLX5_QPC_ST_UC = 0x1,
1716 MLX5_QPC_ST_UD = 0x2,
1717 MLX5_QPC_ST_XRC = 0x3,
1718 MLX5_QPC_ST_DCI = 0x5,
1719 MLX5_QPC_ST_QP0 = 0x7,
1720 MLX5_QPC_ST_QP1 = 0x8,
1721 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1722 MLX5_QPC_ST_REG_UMR = 0xc,
1723 };
1724
1725 enum {
1726 MLX5_QPC_PM_STATE_ARMED = 0x0,
1727 MLX5_QPC_PM_STATE_REARM = 0x1,
1728 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1729 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1730 };
1731
1732 enum {
1733 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1734 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1735 };
1736
1737 enum {
1738 MLX5_QPC_MTU_256_BYTES = 0x1,
1739 MLX5_QPC_MTU_512_BYTES = 0x2,
1740 MLX5_QPC_MTU_1K_BYTES = 0x3,
1741 MLX5_QPC_MTU_2K_BYTES = 0x4,
1742 MLX5_QPC_MTU_4K_BYTES = 0x5,
1743 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1744 };
1745
1746 enum {
1747 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1748 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1749 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1750 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1751 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1752 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1753 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1754 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1755 };
1756
1757 enum {
1758 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1759 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1760 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1761 };
1762
1763 enum {
1764 MLX5_QPC_CS_RES_DISABLE = 0x0,
1765 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1766 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1767 };
1768
1769 struct mlx5_ifc_qpc_bits {
1770 u8 state[0x4];
1771 u8 reserved_at_4[0x4];
1772 u8 st[0x8];
1773 u8 reserved_at_10[0x3];
1774 u8 pm_state[0x2];
1775 u8 reserved_at_15[0x7];
1776 u8 end_padding_mode[0x2];
1777 u8 reserved_at_1e[0x2];
1778
1779 u8 wq_signature[0x1];
1780 u8 block_lb_mc[0x1];
1781 u8 atomic_like_write_en[0x1];
1782 u8 latency_sensitive[0x1];
1783 u8 reserved_at_24[0x1];
1784 u8 drain_sigerr[0x1];
1785 u8 reserved_at_26[0x2];
1786 u8 pd[0x18];
1787
1788 u8 mtu[0x3];
1789 u8 log_msg_max[0x5];
1790 u8 reserved_at_48[0x1];
1791 u8 log_rq_size[0x4];
1792 u8 log_rq_stride[0x3];
1793 u8 no_sq[0x1];
1794 u8 log_sq_size[0x4];
1795 u8 reserved_at_55[0x6];
1796 u8 rlky[0x1];
1797 u8 reserved_at_5c[0x4];
1798
1799 u8 counter_set_id[0x8];
1800 u8 uar_page[0x18];
1801
1802 u8 reserved_at_80[0x8];
1803 u8 user_index[0x18];
1804
1805 u8 reserved_at_a0[0x3];
1806 u8 log_page_size[0x5];
1807 u8 remote_qpn[0x18];
1808
1809 struct mlx5_ifc_ads_bits primary_address_path;
1810
1811 struct mlx5_ifc_ads_bits secondary_address_path;
1812
1813 u8 log_ack_req_freq[0x4];
1814 u8 reserved_at_384[0x4];
1815 u8 log_sra_max[0x3];
1816 u8 reserved_at_38b[0x2];
1817 u8 retry_count[0x3];
1818 u8 rnr_retry[0x3];
1819 u8 reserved_at_393[0x1];
1820 u8 fre[0x1];
1821 u8 cur_rnr_retry[0x3];
1822 u8 cur_retry_count[0x3];
1823 u8 reserved_at_39b[0x5];
1824
1825 u8 reserved_at_3a0[0x20];
1826
1827 u8 reserved_at_3c0[0x8];
1828 u8 next_send_psn[0x18];
1829
1830 u8 reserved_at_3e0[0x8];
1831 u8 cqn_snd[0x18];
1832
1833 u8 reserved_at_400[0x40];
1834
1835 u8 reserved_at_440[0x8];
1836 u8 last_acked_psn[0x18];
1837
1838 u8 reserved_at_460[0x8];
1839 u8 ssn[0x18];
1840
1841 u8 reserved_at_480[0x8];
1842 u8 log_rra_max[0x3];
1843 u8 reserved_at_48b[0x1];
1844 u8 atomic_mode[0x4];
1845 u8 rre[0x1];
1846 u8 rwe[0x1];
1847 u8 rae[0x1];
1848 u8 reserved_at_493[0x1];
1849 u8 page_offset[0x6];
1850 u8 reserved_at_49a[0x3];
1851 u8 cd_slave_receive[0x1];
1852 u8 cd_slave_send[0x1];
1853 u8 cd_master[0x1];
1854
1855 u8 reserved_at_4a0[0x3];
1856 u8 min_rnr_nak[0x5];
1857 u8 next_rcv_psn[0x18];
1858
1859 u8 reserved_at_4c0[0x8];
1860 u8 xrcd[0x18];
1861
1862 u8 reserved_at_4e0[0x8];
1863 u8 cqn_rcv[0x18];
1864
1865 u8 dbr_addr[0x40];
1866
1867 u8 q_key[0x20];
1868
1869 u8 reserved_at_560[0x5];
1870 u8 rq_type[0x3];
1871 u8 srqn_rmpn[0x18];
1872
1873 u8 reserved_at_580[0x8];
1874 u8 rmsn[0x18];
1875
1876 u8 hw_sq_wqebb_counter[0x10];
1877 u8 sw_sq_wqebb_counter[0x10];
1878
1879 u8 hw_rq_counter[0x20];
1880
1881 u8 sw_rq_counter[0x20];
1882
1883 u8 reserved_at_600[0x20];
1884
1885 u8 reserved_at_620[0xf];
1886 u8 cgs[0x1];
1887 u8 cs_req[0x8];
1888 u8 cs_res[0x8];
1889
1890 u8 dc_access_key[0x40];
1891
1892 u8 reserved_at_680[0xc0];
1893 };
1894
1895 struct mlx5_ifc_roce_addr_layout_bits {
1896 u8 source_l3_address[16][0x8];
1897
1898 u8 reserved_at_80[0x3];
1899 u8 vlan_valid[0x1];
1900 u8 vlan_id[0xc];
1901 u8 source_mac_47_32[0x10];
1902
1903 u8 source_mac_31_0[0x20];
1904
1905 u8 reserved_at_c0[0x14];
1906 u8 roce_l3_type[0x4];
1907 u8 roce_version[0x8];
1908
1909 u8 reserved_at_e0[0x20];
1910 };
1911
1912 union mlx5_ifc_hca_cap_union_bits {
1913 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1914 struct mlx5_ifc_odp_cap_bits odp_cap;
1915 struct mlx5_ifc_atomic_caps_bits atomic_caps;
1916 struct mlx5_ifc_roce_cap_bits roce_cap;
1917 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1918 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1919 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
1920 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
1921 u8 reserved_at_0[0x8000];
1922 };
1923
1924 enum {
1925 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
1926 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
1927 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
1928 };
1929
1930 struct mlx5_ifc_flow_context_bits {
1931 u8 reserved_at_0[0x20];
1932
1933 u8 group_id[0x20];
1934
1935 u8 reserved_at_40[0x8];
1936 u8 flow_tag[0x18];
1937
1938 u8 reserved_at_60[0x10];
1939 u8 action[0x10];
1940
1941 u8 reserved_at_80[0x8];
1942 u8 destination_list_size[0x18];
1943
1944 u8 reserved_at_a0[0x160];
1945
1946 struct mlx5_ifc_fte_match_param_bits match_value;
1947
1948 u8 reserved_at_1200[0x600];
1949
1950 struct mlx5_ifc_dest_format_struct_bits destination[0];
1951 };
1952
1953 enum {
1954 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
1955 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
1956 };
1957
1958 struct mlx5_ifc_xrc_srqc_bits {
1959 u8 state[0x4];
1960 u8 log_xrc_srq_size[0x4];
1961 u8 reserved_at_8[0x18];
1962
1963 u8 wq_signature[0x1];
1964 u8 cont_srq[0x1];
1965 u8 reserved_at_22[0x1];
1966 u8 rlky[0x1];
1967 u8 basic_cyclic_rcv_wqe[0x1];
1968 u8 log_rq_stride[0x3];
1969 u8 xrcd[0x18];
1970
1971 u8 page_offset[0x6];
1972 u8 reserved_at_46[0x2];
1973 u8 cqn[0x18];
1974
1975 u8 reserved_at_60[0x20];
1976
1977 u8 user_index_equal_xrc_srqn[0x1];
1978 u8 reserved_at_81[0x1];
1979 u8 log_page_size[0x6];
1980 u8 user_index[0x18];
1981
1982 u8 reserved_at_a0[0x20];
1983
1984 u8 reserved_at_c0[0x8];
1985 u8 pd[0x18];
1986
1987 u8 lwm[0x10];
1988 u8 wqe_cnt[0x10];
1989
1990 u8 reserved_at_100[0x40];
1991
1992 u8 db_record_addr_h[0x20];
1993
1994 u8 db_record_addr_l[0x1e];
1995 u8 reserved_at_17e[0x2];
1996
1997 u8 reserved_at_180[0x80];
1998 };
1999
2000 struct mlx5_ifc_traffic_counter_bits {
2001 u8 packets[0x40];
2002
2003 u8 octets[0x40];
2004 };
2005
2006 struct mlx5_ifc_tisc_bits {
2007 u8 reserved_at_0[0xc];
2008 u8 prio[0x4];
2009 u8 reserved_at_10[0x10];
2010
2011 u8 reserved_at_20[0x100];
2012
2013 u8 reserved_at_120[0x8];
2014 u8 transport_domain[0x18];
2015
2016 u8 reserved_at_140[0x3c0];
2017 };
2018
2019 enum {
2020 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2021 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2022 };
2023
2024 enum {
2025 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2026 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2027 };
2028
2029 enum {
2030 MLX5_RX_HASH_FN_NONE = 0x0,
2031 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2032 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2033 };
2034
2035 enum {
2036 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2037 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2038 };
2039
2040 struct mlx5_ifc_tirc_bits {
2041 u8 reserved_at_0[0x20];
2042
2043 u8 disp_type[0x4];
2044 u8 reserved_at_24[0x1c];
2045
2046 u8 reserved_at_40[0x40];
2047
2048 u8 reserved_at_80[0x4];
2049 u8 lro_timeout_period_usecs[0x10];
2050 u8 lro_enable_mask[0x4];
2051 u8 lro_max_ip_payload_size[0x8];
2052
2053 u8 reserved_at_a0[0x40];
2054
2055 u8 reserved_at_e0[0x8];
2056 u8 inline_rqn[0x18];
2057
2058 u8 rx_hash_symmetric[0x1];
2059 u8 reserved_at_101[0x1];
2060 u8 tunneled_offload_en[0x1];
2061 u8 reserved_at_103[0x5];
2062 u8 indirect_table[0x18];
2063
2064 u8 rx_hash_fn[0x4];
2065 u8 reserved_at_124[0x2];
2066 u8 self_lb_block[0x2];
2067 u8 transport_domain[0x18];
2068
2069 u8 rx_hash_toeplitz_key[10][0x20];
2070
2071 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2072
2073 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2074
2075 u8 reserved_at_2c0[0x4c0];
2076 };
2077
2078 enum {
2079 MLX5_SRQC_STATE_GOOD = 0x0,
2080 MLX5_SRQC_STATE_ERROR = 0x1,
2081 };
2082
2083 struct mlx5_ifc_srqc_bits {
2084 u8 state[0x4];
2085 u8 log_srq_size[0x4];
2086 u8 reserved_at_8[0x18];
2087
2088 u8 wq_signature[0x1];
2089 u8 cont_srq[0x1];
2090 u8 reserved_at_22[0x1];
2091 u8 rlky[0x1];
2092 u8 reserved_at_24[0x1];
2093 u8 log_rq_stride[0x3];
2094 u8 xrcd[0x18];
2095
2096 u8 page_offset[0x6];
2097 u8 reserved_at_46[0x2];
2098 u8 cqn[0x18];
2099
2100 u8 reserved_at_60[0x20];
2101
2102 u8 reserved_at_80[0x2];
2103 u8 log_page_size[0x6];
2104 u8 reserved_at_88[0x18];
2105
2106 u8 reserved_at_a0[0x20];
2107
2108 u8 reserved_at_c0[0x8];
2109 u8 pd[0x18];
2110
2111 u8 lwm[0x10];
2112 u8 wqe_cnt[0x10];
2113
2114 u8 reserved_at_100[0x40];
2115
2116 u8 dbr_addr[0x40];
2117
2118 u8 reserved_at_180[0x80];
2119 };
2120
2121 enum {
2122 MLX5_SQC_STATE_RST = 0x0,
2123 MLX5_SQC_STATE_RDY = 0x1,
2124 MLX5_SQC_STATE_ERR = 0x3,
2125 };
2126
2127 struct mlx5_ifc_sqc_bits {
2128 u8 rlky[0x1];
2129 u8 cd_master[0x1];
2130 u8 fre[0x1];
2131 u8 flush_in_error_en[0x1];
2132 u8 reserved_at_4[0x4];
2133 u8 state[0x4];
2134 u8 reserved_at_c[0x14];
2135
2136 u8 reserved_at_20[0x8];
2137 u8 user_index[0x18];
2138
2139 u8 reserved_at_40[0x8];
2140 u8 cqn[0x18];
2141
2142 u8 reserved_at_60[0xa0];
2143
2144 u8 tis_lst_sz[0x10];
2145 u8 reserved_at_110[0x10];
2146
2147 u8 reserved_at_120[0x40];
2148
2149 u8 reserved_at_160[0x8];
2150 u8 tis_num_0[0x18];
2151
2152 struct mlx5_ifc_wq_bits wq;
2153 };
2154
2155 struct mlx5_ifc_rqtc_bits {
2156 u8 reserved_at_0[0xa0];
2157
2158 u8 reserved_at_a0[0x10];
2159 u8 rqt_max_size[0x10];
2160
2161 u8 reserved_at_c0[0x10];
2162 u8 rqt_actual_size[0x10];
2163
2164 u8 reserved_at_e0[0x6a0];
2165
2166 struct mlx5_ifc_rq_num_bits rq_num[0];
2167 };
2168
2169 enum {
2170 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2171 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2172 };
2173
2174 enum {
2175 MLX5_RQC_STATE_RST = 0x0,
2176 MLX5_RQC_STATE_RDY = 0x1,
2177 MLX5_RQC_STATE_ERR = 0x3,
2178 };
2179
2180 struct mlx5_ifc_rqc_bits {
2181 u8 rlky[0x1];
2182 u8 reserved_at_1[0x2];
2183 u8 vsd[0x1];
2184 u8 mem_rq_type[0x4];
2185 u8 state[0x4];
2186 u8 reserved_at_c[0x1];
2187 u8 flush_in_error_en[0x1];
2188 u8 reserved_at_e[0x12];
2189
2190 u8 reserved_at_20[0x8];
2191 u8 user_index[0x18];
2192
2193 u8 reserved_at_40[0x8];
2194 u8 cqn[0x18];
2195
2196 u8 counter_set_id[0x8];
2197 u8 reserved_at_68[0x18];
2198
2199 u8 reserved_at_80[0x8];
2200 u8 rmpn[0x18];
2201
2202 u8 reserved_at_a0[0xe0];
2203
2204 struct mlx5_ifc_wq_bits wq;
2205 };
2206
2207 enum {
2208 MLX5_RMPC_STATE_RDY = 0x1,
2209 MLX5_RMPC_STATE_ERR = 0x3,
2210 };
2211
2212 struct mlx5_ifc_rmpc_bits {
2213 u8 reserved_at_0[0x8];
2214 u8 state[0x4];
2215 u8 reserved_at_c[0x14];
2216
2217 u8 basic_cyclic_rcv_wqe[0x1];
2218 u8 reserved_at_21[0x1f];
2219
2220 u8 reserved_at_40[0x140];
2221
2222 struct mlx5_ifc_wq_bits wq;
2223 };
2224
2225 struct mlx5_ifc_nic_vport_context_bits {
2226 u8 reserved_at_0[0x1f];
2227 u8 roce_en[0x1];
2228
2229 u8 arm_change_event[0x1];
2230 u8 reserved_at_21[0x1a];
2231 u8 event_on_mtu[0x1];
2232 u8 event_on_promisc_change[0x1];
2233 u8 event_on_vlan_change[0x1];
2234 u8 event_on_mc_address_change[0x1];
2235 u8 event_on_uc_address_change[0x1];
2236
2237 u8 reserved_at_40[0xf0];
2238
2239 u8 mtu[0x10];
2240
2241 u8 system_image_guid[0x40];
2242 u8 port_guid[0x40];
2243 u8 node_guid[0x40];
2244
2245 u8 reserved_at_200[0x140];
2246 u8 qkey_violation_counter[0x10];
2247 u8 reserved_at_350[0x430];
2248
2249 u8 promisc_uc[0x1];
2250 u8 promisc_mc[0x1];
2251 u8 promisc_all[0x1];
2252 u8 reserved_at_783[0x2];
2253 u8 allowed_list_type[0x3];
2254 u8 reserved_at_788[0xc];
2255 u8 allowed_list_size[0xc];
2256
2257 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2258
2259 u8 reserved_at_7e0[0x20];
2260
2261 u8 current_uc_mac_address[0][0x40];
2262 };
2263
2264 enum {
2265 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2266 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2267 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2268 };
2269
2270 struct mlx5_ifc_mkc_bits {
2271 u8 reserved_at_0[0x1];
2272 u8 free[0x1];
2273 u8 reserved_at_2[0xd];
2274 u8 small_fence_on_rdma_read_response[0x1];
2275 u8 umr_en[0x1];
2276 u8 a[0x1];
2277 u8 rw[0x1];
2278 u8 rr[0x1];
2279 u8 lw[0x1];
2280 u8 lr[0x1];
2281 u8 access_mode[0x2];
2282 u8 reserved_at_18[0x8];
2283
2284 u8 qpn[0x18];
2285 u8 mkey_7_0[0x8];
2286
2287 u8 reserved_at_40[0x20];
2288
2289 u8 length64[0x1];
2290 u8 bsf_en[0x1];
2291 u8 sync_umr[0x1];
2292 u8 reserved_at_63[0x2];
2293 u8 expected_sigerr_count[0x1];
2294 u8 reserved_at_66[0x1];
2295 u8 en_rinval[0x1];
2296 u8 pd[0x18];
2297
2298 u8 start_addr[0x40];
2299
2300 u8 len[0x40];
2301
2302 u8 bsf_octword_size[0x20];
2303
2304 u8 reserved_at_120[0x80];
2305
2306 u8 translations_octword_size[0x20];
2307
2308 u8 reserved_at_1c0[0x1b];
2309 u8 log_page_size[0x5];
2310
2311 u8 reserved_at_1e0[0x20];
2312 };
2313
2314 struct mlx5_ifc_pkey_bits {
2315 u8 reserved_at_0[0x10];
2316 u8 pkey[0x10];
2317 };
2318
2319 struct mlx5_ifc_array128_auto_bits {
2320 u8 array128_auto[16][0x8];
2321 };
2322
2323 struct mlx5_ifc_hca_vport_context_bits {
2324 u8 field_select[0x20];
2325
2326 u8 reserved_at_20[0xe0];
2327
2328 u8 sm_virt_aware[0x1];
2329 u8 has_smi[0x1];
2330 u8 has_raw[0x1];
2331 u8 grh_required[0x1];
2332 u8 reserved_at_104[0xc];
2333 u8 port_physical_state[0x4];
2334 u8 vport_state_policy[0x4];
2335 u8 port_state[0x4];
2336 u8 vport_state[0x4];
2337
2338 u8 reserved_at_120[0x20];
2339
2340 u8 system_image_guid[0x40];
2341
2342 u8 port_guid[0x40];
2343
2344 u8 node_guid[0x40];
2345
2346 u8 cap_mask1[0x20];
2347
2348 u8 cap_mask1_field_select[0x20];
2349
2350 u8 cap_mask2[0x20];
2351
2352 u8 cap_mask2_field_select[0x20];
2353
2354 u8 reserved_at_280[0x80];
2355
2356 u8 lid[0x10];
2357 u8 reserved_at_310[0x4];
2358 u8 init_type_reply[0x4];
2359 u8 lmc[0x3];
2360 u8 subnet_timeout[0x5];
2361
2362 u8 sm_lid[0x10];
2363 u8 sm_sl[0x4];
2364 u8 reserved_at_334[0xc];
2365
2366 u8 qkey_violation_counter[0x10];
2367 u8 pkey_violation_counter[0x10];
2368
2369 u8 reserved_at_360[0xca0];
2370 };
2371
2372 struct mlx5_ifc_esw_vport_context_bits {
2373 u8 reserved_at_0[0x3];
2374 u8 vport_svlan_strip[0x1];
2375 u8 vport_cvlan_strip[0x1];
2376 u8 vport_svlan_insert[0x1];
2377 u8 vport_cvlan_insert[0x2];
2378 u8 reserved_at_8[0x18];
2379
2380 u8 reserved_at_20[0x20];
2381
2382 u8 svlan_cfi[0x1];
2383 u8 svlan_pcp[0x3];
2384 u8 svlan_id[0xc];
2385 u8 cvlan_cfi[0x1];
2386 u8 cvlan_pcp[0x3];
2387 u8 cvlan_id[0xc];
2388
2389 u8 reserved_at_60[0x7a0];
2390 };
2391
2392 enum {
2393 MLX5_EQC_STATUS_OK = 0x0,
2394 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2395 };
2396
2397 enum {
2398 MLX5_EQC_ST_ARMED = 0x9,
2399 MLX5_EQC_ST_FIRED = 0xa,
2400 };
2401
2402 struct mlx5_ifc_eqc_bits {
2403 u8 status[0x4];
2404 u8 reserved_at_4[0x9];
2405 u8 ec[0x1];
2406 u8 oi[0x1];
2407 u8 reserved_at_f[0x5];
2408 u8 st[0x4];
2409 u8 reserved_at_18[0x8];
2410
2411 u8 reserved_at_20[0x20];
2412
2413 u8 reserved_at_40[0x14];
2414 u8 page_offset[0x6];
2415 u8 reserved_at_5a[0x6];
2416
2417 u8 reserved_at_60[0x3];
2418 u8 log_eq_size[0x5];
2419 u8 uar_page[0x18];
2420
2421 u8 reserved_at_80[0x20];
2422
2423 u8 reserved_at_a0[0x18];
2424 u8 intr[0x8];
2425
2426 u8 reserved_at_c0[0x3];
2427 u8 log_page_size[0x5];
2428 u8 reserved_at_c8[0x18];
2429
2430 u8 reserved_at_e0[0x60];
2431
2432 u8 reserved_at_140[0x8];
2433 u8 consumer_counter[0x18];
2434
2435 u8 reserved_at_160[0x8];
2436 u8 producer_counter[0x18];
2437
2438 u8 reserved_at_180[0x80];
2439 };
2440
2441 enum {
2442 MLX5_DCTC_STATE_ACTIVE = 0x0,
2443 MLX5_DCTC_STATE_DRAINING = 0x1,
2444 MLX5_DCTC_STATE_DRAINED = 0x2,
2445 };
2446
2447 enum {
2448 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2449 MLX5_DCTC_CS_RES_NA = 0x1,
2450 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2451 };
2452
2453 enum {
2454 MLX5_DCTC_MTU_256_BYTES = 0x1,
2455 MLX5_DCTC_MTU_512_BYTES = 0x2,
2456 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2457 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2458 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2459 };
2460
2461 struct mlx5_ifc_dctc_bits {
2462 u8 reserved_at_0[0x4];
2463 u8 state[0x4];
2464 u8 reserved_at_8[0x18];
2465
2466 u8 reserved_at_20[0x8];
2467 u8 user_index[0x18];
2468
2469 u8 reserved_at_40[0x8];
2470 u8 cqn[0x18];
2471
2472 u8 counter_set_id[0x8];
2473 u8 atomic_mode[0x4];
2474 u8 rre[0x1];
2475 u8 rwe[0x1];
2476 u8 rae[0x1];
2477 u8 atomic_like_write_en[0x1];
2478 u8 latency_sensitive[0x1];
2479 u8 rlky[0x1];
2480 u8 free_ar[0x1];
2481 u8 reserved_at_73[0xd];
2482
2483 u8 reserved_at_80[0x8];
2484 u8 cs_res[0x8];
2485 u8 reserved_at_90[0x3];
2486 u8 min_rnr_nak[0x5];
2487 u8 reserved_at_98[0x8];
2488
2489 u8 reserved_at_a0[0x8];
2490 u8 srqn[0x18];
2491
2492 u8 reserved_at_c0[0x8];
2493 u8 pd[0x18];
2494
2495 u8 tclass[0x8];
2496 u8 reserved_at_e8[0x4];
2497 u8 flow_label[0x14];
2498
2499 u8 dc_access_key[0x40];
2500
2501 u8 reserved_at_140[0x5];
2502 u8 mtu[0x3];
2503 u8 port[0x8];
2504 u8 pkey_index[0x10];
2505
2506 u8 reserved_at_160[0x8];
2507 u8 my_addr_index[0x8];
2508 u8 reserved_at_170[0x8];
2509 u8 hop_limit[0x8];
2510
2511 u8 dc_access_key_violation_count[0x20];
2512
2513 u8 reserved_at_1a0[0x14];
2514 u8 dei_cfi[0x1];
2515 u8 eth_prio[0x3];
2516 u8 ecn[0x2];
2517 u8 dscp[0x6];
2518
2519 u8 reserved_at_1c0[0x40];
2520 };
2521
2522 enum {
2523 MLX5_CQC_STATUS_OK = 0x0,
2524 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2525 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2526 };
2527
2528 enum {
2529 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2530 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2531 };
2532
2533 enum {
2534 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2535 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2536 MLX5_CQC_ST_FIRED = 0xa,
2537 };
2538
2539 struct mlx5_ifc_cqc_bits {
2540 u8 status[0x4];
2541 u8 reserved_at_4[0x4];
2542 u8 cqe_sz[0x3];
2543 u8 cc[0x1];
2544 u8 reserved_at_c[0x1];
2545 u8 scqe_break_moderation_en[0x1];
2546 u8 oi[0x1];
2547 u8 reserved_at_f[0x2];
2548 u8 cqe_zip_en[0x1];
2549 u8 mini_cqe_res_format[0x2];
2550 u8 st[0x4];
2551 u8 reserved_at_18[0x8];
2552
2553 u8 reserved_at_20[0x20];
2554
2555 u8 reserved_at_40[0x14];
2556 u8 page_offset[0x6];
2557 u8 reserved_at_5a[0x6];
2558
2559 u8 reserved_at_60[0x3];
2560 u8 log_cq_size[0x5];
2561 u8 uar_page[0x18];
2562
2563 u8 reserved_at_80[0x4];
2564 u8 cq_period[0xc];
2565 u8 cq_max_count[0x10];
2566
2567 u8 reserved_at_a0[0x18];
2568 u8 c_eqn[0x8];
2569
2570 u8 reserved_at_c0[0x3];
2571 u8 log_page_size[0x5];
2572 u8 reserved_at_c8[0x18];
2573
2574 u8 reserved_at_e0[0x20];
2575
2576 u8 reserved_at_100[0x8];
2577 u8 last_notified_index[0x18];
2578
2579 u8 reserved_at_120[0x8];
2580 u8 last_solicit_index[0x18];
2581
2582 u8 reserved_at_140[0x8];
2583 u8 consumer_counter[0x18];
2584
2585 u8 reserved_at_160[0x8];
2586 u8 producer_counter[0x18];
2587
2588 u8 reserved_at_180[0x40];
2589
2590 u8 dbr_addr[0x40];
2591 };
2592
2593 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2594 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2595 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2596 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2597 u8 reserved_at_0[0x800];
2598 };
2599
2600 struct mlx5_ifc_query_adapter_param_block_bits {
2601 u8 reserved_at_0[0xc0];
2602
2603 u8 reserved_at_c0[0x8];
2604 u8 ieee_vendor_id[0x18];
2605
2606 u8 reserved_at_e0[0x10];
2607 u8 vsd_vendor_id[0x10];
2608
2609 u8 vsd[208][0x8];
2610
2611 u8 vsd_contd_psid[16][0x8];
2612 };
2613
2614 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2615 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2616 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2617 u8 reserved_at_0[0x20];
2618 };
2619
2620 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2621 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2622 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2623 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2624 u8 reserved_at_0[0x20];
2625 };
2626
2627 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2628 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2629 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2630 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2631 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2632 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2633 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2634 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2635 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2636 u8 reserved_at_0[0x7c0];
2637 };
2638
2639 union mlx5_ifc_event_auto_bits {
2640 struct mlx5_ifc_comp_event_bits comp_event;
2641 struct mlx5_ifc_dct_events_bits dct_events;
2642 struct mlx5_ifc_qp_events_bits qp_events;
2643 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2644 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2645 struct mlx5_ifc_cq_error_bits cq_error;
2646 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2647 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2648 struct mlx5_ifc_gpio_event_bits gpio_event;
2649 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2650 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2651 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2652 u8 reserved_at_0[0xe0];
2653 };
2654
2655 struct mlx5_ifc_health_buffer_bits {
2656 u8 reserved_at_0[0x100];
2657
2658 u8 assert_existptr[0x20];
2659
2660 u8 assert_callra[0x20];
2661
2662 u8 reserved_at_140[0x40];
2663
2664 u8 fw_version[0x20];
2665
2666 u8 hw_id[0x20];
2667
2668 u8 reserved_at_1c0[0x20];
2669
2670 u8 irisc_index[0x8];
2671 u8 synd[0x8];
2672 u8 ext_synd[0x10];
2673 };
2674
2675 struct mlx5_ifc_register_loopback_control_bits {
2676 u8 no_lb[0x1];
2677 u8 reserved_at_1[0x7];
2678 u8 port[0x8];
2679 u8 reserved_at_10[0x10];
2680
2681 u8 reserved_at_20[0x60];
2682 };
2683
2684 struct mlx5_ifc_teardown_hca_out_bits {
2685 u8 status[0x8];
2686 u8 reserved_at_8[0x18];
2687
2688 u8 syndrome[0x20];
2689
2690 u8 reserved_at_40[0x40];
2691 };
2692
2693 enum {
2694 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2695 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2696 };
2697
2698 struct mlx5_ifc_teardown_hca_in_bits {
2699 u8 opcode[0x10];
2700 u8 reserved_at_10[0x10];
2701
2702 u8 reserved_at_20[0x10];
2703 u8 op_mod[0x10];
2704
2705 u8 reserved_at_40[0x10];
2706 u8 profile[0x10];
2707
2708 u8 reserved_at_60[0x20];
2709 };
2710
2711 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2712 u8 status[0x8];
2713 u8 reserved_at_8[0x18];
2714
2715 u8 syndrome[0x20];
2716
2717 u8 reserved_at_40[0x40];
2718 };
2719
2720 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2721 u8 opcode[0x10];
2722 u8 reserved_at_10[0x10];
2723
2724 u8 reserved_at_20[0x10];
2725 u8 op_mod[0x10];
2726
2727 u8 reserved_at_40[0x8];
2728 u8 qpn[0x18];
2729
2730 u8 reserved_at_60[0x20];
2731
2732 u8 opt_param_mask[0x20];
2733
2734 u8 reserved_at_a0[0x20];
2735
2736 struct mlx5_ifc_qpc_bits qpc;
2737
2738 u8 reserved_at_800[0x80];
2739 };
2740
2741 struct mlx5_ifc_sqd2rts_qp_out_bits {
2742 u8 status[0x8];
2743 u8 reserved_at_8[0x18];
2744
2745 u8 syndrome[0x20];
2746
2747 u8 reserved_at_40[0x40];
2748 };
2749
2750 struct mlx5_ifc_sqd2rts_qp_in_bits {
2751 u8 opcode[0x10];
2752 u8 reserved_at_10[0x10];
2753
2754 u8 reserved_at_20[0x10];
2755 u8 op_mod[0x10];
2756
2757 u8 reserved_at_40[0x8];
2758 u8 qpn[0x18];
2759
2760 u8 reserved_at_60[0x20];
2761
2762 u8 opt_param_mask[0x20];
2763
2764 u8 reserved_at_a0[0x20];
2765
2766 struct mlx5_ifc_qpc_bits qpc;
2767
2768 u8 reserved_at_800[0x80];
2769 };
2770
2771 struct mlx5_ifc_set_roce_address_out_bits {
2772 u8 status[0x8];
2773 u8 reserved_at_8[0x18];
2774
2775 u8 syndrome[0x20];
2776
2777 u8 reserved_at_40[0x40];
2778 };
2779
2780 struct mlx5_ifc_set_roce_address_in_bits {
2781 u8 opcode[0x10];
2782 u8 reserved_at_10[0x10];
2783
2784 u8 reserved_at_20[0x10];
2785 u8 op_mod[0x10];
2786
2787 u8 roce_address_index[0x10];
2788 u8 reserved_at_50[0x10];
2789
2790 u8 reserved_at_60[0x20];
2791
2792 struct mlx5_ifc_roce_addr_layout_bits roce_address;
2793 };
2794
2795 struct mlx5_ifc_set_mad_demux_out_bits {
2796 u8 status[0x8];
2797 u8 reserved_at_8[0x18];
2798
2799 u8 syndrome[0x20];
2800
2801 u8 reserved_at_40[0x40];
2802 };
2803
2804 enum {
2805 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
2806 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
2807 };
2808
2809 struct mlx5_ifc_set_mad_demux_in_bits {
2810 u8 opcode[0x10];
2811 u8 reserved_at_10[0x10];
2812
2813 u8 reserved_at_20[0x10];
2814 u8 op_mod[0x10];
2815
2816 u8 reserved_at_40[0x20];
2817
2818 u8 reserved_at_60[0x6];
2819 u8 demux_mode[0x2];
2820 u8 reserved_at_68[0x18];
2821 };
2822
2823 struct mlx5_ifc_set_l2_table_entry_out_bits {
2824 u8 status[0x8];
2825 u8 reserved_at_8[0x18];
2826
2827 u8 syndrome[0x20];
2828
2829 u8 reserved_at_40[0x40];
2830 };
2831
2832 struct mlx5_ifc_set_l2_table_entry_in_bits {
2833 u8 opcode[0x10];
2834 u8 reserved_at_10[0x10];
2835
2836 u8 reserved_at_20[0x10];
2837 u8 op_mod[0x10];
2838
2839 u8 reserved_at_40[0x60];
2840
2841 u8 reserved_at_a0[0x8];
2842 u8 table_index[0x18];
2843
2844 u8 reserved_at_c0[0x20];
2845
2846 u8 reserved_at_e0[0x13];
2847 u8 vlan_valid[0x1];
2848 u8 vlan[0xc];
2849
2850 struct mlx5_ifc_mac_address_layout_bits mac_address;
2851
2852 u8 reserved_at_140[0xc0];
2853 };
2854
2855 struct mlx5_ifc_set_issi_out_bits {
2856 u8 status[0x8];
2857 u8 reserved_at_8[0x18];
2858
2859 u8 syndrome[0x20];
2860
2861 u8 reserved_at_40[0x40];
2862 };
2863
2864 struct mlx5_ifc_set_issi_in_bits {
2865 u8 opcode[0x10];
2866 u8 reserved_at_10[0x10];
2867
2868 u8 reserved_at_20[0x10];
2869 u8 op_mod[0x10];
2870
2871 u8 reserved_at_40[0x10];
2872 u8 current_issi[0x10];
2873
2874 u8 reserved_at_60[0x20];
2875 };
2876
2877 struct mlx5_ifc_set_hca_cap_out_bits {
2878 u8 status[0x8];
2879 u8 reserved_at_8[0x18];
2880
2881 u8 syndrome[0x20];
2882
2883 u8 reserved_at_40[0x40];
2884 };
2885
2886 struct mlx5_ifc_set_hca_cap_in_bits {
2887 u8 opcode[0x10];
2888 u8 reserved_at_10[0x10];
2889
2890 u8 reserved_at_20[0x10];
2891 u8 op_mod[0x10];
2892
2893 u8 reserved_at_40[0x40];
2894
2895 union mlx5_ifc_hca_cap_union_bits capability;
2896 };
2897
2898 enum {
2899 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
2900 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
2901 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
2902 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
2903 };
2904
2905 struct mlx5_ifc_set_fte_out_bits {
2906 u8 status[0x8];
2907 u8 reserved_at_8[0x18];
2908
2909 u8 syndrome[0x20];
2910
2911 u8 reserved_at_40[0x40];
2912 };
2913
2914 struct mlx5_ifc_set_fte_in_bits {
2915 u8 opcode[0x10];
2916 u8 reserved_at_10[0x10];
2917
2918 u8 reserved_at_20[0x10];
2919 u8 op_mod[0x10];
2920
2921 u8 reserved_at_40[0x40];
2922
2923 u8 table_type[0x8];
2924 u8 reserved_at_88[0x18];
2925
2926 u8 reserved_at_a0[0x8];
2927 u8 table_id[0x18];
2928
2929 u8 reserved_at_c0[0x18];
2930 u8 modify_enable_mask[0x8];
2931
2932 u8 reserved_at_e0[0x20];
2933
2934 u8 flow_index[0x20];
2935
2936 u8 reserved_at_120[0xe0];
2937
2938 struct mlx5_ifc_flow_context_bits flow_context;
2939 };
2940
2941 struct mlx5_ifc_rts2rts_qp_out_bits {
2942 u8 status[0x8];
2943 u8 reserved_at_8[0x18];
2944
2945 u8 syndrome[0x20];
2946
2947 u8 reserved_at_40[0x40];
2948 };
2949
2950 struct mlx5_ifc_rts2rts_qp_in_bits {
2951 u8 opcode[0x10];
2952 u8 reserved_at_10[0x10];
2953
2954 u8 reserved_at_20[0x10];
2955 u8 op_mod[0x10];
2956
2957 u8 reserved_at_40[0x8];
2958 u8 qpn[0x18];
2959
2960 u8 reserved_at_60[0x20];
2961
2962 u8 opt_param_mask[0x20];
2963
2964 u8 reserved_at_a0[0x20];
2965
2966 struct mlx5_ifc_qpc_bits qpc;
2967
2968 u8 reserved_at_800[0x80];
2969 };
2970
2971 struct mlx5_ifc_rtr2rts_qp_out_bits {
2972 u8 status[0x8];
2973 u8 reserved_at_8[0x18];
2974
2975 u8 syndrome[0x20];
2976
2977 u8 reserved_at_40[0x40];
2978 };
2979
2980 struct mlx5_ifc_rtr2rts_qp_in_bits {
2981 u8 opcode[0x10];
2982 u8 reserved_at_10[0x10];
2983
2984 u8 reserved_at_20[0x10];
2985 u8 op_mod[0x10];
2986
2987 u8 reserved_at_40[0x8];
2988 u8 qpn[0x18];
2989
2990 u8 reserved_at_60[0x20];
2991
2992 u8 opt_param_mask[0x20];
2993
2994 u8 reserved_at_a0[0x20];
2995
2996 struct mlx5_ifc_qpc_bits qpc;
2997
2998 u8 reserved_at_800[0x80];
2999 };
3000
3001 struct mlx5_ifc_rst2init_qp_out_bits {
3002 u8 status[0x8];
3003 u8 reserved_at_8[0x18];
3004
3005 u8 syndrome[0x20];
3006
3007 u8 reserved_at_40[0x40];
3008 };
3009
3010 struct mlx5_ifc_rst2init_qp_in_bits {
3011 u8 opcode[0x10];
3012 u8 reserved_at_10[0x10];
3013
3014 u8 reserved_at_20[0x10];
3015 u8 op_mod[0x10];
3016
3017 u8 reserved_at_40[0x8];
3018 u8 qpn[0x18];
3019
3020 u8 reserved_at_60[0x20];
3021
3022 u8 opt_param_mask[0x20];
3023
3024 u8 reserved_at_a0[0x20];
3025
3026 struct mlx5_ifc_qpc_bits qpc;
3027
3028 u8 reserved_at_800[0x80];
3029 };
3030
3031 struct mlx5_ifc_query_xrc_srq_out_bits {
3032 u8 status[0x8];
3033 u8 reserved_at_8[0x18];
3034
3035 u8 syndrome[0x20];
3036
3037 u8 reserved_at_40[0x40];
3038
3039 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3040
3041 u8 reserved_at_280[0x600];
3042
3043 u8 pas[0][0x40];
3044 };
3045
3046 struct mlx5_ifc_query_xrc_srq_in_bits {
3047 u8 opcode[0x10];
3048 u8 reserved_at_10[0x10];
3049
3050 u8 reserved_at_20[0x10];
3051 u8 op_mod[0x10];
3052
3053 u8 reserved_at_40[0x8];
3054 u8 xrc_srqn[0x18];
3055
3056 u8 reserved_at_60[0x20];
3057 };
3058
3059 enum {
3060 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3061 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3062 };
3063
3064 struct mlx5_ifc_query_vport_state_out_bits {
3065 u8 status[0x8];
3066 u8 reserved_at_8[0x18];
3067
3068 u8 syndrome[0x20];
3069
3070 u8 reserved_at_40[0x20];
3071
3072 u8 reserved_at_60[0x18];
3073 u8 admin_state[0x4];
3074 u8 state[0x4];
3075 };
3076
3077 enum {
3078 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3079 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3080 };
3081
3082 struct mlx5_ifc_query_vport_state_in_bits {
3083 u8 opcode[0x10];
3084 u8 reserved_at_10[0x10];
3085
3086 u8 reserved_at_20[0x10];
3087 u8 op_mod[0x10];
3088
3089 u8 other_vport[0x1];
3090 u8 reserved_at_41[0xf];
3091 u8 vport_number[0x10];
3092
3093 u8 reserved_at_60[0x20];
3094 };
3095
3096 struct mlx5_ifc_query_vport_counter_out_bits {
3097 u8 status[0x8];
3098 u8 reserved_at_8[0x18];
3099
3100 u8 syndrome[0x20];
3101
3102 u8 reserved_at_40[0x40];
3103
3104 struct mlx5_ifc_traffic_counter_bits received_errors;
3105
3106 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3107
3108 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3109
3110 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3111
3112 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3113
3114 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3115
3116 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3117
3118 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3119
3120 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3121
3122 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3123
3124 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3125
3126 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3127
3128 u8 reserved_at_680[0xa00];
3129 };
3130
3131 enum {
3132 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3133 };
3134
3135 struct mlx5_ifc_query_vport_counter_in_bits {
3136 u8 opcode[0x10];
3137 u8 reserved_at_10[0x10];
3138
3139 u8 reserved_at_20[0x10];
3140 u8 op_mod[0x10];
3141
3142 u8 other_vport[0x1];
3143 u8 reserved_at_41[0xf];
3144 u8 vport_number[0x10];
3145
3146 u8 reserved_at_60[0x60];
3147
3148 u8 clear[0x1];
3149 u8 reserved_at_c1[0x1f];
3150
3151 u8 reserved_at_e0[0x20];
3152 };
3153
3154 struct mlx5_ifc_query_tis_out_bits {
3155 u8 status[0x8];
3156 u8 reserved_at_8[0x18];
3157
3158 u8 syndrome[0x20];
3159
3160 u8 reserved_at_40[0x40];
3161
3162 struct mlx5_ifc_tisc_bits tis_context;
3163 };
3164
3165 struct mlx5_ifc_query_tis_in_bits {
3166 u8 opcode[0x10];
3167 u8 reserved_at_10[0x10];
3168
3169 u8 reserved_at_20[0x10];
3170 u8 op_mod[0x10];
3171
3172 u8 reserved_at_40[0x8];
3173 u8 tisn[0x18];
3174
3175 u8 reserved_at_60[0x20];
3176 };
3177
3178 struct mlx5_ifc_query_tir_out_bits {
3179 u8 status[0x8];
3180 u8 reserved_at_8[0x18];
3181
3182 u8 syndrome[0x20];
3183
3184 u8 reserved_at_40[0xc0];
3185
3186 struct mlx5_ifc_tirc_bits tir_context;
3187 };
3188
3189 struct mlx5_ifc_query_tir_in_bits {
3190 u8 opcode[0x10];
3191 u8 reserved_at_10[0x10];
3192
3193 u8 reserved_at_20[0x10];
3194 u8 op_mod[0x10];
3195
3196 u8 reserved_at_40[0x8];
3197 u8 tirn[0x18];
3198
3199 u8 reserved_at_60[0x20];
3200 };
3201
3202 struct mlx5_ifc_query_srq_out_bits {
3203 u8 status[0x8];
3204 u8 reserved_at_8[0x18];
3205
3206 u8 syndrome[0x20];
3207
3208 u8 reserved_at_40[0x40];
3209
3210 struct mlx5_ifc_srqc_bits srq_context_entry;
3211
3212 u8 reserved_at_280[0x600];
3213
3214 u8 pas[0][0x40];
3215 };
3216
3217 struct mlx5_ifc_query_srq_in_bits {
3218 u8 opcode[0x10];
3219 u8 reserved_at_10[0x10];
3220
3221 u8 reserved_at_20[0x10];
3222 u8 op_mod[0x10];
3223
3224 u8 reserved_at_40[0x8];
3225 u8 srqn[0x18];
3226
3227 u8 reserved_at_60[0x20];
3228 };
3229
3230 struct mlx5_ifc_query_sq_out_bits {
3231 u8 status[0x8];
3232 u8 reserved_at_8[0x18];
3233
3234 u8 syndrome[0x20];
3235
3236 u8 reserved_at_40[0xc0];
3237
3238 struct mlx5_ifc_sqc_bits sq_context;
3239 };
3240
3241 struct mlx5_ifc_query_sq_in_bits {
3242 u8 opcode[0x10];
3243 u8 reserved_at_10[0x10];
3244
3245 u8 reserved_at_20[0x10];
3246 u8 op_mod[0x10];
3247
3248 u8 reserved_at_40[0x8];
3249 u8 sqn[0x18];
3250
3251 u8 reserved_at_60[0x20];
3252 };
3253
3254 struct mlx5_ifc_query_special_contexts_out_bits {
3255 u8 status[0x8];
3256 u8 reserved_at_8[0x18];
3257
3258 u8 syndrome[0x20];
3259
3260 u8 reserved_at_40[0x20];
3261
3262 u8 resd_lkey[0x20];
3263 };
3264
3265 struct mlx5_ifc_query_special_contexts_in_bits {
3266 u8 opcode[0x10];
3267 u8 reserved_at_10[0x10];
3268
3269 u8 reserved_at_20[0x10];
3270 u8 op_mod[0x10];
3271
3272 u8 reserved_at_40[0x40];
3273 };
3274
3275 struct mlx5_ifc_query_rqt_out_bits {
3276 u8 status[0x8];
3277 u8 reserved_at_8[0x18];
3278
3279 u8 syndrome[0x20];
3280
3281 u8 reserved_at_40[0xc0];
3282
3283 struct mlx5_ifc_rqtc_bits rqt_context;
3284 };
3285
3286 struct mlx5_ifc_query_rqt_in_bits {
3287 u8 opcode[0x10];
3288 u8 reserved_at_10[0x10];
3289
3290 u8 reserved_at_20[0x10];
3291 u8 op_mod[0x10];
3292
3293 u8 reserved_at_40[0x8];
3294 u8 rqtn[0x18];
3295
3296 u8 reserved_at_60[0x20];
3297 };
3298
3299 struct mlx5_ifc_query_rq_out_bits {
3300 u8 status[0x8];
3301 u8 reserved_at_8[0x18];
3302
3303 u8 syndrome[0x20];
3304
3305 u8 reserved_at_40[0xc0];
3306
3307 struct mlx5_ifc_rqc_bits rq_context;
3308 };
3309
3310 struct mlx5_ifc_query_rq_in_bits {
3311 u8 opcode[0x10];
3312 u8 reserved_at_10[0x10];
3313
3314 u8 reserved_at_20[0x10];
3315 u8 op_mod[0x10];
3316
3317 u8 reserved_at_40[0x8];
3318 u8 rqn[0x18];
3319
3320 u8 reserved_at_60[0x20];
3321 };
3322
3323 struct mlx5_ifc_query_roce_address_out_bits {
3324 u8 status[0x8];
3325 u8 reserved_at_8[0x18];
3326
3327 u8 syndrome[0x20];
3328
3329 u8 reserved_at_40[0x40];
3330
3331 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3332 };
3333
3334 struct mlx5_ifc_query_roce_address_in_bits {
3335 u8 opcode[0x10];
3336 u8 reserved_at_10[0x10];
3337
3338 u8 reserved_at_20[0x10];
3339 u8 op_mod[0x10];
3340
3341 u8 roce_address_index[0x10];
3342 u8 reserved_at_50[0x10];
3343
3344 u8 reserved_at_60[0x20];
3345 };
3346
3347 struct mlx5_ifc_query_rmp_out_bits {
3348 u8 status[0x8];
3349 u8 reserved_at_8[0x18];
3350
3351 u8 syndrome[0x20];
3352
3353 u8 reserved_at_40[0xc0];
3354
3355 struct mlx5_ifc_rmpc_bits rmp_context;
3356 };
3357
3358 struct mlx5_ifc_query_rmp_in_bits {
3359 u8 opcode[0x10];
3360 u8 reserved_at_10[0x10];
3361
3362 u8 reserved_at_20[0x10];
3363 u8 op_mod[0x10];
3364
3365 u8 reserved_at_40[0x8];
3366 u8 rmpn[0x18];
3367
3368 u8 reserved_at_60[0x20];
3369 };
3370
3371 struct mlx5_ifc_query_qp_out_bits {
3372 u8 status[0x8];
3373 u8 reserved_at_8[0x18];
3374
3375 u8 syndrome[0x20];
3376
3377 u8 reserved_at_40[0x40];
3378
3379 u8 opt_param_mask[0x20];
3380
3381 u8 reserved_at_a0[0x20];
3382
3383 struct mlx5_ifc_qpc_bits qpc;
3384
3385 u8 reserved_at_800[0x80];
3386
3387 u8 pas[0][0x40];
3388 };
3389
3390 struct mlx5_ifc_query_qp_in_bits {
3391 u8 opcode[0x10];
3392 u8 reserved_at_10[0x10];
3393
3394 u8 reserved_at_20[0x10];
3395 u8 op_mod[0x10];
3396
3397 u8 reserved_at_40[0x8];
3398 u8 qpn[0x18];
3399
3400 u8 reserved_at_60[0x20];
3401 };
3402
3403 struct mlx5_ifc_query_q_counter_out_bits {
3404 u8 status[0x8];
3405 u8 reserved_at_8[0x18];
3406
3407 u8 syndrome[0x20];
3408
3409 u8 reserved_at_40[0x40];
3410
3411 u8 rx_write_requests[0x20];
3412
3413 u8 reserved_at_a0[0x20];
3414
3415 u8 rx_read_requests[0x20];
3416
3417 u8 reserved_at_e0[0x20];
3418
3419 u8 rx_atomic_requests[0x20];
3420
3421 u8 reserved_at_120[0x20];
3422
3423 u8 rx_dct_connect[0x20];
3424
3425 u8 reserved_at_160[0x20];
3426
3427 u8 out_of_buffer[0x20];
3428
3429 u8 reserved_at_1a0[0x20];
3430
3431 u8 out_of_sequence[0x20];
3432
3433 u8 reserved_at_1e0[0x620];
3434 };
3435
3436 struct mlx5_ifc_query_q_counter_in_bits {
3437 u8 opcode[0x10];
3438 u8 reserved_at_10[0x10];
3439
3440 u8 reserved_at_20[0x10];
3441 u8 op_mod[0x10];
3442
3443 u8 reserved_at_40[0x80];
3444
3445 u8 clear[0x1];
3446 u8 reserved_at_c1[0x1f];
3447
3448 u8 reserved_at_e0[0x18];
3449 u8 counter_set_id[0x8];
3450 };
3451
3452 struct mlx5_ifc_query_pages_out_bits {
3453 u8 status[0x8];
3454 u8 reserved_at_8[0x18];
3455
3456 u8 syndrome[0x20];
3457
3458 u8 reserved_at_40[0x10];
3459 u8 function_id[0x10];
3460
3461 u8 num_pages[0x20];
3462 };
3463
3464 enum {
3465 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3466 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3467 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3468 };
3469
3470 struct mlx5_ifc_query_pages_in_bits {
3471 u8 opcode[0x10];
3472 u8 reserved_at_10[0x10];
3473
3474 u8 reserved_at_20[0x10];
3475 u8 op_mod[0x10];
3476
3477 u8 reserved_at_40[0x10];
3478 u8 function_id[0x10];
3479
3480 u8 reserved_at_60[0x20];
3481 };
3482
3483 struct mlx5_ifc_query_nic_vport_context_out_bits {
3484 u8 status[0x8];
3485 u8 reserved_at_8[0x18];
3486
3487 u8 syndrome[0x20];
3488
3489 u8 reserved_at_40[0x40];
3490
3491 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3492 };
3493
3494 struct mlx5_ifc_query_nic_vport_context_in_bits {
3495 u8 opcode[0x10];
3496 u8 reserved_at_10[0x10];
3497
3498 u8 reserved_at_20[0x10];
3499 u8 op_mod[0x10];
3500
3501 u8 other_vport[0x1];
3502 u8 reserved_at_41[0xf];
3503 u8 vport_number[0x10];
3504
3505 u8 reserved_at_60[0x5];
3506 u8 allowed_list_type[0x3];
3507 u8 reserved_at_68[0x18];
3508 };
3509
3510 struct mlx5_ifc_query_mkey_out_bits {
3511 u8 status[0x8];
3512 u8 reserved_at_8[0x18];
3513
3514 u8 syndrome[0x20];
3515
3516 u8 reserved_at_40[0x40];
3517
3518 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3519
3520 u8 reserved_at_280[0x600];
3521
3522 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3523
3524 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3525 };
3526
3527 struct mlx5_ifc_query_mkey_in_bits {
3528 u8 opcode[0x10];
3529 u8 reserved_at_10[0x10];
3530
3531 u8 reserved_at_20[0x10];
3532 u8 op_mod[0x10];
3533
3534 u8 reserved_at_40[0x8];
3535 u8 mkey_index[0x18];
3536
3537 u8 pg_access[0x1];
3538 u8 reserved_at_61[0x1f];
3539 };
3540
3541 struct mlx5_ifc_query_mad_demux_out_bits {
3542 u8 status[0x8];
3543 u8 reserved_at_8[0x18];
3544
3545 u8 syndrome[0x20];
3546
3547 u8 reserved_at_40[0x40];
3548
3549 u8 mad_dumux_parameters_block[0x20];
3550 };
3551
3552 struct mlx5_ifc_query_mad_demux_in_bits {
3553 u8 opcode[0x10];
3554 u8 reserved_at_10[0x10];
3555
3556 u8 reserved_at_20[0x10];
3557 u8 op_mod[0x10];
3558
3559 u8 reserved_at_40[0x40];
3560 };
3561
3562 struct mlx5_ifc_query_l2_table_entry_out_bits {
3563 u8 status[0x8];
3564 u8 reserved_at_8[0x18];
3565
3566 u8 syndrome[0x20];
3567
3568 u8 reserved_at_40[0xa0];
3569
3570 u8 reserved_at_e0[0x13];
3571 u8 vlan_valid[0x1];
3572 u8 vlan[0xc];
3573
3574 struct mlx5_ifc_mac_address_layout_bits mac_address;
3575
3576 u8 reserved_at_140[0xc0];
3577 };
3578
3579 struct mlx5_ifc_query_l2_table_entry_in_bits {
3580 u8 opcode[0x10];
3581 u8 reserved_at_10[0x10];
3582
3583 u8 reserved_at_20[0x10];
3584 u8 op_mod[0x10];
3585
3586 u8 reserved_at_40[0x60];
3587
3588 u8 reserved_at_a0[0x8];
3589 u8 table_index[0x18];
3590
3591 u8 reserved_at_c0[0x140];
3592 };
3593
3594 struct mlx5_ifc_query_issi_out_bits {
3595 u8 status[0x8];
3596 u8 reserved_at_8[0x18];
3597
3598 u8 syndrome[0x20];
3599
3600 u8 reserved_at_40[0x10];
3601 u8 current_issi[0x10];
3602
3603 u8 reserved_at_60[0xa0];
3604
3605 u8 reserved_at_100[76][0x8];
3606 u8 supported_issi_dw0[0x20];
3607 };
3608
3609 struct mlx5_ifc_query_issi_in_bits {
3610 u8 opcode[0x10];
3611 u8 reserved_at_10[0x10];
3612
3613 u8 reserved_at_20[0x10];
3614 u8 op_mod[0x10];
3615
3616 u8 reserved_at_40[0x40];
3617 };
3618
3619 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3620 u8 status[0x8];
3621 u8 reserved_at_8[0x18];
3622
3623 u8 syndrome[0x20];
3624
3625 u8 reserved_at_40[0x40];
3626
3627 struct mlx5_ifc_pkey_bits pkey[0];
3628 };
3629
3630 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3631 u8 opcode[0x10];
3632 u8 reserved_at_10[0x10];
3633
3634 u8 reserved_at_20[0x10];
3635 u8 op_mod[0x10];
3636
3637 u8 other_vport[0x1];
3638 u8 reserved_at_41[0xb];
3639 u8 port_num[0x4];
3640 u8 vport_number[0x10];
3641
3642 u8 reserved_at_60[0x10];
3643 u8 pkey_index[0x10];
3644 };
3645
3646 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3647 u8 status[0x8];
3648 u8 reserved_at_8[0x18];
3649
3650 u8 syndrome[0x20];
3651
3652 u8 reserved_at_40[0x20];
3653
3654 u8 gids_num[0x10];
3655 u8 reserved_at_70[0x10];
3656
3657 struct mlx5_ifc_array128_auto_bits gid[0];
3658 };
3659
3660 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3661 u8 opcode[0x10];
3662 u8 reserved_at_10[0x10];
3663
3664 u8 reserved_at_20[0x10];
3665 u8 op_mod[0x10];
3666
3667 u8 other_vport[0x1];
3668 u8 reserved_at_41[0xb];
3669 u8 port_num[0x4];
3670 u8 vport_number[0x10];
3671
3672 u8 reserved_at_60[0x10];
3673 u8 gid_index[0x10];
3674 };
3675
3676 struct mlx5_ifc_query_hca_vport_context_out_bits {
3677 u8 status[0x8];
3678 u8 reserved_at_8[0x18];
3679
3680 u8 syndrome[0x20];
3681
3682 u8 reserved_at_40[0x40];
3683
3684 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3685 };
3686
3687 struct mlx5_ifc_query_hca_vport_context_in_bits {
3688 u8 opcode[0x10];
3689 u8 reserved_at_10[0x10];
3690
3691 u8 reserved_at_20[0x10];
3692 u8 op_mod[0x10];
3693
3694 u8 other_vport[0x1];
3695 u8 reserved_at_41[0xb];
3696 u8 port_num[0x4];
3697 u8 vport_number[0x10];
3698
3699 u8 reserved_at_60[0x20];
3700 };
3701
3702 struct mlx5_ifc_query_hca_cap_out_bits {
3703 u8 status[0x8];
3704 u8 reserved_at_8[0x18];
3705
3706 u8 syndrome[0x20];
3707
3708 u8 reserved_at_40[0x40];
3709
3710 union mlx5_ifc_hca_cap_union_bits capability;
3711 };
3712
3713 struct mlx5_ifc_query_hca_cap_in_bits {
3714 u8 opcode[0x10];
3715 u8 reserved_at_10[0x10];
3716
3717 u8 reserved_at_20[0x10];
3718 u8 op_mod[0x10];
3719
3720 u8 reserved_at_40[0x40];
3721 };
3722
3723 struct mlx5_ifc_query_flow_table_out_bits {
3724 u8 status[0x8];
3725 u8 reserved_at_8[0x18];
3726
3727 u8 syndrome[0x20];
3728
3729 u8 reserved_at_40[0x80];
3730
3731 u8 reserved_at_c0[0x8];
3732 u8 level[0x8];
3733 u8 reserved_at_d0[0x8];
3734 u8 log_size[0x8];
3735
3736 u8 reserved_at_e0[0x120];
3737 };
3738
3739 struct mlx5_ifc_query_flow_table_in_bits {
3740 u8 opcode[0x10];
3741 u8 reserved_at_10[0x10];
3742
3743 u8 reserved_at_20[0x10];
3744 u8 op_mod[0x10];
3745
3746 u8 reserved_at_40[0x40];
3747
3748 u8 table_type[0x8];
3749 u8 reserved_at_88[0x18];
3750
3751 u8 reserved_at_a0[0x8];
3752 u8 table_id[0x18];
3753
3754 u8 reserved_at_c0[0x140];
3755 };
3756
3757 struct mlx5_ifc_query_fte_out_bits {
3758 u8 status[0x8];
3759 u8 reserved_at_8[0x18];
3760
3761 u8 syndrome[0x20];
3762
3763 u8 reserved_at_40[0x1c0];
3764
3765 struct mlx5_ifc_flow_context_bits flow_context;
3766 };
3767
3768 struct mlx5_ifc_query_fte_in_bits {
3769 u8 opcode[0x10];
3770 u8 reserved_at_10[0x10];
3771
3772 u8 reserved_at_20[0x10];
3773 u8 op_mod[0x10];
3774
3775 u8 reserved_at_40[0x40];
3776
3777 u8 table_type[0x8];
3778 u8 reserved_at_88[0x18];
3779
3780 u8 reserved_at_a0[0x8];
3781 u8 table_id[0x18];
3782
3783 u8 reserved_at_c0[0x40];
3784
3785 u8 flow_index[0x20];
3786
3787 u8 reserved_at_120[0xe0];
3788 };
3789
3790 enum {
3791 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
3792 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
3793 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
3794 };
3795
3796 struct mlx5_ifc_query_flow_group_out_bits {
3797 u8 status[0x8];
3798 u8 reserved_at_8[0x18];
3799
3800 u8 syndrome[0x20];
3801
3802 u8 reserved_at_40[0xa0];
3803
3804 u8 start_flow_index[0x20];
3805
3806 u8 reserved_at_100[0x20];
3807
3808 u8 end_flow_index[0x20];
3809
3810 u8 reserved_at_140[0xa0];
3811
3812 u8 reserved_at_1e0[0x18];
3813 u8 match_criteria_enable[0x8];
3814
3815 struct mlx5_ifc_fte_match_param_bits match_criteria;
3816
3817 u8 reserved_at_1200[0xe00];
3818 };
3819
3820 struct mlx5_ifc_query_flow_group_in_bits {
3821 u8 opcode[0x10];
3822 u8 reserved_at_10[0x10];
3823
3824 u8 reserved_at_20[0x10];
3825 u8 op_mod[0x10];
3826
3827 u8 reserved_at_40[0x40];
3828
3829 u8 table_type[0x8];
3830 u8 reserved_at_88[0x18];
3831
3832 u8 reserved_at_a0[0x8];
3833 u8 table_id[0x18];
3834
3835 u8 group_id[0x20];
3836
3837 u8 reserved_at_e0[0x120];
3838 };
3839
3840 struct mlx5_ifc_query_esw_vport_context_out_bits {
3841 u8 status[0x8];
3842 u8 reserved_at_8[0x18];
3843
3844 u8 syndrome[0x20];
3845
3846 u8 reserved_at_40[0x40];
3847
3848 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3849 };
3850
3851 struct mlx5_ifc_query_esw_vport_context_in_bits {
3852 u8 opcode[0x10];
3853 u8 reserved_at_10[0x10];
3854
3855 u8 reserved_at_20[0x10];
3856 u8 op_mod[0x10];
3857
3858 u8 other_vport[0x1];
3859 u8 reserved_at_41[0xf];
3860 u8 vport_number[0x10];
3861
3862 u8 reserved_at_60[0x20];
3863 };
3864
3865 struct mlx5_ifc_modify_esw_vport_context_out_bits {
3866 u8 status[0x8];
3867 u8 reserved_at_8[0x18];
3868
3869 u8 syndrome[0x20];
3870
3871 u8 reserved_at_40[0x40];
3872 };
3873
3874 struct mlx5_ifc_esw_vport_context_fields_select_bits {
3875 u8 reserved_at_0[0x1c];
3876 u8 vport_cvlan_insert[0x1];
3877 u8 vport_svlan_insert[0x1];
3878 u8 vport_cvlan_strip[0x1];
3879 u8 vport_svlan_strip[0x1];
3880 };
3881
3882 struct mlx5_ifc_modify_esw_vport_context_in_bits {
3883 u8 opcode[0x10];
3884 u8 reserved_at_10[0x10];
3885
3886 u8 reserved_at_20[0x10];
3887 u8 op_mod[0x10];
3888
3889 u8 other_vport[0x1];
3890 u8 reserved_at_41[0xf];
3891 u8 vport_number[0x10];
3892
3893 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
3894
3895 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3896 };
3897
3898 struct mlx5_ifc_query_eq_out_bits {
3899 u8 status[0x8];
3900 u8 reserved_at_8[0x18];
3901
3902 u8 syndrome[0x20];
3903
3904 u8 reserved_at_40[0x40];
3905
3906 struct mlx5_ifc_eqc_bits eq_context_entry;
3907
3908 u8 reserved_at_280[0x40];
3909
3910 u8 event_bitmask[0x40];
3911
3912 u8 reserved_at_300[0x580];
3913
3914 u8 pas[0][0x40];
3915 };
3916
3917 struct mlx5_ifc_query_eq_in_bits {
3918 u8 opcode[0x10];
3919 u8 reserved_at_10[0x10];
3920
3921 u8 reserved_at_20[0x10];
3922 u8 op_mod[0x10];
3923
3924 u8 reserved_at_40[0x18];
3925 u8 eq_number[0x8];
3926
3927 u8 reserved_at_60[0x20];
3928 };
3929
3930 struct mlx5_ifc_query_dct_out_bits {
3931 u8 status[0x8];
3932 u8 reserved_at_8[0x18];
3933
3934 u8 syndrome[0x20];
3935
3936 u8 reserved_at_40[0x40];
3937
3938 struct mlx5_ifc_dctc_bits dct_context_entry;
3939
3940 u8 reserved_at_280[0x180];
3941 };
3942
3943 struct mlx5_ifc_query_dct_in_bits {
3944 u8 opcode[0x10];
3945 u8 reserved_at_10[0x10];
3946
3947 u8 reserved_at_20[0x10];
3948 u8 op_mod[0x10];
3949
3950 u8 reserved_at_40[0x8];
3951 u8 dctn[0x18];
3952
3953 u8 reserved_at_60[0x20];
3954 };
3955
3956 struct mlx5_ifc_query_cq_out_bits {
3957 u8 status[0x8];
3958 u8 reserved_at_8[0x18];
3959
3960 u8 syndrome[0x20];
3961
3962 u8 reserved_at_40[0x40];
3963
3964 struct mlx5_ifc_cqc_bits cq_context;
3965
3966 u8 reserved_at_280[0x600];
3967
3968 u8 pas[0][0x40];
3969 };
3970
3971 struct mlx5_ifc_query_cq_in_bits {
3972 u8 opcode[0x10];
3973 u8 reserved_at_10[0x10];
3974
3975 u8 reserved_at_20[0x10];
3976 u8 op_mod[0x10];
3977
3978 u8 reserved_at_40[0x8];
3979 u8 cqn[0x18];
3980
3981 u8 reserved_at_60[0x20];
3982 };
3983
3984 struct mlx5_ifc_query_cong_status_out_bits {
3985 u8 status[0x8];
3986 u8 reserved_at_8[0x18];
3987
3988 u8 syndrome[0x20];
3989
3990 u8 reserved_at_40[0x20];
3991
3992 u8 enable[0x1];
3993 u8 tag_enable[0x1];
3994 u8 reserved_at_62[0x1e];
3995 };
3996
3997 struct mlx5_ifc_query_cong_status_in_bits {
3998 u8 opcode[0x10];
3999 u8 reserved_at_10[0x10];
4000
4001 u8 reserved_at_20[0x10];
4002 u8 op_mod[0x10];
4003
4004 u8 reserved_at_40[0x18];
4005 u8 priority[0x4];
4006 u8 cong_protocol[0x4];
4007
4008 u8 reserved_at_60[0x20];
4009 };
4010
4011 struct mlx5_ifc_query_cong_statistics_out_bits {
4012 u8 status[0x8];
4013 u8 reserved_at_8[0x18];
4014
4015 u8 syndrome[0x20];
4016
4017 u8 reserved_at_40[0x40];
4018
4019 u8 cur_flows[0x20];
4020
4021 u8 sum_flows[0x20];
4022
4023 u8 cnp_ignored_high[0x20];
4024
4025 u8 cnp_ignored_low[0x20];
4026
4027 u8 cnp_handled_high[0x20];
4028
4029 u8 cnp_handled_low[0x20];
4030
4031 u8 reserved_at_140[0x100];
4032
4033 u8 time_stamp_high[0x20];
4034
4035 u8 time_stamp_low[0x20];
4036
4037 u8 accumulators_period[0x20];
4038
4039 u8 ecn_marked_roce_packets_high[0x20];
4040
4041 u8 ecn_marked_roce_packets_low[0x20];
4042
4043 u8 cnps_sent_high[0x20];
4044
4045 u8 cnps_sent_low[0x20];
4046
4047 u8 reserved_at_320[0x560];
4048 };
4049
4050 struct mlx5_ifc_query_cong_statistics_in_bits {
4051 u8 opcode[0x10];
4052 u8 reserved_at_10[0x10];
4053
4054 u8 reserved_at_20[0x10];
4055 u8 op_mod[0x10];
4056
4057 u8 clear[0x1];
4058 u8 reserved_at_41[0x1f];
4059
4060 u8 reserved_at_60[0x20];
4061 };
4062
4063 struct mlx5_ifc_query_cong_params_out_bits {
4064 u8 status[0x8];
4065 u8 reserved_at_8[0x18];
4066
4067 u8 syndrome[0x20];
4068
4069 u8 reserved_at_40[0x40];
4070
4071 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4072 };
4073
4074 struct mlx5_ifc_query_cong_params_in_bits {
4075 u8 opcode[0x10];
4076 u8 reserved_at_10[0x10];
4077
4078 u8 reserved_at_20[0x10];
4079 u8 op_mod[0x10];
4080
4081 u8 reserved_at_40[0x1c];
4082 u8 cong_protocol[0x4];
4083
4084 u8 reserved_at_60[0x20];
4085 };
4086
4087 struct mlx5_ifc_query_adapter_out_bits {
4088 u8 status[0x8];
4089 u8 reserved_at_8[0x18];
4090
4091 u8 syndrome[0x20];
4092
4093 u8 reserved_at_40[0x40];
4094
4095 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4096 };
4097
4098 struct mlx5_ifc_query_adapter_in_bits {
4099 u8 opcode[0x10];
4100 u8 reserved_at_10[0x10];
4101
4102 u8 reserved_at_20[0x10];
4103 u8 op_mod[0x10];
4104
4105 u8 reserved_at_40[0x40];
4106 };
4107
4108 struct mlx5_ifc_qp_2rst_out_bits {
4109 u8 status[0x8];
4110 u8 reserved_at_8[0x18];
4111
4112 u8 syndrome[0x20];
4113
4114 u8 reserved_at_40[0x40];
4115 };
4116
4117 struct mlx5_ifc_qp_2rst_in_bits {
4118 u8 opcode[0x10];
4119 u8 reserved_at_10[0x10];
4120
4121 u8 reserved_at_20[0x10];
4122 u8 op_mod[0x10];
4123
4124 u8 reserved_at_40[0x8];
4125 u8 qpn[0x18];
4126
4127 u8 reserved_at_60[0x20];
4128 };
4129
4130 struct mlx5_ifc_qp_2err_out_bits {
4131 u8 status[0x8];
4132 u8 reserved_at_8[0x18];
4133
4134 u8 syndrome[0x20];
4135
4136 u8 reserved_at_40[0x40];
4137 };
4138
4139 struct mlx5_ifc_qp_2err_in_bits {
4140 u8 opcode[0x10];
4141 u8 reserved_at_10[0x10];
4142
4143 u8 reserved_at_20[0x10];
4144 u8 op_mod[0x10];
4145
4146 u8 reserved_at_40[0x8];
4147 u8 qpn[0x18];
4148
4149 u8 reserved_at_60[0x20];
4150 };
4151
4152 struct mlx5_ifc_page_fault_resume_out_bits {
4153 u8 status[0x8];
4154 u8 reserved_at_8[0x18];
4155
4156 u8 syndrome[0x20];
4157
4158 u8 reserved_at_40[0x40];
4159 };
4160
4161 struct mlx5_ifc_page_fault_resume_in_bits {
4162 u8 opcode[0x10];
4163 u8 reserved_at_10[0x10];
4164
4165 u8 reserved_at_20[0x10];
4166 u8 op_mod[0x10];
4167
4168 u8 error[0x1];
4169 u8 reserved_at_41[0x4];
4170 u8 rdma[0x1];
4171 u8 read_write[0x1];
4172 u8 req_res[0x1];
4173 u8 qpn[0x18];
4174
4175 u8 reserved_at_60[0x20];
4176 };
4177
4178 struct mlx5_ifc_nop_out_bits {
4179 u8 status[0x8];
4180 u8 reserved_at_8[0x18];
4181
4182 u8 syndrome[0x20];
4183
4184 u8 reserved_at_40[0x40];
4185 };
4186
4187 struct mlx5_ifc_nop_in_bits {
4188 u8 opcode[0x10];
4189 u8 reserved_at_10[0x10];
4190
4191 u8 reserved_at_20[0x10];
4192 u8 op_mod[0x10];
4193
4194 u8 reserved_at_40[0x40];
4195 };
4196
4197 struct mlx5_ifc_modify_vport_state_out_bits {
4198 u8 status[0x8];
4199 u8 reserved_at_8[0x18];
4200
4201 u8 syndrome[0x20];
4202
4203 u8 reserved_at_40[0x40];
4204 };
4205
4206 struct mlx5_ifc_modify_vport_state_in_bits {
4207 u8 opcode[0x10];
4208 u8 reserved_at_10[0x10];
4209
4210 u8 reserved_at_20[0x10];
4211 u8 op_mod[0x10];
4212
4213 u8 other_vport[0x1];
4214 u8 reserved_at_41[0xf];
4215 u8 vport_number[0x10];
4216
4217 u8 reserved_at_60[0x18];
4218 u8 admin_state[0x4];
4219 u8 reserved_at_7c[0x4];
4220 };
4221
4222 struct mlx5_ifc_modify_tis_out_bits {
4223 u8 status[0x8];
4224 u8 reserved_at_8[0x18];
4225
4226 u8 syndrome[0x20];
4227
4228 u8 reserved_at_40[0x40];
4229 };
4230
4231 struct mlx5_ifc_modify_tis_bitmask_bits {
4232 u8 reserved_at_0[0x20];
4233
4234 u8 reserved_at_20[0x1f];
4235 u8 prio[0x1];
4236 };
4237
4238 struct mlx5_ifc_modify_tis_in_bits {
4239 u8 opcode[0x10];
4240 u8 reserved_at_10[0x10];
4241
4242 u8 reserved_at_20[0x10];
4243 u8 op_mod[0x10];
4244
4245 u8 reserved_at_40[0x8];
4246 u8 tisn[0x18];
4247
4248 u8 reserved_at_60[0x20];
4249
4250 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4251
4252 u8 reserved_at_c0[0x40];
4253
4254 struct mlx5_ifc_tisc_bits ctx;
4255 };
4256
4257 struct mlx5_ifc_modify_tir_bitmask_bits {
4258 u8 reserved_at_0[0x20];
4259
4260 u8 reserved_at_20[0x1b];
4261 u8 self_lb_en[0x1];
4262 u8 reserved_at_3c[0x1];
4263 u8 hash[0x1];
4264 u8 reserved_at_3e[0x1];
4265 u8 lro[0x1];
4266 };
4267
4268 struct mlx5_ifc_modify_tir_out_bits {
4269 u8 status[0x8];
4270 u8 reserved_at_8[0x18];
4271
4272 u8 syndrome[0x20];
4273
4274 u8 reserved_at_40[0x40];
4275 };
4276
4277 struct mlx5_ifc_modify_tir_in_bits {
4278 u8 opcode[0x10];
4279 u8 reserved_at_10[0x10];
4280
4281 u8 reserved_at_20[0x10];
4282 u8 op_mod[0x10];
4283
4284 u8 reserved_at_40[0x8];
4285 u8 tirn[0x18];
4286
4287 u8 reserved_at_60[0x20];
4288
4289 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4290
4291 u8 reserved_at_c0[0x40];
4292
4293 struct mlx5_ifc_tirc_bits ctx;
4294 };
4295
4296 struct mlx5_ifc_modify_sq_out_bits {
4297 u8 status[0x8];
4298 u8 reserved_at_8[0x18];
4299
4300 u8 syndrome[0x20];
4301
4302 u8 reserved_at_40[0x40];
4303 };
4304
4305 struct mlx5_ifc_modify_sq_in_bits {
4306 u8 opcode[0x10];
4307 u8 reserved_at_10[0x10];
4308
4309 u8 reserved_at_20[0x10];
4310 u8 op_mod[0x10];
4311
4312 u8 sq_state[0x4];
4313 u8 reserved_at_44[0x4];
4314 u8 sqn[0x18];
4315
4316 u8 reserved_at_60[0x20];
4317
4318 u8 modify_bitmask[0x40];
4319
4320 u8 reserved_at_c0[0x40];
4321
4322 struct mlx5_ifc_sqc_bits ctx;
4323 };
4324
4325 struct mlx5_ifc_modify_rqt_out_bits {
4326 u8 status[0x8];
4327 u8 reserved_at_8[0x18];
4328
4329 u8 syndrome[0x20];
4330
4331 u8 reserved_at_40[0x40];
4332 };
4333
4334 struct mlx5_ifc_rqt_bitmask_bits {
4335 u8 reserved_at_0[0x20];
4336
4337 u8 reserved_at_20[0x1f];
4338 u8 rqn_list[0x1];
4339 };
4340
4341 struct mlx5_ifc_modify_rqt_in_bits {
4342 u8 opcode[0x10];
4343 u8 reserved_at_10[0x10];
4344
4345 u8 reserved_at_20[0x10];
4346 u8 op_mod[0x10];
4347
4348 u8 reserved_at_40[0x8];
4349 u8 rqtn[0x18];
4350
4351 u8 reserved_at_60[0x20];
4352
4353 struct mlx5_ifc_rqt_bitmask_bits bitmask;
4354
4355 u8 reserved_at_c0[0x40];
4356
4357 struct mlx5_ifc_rqtc_bits ctx;
4358 };
4359
4360 struct mlx5_ifc_modify_rq_out_bits {
4361 u8 status[0x8];
4362 u8 reserved_at_8[0x18];
4363
4364 u8 syndrome[0x20];
4365
4366 u8 reserved_at_40[0x40];
4367 };
4368
4369 struct mlx5_ifc_modify_rq_in_bits {
4370 u8 opcode[0x10];
4371 u8 reserved_at_10[0x10];
4372
4373 u8 reserved_at_20[0x10];
4374 u8 op_mod[0x10];
4375
4376 u8 rq_state[0x4];
4377 u8 reserved_at_44[0x4];
4378 u8 rqn[0x18];
4379
4380 u8 reserved_at_60[0x20];
4381
4382 u8 modify_bitmask[0x40];
4383
4384 u8 reserved_at_c0[0x40];
4385
4386 struct mlx5_ifc_rqc_bits ctx;
4387 };
4388
4389 struct mlx5_ifc_modify_rmp_out_bits {
4390 u8 status[0x8];
4391 u8 reserved_at_8[0x18];
4392
4393 u8 syndrome[0x20];
4394
4395 u8 reserved_at_40[0x40];
4396 };
4397
4398 struct mlx5_ifc_rmp_bitmask_bits {
4399 u8 reserved_at_0[0x20];
4400
4401 u8 reserved_at_20[0x1f];
4402 u8 lwm[0x1];
4403 };
4404
4405 struct mlx5_ifc_modify_rmp_in_bits {
4406 u8 opcode[0x10];
4407 u8 reserved_at_10[0x10];
4408
4409 u8 reserved_at_20[0x10];
4410 u8 op_mod[0x10];
4411
4412 u8 rmp_state[0x4];
4413 u8 reserved_at_44[0x4];
4414 u8 rmpn[0x18];
4415
4416 u8 reserved_at_60[0x20];
4417
4418 struct mlx5_ifc_rmp_bitmask_bits bitmask;
4419
4420 u8 reserved_at_c0[0x40];
4421
4422 struct mlx5_ifc_rmpc_bits ctx;
4423 };
4424
4425 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4426 u8 status[0x8];
4427 u8 reserved_at_8[0x18];
4428
4429 u8 syndrome[0x20];
4430
4431 u8 reserved_at_40[0x40];
4432 };
4433
4434 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4435 u8 reserved_at_0[0x19];
4436 u8 mtu[0x1];
4437 u8 change_event[0x1];
4438 u8 promisc[0x1];
4439 u8 permanent_address[0x1];
4440 u8 addresses_list[0x1];
4441 u8 roce_en[0x1];
4442 u8 reserved_at_1f[0x1];
4443 };
4444
4445 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4446 u8 opcode[0x10];
4447 u8 reserved_at_10[0x10];
4448
4449 u8 reserved_at_20[0x10];
4450 u8 op_mod[0x10];
4451
4452 u8 other_vport[0x1];
4453 u8 reserved_at_41[0xf];
4454 u8 vport_number[0x10];
4455
4456 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4457
4458 u8 reserved_at_80[0x780];
4459
4460 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4461 };
4462
4463 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4464 u8 status[0x8];
4465 u8 reserved_at_8[0x18];
4466
4467 u8 syndrome[0x20];
4468
4469 u8 reserved_at_40[0x40];
4470 };
4471
4472 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4473 u8 opcode[0x10];
4474 u8 reserved_at_10[0x10];
4475
4476 u8 reserved_at_20[0x10];
4477 u8 op_mod[0x10];
4478
4479 u8 other_vport[0x1];
4480 u8 reserved_at_41[0xb];
4481 u8 port_num[0x4];
4482 u8 vport_number[0x10];
4483
4484 u8 reserved_at_60[0x20];
4485
4486 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4487 };
4488
4489 struct mlx5_ifc_modify_cq_out_bits {
4490 u8 status[0x8];
4491 u8 reserved_at_8[0x18];
4492
4493 u8 syndrome[0x20];
4494
4495 u8 reserved_at_40[0x40];
4496 };
4497
4498 enum {
4499 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4500 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4501 };
4502
4503 struct mlx5_ifc_modify_cq_in_bits {
4504 u8 opcode[0x10];
4505 u8 reserved_at_10[0x10];
4506
4507 u8 reserved_at_20[0x10];
4508 u8 op_mod[0x10];
4509
4510 u8 reserved_at_40[0x8];
4511 u8 cqn[0x18];
4512
4513 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4514
4515 struct mlx5_ifc_cqc_bits cq_context;
4516
4517 u8 reserved_at_280[0x600];
4518
4519 u8 pas[0][0x40];
4520 };
4521
4522 struct mlx5_ifc_modify_cong_status_out_bits {
4523 u8 status[0x8];
4524 u8 reserved_at_8[0x18];
4525
4526 u8 syndrome[0x20];
4527
4528 u8 reserved_at_40[0x40];
4529 };
4530
4531 struct mlx5_ifc_modify_cong_status_in_bits {
4532 u8 opcode[0x10];
4533 u8 reserved_at_10[0x10];
4534
4535 u8 reserved_at_20[0x10];
4536 u8 op_mod[0x10];
4537
4538 u8 reserved_at_40[0x18];
4539 u8 priority[0x4];
4540 u8 cong_protocol[0x4];
4541
4542 u8 enable[0x1];
4543 u8 tag_enable[0x1];
4544 u8 reserved_at_62[0x1e];
4545 };
4546
4547 struct mlx5_ifc_modify_cong_params_out_bits {
4548 u8 status[0x8];
4549 u8 reserved_at_8[0x18];
4550
4551 u8 syndrome[0x20];
4552
4553 u8 reserved_at_40[0x40];
4554 };
4555
4556 struct mlx5_ifc_modify_cong_params_in_bits {
4557 u8 opcode[0x10];
4558 u8 reserved_at_10[0x10];
4559
4560 u8 reserved_at_20[0x10];
4561 u8 op_mod[0x10];
4562
4563 u8 reserved_at_40[0x1c];
4564 u8 cong_protocol[0x4];
4565
4566 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4567
4568 u8 reserved_at_80[0x80];
4569
4570 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4571 };
4572
4573 struct mlx5_ifc_manage_pages_out_bits {
4574 u8 status[0x8];
4575 u8 reserved_at_8[0x18];
4576
4577 u8 syndrome[0x20];
4578
4579 u8 output_num_entries[0x20];
4580
4581 u8 reserved_at_60[0x20];
4582
4583 u8 pas[0][0x40];
4584 };
4585
4586 enum {
4587 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4588 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
4589 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
4590 };
4591
4592 struct mlx5_ifc_manage_pages_in_bits {
4593 u8 opcode[0x10];
4594 u8 reserved_at_10[0x10];
4595
4596 u8 reserved_at_20[0x10];
4597 u8 op_mod[0x10];
4598
4599 u8 reserved_at_40[0x10];
4600 u8 function_id[0x10];
4601
4602 u8 input_num_entries[0x20];
4603
4604 u8 pas[0][0x40];
4605 };
4606
4607 struct mlx5_ifc_mad_ifc_out_bits {
4608 u8 status[0x8];
4609 u8 reserved_at_8[0x18];
4610
4611 u8 syndrome[0x20];
4612
4613 u8 reserved_at_40[0x40];
4614
4615 u8 response_mad_packet[256][0x8];
4616 };
4617
4618 struct mlx5_ifc_mad_ifc_in_bits {
4619 u8 opcode[0x10];
4620 u8 reserved_at_10[0x10];
4621
4622 u8 reserved_at_20[0x10];
4623 u8 op_mod[0x10];
4624
4625 u8 remote_lid[0x10];
4626 u8 reserved_at_50[0x8];
4627 u8 port[0x8];
4628
4629 u8 reserved_at_60[0x20];
4630
4631 u8 mad[256][0x8];
4632 };
4633
4634 struct mlx5_ifc_init_hca_out_bits {
4635 u8 status[0x8];
4636 u8 reserved_at_8[0x18];
4637
4638 u8 syndrome[0x20];
4639
4640 u8 reserved_at_40[0x40];
4641 };
4642
4643 struct mlx5_ifc_init_hca_in_bits {
4644 u8 opcode[0x10];
4645 u8 reserved_at_10[0x10];
4646
4647 u8 reserved_at_20[0x10];
4648 u8 op_mod[0x10];
4649
4650 u8 reserved_at_40[0x40];
4651 };
4652
4653 struct mlx5_ifc_init2rtr_qp_out_bits {
4654 u8 status[0x8];
4655 u8 reserved_at_8[0x18];
4656
4657 u8 syndrome[0x20];
4658
4659 u8 reserved_at_40[0x40];
4660 };
4661
4662 struct mlx5_ifc_init2rtr_qp_in_bits {
4663 u8 opcode[0x10];
4664 u8 reserved_at_10[0x10];
4665
4666 u8 reserved_at_20[0x10];
4667 u8 op_mod[0x10];
4668
4669 u8 reserved_at_40[0x8];
4670 u8 qpn[0x18];
4671
4672 u8 reserved_at_60[0x20];
4673
4674 u8 opt_param_mask[0x20];
4675
4676 u8 reserved_at_a0[0x20];
4677
4678 struct mlx5_ifc_qpc_bits qpc;
4679
4680 u8 reserved_at_800[0x80];
4681 };
4682
4683 struct mlx5_ifc_init2init_qp_out_bits {
4684 u8 status[0x8];
4685 u8 reserved_at_8[0x18];
4686
4687 u8 syndrome[0x20];
4688
4689 u8 reserved_at_40[0x40];
4690 };
4691
4692 struct mlx5_ifc_init2init_qp_in_bits {
4693 u8 opcode[0x10];
4694 u8 reserved_at_10[0x10];
4695
4696 u8 reserved_at_20[0x10];
4697 u8 op_mod[0x10];
4698
4699 u8 reserved_at_40[0x8];
4700 u8 qpn[0x18];
4701
4702 u8 reserved_at_60[0x20];
4703
4704 u8 opt_param_mask[0x20];
4705
4706 u8 reserved_at_a0[0x20];
4707
4708 struct mlx5_ifc_qpc_bits qpc;
4709
4710 u8 reserved_at_800[0x80];
4711 };
4712
4713 struct mlx5_ifc_get_dropped_packet_log_out_bits {
4714 u8 status[0x8];
4715 u8 reserved_at_8[0x18];
4716
4717 u8 syndrome[0x20];
4718
4719 u8 reserved_at_40[0x40];
4720
4721 u8 packet_headers_log[128][0x8];
4722
4723 u8 packet_syndrome[64][0x8];
4724 };
4725
4726 struct mlx5_ifc_get_dropped_packet_log_in_bits {
4727 u8 opcode[0x10];
4728 u8 reserved_at_10[0x10];
4729
4730 u8 reserved_at_20[0x10];
4731 u8 op_mod[0x10];
4732
4733 u8 reserved_at_40[0x40];
4734 };
4735
4736 struct mlx5_ifc_gen_eqe_in_bits {
4737 u8 opcode[0x10];
4738 u8 reserved_at_10[0x10];
4739
4740 u8 reserved_at_20[0x10];
4741 u8 op_mod[0x10];
4742
4743 u8 reserved_at_40[0x18];
4744 u8 eq_number[0x8];
4745
4746 u8 reserved_at_60[0x20];
4747
4748 u8 eqe[64][0x8];
4749 };
4750
4751 struct mlx5_ifc_gen_eq_out_bits {
4752 u8 status[0x8];
4753 u8 reserved_at_8[0x18];
4754
4755 u8 syndrome[0x20];
4756
4757 u8 reserved_at_40[0x40];
4758 };
4759
4760 struct mlx5_ifc_enable_hca_out_bits {
4761 u8 status[0x8];
4762 u8 reserved_at_8[0x18];
4763
4764 u8 syndrome[0x20];
4765
4766 u8 reserved_at_40[0x20];
4767 };
4768
4769 struct mlx5_ifc_enable_hca_in_bits {
4770 u8 opcode[0x10];
4771 u8 reserved_at_10[0x10];
4772
4773 u8 reserved_at_20[0x10];
4774 u8 op_mod[0x10];
4775
4776 u8 reserved_at_40[0x10];
4777 u8 function_id[0x10];
4778
4779 u8 reserved_at_60[0x20];
4780 };
4781
4782 struct mlx5_ifc_drain_dct_out_bits {
4783 u8 status[0x8];
4784 u8 reserved_at_8[0x18];
4785
4786 u8 syndrome[0x20];
4787
4788 u8 reserved_at_40[0x40];
4789 };
4790
4791 struct mlx5_ifc_drain_dct_in_bits {
4792 u8 opcode[0x10];
4793 u8 reserved_at_10[0x10];
4794
4795 u8 reserved_at_20[0x10];
4796 u8 op_mod[0x10];
4797
4798 u8 reserved_at_40[0x8];
4799 u8 dctn[0x18];
4800
4801 u8 reserved_at_60[0x20];
4802 };
4803
4804 struct mlx5_ifc_disable_hca_out_bits {
4805 u8 status[0x8];
4806 u8 reserved_at_8[0x18];
4807
4808 u8 syndrome[0x20];
4809
4810 u8 reserved_at_40[0x20];
4811 };
4812
4813 struct mlx5_ifc_disable_hca_in_bits {
4814 u8 opcode[0x10];
4815 u8 reserved_at_10[0x10];
4816
4817 u8 reserved_at_20[0x10];
4818 u8 op_mod[0x10];
4819
4820 u8 reserved_at_40[0x10];
4821 u8 function_id[0x10];
4822
4823 u8 reserved_at_60[0x20];
4824 };
4825
4826 struct mlx5_ifc_detach_from_mcg_out_bits {
4827 u8 status[0x8];
4828 u8 reserved_at_8[0x18];
4829
4830 u8 syndrome[0x20];
4831
4832 u8 reserved_at_40[0x40];
4833 };
4834
4835 struct mlx5_ifc_detach_from_mcg_in_bits {
4836 u8 opcode[0x10];
4837 u8 reserved_at_10[0x10];
4838
4839 u8 reserved_at_20[0x10];
4840 u8 op_mod[0x10];
4841
4842 u8 reserved_at_40[0x8];
4843 u8 qpn[0x18];
4844
4845 u8 reserved_at_60[0x20];
4846
4847 u8 multicast_gid[16][0x8];
4848 };
4849
4850 struct mlx5_ifc_destroy_xrc_srq_out_bits {
4851 u8 status[0x8];
4852 u8 reserved_at_8[0x18];
4853
4854 u8 syndrome[0x20];
4855
4856 u8 reserved_at_40[0x40];
4857 };
4858
4859 struct mlx5_ifc_destroy_xrc_srq_in_bits {
4860 u8 opcode[0x10];
4861 u8 reserved_at_10[0x10];
4862
4863 u8 reserved_at_20[0x10];
4864 u8 op_mod[0x10];
4865
4866 u8 reserved_at_40[0x8];
4867 u8 xrc_srqn[0x18];
4868
4869 u8 reserved_at_60[0x20];
4870 };
4871
4872 struct mlx5_ifc_destroy_tis_out_bits {
4873 u8 status[0x8];
4874 u8 reserved_at_8[0x18];
4875
4876 u8 syndrome[0x20];
4877
4878 u8 reserved_at_40[0x40];
4879 };
4880
4881 struct mlx5_ifc_destroy_tis_in_bits {
4882 u8 opcode[0x10];
4883 u8 reserved_at_10[0x10];
4884
4885 u8 reserved_at_20[0x10];
4886 u8 op_mod[0x10];
4887
4888 u8 reserved_at_40[0x8];
4889 u8 tisn[0x18];
4890
4891 u8 reserved_at_60[0x20];
4892 };
4893
4894 struct mlx5_ifc_destroy_tir_out_bits {
4895 u8 status[0x8];
4896 u8 reserved_at_8[0x18];
4897
4898 u8 syndrome[0x20];
4899
4900 u8 reserved_at_40[0x40];
4901 };
4902
4903 struct mlx5_ifc_destroy_tir_in_bits {
4904 u8 opcode[0x10];
4905 u8 reserved_at_10[0x10];
4906
4907 u8 reserved_at_20[0x10];
4908 u8 op_mod[0x10];
4909
4910 u8 reserved_at_40[0x8];
4911 u8 tirn[0x18];
4912
4913 u8 reserved_at_60[0x20];
4914 };
4915
4916 struct mlx5_ifc_destroy_srq_out_bits {
4917 u8 status[0x8];
4918 u8 reserved_at_8[0x18];
4919
4920 u8 syndrome[0x20];
4921
4922 u8 reserved_at_40[0x40];
4923 };
4924
4925 struct mlx5_ifc_destroy_srq_in_bits {
4926 u8 opcode[0x10];
4927 u8 reserved_at_10[0x10];
4928
4929 u8 reserved_at_20[0x10];
4930 u8 op_mod[0x10];
4931
4932 u8 reserved_at_40[0x8];
4933 u8 srqn[0x18];
4934
4935 u8 reserved_at_60[0x20];
4936 };
4937
4938 struct mlx5_ifc_destroy_sq_out_bits {
4939 u8 status[0x8];
4940 u8 reserved_at_8[0x18];
4941
4942 u8 syndrome[0x20];
4943
4944 u8 reserved_at_40[0x40];
4945 };
4946
4947 struct mlx5_ifc_destroy_sq_in_bits {
4948 u8 opcode[0x10];
4949 u8 reserved_at_10[0x10];
4950
4951 u8 reserved_at_20[0x10];
4952 u8 op_mod[0x10];
4953
4954 u8 reserved_at_40[0x8];
4955 u8 sqn[0x18];
4956
4957 u8 reserved_at_60[0x20];
4958 };
4959
4960 struct mlx5_ifc_destroy_rqt_out_bits {
4961 u8 status[0x8];
4962 u8 reserved_at_8[0x18];
4963
4964 u8 syndrome[0x20];
4965
4966 u8 reserved_at_40[0x40];
4967 };
4968
4969 struct mlx5_ifc_destroy_rqt_in_bits {
4970 u8 opcode[0x10];
4971 u8 reserved_at_10[0x10];
4972
4973 u8 reserved_at_20[0x10];
4974 u8 op_mod[0x10];
4975
4976 u8 reserved_at_40[0x8];
4977 u8 rqtn[0x18];
4978
4979 u8 reserved_at_60[0x20];
4980 };
4981
4982 struct mlx5_ifc_destroy_rq_out_bits {
4983 u8 status[0x8];
4984 u8 reserved_at_8[0x18];
4985
4986 u8 syndrome[0x20];
4987
4988 u8 reserved_at_40[0x40];
4989 };
4990
4991 struct mlx5_ifc_destroy_rq_in_bits {
4992 u8 opcode[0x10];
4993 u8 reserved_at_10[0x10];
4994
4995 u8 reserved_at_20[0x10];
4996 u8 op_mod[0x10];
4997
4998 u8 reserved_at_40[0x8];
4999 u8 rqn[0x18];
5000
5001 u8 reserved_at_60[0x20];
5002 };
5003
5004 struct mlx5_ifc_destroy_rmp_out_bits {
5005 u8 status[0x8];
5006 u8 reserved_at_8[0x18];
5007
5008 u8 syndrome[0x20];
5009
5010 u8 reserved_at_40[0x40];
5011 };
5012
5013 struct mlx5_ifc_destroy_rmp_in_bits {
5014 u8 opcode[0x10];
5015 u8 reserved_at_10[0x10];
5016
5017 u8 reserved_at_20[0x10];
5018 u8 op_mod[0x10];
5019
5020 u8 reserved_at_40[0x8];
5021 u8 rmpn[0x18];
5022
5023 u8 reserved_at_60[0x20];
5024 };
5025
5026 struct mlx5_ifc_destroy_qp_out_bits {
5027 u8 status[0x8];
5028 u8 reserved_at_8[0x18];
5029
5030 u8 syndrome[0x20];
5031
5032 u8 reserved_at_40[0x40];
5033 };
5034
5035 struct mlx5_ifc_destroy_qp_in_bits {
5036 u8 opcode[0x10];
5037 u8 reserved_at_10[0x10];
5038
5039 u8 reserved_at_20[0x10];
5040 u8 op_mod[0x10];
5041
5042 u8 reserved_at_40[0x8];
5043 u8 qpn[0x18];
5044
5045 u8 reserved_at_60[0x20];
5046 };
5047
5048 struct mlx5_ifc_destroy_psv_out_bits {
5049 u8 status[0x8];
5050 u8 reserved_at_8[0x18];
5051
5052 u8 syndrome[0x20];
5053
5054 u8 reserved_at_40[0x40];
5055 };
5056
5057 struct mlx5_ifc_destroy_psv_in_bits {
5058 u8 opcode[0x10];
5059 u8 reserved_at_10[0x10];
5060
5061 u8 reserved_at_20[0x10];
5062 u8 op_mod[0x10];
5063
5064 u8 reserved_at_40[0x8];
5065 u8 psvn[0x18];
5066
5067 u8 reserved_at_60[0x20];
5068 };
5069
5070 struct mlx5_ifc_destroy_mkey_out_bits {
5071 u8 status[0x8];
5072 u8 reserved_at_8[0x18];
5073
5074 u8 syndrome[0x20];
5075
5076 u8 reserved_at_40[0x40];
5077 };
5078
5079 struct mlx5_ifc_destroy_mkey_in_bits {
5080 u8 opcode[0x10];
5081 u8 reserved_at_10[0x10];
5082
5083 u8 reserved_at_20[0x10];
5084 u8 op_mod[0x10];
5085
5086 u8 reserved_at_40[0x8];
5087 u8 mkey_index[0x18];
5088
5089 u8 reserved_at_60[0x20];
5090 };
5091
5092 struct mlx5_ifc_destroy_flow_table_out_bits {
5093 u8 status[0x8];
5094 u8 reserved_at_8[0x18];
5095
5096 u8 syndrome[0x20];
5097
5098 u8 reserved_at_40[0x40];
5099 };
5100
5101 struct mlx5_ifc_destroy_flow_table_in_bits {
5102 u8 opcode[0x10];
5103 u8 reserved_at_10[0x10];
5104
5105 u8 reserved_at_20[0x10];
5106 u8 op_mod[0x10];
5107
5108 u8 reserved_at_40[0x40];
5109
5110 u8 table_type[0x8];
5111 u8 reserved_at_88[0x18];
5112
5113 u8 reserved_at_a0[0x8];
5114 u8 table_id[0x18];
5115
5116 u8 reserved_at_c0[0x140];
5117 };
5118
5119 struct mlx5_ifc_destroy_flow_group_out_bits {
5120 u8 status[0x8];
5121 u8 reserved_at_8[0x18];
5122
5123 u8 syndrome[0x20];
5124
5125 u8 reserved_at_40[0x40];
5126 };
5127
5128 struct mlx5_ifc_destroy_flow_group_in_bits {
5129 u8 opcode[0x10];
5130 u8 reserved_at_10[0x10];
5131
5132 u8 reserved_at_20[0x10];
5133 u8 op_mod[0x10];
5134
5135 u8 reserved_at_40[0x40];
5136
5137 u8 table_type[0x8];
5138 u8 reserved_at_88[0x18];
5139
5140 u8 reserved_at_a0[0x8];
5141 u8 table_id[0x18];
5142
5143 u8 group_id[0x20];
5144
5145 u8 reserved_at_e0[0x120];
5146 };
5147
5148 struct mlx5_ifc_destroy_eq_out_bits {
5149 u8 status[0x8];
5150 u8 reserved_at_8[0x18];
5151
5152 u8 syndrome[0x20];
5153
5154 u8 reserved_at_40[0x40];
5155 };
5156
5157 struct mlx5_ifc_destroy_eq_in_bits {
5158 u8 opcode[0x10];
5159 u8 reserved_at_10[0x10];
5160
5161 u8 reserved_at_20[0x10];
5162 u8 op_mod[0x10];
5163
5164 u8 reserved_at_40[0x18];
5165 u8 eq_number[0x8];
5166
5167 u8 reserved_at_60[0x20];
5168 };
5169
5170 struct mlx5_ifc_destroy_dct_out_bits {
5171 u8 status[0x8];
5172 u8 reserved_at_8[0x18];
5173
5174 u8 syndrome[0x20];
5175
5176 u8 reserved_at_40[0x40];
5177 };
5178
5179 struct mlx5_ifc_destroy_dct_in_bits {
5180 u8 opcode[0x10];
5181 u8 reserved_at_10[0x10];
5182
5183 u8 reserved_at_20[0x10];
5184 u8 op_mod[0x10];
5185
5186 u8 reserved_at_40[0x8];
5187 u8 dctn[0x18];
5188
5189 u8 reserved_at_60[0x20];
5190 };
5191
5192 struct mlx5_ifc_destroy_cq_out_bits {
5193 u8 status[0x8];
5194 u8 reserved_at_8[0x18];
5195
5196 u8 syndrome[0x20];
5197
5198 u8 reserved_at_40[0x40];
5199 };
5200
5201 struct mlx5_ifc_destroy_cq_in_bits {
5202 u8 opcode[0x10];
5203 u8 reserved_at_10[0x10];
5204
5205 u8 reserved_at_20[0x10];
5206 u8 op_mod[0x10];
5207
5208 u8 reserved_at_40[0x8];
5209 u8 cqn[0x18];
5210
5211 u8 reserved_at_60[0x20];
5212 };
5213
5214 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5215 u8 status[0x8];
5216 u8 reserved_at_8[0x18];
5217
5218 u8 syndrome[0x20];
5219
5220 u8 reserved_at_40[0x40];
5221 };
5222
5223 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5224 u8 opcode[0x10];
5225 u8 reserved_at_10[0x10];
5226
5227 u8 reserved_at_20[0x10];
5228 u8 op_mod[0x10];
5229
5230 u8 reserved_at_40[0x20];
5231
5232 u8 reserved_at_60[0x10];
5233 u8 vxlan_udp_port[0x10];
5234 };
5235
5236 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5237 u8 status[0x8];
5238 u8 reserved_at_8[0x18];
5239
5240 u8 syndrome[0x20];
5241
5242 u8 reserved_at_40[0x40];
5243 };
5244
5245 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5246 u8 opcode[0x10];
5247 u8 reserved_at_10[0x10];
5248
5249 u8 reserved_at_20[0x10];
5250 u8 op_mod[0x10];
5251
5252 u8 reserved_at_40[0x60];
5253
5254 u8 reserved_at_a0[0x8];
5255 u8 table_index[0x18];
5256
5257 u8 reserved_at_c0[0x140];
5258 };
5259
5260 struct mlx5_ifc_delete_fte_out_bits {
5261 u8 status[0x8];
5262 u8 reserved_at_8[0x18];
5263
5264 u8 syndrome[0x20];
5265
5266 u8 reserved_at_40[0x40];
5267 };
5268
5269 struct mlx5_ifc_delete_fte_in_bits {
5270 u8 opcode[0x10];
5271 u8 reserved_at_10[0x10];
5272
5273 u8 reserved_at_20[0x10];
5274 u8 op_mod[0x10];
5275
5276 u8 reserved_at_40[0x40];
5277
5278 u8 table_type[0x8];
5279 u8 reserved_at_88[0x18];
5280
5281 u8 reserved_at_a0[0x8];
5282 u8 table_id[0x18];
5283
5284 u8 reserved_at_c0[0x40];
5285
5286 u8 flow_index[0x20];
5287
5288 u8 reserved_at_120[0xe0];
5289 };
5290
5291 struct mlx5_ifc_dealloc_xrcd_out_bits {
5292 u8 status[0x8];
5293 u8 reserved_at_8[0x18];
5294
5295 u8 syndrome[0x20];
5296
5297 u8 reserved_at_40[0x40];
5298 };
5299
5300 struct mlx5_ifc_dealloc_xrcd_in_bits {
5301 u8 opcode[0x10];
5302 u8 reserved_at_10[0x10];
5303
5304 u8 reserved_at_20[0x10];
5305 u8 op_mod[0x10];
5306
5307 u8 reserved_at_40[0x8];
5308 u8 xrcd[0x18];
5309
5310 u8 reserved_at_60[0x20];
5311 };
5312
5313 struct mlx5_ifc_dealloc_uar_out_bits {
5314 u8 status[0x8];
5315 u8 reserved_at_8[0x18];
5316
5317 u8 syndrome[0x20];
5318
5319 u8 reserved_at_40[0x40];
5320 };
5321
5322 struct mlx5_ifc_dealloc_uar_in_bits {
5323 u8 opcode[0x10];
5324 u8 reserved_at_10[0x10];
5325
5326 u8 reserved_at_20[0x10];
5327 u8 op_mod[0x10];
5328
5329 u8 reserved_at_40[0x8];
5330 u8 uar[0x18];
5331
5332 u8 reserved_at_60[0x20];
5333 };
5334
5335 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5336 u8 status[0x8];
5337 u8 reserved_at_8[0x18];
5338
5339 u8 syndrome[0x20];
5340
5341 u8 reserved_at_40[0x40];
5342 };
5343
5344 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5345 u8 opcode[0x10];
5346 u8 reserved_at_10[0x10];
5347
5348 u8 reserved_at_20[0x10];
5349 u8 op_mod[0x10];
5350
5351 u8 reserved_at_40[0x8];
5352 u8 transport_domain[0x18];
5353
5354 u8 reserved_at_60[0x20];
5355 };
5356
5357 struct mlx5_ifc_dealloc_q_counter_out_bits {
5358 u8 status[0x8];
5359 u8 reserved_at_8[0x18];
5360
5361 u8 syndrome[0x20];
5362
5363 u8 reserved_at_40[0x40];
5364 };
5365
5366 struct mlx5_ifc_dealloc_q_counter_in_bits {
5367 u8 opcode[0x10];
5368 u8 reserved_at_10[0x10];
5369
5370 u8 reserved_at_20[0x10];
5371 u8 op_mod[0x10];
5372
5373 u8 reserved_at_40[0x18];
5374 u8 counter_set_id[0x8];
5375
5376 u8 reserved_at_60[0x20];
5377 };
5378
5379 struct mlx5_ifc_dealloc_pd_out_bits {
5380 u8 status[0x8];
5381 u8 reserved_at_8[0x18];
5382
5383 u8 syndrome[0x20];
5384
5385 u8 reserved_at_40[0x40];
5386 };
5387
5388 struct mlx5_ifc_dealloc_pd_in_bits {
5389 u8 opcode[0x10];
5390 u8 reserved_at_10[0x10];
5391
5392 u8 reserved_at_20[0x10];
5393 u8 op_mod[0x10];
5394
5395 u8 reserved_at_40[0x8];
5396 u8 pd[0x18];
5397
5398 u8 reserved_at_60[0x20];
5399 };
5400
5401 struct mlx5_ifc_create_xrc_srq_out_bits {
5402 u8 status[0x8];
5403 u8 reserved_at_8[0x18];
5404
5405 u8 syndrome[0x20];
5406
5407 u8 reserved_at_40[0x8];
5408 u8 xrc_srqn[0x18];
5409
5410 u8 reserved_at_60[0x20];
5411 };
5412
5413 struct mlx5_ifc_create_xrc_srq_in_bits {
5414 u8 opcode[0x10];
5415 u8 reserved_at_10[0x10];
5416
5417 u8 reserved_at_20[0x10];
5418 u8 op_mod[0x10];
5419
5420 u8 reserved_at_40[0x40];
5421
5422 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5423
5424 u8 reserved_at_280[0x600];
5425
5426 u8 pas[0][0x40];
5427 };
5428
5429 struct mlx5_ifc_create_tis_out_bits {
5430 u8 status[0x8];
5431 u8 reserved_at_8[0x18];
5432
5433 u8 syndrome[0x20];
5434
5435 u8 reserved_at_40[0x8];
5436 u8 tisn[0x18];
5437
5438 u8 reserved_at_60[0x20];
5439 };
5440
5441 struct mlx5_ifc_create_tis_in_bits {
5442 u8 opcode[0x10];
5443 u8 reserved_at_10[0x10];
5444
5445 u8 reserved_at_20[0x10];
5446 u8 op_mod[0x10];
5447
5448 u8 reserved_at_40[0xc0];
5449
5450 struct mlx5_ifc_tisc_bits ctx;
5451 };
5452
5453 struct mlx5_ifc_create_tir_out_bits {
5454 u8 status[0x8];
5455 u8 reserved_at_8[0x18];
5456
5457 u8 syndrome[0x20];
5458
5459 u8 reserved_at_40[0x8];
5460 u8 tirn[0x18];
5461
5462 u8 reserved_at_60[0x20];
5463 };
5464
5465 struct mlx5_ifc_create_tir_in_bits {
5466 u8 opcode[0x10];
5467 u8 reserved_at_10[0x10];
5468
5469 u8 reserved_at_20[0x10];
5470 u8 op_mod[0x10];
5471
5472 u8 reserved_at_40[0xc0];
5473
5474 struct mlx5_ifc_tirc_bits ctx;
5475 };
5476
5477 struct mlx5_ifc_create_srq_out_bits {
5478 u8 status[0x8];
5479 u8 reserved_at_8[0x18];
5480
5481 u8 syndrome[0x20];
5482
5483 u8 reserved_at_40[0x8];
5484 u8 srqn[0x18];
5485
5486 u8 reserved_at_60[0x20];
5487 };
5488
5489 struct mlx5_ifc_create_srq_in_bits {
5490 u8 opcode[0x10];
5491 u8 reserved_at_10[0x10];
5492
5493 u8 reserved_at_20[0x10];
5494 u8 op_mod[0x10];
5495
5496 u8 reserved_at_40[0x40];
5497
5498 struct mlx5_ifc_srqc_bits srq_context_entry;
5499
5500 u8 reserved_at_280[0x600];
5501
5502 u8 pas[0][0x40];
5503 };
5504
5505 struct mlx5_ifc_create_sq_out_bits {
5506 u8 status[0x8];
5507 u8 reserved_at_8[0x18];
5508
5509 u8 syndrome[0x20];
5510
5511 u8 reserved_at_40[0x8];
5512 u8 sqn[0x18];
5513
5514 u8 reserved_at_60[0x20];
5515 };
5516
5517 struct mlx5_ifc_create_sq_in_bits {
5518 u8 opcode[0x10];
5519 u8 reserved_at_10[0x10];
5520
5521 u8 reserved_at_20[0x10];
5522 u8 op_mod[0x10];
5523
5524 u8 reserved_at_40[0xc0];
5525
5526 struct mlx5_ifc_sqc_bits ctx;
5527 };
5528
5529 struct mlx5_ifc_create_rqt_out_bits {
5530 u8 status[0x8];
5531 u8 reserved_at_8[0x18];
5532
5533 u8 syndrome[0x20];
5534
5535 u8 reserved_at_40[0x8];
5536 u8 rqtn[0x18];
5537
5538 u8 reserved_at_60[0x20];
5539 };
5540
5541 struct mlx5_ifc_create_rqt_in_bits {
5542 u8 opcode[0x10];
5543 u8 reserved_at_10[0x10];
5544
5545 u8 reserved_at_20[0x10];
5546 u8 op_mod[0x10];
5547
5548 u8 reserved_at_40[0xc0];
5549
5550 struct mlx5_ifc_rqtc_bits rqt_context;
5551 };
5552
5553 struct mlx5_ifc_create_rq_out_bits {
5554 u8 status[0x8];
5555 u8 reserved_at_8[0x18];
5556
5557 u8 syndrome[0x20];
5558
5559 u8 reserved_at_40[0x8];
5560 u8 rqn[0x18];
5561
5562 u8 reserved_at_60[0x20];
5563 };
5564
5565 struct mlx5_ifc_create_rq_in_bits {
5566 u8 opcode[0x10];
5567 u8 reserved_at_10[0x10];
5568
5569 u8 reserved_at_20[0x10];
5570 u8 op_mod[0x10];
5571
5572 u8 reserved_at_40[0xc0];
5573
5574 struct mlx5_ifc_rqc_bits ctx;
5575 };
5576
5577 struct mlx5_ifc_create_rmp_out_bits {
5578 u8 status[0x8];
5579 u8 reserved_at_8[0x18];
5580
5581 u8 syndrome[0x20];
5582
5583 u8 reserved_at_40[0x8];
5584 u8 rmpn[0x18];
5585
5586 u8 reserved_at_60[0x20];
5587 };
5588
5589 struct mlx5_ifc_create_rmp_in_bits {
5590 u8 opcode[0x10];
5591 u8 reserved_at_10[0x10];
5592
5593 u8 reserved_at_20[0x10];
5594 u8 op_mod[0x10];
5595
5596 u8 reserved_at_40[0xc0];
5597
5598 struct mlx5_ifc_rmpc_bits ctx;
5599 };
5600
5601 struct mlx5_ifc_create_qp_out_bits {
5602 u8 status[0x8];
5603 u8 reserved_at_8[0x18];
5604
5605 u8 syndrome[0x20];
5606
5607 u8 reserved_at_40[0x8];
5608 u8 qpn[0x18];
5609
5610 u8 reserved_at_60[0x20];
5611 };
5612
5613 struct mlx5_ifc_create_qp_in_bits {
5614 u8 opcode[0x10];
5615 u8 reserved_at_10[0x10];
5616
5617 u8 reserved_at_20[0x10];
5618 u8 op_mod[0x10];
5619
5620 u8 reserved_at_40[0x40];
5621
5622 u8 opt_param_mask[0x20];
5623
5624 u8 reserved_at_a0[0x20];
5625
5626 struct mlx5_ifc_qpc_bits qpc;
5627
5628 u8 reserved_at_800[0x80];
5629
5630 u8 pas[0][0x40];
5631 };
5632
5633 struct mlx5_ifc_create_psv_out_bits {
5634 u8 status[0x8];
5635 u8 reserved_at_8[0x18];
5636
5637 u8 syndrome[0x20];
5638
5639 u8 reserved_at_40[0x40];
5640
5641 u8 reserved_at_80[0x8];
5642 u8 psv0_index[0x18];
5643
5644 u8 reserved_at_a0[0x8];
5645 u8 psv1_index[0x18];
5646
5647 u8 reserved_at_c0[0x8];
5648 u8 psv2_index[0x18];
5649
5650 u8 reserved_at_e0[0x8];
5651 u8 psv3_index[0x18];
5652 };
5653
5654 struct mlx5_ifc_create_psv_in_bits {
5655 u8 opcode[0x10];
5656 u8 reserved_at_10[0x10];
5657
5658 u8 reserved_at_20[0x10];
5659 u8 op_mod[0x10];
5660
5661 u8 num_psv[0x4];
5662 u8 reserved_at_44[0x4];
5663 u8 pd[0x18];
5664
5665 u8 reserved_at_60[0x20];
5666 };
5667
5668 struct mlx5_ifc_create_mkey_out_bits {
5669 u8 status[0x8];
5670 u8 reserved_at_8[0x18];
5671
5672 u8 syndrome[0x20];
5673
5674 u8 reserved_at_40[0x8];
5675 u8 mkey_index[0x18];
5676
5677 u8 reserved_at_60[0x20];
5678 };
5679
5680 struct mlx5_ifc_create_mkey_in_bits {
5681 u8 opcode[0x10];
5682 u8 reserved_at_10[0x10];
5683
5684 u8 reserved_at_20[0x10];
5685 u8 op_mod[0x10];
5686
5687 u8 reserved_at_40[0x20];
5688
5689 u8 pg_access[0x1];
5690 u8 reserved_at_61[0x1f];
5691
5692 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5693
5694 u8 reserved_at_280[0x80];
5695
5696 u8 translations_octword_actual_size[0x20];
5697
5698 u8 reserved_at_320[0x560];
5699
5700 u8 klm_pas_mtt[0][0x20];
5701 };
5702
5703 struct mlx5_ifc_create_flow_table_out_bits {
5704 u8 status[0x8];
5705 u8 reserved_at_8[0x18];
5706
5707 u8 syndrome[0x20];
5708
5709 u8 reserved_at_40[0x8];
5710 u8 table_id[0x18];
5711
5712 u8 reserved_at_60[0x20];
5713 };
5714
5715 struct mlx5_ifc_create_flow_table_in_bits {
5716 u8 opcode[0x10];
5717 u8 reserved_at_10[0x10];
5718
5719 u8 reserved_at_20[0x10];
5720 u8 op_mod[0x10];
5721
5722 u8 reserved_at_40[0x40];
5723
5724 u8 table_type[0x8];
5725 u8 reserved_at_88[0x18];
5726
5727 u8 reserved_at_a0[0x20];
5728
5729 u8 reserved_at_c0[0x4];
5730 u8 table_miss_mode[0x4];
5731 u8 level[0x8];
5732 u8 reserved_at_d0[0x8];
5733 u8 log_size[0x8];
5734
5735 u8 reserved_at_e0[0x8];
5736 u8 table_miss_id[0x18];
5737
5738 u8 reserved_at_100[0x100];
5739 };
5740
5741 struct mlx5_ifc_create_flow_group_out_bits {
5742 u8 status[0x8];
5743 u8 reserved_at_8[0x18];
5744
5745 u8 syndrome[0x20];
5746
5747 u8 reserved_at_40[0x8];
5748 u8 group_id[0x18];
5749
5750 u8 reserved_at_60[0x20];
5751 };
5752
5753 enum {
5754 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5755 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5756 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5757 };
5758
5759 struct mlx5_ifc_create_flow_group_in_bits {
5760 u8 opcode[0x10];
5761 u8 reserved_at_10[0x10];
5762
5763 u8 reserved_at_20[0x10];
5764 u8 op_mod[0x10];
5765
5766 u8 reserved_at_40[0x40];
5767
5768 u8 table_type[0x8];
5769 u8 reserved_at_88[0x18];
5770
5771 u8 reserved_at_a0[0x8];
5772 u8 table_id[0x18];
5773
5774 u8 reserved_at_c0[0x20];
5775
5776 u8 start_flow_index[0x20];
5777
5778 u8 reserved_at_100[0x20];
5779
5780 u8 end_flow_index[0x20];
5781
5782 u8 reserved_at_140[0xa0];
5783
5784 u8 reserved_at_1e0[0x18];
5785 u8 match_criteria_enable[0x8];
5786
5787 struct mlx5_ifc_fte_match_param_bits match_criteria;
5788
5789 u8 reserved_at_1200[0xe00];
5790 };
5791
5792 struct mlx5_ifc_create_eq_out_bits {
5793 u8 status[0x8];
5794 u8 reserved_at_8[0x18];
5795
5796 u8 syndrome[0x20];
5797
5798 u8 reserved_at_40[0x18];
5799 u8 eq_number[0x8];
5800
5801 u8 reserved_at_60[0x20];
5802 };
5803
5804 struct mlx5_ifc_create_eq_in_bits {
5805 u8 opcode[0x10];
5806 u8 reserved_at_10[0x10];
5807
5808 u8 reserved_at_20[0x10];
5809 u8 op_mod[0x10];
5810
5811 u8 reserved_at_40[0x40];
5812
5813 struct mlx5_ifc_eqc_bits eq_context_entry;
5814
5815 u8 reserved_at_280[0x40];
5816
5817 u8 event_bitmask[0x40];
5818
5819 u8 reserved_at_300[0x580];
5820
5821 u8 pas[0][0x40];
5822 };
5823
5824 struct mlx5_ifc_create_dct_out_bits {
5825 u8 status[0x8];
5826 u8 reserved_at_8[0x18];
5827
5828 u8 syndrome[0x20];
5829
5830 u8 reserved_at_40[0x8];
5831 u8 dctn[0x18];
5832
5833 u8 reserved_at_60[0x20];
5834 };
5835
5836 struct mlx5_ifc_create_dct_in_bits {
5837 u8 opcode[0x10];
5838 u8 reserved_at_10[0x10];
5839
5840 u8 reserved_at_20[0x10];
5841 u8 op_mod[0x10];
5842
5843 u8 reserved_at_40[0x40];
5844
5845 struct mlx5_ifc_dctc_bits dct_context_entry;
5846
5847 u8 reserved_at_280[0x180];
5848 };
5849
5850 struct mlx5_ifc_create_cq_out_bits {
5851 u8 status[0x8];
5852 u8 reserved_at_8[0x18];
5853
5854 u8 syndrome[0x20];
5855
5856 u8 reserved_at_40[0x8];
5857 u8 cqn[0x18];
5858
5859 u8 reserved_at_60[0x20];
5860 };
5861
5862 struct mlx5_ifc_create_cq_in_bits {
5863 u8 opcode[0x10];
5864 u8 reserved_at_10[0x10];
5865
5866 u8 reserved_at_20[0x10];
5867 u8 op_mod[0x10];
5868
5869 u8 reserved_at_40[0x40];
5870
5871 struct mlx5_ifc_cqc_bits cq_context;
5872
5873 u8 reserved_at_280[0x600];
5874
5875 u8 pas[0][0x40];
5876 };
5877
5878 struct mlx5_ifc_config_int_moderation_out_bits {
5879 u8 status[0x8];
5880 u8 reserved_at_8[0x18];
5881
5882 u8 syndrome[0x20];
5883
5884 u8 reserved_at_40[0x4];
5885 u8 min_delay[0xc];
5886 u8 int_vector[0x10];
5887
5888 u8 reserved_at_60[0x20];
5889 };
5890
5891 enum {
5892 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
5893 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
5894 };
5895
5896 struct mlx5_ifc_config_int_moderation_in_bits {
5897 u8 opcode[0x10];
5898 u8 reserved_at_10[0x10];
5899
5900 u8 reserved_at_20[0x10];
5901 u8 op_mod[0x10];
5902
5903 u8 reserved_at_40[0x4];
5904 u8 min_delay[0xc];
5905 u8 int_vector[0x10];
5906
5907 u8 reserved_at_60[0x20];
5908 };
5909
5910 struct mlx5_ifc_attach_to_mcg_out_bits {
5911 u8 status[0x8];
5912 u8 reserved_at_8[0x18];
5913
5914 u8 syndrome[0x20];
5915
5916 u8 reserved_at_40[0x40];
5917 };
5918
5919 struct mlx5_ifc_attach_to_mcg_in_bits {
5920 u8 opcode[0x10];
5921 u8 reserved_at_10[0x10];
5922
5923 u8 reserved_at_20[0x10];
5924 u8 op_mod[0x10];
5925
5926 u8 reserved_at_40[0x8];
5927 u8 qpn[0x18];
5928
5929 u8 reserved_at_60[0x20];
5930
5931 u8 multicast_gid[16][0x8];
5932 };
5933
5934 struct mlx5_ifc_arm_xrc_srq_out_bits {
5935 u8 status[0x8];
5936 u8 reserved_at_8[0x18];
5937
5938 u8 syndrome[0x20];
5939
5940 u8 reserved_at_40[0x40];
5941 };
5942
5943 enum {
5944 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
5945 };
5946
5947 struct mlx5_ifc_arm_xrc_srq_in_bits {
5948 u8 opcode[0x10];
5949 u8 reserved_at_10[0x10];
5950
5951 u8 reserved_at_20[0x10];
5952 u8 op_mod[0x10];
5953
5954 u8 reserved_at_40[0x8];
5955 u8 xrc_srqn[0x18];
5956
5957 u8 reserved_at_60[0x10];
5958 u8 lwm[0x10];
5959 };
5960
5961 struct mlx5_ifc_arm_rq_out_bits {
5962 u8 status[0x8];
5963 u8 reserved_at_8[0x18];
5964
5965 u8 syndrome[0x20];
5966
5967 u8 reserved_at_40[0x40];
5968 };
5969
5970 enum {
5971 MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1,
5972 };
5973
5974 struct mlx5_ifc_arm_rq_in_bits {
5975 u8 opcode[0x10];
5976 u8 reserved_at_10[0x10];
5977
5978 u8 reserved_at_20[0x10];
5979 u8 op_mod[0x10];
5980
5981 u8 reserved_at_40[0x8];
5982 u8 srq_number[0x18];
5983
5984 u8 reserved_at_60[0x10];
5985 u8 lwm[0x10];
5986 };
5987
5988 struct mlx5_ifc_arm_dct_out_bits {
5989 u8 status[0x8];
5990 u8 reserved_at_8[0x18];
5991
5992 u8 syndrome[0x20];
5993
5994 u8 reserved_at_40[0x40];
5995 };
5996
5997 struct mlx5_ifc_arm_dct_in_bits {
5998 u8 opcode[0x10];
5999 u8 reserved_at_10[0x10];
6000
6001 u8 reserved_at_20[0x10];
6002 u8 op_mod[0x10];
6003
6004 u8 reserved_at_40[0x8];
6005 u8 dct_number[0x18];
6006
6007 u8 reserved_at_60[0x20];
6008 };
6009
6010 struct mlx5_ifc_alloc_xrcd_out_bits {
6011 u8 status[0x8];
6012 u8 reserved_at_8[0x18];
6013
6014 u8 syndrome[0x20];
6015
6016 u8 reserved_at_40[0x8];
6017 u8 xrcd[0x18];
6018
6019 u8 reserved_at_60[0x20];
6020 };
6021
6022 struct mlx5_ifc_alloc_xrcd_in_bits {
6023 u8 opcode[0x10];
6024 u8 reserved_at_10[0x10];
6025
6026 u8 reserved_at_20[0x10];
6027 u8 op_mod[0x10];
6028
6029 u8 reserved_at_40[0x40];
6030 };
6031
6032 struct mlx5_ifc_alloc_uar_out_bits {
6033 u8 status[0x8];
6034 u8 reserved_at_8[0x18];
6035
6036 u8 syndrome[0x20];
6037
6038 u8 reserved_at_40[0x8];
6039 u8 uar[0x18];
6040
6041 u8 reserved_at_60[0x20];
6042 };
6043
6044 struct mlx5_ifc_alloc_uar_in_bits {
6045 u8 opcode[0x10];
6046 u8 reserved_at_10[0x10];
6047
6048 u8 reserved_at_20[0x10];
6049 u8 op_mod[0x10];
6050
6051 u8 reserved_at_40[0x40];
6052 };
6053
6054 struct mlx5_ifc_alloc_transport_domain_out_bits {
6055 u8 status[0x8];
6056 u8 reserved_at_8[0x18];
6057
6058 u8 syndrome[0x20];
6059
6060 u8 reserved_at_40[0x8];
6061 u8 transport_domain[0x18];
6062
6063 u8 reserved_at_60[0x20];
6064 };
6065
6066 struct mlx5_ifc_alloc_transport_domain_in_bits {
6067 u8 opcode[0x10];
6068 u8 reserved_at_10[0x10];
6069
6070 u8 reserved_at_20[0x10];
6071 u8 op_mod[0x10];
6072
6073 u8 reserved_at_40[0x40];
6074 };
6075
6076 struct mlx5_ifc_alloc_q_counter_out_bits {
6077 u8 status[0x8];
6078 u8 reserved_at_8[0x18];
6079
6080 u8 syndrome[0x20];
6081
6082 u8 reserved_at_40[0x18];
6083 u8 counter_set_id[0x8];
6084
6085 u8 reserved_at_60[0x20];
6086 };
6087
6088 struct mlx5_ifc_alloc_q_counter_in_bits {
6089 u8 opcode[0x10];
6090 u8 reserved_at_10[0x10];
6091
6092 u8 reserved_at_20[0x10];
6093 u8 op_mod[0x10];
6094
6095 u8 reserved_at_40[0x40];
6096 };
6097
6098 struct mlx5_ifc_alloc_pd_out_bits {
6099 u8 status[0x8];
6100 u8 reserved_at_8[0x18];
6101
6102 u8 syndrome[0x20];
6103
6104 u8 reserved_at_40[0x8];
6105 u8 pd[0x18];
6106
6107 u8 reserved_at_60[0x20];
6108 };
6109
6110 struct mlx5_ifc_alloc_pd_in_bits {
6111 u8 opcode[0x10];
6112 u8 reserved_at_10[0x10];
6113
6114 u8 reserved_at_20[0x10];
6115 u8 op_mod[0x10];
6116
6117 u8 reserved_at_40[0x40];
6118 };
6119
6120 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6121 u8 status[0x8];
6122 u8 reserved_at_8[0x18];
6123
6124 u8 syndrome[0x20];
6125
6126 u8 reserved_at_40[0x40];
6127 };
6128
6129 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6130 u8 opcode[0x10];
6131 u8 reserved_at_10[0x10];
6132
6133 u8 reserved_at_20[0x10];
6134 u8 op_mod[0x10];
6135
6136 u8 reserved_at_40[0x20];
6137
6138 u8 reserved_at_60[0x10];
6139 u8 vxlan_udp_port[0x10];
6140 };
6141
6142 struct mlx5_ifc_access_register_out_bits {
6143 u8 status[0x8];
6144 u8 reserved_at_8[0x18];
6145
6146 u8 syndrome[0x20];
6147
6148 u8 reserved_at_40[0x40];
6149
6150 u8 register_data[0][0x20];
6151 };
6152
6153 enum {
6154 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
6155 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
6156 };
6157
6158 struct mlx5_ifc_access_register_in_bits {
6159 u8 opcode[0x10];
6160 u8 reserved_at_10[0x10];
6161
6162 u8 reserved_at_20[0x10];
6163 u8 op_mod[0x10];
6164
6165 u8 reserved_at_40[0x10];
6166 u8 register_id[0x10];
6167
6168 u8 argument[0x20];
6169
6170 u8 register_data[0][0x20];
6171 };
6172
6173 struct mlx5_ifc_sltp_reg_bits {
6174 u8 status[0x4];
6175 u8 version[0x4];
6176 u8 local_port[0x8];
6177 u8 pnat[0x2];
6178 u8 reserved_at_12[0x2];
6179 u8 lane[0x4];
6180 u8 reserved_at_18[0x8];
6181
6182 u8 reserved_at_20[0x20];
6183
6184 u8 reserved_at_40[0x7];
6185 u8 polarity[0x1];
6186 u8 ob_tap0[0x8];
6187 u8 ob_tap1[0x8];
6188 u8 ob_tap2[0x8];
6189
6190 u8 reserved_at_60[0xc];
6191 u8 ob_preemp_mode[0x4];
6192 u8 ob_reg[0x8];
6193 u8 ob_bias[0x8];
6194
6195 u8 reserved_at_80[0x20];
6196 };
6197
6198 struct mlx5_ifc_slrg_reg_bits {
6199 u8 status[0x4];
6200 u8 version[0x4];
6201 u8 local_port[0x8];
6202 u8 pnat[0x2];
6203 u8 reserved_at_12[0x2];
6204 u8 lane[0x4];
6205 u8 reserved_at_18[0x8];
6206
6207 u8 time_to_link_up[0x10];
6208 u8 reserved_at_30[0xc];
6209 u8 grade_lane_speed[0x4];
6210
6211 u8 grade_version[0x8];
6212 u8 grade[0x18];
6213
6214 u8 reserved_at_60[0x4];
6215 u8 height_grade_type[0x4];
6216 u8 height_grade[0x18];
6217
6218 u8 height_dz[0x10];
6219 u8 height_dv[0x10];
6220
6221 u8 reserved_at_a0[0x10];
6222 u8 height_sigma[0x10];
6223
6224 u8 reserved_at_c0[0x20];
6225
6226 u8 reserved_at_e0[0x4];
6227 u8 phase_grade_type[0x4];
6228 u8 phase_grade[0x18];
6229
6230 u8 reserved_at_100[0x8];
6231 u8 phase_eo_pos[0x8];
6232 u8 reserved_at_110[0x8];
6233 u8 phase_eo_neg[0x8];
6234
6235 u8 ffe_set_tested[0x10];
6236 u8 test_errors_per_lane[0x10];
6237 };
6238
6239 struct mlx5_ifc_pvlc_reg_bits {
6240 u8 reserved_at_0[0x8];
6241 u8 local_port[0x8];
6242 u8 reserved_at_10[0x10];
6243
6244 u8 reserved_at_20[0x1c];
6245 u8 vl_hw_cap[0x4];
6246
6247 u8 reserved_at_40[0x1c];
6248 u8 vl_admin[0x4];
6249
6250 u8 reserved_at_60[0x1c];
6251 u8 vl_operational[0x4];
6252 };
6253
6254 struct mlx5_ifc_pude_reg_bits {
6255 u8 swid[0x8];
6256 u8 local_port[0x8];
6257 u8 reserved_at_10[0x4];
6258 u8 admin_status[0x4];
6259 u8 reserved_at_18[0x4];
6260 u8 oper_status[0x4];
6261
6262 u8 reserved_at_20[0x60];
6263 };
6264
6265 struct mlx5_ifc_ptys_reg_bits {
6266 u8 reserved_at_0[0x8];
6267 u8 local_port[0x8];
6268 u8 reserved_at_10[0xd];
6269 u8 proto_mask[0x3];
6270
6271 u8 reserved_at_20[0x40];
6272
6273 u8 eth_proto_capability[0x20];
6274
6275 u8 ib_link_width_capability[0x10];
6276 u8 ib_proto_capability[0x10];
6277
6278 u8 reserved_at_a0[0x20];
6279
6280 u8 eth_proto_admin[0x20];
6281
6282 u8 ib_link_width_admin[0x10];
6283 u8 ib_proto_admin[0x10];
6284
6285 u8 reserved_at_100[0x20];
6286
6287 u8 eth_proto_oper[0x20];
6288
6289 u8 ib_link_width_oper[0x10];
6290 u8 ib_proto_oper[0x10];
6291
6292 u8 reserved_at_160[0x20];
6293
6294 u8 eth_proto_lp_advertise[0x20];
6295
6296 u8 reserved_at_1a0[0x60];
6297 };
6298
6299 struct mlx5_ifc_ptas_reg_bits {
6300 u8 reserved_at_0[0x20];
6301
6302 u8 algorithm_options[0x10];
6303 u8 reserved_at_30[0x4];
6304 u8 repetitions_mode[0x4];
6305 u8 num_of_repetitions[0x8];
6306
6307 u8 grade_version[0x8];
6308 u8 height_grade_type[0x4];
6309 u8 phase_grade_type[0x4];
6310 u8 height_grade_weight[0x8];
6311 u8 phase_grade_weight[0x8];
6312
6313 u8 gisim_measure_bits[0x10];
6314 u8 adaptive_tap_measure_bits[0x10];
6315
6316 u8 ber_bath_high_error_threshold[0x10];
6317 u8 ber_bath_mid_error_threshold[0x10];
6318
6319 u8 ber_bath_low_error_threshold[0x10];
6320 u8 one_ratio_high_threshold[0x10];
6321
6322 u8 one_ratio_high_mid_threshold[0x10];
6323 u8 one_ratio_low_mid_threshold[0x10];
6324
6325 u8 one_ratio_low_threshold[0x10];
6326 u8 ndeo_error_threshold[0x10];
6327
6328 u8 mixer_offset_step_size[0x10];
6329 u8 reserved_at_110[0x8];
6330 u8 mix90_phase_for_voltage_bath[0x8];
6331
6332 u8 mixer_offset_start[0x10];
6333 u8 mixer_offset_end[0x10];
6334
6335 u8 reserved_at_140[0x15];
6336 u8 ber_test_time[0xb];
6337 };
6338
6339 struct mlx5_ifc_pspa_reg_bits {
6340 u8 swid[0x8];
6341 u8 local_port[0x8];
6342 u8 sub_port[0x8];
6343 u8 reserved_at_18[0x8];
6344
6345 u8 reserved_at_20[0x20];
6346 };
6347
6348 struct mlx5_ifc_pqdr_reg_bits {
6349 u8 reserved_at_0[0x8];
6350 u8 local_port[0x8];
6351 u8 reserved_at_10[0x5];
6352 u8 prio[0x3];
6353 u8 reserved_at_18[0x6];
6354 u8 mode[0x2];
6355
6356 u8 reserved_at_20[0x20];
6357
6358 u8 reserved_at_40[0x10];
6359 u8 min_threshold[0x10];
6360
6361 u8 reserved_at_60[0x10];
6362 u8 max_threshold[0x10];
6363
6364 u8 reserved_at_80[0x10];
6365 u8 mark_probability_denominator[0x10];
6366
6367 u8 reserved_at_a0[0x60];
6368 };
6369
6370 struct mlx5_ifc_ppsc_reg_bits {
6371 u8 reserved_at_0[0x8];
6372 u8 local_port[0x8];
6373 u8 reserved_at_10[0x10];
6374
6375 u8 reserved_at_20[0x60];
6376
6377 u8 reserved_at_80[0x1c];
6378 u8 wrps_admin[0x4];
6379
6380 u8 reserved_at_a0[0x1c];
6381 u8 wrps_status[0x4];
6382
6383 u8 reserved_at_c0[0x8];
6384 u8 up_threshold[0x8];
6385 u8 reserved_at_d0[0x8];
6386 u8 down_threshold[0x8];
6387
6388 u8 reserved_at_e0[0x20];
6389
6390 u8 reserved_at_100[0x1c];
6391 u8 srps_admin[0x4];
6392
6393 u8 reserved_at_120[0x1c];
6394 u8 srps_status[0x4];
6395
6396 u8 reserved_at_140[0x40];
6397 };
6398
6399 struct mlx5_ifc_pplr_reg_bits {
6400 u8 reserved_at_0[0x8];
6401 u8 local_port[0x8];
6402 u8 reserved_at_10[0x10];
6403
6404 u8 reserved_at_20[0x8];
6405 u8 lb_cap[0x8];
6406 u8 reserved_at_30[0x8];
6407 u8 lb_en[0x8];
6408 };
6409
6410 struct mlx5_ifc_pplm_reg_bits {
6411 u8 reserved_at_0[0x8];
6412 u8 local_port[0x8];
6413 u8 reserved_at_10[0x10];
6414
6415 u8 reserved_at_20[0x20];
6416
6417 u8 port_profile_mode[0x8];
6418 u8 static_port_profile[0x8];
6419 u8 active_port_profile[0x8];
6420 u8 reserved_at_58[0x8];
6421
6422 u8 retransmission_active[0x8];
6423 u8 fec_mode_active[0x18];
6424
6425 u8 reserved_at_80[0x20];
6426 };
6427
6428 struct mlx5_ifc_ppcnt_reg_bits {
6429 u8 swid[0x8];
6430 u8 local_port[0x8];
6431 u8 pnat[0x2];
6432 u8 reserved_at_12[0x8];
6433 u8 grp[0x6];
6434
6435 u8 clr[0x1];
6436 u8 reserved_at_21[0x1c];
6437 u8 prio_tc[0x3];
6438
6439 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6440 };
6441
6442 struct mlx5_ifc_ppad_reg_bits {
6443 u8 reserved_at_0[0x3];
6444 u8 single_mac[0x1];
6445 u8 reserved_at_4[0x4];
6446 u8 local_port[0x8];
6447 u8 mac_47_32[0x10];
6448
6449 u8 mac_31_0[0x20];
6450
6451 u8 reserved_at_40[0x40];
6452 };
6453
6454 struct mlx5_ifc_pmtu_reg_bits {
6455 u8 reserved_at_0[0x8];
6456 u8 local_port[0x8];
6457 u8 reserved_at_10[0x10];
6458
6459 u8 max_mtu[0x10];
6460 u8 reserved_at_30[0x10];
6461
6462 u8 admin_mtu[0x10];
6463 u8 reserved_at_50[0x10];
6464
6465 u8 oper_mtu[0x10];
6466 u8 reserved_at_70[0x10];
6467 };
6468
6469 struct mlx5_ifc_pmpr_reg_bits {
6470 u8 reserved_at_0[0x8];
6471 u8 module[0x8];
6472 u8 reserved_at_10[0x10];
6473
6474 u8 reserved_at_20[0x18];
6475 u8 attenuation_5g[0x8];
6476
6477 u8 reserved_at_40[0x18];
6478 u8 attenuation_7g[0x8];
6479
6480 u8 reserved_at_60[0x18];
6481 u8 attenuation_12g[0x8];
6482 };
6483
6484 struct mlx5_ifc_pmpe_reg_bits {
6485 u8 reserved_at_0[0x8];
6486 u8 module[0x8];
6487 u8 reserved_at_10[0xc];
6488 u8 module_status[0x4];
6489
6490 u8 reserved_at_20[0x60];
6491 };
6492
6493 struct mlx5_ifc_pmpc_reg_bits {
6494 u8 module_state_updated[32][0x8];
6495 };
6496
6497 struct mlx5_ifc_pmlpn_reg_bits {
6498 u8 reserved_at_0[0x4];
6499 u8 mlpn_status[0x4];
6500 u8 local_port[0x8];
6501 u8 reserved_at_10[0x10];
6502
6503 u8 e[0x1];
6504 u8 reserved_at_21[0x1f];
6505 };
6506
6507 struct mlx5_ifc_pmlp_reg_bits {
6508 u8 rxtx[0x1];
6509 u8 reserved_at_1[0x7];
6510 u8 local_port[0x8];
6511 u8 reserved_at_10[0x8];
6512 u8 width[0x8];
6513
6514 u8 lane0_module_mapping[0x20];
6515
6516 u8 lane1_module_mapping[0x20];
6517
6518 u8 lane2_module_mapping[0x20];
6519
6520 u8 lane3_module_mapping[0x20];
6521
6522 u8 reserved_at_a0[0x160];
6523 };
6524
6525 struct mlx5_ifc_pmaos_reg_bits {
6526 u8 reserved_at_0[0x8];
6527 u8 module[0x8];
6528 u8 reserved_at_10[0x4];
6529 u8 admin_status[0x4];
6530 u8 reserved_at_18[0x4];
6531 u8 oper_status[0x4];
6532
6533 u8 ase[0x1];
6534 u8 ee[0x1];
6535 u8 reserved_at_22[0x1c];
6536 u8 e[0x2];
6537
6538 u8 reserved_at_40[0x40];
6539 };
6540
6541 struct mlx5_ifc_plpc_reg_bits {
6542 u8 reserved_at_0[0x4];
6543 u8 profile_id[0xc];
6544 u8 reserved_at_10[0x4];
6545 u8 proto_mask[0x4];
6546 u8 reserved_at_18[0x8];
6547
6548 u8 reserved_at_20[0x10];
6549 u8 lane_speed[0x10];
6550
6551 u8 reserved_at_40[0x17];
6552 u8 lpbf[0x1];
6553 u8 fec_mode_policy[0x8];
6554
6555 u8 retransmission_capability[0x8];
6556 u8 fec_mode_capability[0x18];
6557
6558 u8 retransmission_support_admin[0x8];
6559 u8 fec_mode_support_admin[0x18];
6560
6561 u8 retransmission_request_admin[0x8];
6562 u8 fec_mode_request_admin[0x18];
6563
6564 u8 reserved_at_c0[0x80];
6565 };
6566
6567 struct mlx5_ifc_plib_reg_bits {
6568 u8 reserved_at_0[0x8];
6569 u8 local_port[0x8];
6570 u8 reserved_at_10[0x8];
6571 u8 ib_port[0x8];
6572
6573 u8 reserved_at_20[0x60];
6574 };
6575
6576 struct mlx5_ifc_plbf_reg_bits {
6577 u8 reserved_at_0[0x8];
6578 u8 local_port[0x8];
6579 u8 reserved_at_10[0xd];
6580 u8 lbf_mode[0x3];
6581
6582 u8 reserved_at_20[0x20];
6583 };
6584
6585 struct mlx5_ifc_pipg_reg_bits {
6586 u8 reserved_at_0[0x8];
6587 u8 local_port[0x8];
6588 u8 reserved_at_10[0x10];
6589
6590 u8 dic[0x1];
6591 u8 reserved_at_21[0x19];
6592 u8 ipg[0x4];
6593 u8 reserved_at_3e[0x2];
6594 };
6595
6596 struct mlx5_ifc_pifr_reg_bits {
6597 u8 reserved_at_0[0x8];
6598 u8 local_port[0x8];
6599 u8 reserved_at_10[0x10];
6600
6601 u8 reserved_at_20[0xe0];
6602
6603 u8 port_filter[8][0x20];
6604
6605 u8 port_filter_update_en[8][0x20];
6606 };
6607
6608 struct mlx5_ifc_pfcc_reg_bits {
6609 u8 reserved_at_0[0x8];
6610 u8 local_port[0x8];
6611 u8 reserved_at_10[0x10];
6612
6613 u8 ppan[0x4];
6614 u8 reserved_at_24[0x4];
6615 u8 prio_mask_tx[0x8];
6616 u8 reserved_at_30[0x8];
6617 u8 prio_mask_rx[0x8];
6618
6619 u8 pptx[0x1];
6620 u8 aptx[0x1];
6621 u8 reserved_at_42[0x6];
6622 u8 pfctx[0x8];
6623 u8 reserved_at_50[0x10];
6624
6625 u8 pprx[0x1];
6626 u8 aprx[0x1];
6627 u8 reserved_at_62[0x6];
6628 u8 pfcrx[0x8];
6629 u8 reserved_at_70[0x10];
6630
6631 u8 reserved_at_80[0x80];
6632 };
6633
6634 struct mlx5_ifc_pelc_reg_bits {
6635 u8 op[0x4];
6636 u8 reserved_at_4[0x4];
6637 u8 local_port[0x8];
6638 u8 reserved_at_10[0x10];
6639
6640 u8 op_admin[0x8];
6641 u8 op_capability[0x8];
6642 u8 op_request[0x8];
6643 u8 op_active[0x8];
6644
6645 u8 admin[0x40];
6646
6647 u8 capability[0x40];
6648
6649 u8 request[0x40];
6650
6651 u8 active[0x40];
6652
6653 u8 reserved_at_140[0x80];
6654 };
6655
6656 struct mlx5_ifc_peir_reg_bits {
6657 u8 reserved_at_0[0x8];
6658 u8 local_port[0x8];
6659 u8 reserved_at_10[0x10];
6660
6661 u8 reserved_at_20[0xc];
6662 u8 error_count[0x4];
6663 u8 reserved_at_30[0x10];
6664
6665 u8 reserved_at_40[0xc];
6666 u8 lane[0x4];
6667 u8 reserved_at_50[0x8];
6668 u8 error_type[0x8];
6669 };
6670
6671 struct mlx5_ifc_pcap_reg_bits {
6672 u8 reserved_at_0[0x8];
6673 u8 local_port[0x8];
6674 u8 reserved_at_10[0x10];
6675
6676 u8 port_capability_mask[4][0x20];
6677 };
6678
6679 struct mlx5_ifc_paos_reg_bits {
6680 u8 swid[0x8];
6681 u8 local_port[0x8];
6682 u8 reserved_at_10[0x4];
6683 u8 admin_status[0x4];
6684 u8 reserved_at_18[0x4];
6685 u8 oper_status[0x4];
6686
6687 u8 ase[0x1];
6688 u8 ee[0x1];
6689 u8 reserved_at_22[0x1c];
6690 u8 e[0x2];
6691
6692 u8 reserved_at_40[0x40];
6693 };
6694
6695 struct mlx5_ifc_pamp_reg_bits {
6696 u8 reserved_at_0[0x8];
6697 u8 opamp_group[0x8];
6698 u8 reserved_at_10[0xc];
6699 u8 opamp_group_type[0x4];
6700
6701 u8 start_index[0x10];
6702 u8 reserved_at_30[0x4];
6703 u8 num_of_indices[0xc];
6704
6705 u8 index_data[18][0x10];
6706 };
6707
6708 struct mlx5_ifc_lane_2_module_mapping_bits {
6709 u8 reserved_at_0[0x6];
6710 u8 rx_lane[0x2];
6711 u8 reserved_at_8[0x6];
6712 u8 tx_lane[0x2];
6713 u8 reserved_at_10[0x8];
6714 u8 module[0x8];
6715 };
6716
6717 struct mlx5_ifc_bufferx_reg_bits {
6718 u8 reserved_at_0[0x6];
6719 u8 lossy[0x1];
6720 u8 epsb[0x1];
6721 u8 reserved_at_8[0xc];
6722 u8 size[0xc];
6723
6724 u8 xoff_threshold[0x10];
6725 u8 xon_threshold[0x10];
6726 };
6727
6728 struct mlx5_ifc_set_node_in_bits {
6729 u8 node_description[64][0x8];
6730 };
6731
6732 struct mlx5_ifc_register_power_settings_bits {
6733 u8 reserved_at_0[0x18];
6734 u8 power_settings_level[0x8];
6735
6736 u8 reserved_at_20[0x60];
6737 };
6738
6739 struct mlx5_ifc_register_host_endianness_bits {
6740 u8 he[0x1];
6741 u8 reserved_at_1[0x1f];
6742
6743 u8 reserved_at_20[0x60];
6744 };
6745
6746 struct mlx5_ifc_umr_pointer_desc_argument_bits {
6747 u8 reserved_at_0[0x20];
6748
6749 u8 mkey[0x20];
6750
6751 u8 addressh_63_32[0x20];
6752
6753 u8 addressl_31_0[0x20];
6754 };
6755
6756 struct mlx5_ifc_ud_adrs_vector_bits {
6757 u8 dc_key[0x40];
6758
6759 u8 ext[0x1];
6760 u8 reserved_at_41[0x7];
6761 u8 destination_qp_dct[0x18];
6762
6763 u8 static_rate[0x4];
6764 u8 sl_eth_prio[0x4];
6765 u8 fl[0x1];
6766 u8 mlid[0x7];
6767 u8 rlid_udp_sport[0x10];
6768
6769 u8 reserved_at_80[0x20];
6770
6771 u8 rmac_47_16[0x20];
6772
6773 u8 rmac_15_0[0x10];
6774 u8 tclass[0x8];
6775 u8 hop_limit[0x8];
6776
6777 u8 reserved_at_e0[0x1];
6778 u8 grh[0x1];
6779 u8 reserved_at_e2[0x2];
6780 u8 src_addr_index[0x8];
6781 u8 flow_label[0x14];
6782
6783 u8 rgid_rip[16][0x8];
6784 };
6785
6786 struct mlx5_ifc_pages_req_event_bits {
6787 u8 reserved_at_0[0x10];
6788 u8 function_id[0x10];
6789
6790 u8 num_pages[0x20];
6791
6792 u8 reserved_at_40[0xa0];
6793 };
6794
6795 struct mlx5_ifc_eqe_bits {
6796 u8 reserved_at_0[0x8];
6797 u8 event_type[0x8];
6798 u8 reserved_at_10[0x8];
6799 u8 event_sub_type[0x8];
6800
6801 u8 reserved_at_20[0xe0];
6802
6803 union mlx5_ifc_event_auto_bits event_data;
6804
6805 u8 reserved_at_1e0[0x10];
6806 u8 signature[0x8];
6807 u8 reserved_at_1f8[0x7];
6808 u8 owner[0x1];
6809 };
6810
6811 enum {
6812 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
6813 };
6814
6815 struct mlx5_ifc_cmd_queue_entry_bits {
6816 u8 type[0x8];
6817 u8 reserved_at_8[0x18];
6818
6819 u8 input_length[0x20];
6820
6821 u8 input_mailbox_pointer_63_32[0x20];
6822
6823 u8 input_mailbox_pointer_31_9[0x17];
6824 u8 reserved_at_77[0x9];
6825
6826 u8 command_input_inline_data[16][0x8];
6827
6828 u8 command_output_inline_data[16][0x8];
6829
6830 u8 output_mailbox_pointer_63_32[0x20];
6831
6832 u8 output_mailbox_pointer_31_9[0x17];
6833 u8 reserved_at_1b7[0x9];
6834
6835 u8 output_length[0x20];
6836
6837 u8 token[0x8];
6838 u8 signature[0x8];
6839 u8 reserved_at_1f0[0x8];
6840 u8 status[0x7];
6841 u8 ownership[0x1];
6842 };
6843
6844 struct mlx5_ifc_cmd_out_bits {
6845 u8 status[0x8];
6846 u8 reserved_at_8[0x18];
6847
6848 u8 syndrome[0x20];
6849
6850 u8 command_output[0x20];
6851 };
6852
6853 struct mlx5_ifc_cmd_in_bits {
6854 u8 opcode[0x10];
6855 u8 reserved_at_10[0x10];
6856
6857 u8 reserved_at_20[0x10];
6858 u8 op_mod[0x10];
6859
6860 u8 command[0][0x20];
6861 };
6862
6863 struct mlx5_ifc_cmd_if_box_bits {
6864 u8 mailbox_data[512][0x8];
6865
6866 u8 reserved_at_1000[0x180];
6867
6868 u8 next_pointer_63_32[0x20];
6869
6870 u8 next_pointer_31_10[0x16];
6871 u8 reserved_at_11b6[0xa];
6872
6873 u8 block_number[0x20];
6874
6875 u8 reserved_at_11e0[0x8];
6876 u8 token[0x8];
6877 u8 ctrl_signature[0x8];
6878 u8 signature[0x8];
6879 };
6880
6881 struct mlx5_ifc_mtt_bits {
6882 u8 ptag_63_32[0x20];
6883
6884 u8 ptag_31_8[0x18];
6885 u8 reserved_at_38[0x6];
6886 u8 wr_en[0x1];
6887 u8 rd_en[0x1];
6888 };
6889
6890 struct mlx5_ifc_query_wol_rol_out_bits {
6891 u8 status[0x8];
6892 u8 reserved_at_8[0x18];
6893
6894 u8 syndrome[0x20];
6895
6896 u8 reserved_at_40[0x10];
6897 u8 rol_mode[0x8];
6898 u8 wol_mode[0x8];
6899
6900 u8 reserved_at_60[0x20];
6901 };
6902
6903 struct mlx5_ifc_query_wol_rol_in_bits {
6904 u8 opcode[0x10];
6905 u8 reserved_at_10[0x10];
6906
6907 u8 reserved_at_20[0x10];
6908 u8 op_mod[0x10];
6909
6910 u8 reserved_at_40[0x40];
6911 };
6912
6913 struct mlx5_ifc_set_wol_rol_out_bits {
6914 u8 status[0x8];
6915 u8 reserved_at_8[0x18];
6916
6917 u8 syndrome[0x20];
6918
6919 u8 reserved_at_40[0x40];
6920 };
6921
6922 struct mlx5_ifc_set_wol_rol_in_bits {
6923 u8 opcode[0x10];
6924 u8 reserved_at_10[0x10];
6925
6926 u8 reserved_at_20[0x10];
6927 u8 op_mod[0x10];
6928
6929 u8 rol_mode_valid[0x1];
6930 u8 wol_mode_valid[0x1];
6931 u8 reserved_at_42[0xe];
6932 u8 rol_mode[0x8];
6933 u8 wol_mode[0x8];
6934
6935 u8 reserved_at_60[0x20];
6936 };
6937
6938 enum {
6939 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
6940 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
6941 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
6942 };
6943
6944 enum {
6945 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
6946 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
6947 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
6948 };
6949
6950 enum {
6951 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
6952 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
6953 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
6954 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
6955 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
6956 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
6957 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
6958 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
6959 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
6960 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
6961 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
6962 };
6963
6964 struct mlx5_ifc_initial_seg_bits {
6965 u8 fw_rev_minor[0x10];
6966 u8 fw_rev_major[0x10];
6967
6968 u8 cmd_interface_rev[0x10];
6969 u8 fw_rev_subminor[0x10];
6970
6971 u8 reserved_at_40[0x40];
6972
6973 u8 cmdq_phy_addr_63_32[0x20];
6974
6975 u8 cmdq_phy_addr_31_12[0x14];
6976 u8 reserved_at_b4[0x2];
6977 u8 nic_interface[0x2];
6978 u8 log_cmdq_size[0x4];
6979 u8 log_cmdq_stride[0x4];
6980
6981 u8 command_doorbell_vector[0x20];
6982
6983 u8 reserved_at_e0[0xf00];
6984
6985 u8 initializing[0x1];
6986 u8 reserved_at_fe1[0x4];
6987 u8 nic_interface_supported[0x3];
6988 u8 reserved_at_fe8[0x18];
6989
6990 struct mlx5_ifc_health_buffer_bits health_buffer;
6991
6992 u8 no_dram_nic_offset[0x20];
6993
6994 u8 reserved_at_1220[0x6e40];
6995
6996 u8 reserved_at_8060[0x1f];
6997 u8 clear_int[0x1];
6998
6999 u8 health_syndrome[0x8];
7000 u8 health_counter[0x18];
7001
7002 u8 reserved_at_80a0[0x17fc0];
7003 };
7004
7005 union mlx5_ifc_ports_control_registers_document_bits {
7006 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7007 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7008 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7009 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7010 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7011 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7012 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7013 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7014 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7015 struct mlx5_ifc_pamp_reg_bits pamp_reg;
7016 struct mlx5_ifc_paos_reg_bits paos_reg;
7017 struct mlx5_ifc_pcap_reg_bits pcap_reg;
7018 struct mlx5_ifc_peir_reg_bits peir_reg;
7019 struct mlx5_ifc_pelc_reg_bits pelc_reg;
7020 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
7021 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7022 struct mlx5_ifc_pifr_reg_bits pifr_reg;
7023 struct mlx5_ifc_pipg_reg_bits pipg_reg;
7024 struct mlx5_ifc_plbf_reg_bits plbf_reg;
7025 struct mlx5_ifc_plib_reg_bits plib_reg;
7026 struct mlx5_ifc_plpc_reg_bits plpc_reg;
7027 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7028 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7029 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7030 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7031 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7032 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7033 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7034 struct mlx5_ifc_ppad_reg_bits ppad_reg;
7035 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7036 struct mlx5_ifc_pplm_reg_bits pplm_reg;
7037 struct mlx5_ifc_pplr_reg_bits pplr_reg;
7038 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7039 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7040 struct mlx5_ifc_pspa_reg_bits pspa_reg;
7041 struct mlx5_ifc_ptas_reg_bits ptas_reg;
7042 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7043 struct mlx5_ifc_pude_reg_bits pude_reg;
7044 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7045 struct mlx5_ifc_slrg_reg_bits slrg_reg;
7046 struct mlx5_ifc_sltp_reg_bits sltp_reg;
7047 u8 reserved_at_0[0x60e0];
7048 };
7049
7050 union mlx5_ifc_debug_enhancements_document_bits {
7051 struct mlx5_ifc_health_buffer_bits health_buffer;
7052 u8 reserved_at_0[0x200];
7053 };
7054
7055 union mlx5_ifc_uplink_pci_interface_document_bits {
7056 struct mlx5_ifc_initial_seg_bits initial_seg;
7057 u8 reserved_at_0[0x20060];
7058 };
7059
7060 struct mlx5_ifc_set_flow_table_root_out_bits {
7061 u8 status[0x8];
7062 u8 reserved_at_8[0x18];
7063
7064 u8 syndrome[0x20];
7065
7066 u8 reserved_at_40[0x40];
7067 };
7068
7069 struct mlx5_ifc_set_flow_table_root_in_bits {
7070 u8 opcode[0x10];
7071 u8 reserved_at_10[0x10];
7072
7073 u8 reserved_at_20[0x10];
7074 u8 op_mod[0x10];
7075
7076 u8 reserved_at_40[0x40];
7077
7078 u8 table_type[0x8];
7079 u8 reserved_at_88[0x18];
7080
7081 u8 reserved_at_a0[0x8];
7082 u8 table_id[0x18];
7083
7084 u8 reserved_at_c0[0x140];
7085 };
7086
7087 enum {
7088 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
7089 };
7090
7091 struct mlx5_ifc_modify_flow_table_out_bits {
7092 u8 status[0x8];
7093 u8 reserved_at_8[0x18];
7094
7095 u8 syndrome[0x20];
7096
7097 u8 reserved_at_40[0x40];
7098 };
7099
7100 struct mlx5_ifc_modify_flow_table_in_bits {
7101 u8 opcode[0x10];
7102 u8 reserved_at_10[0x10];
7103
7104 u8 reserved_at_20[0x10];
7105 u8 op_mod[0x10];
7106
7107 u8 reserved_at_40[0x20];
7108
7109 u8 reserved_at_60[0x10];
7110 u8 modify_field_select[0x10];
7111
7112 u8 table_type[0x8];
7113 u8 reserved_at_88[0x18];
7114
7115 u8 reserved_at_a0[0x8];
7116 u8 table_id[0x18];
7117
7118 u8 reserved_at_c0[0x4];
7119 u8 table_miss_mode[0x4];
7120 u8 reserved_at_c8[0x18];
7121
7122 u8 reserved_at_e0[0x8];
7123 u8 table_miss_id[0x18];
7124
7125 u8 reserved_at_100[0x100];
7126 };
7127
7128 struct mlx5_ifc_ets_tcn_config_reg_bits {
7129 u8 g[0x1];
7130 u8 b[0x1];
7131 u8 r[0x1];
7132 u8 reserved_at_3[0x9];
7133 u8 group[0x4];
7134 u8 reserved_at_10[0x9];
7135 u8 bw_allocation[0x7];
7136
7137 u8 reserved_at_20[0xc];
7138 u8 max_bw_units[0x4];
7139 u8 reserved_at_30[0x8];
7140 u8 max_bw_value[0x8];
7141 };
7142
7143 struct mlx5_ifc_ets_global_config_reg_bits {
7144 u8 reserved_at_0[0x2];
7145 u8 r[0x1];
7146 u8 reserved_at_3[0x1d];
7147
7148 u8 reserved_at_20[0xc];
7149 u8 max_bw_units[0x4];
7150 u8 reserved_at_30[0x8];
7151 u8 max_bw_value[0x8];
7152 };
7153
7154 struct mlx5_ifc_qetc_reg_bits {
7155 u8 reserved_at_0[0x8];
7156 u8 port_number[0x8];
7157 u8 reserved_at_10[0x30];
7158
7159 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
7160 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
7161 };
7162
7163 struct mlx5_ifc_qtct_reg_bits {
7164 u8 reserved_at_0[0x8];
7165 u8 port_number[0x8];
7166 u8 reserved_at_10[0xd];
7167 u8 prio[0x3];
7168
7169 u8 reserved_at_20[0x1d];
7170 u8 tclass[0x3];
7171 };
7172
7173 #endif /* MLX5_IFC_H */
Linux kernel - Deliverables
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