include/opcode/ChangeLog

   1 2009-04-15  Anthony Green  <green@moxielogic.com>
   2
   3         * moxie.h: Created.
   4
   5 2009-04-06  DJ Delorie  <dj@redhat.com>
   6
   7         * h8300.h: Add relaxation attributes to MOVA opcodes.
   8
   9 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
  10
  11         * ppc.h (ppc_parse_cpu): Declare.
  12
  13 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
  14
  15         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
  16         and _IMM11 for mbitclr and mbitset.
  17         * score-datadep.h: Update dependency information.
  18
  19 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
  20
  21         * ppc.h (PPC_OPCODE_POWER7): New.
  22
  23 2009-02-06  Doug Evans  <dje@google.com>
  24
  25         * i386.h: Add comment regarding sse* insns and prefixes.
  26
  27 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
  28
  29         * mips.h (INSN_XLR): Define.
  30         (INSN_CHIP_MASK): Update.
  31         (CPU_XLR): Define.
  32         (OPCODE_IS_MEMBER): Update.
  33         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
  34
  35 2009-01-28  Doug Evans  <dje@google.com>
  36
  37         * opcode/i386.h: Add multiple inclusion protection.
  38         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
  39         (EDI_REG_NUM): New macros.
  40         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
  41         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
  42         (REX_PREFIX_P): New macro.
  43
  44 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
  45
  46         * ppc.h (struct powerpc_opcode): New field "deprecated".
  47         (PPC_OPCODE_NOPOWER4): Delete.
  48
  49 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
  50
  51         * mips.h: Define CPU_R14000, CPU_R16000.
  52         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
  53
  54 2008-11-18  Catherine Moore  <clm@codesourcery.com>
  55
  56         * arm.h (FPU_NEON_FP16): New.
  57         (FPU_ARCH_NEON_FP16): New.
  58
  59 2008-11-06  Chao-ying Fu  <fu@mips.com>
  60
  61         * mips.h: Doucument '1' for 5-bit sync type.
  62
  63 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
  64
  65         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
  66         IA64_RS_CR.
  67
  68 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
  69
  70         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
  71
  72 2008-07-30  Michael J. Eager  <eager@eagercon.com>
  73
  74         * ppc.h (PPC_OPCODE_405): Define.
  75         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
  76
  77 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
  78
  79         * ppc.h (ppc_cpu_t): New typedef.
  80         (struct powerpc_opcode <flags>): Use it.
  81         (struct powerpc_operand <insert, extract>): Likewise.
  82         (struct powerpc_macro <flags>): Likewise.
  83
  84 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
  85
  86         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
  87         Update comment before MIPS16 field descriptors to mention MIPS16.
  88         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
  89         BBIT.
  90         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
  91         New bit masks and shift counts for cins and exts.
  92
  93         * mips.h: Document new field descriptors +Q.
  94         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
  95
  96 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
  97
  98         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
  99         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 100
 101 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 102
 103         * ppc.h: (PPC_OPCODE_E500MC): New.
 104
 105 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 106
 107         * i386.h (MAX_OPERANDS): Set to 5.
 108         (MAX_MNEM_SIZE): Changed to 20.
 109
 110 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 111
 112         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 113
 114 2008-03-09  Paul Brook  <paul@codesourcery.com>
 115
 116         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 117
 118 2008-03-04  Paul Brook  <paul@codesourcery.com>
 119
 120         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 121         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 122         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 123
 124 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 125             Nick Clifton  <nickc@redhat.com>
 126
 127         PR 3134
 128         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 129         with a 32-bit displacement but without the top bit of the 4th byte
 130         set.
 131
 132 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 133
 134         * cr16.h (cr16_num_optab): Declared.
 135
 136 2008-02-14  Hakan Ardo  <hakan@debian.org>
 137
 138         PR gas/2626
 139         * avr.h (AVR_ISA_2xxe): Define.
 140
 141 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 142
 143         * mips.h: Update copyright.
 144         (INSN_CHIP_MASK): New macro.
 145         (INSN_OCTEON): New macro.
 146         (CPU_OCTEON): New macro.
 147         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 148
 149 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 150
 151         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 152
 153 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 154
 155         * avr.h (AVR_ISA_USB162): Add new opcode set.
 156         (AVR_ISA_AVR3): Likewise.
 157
 158 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 159
 160         * mips.h (INSN_LOONGSON_2E): New.
 161         (INSN_LOONGSON_2F): New.
 162         (CPU_LOONGSON_2E): New.
 163         (CPU_LOONGSON_2F): New.
 164         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 165
 166 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 167
 168         * mips.h (INSN_ISA*): Redefine certain values as an
 169         enumeration.  Update comments.
 170         (mips_isa_table): New.
 171         (ISA_MIPS*): Redefine to match enumeration.
 172         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 173         values.
 174
 175 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 176
 177         * ppc.h (PPC_OPCODE_PPCPS): New.
 178
 179 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 180
 181         * m68k.h: Document j K & E.
 182
 183 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 184
 185         * cr16.h: New file for CR16 target.
 186
 187 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 188
 189         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 190
 191 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 192
 193         * m68k.h (mcfisa_c): New.
 194         (mcfusp, mcf_mask): Adjust.
 195
 196 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 197
 198         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 199         (num_powerpc_operands): Declare.
 200         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 201         (PPC_OPERAND_PLUS1): Define.
 202
 203 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 204
 205         * i386.h (REX_MODE64): Renamed to ...
 206         (REX_W): This.
 207         (REX_EXTX): Renamed to ...
 208         (REX_R): This.
 209         (REX_EXTY): Renamed to ...
 210         (REX_X): This.
 211         (REX_EXTZ): Renamed to ...
 212         (REX_B): This.
 213
 214 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 215
 216         * i386.h: Add entries from config/tc-i386.h and move tables
 217         to opcodes/i386-opc.h.
 218
 219 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 220
 221         * i386.h (FloatDR): Removed.
 222         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 223
 224 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 225
 226         * spu-insns.h: Add soma double-float insns.
 227
 228 2007-02-20  Thiemo Seufer  <ths@mips.com>
 229             Chao-Ying Fu  <fu@mips.com>
 230
 231         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 232         (INSN_DSPR2): Add flag for DSP R2 instructions.
 233         (M_BALIGN): New macro.
 234
 235 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 236
 237         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 238         and Seg3ShortFrom with Shortform.
 239
 240 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 241
 242         PR gas/4027
 243         * i386.h (i386_optab): Put the real "test" before the pseudo
 244         one.
 245
 246 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 247
 248         * m68k.h (m68010up): OR fido_a.
 249
 250 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 251
 252         * m68k.h (fido_a): New.
 253
 254 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 255
 256         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 257         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 258         values.
 259
 260 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 261
 262         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 263
 264 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 265
 266         * score-inst.h (enum score_insn_type): Add Insn_internal.
 267
 268 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 269             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 270             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 271             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 272             Alan Modra  <amodra@bigpond.net.au>
 273
 274         * spu-insns.h: New file.
 275         * spu.h: New file.
 276
 277 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 278
 279         * ppc.h (PPC_OPCODE_CELL): Define.
 280
 281 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 282
 283         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 284         in amdfam10 architecture.
 285
 286 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 287
 288         * i386.h: Replace CpuMNI with CpuSSSE3.
 289
 290 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 291             Joseph Myers  <joseph@codesourcery.com>
 292             Ian Lance Taylor  <ian@wasabisystems.com>
 293             Ben Elliston  <bje@wasabisystems.com>
 294
 295         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 296
 297 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 298
 299         * score-datadep.h: New file.
 300         * score-inst.h: New file.
 301
 302 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 303
 304         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 305         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 306         movdq2q and movq2dq.
 307
 308 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 309            Michael Meissner             <michael.meissner@amd.com>
 310
 311         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 312
 313 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 314
 315         * i386.h (i386_optab): Add "nop" with memory reference.
 316
 317 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 318
 319         * i386.h (i386_optab): Update comment for 64bit NOP.
 320
 321 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 322             Anton Blanchard  <anton@samba.org>
 323
 324         * ppc.h (PPC_OPCODE_POWER6): Define.
 325         Adjust whitespace.
 326
 327 2006-06-05  Thiemo Seufer  <ths@mips.com>
 328
 329         * mips.h: Improve description of MT flags.
 330
 331 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 332
 333         * m68k.h (mcf_mask): Define.
 334
 335 2006-05-05  Thiemo Seufer  <ths@mips.com>
 336             David Ung  <davidu@mips.com>
 337
 338         * mips.h (enum): Add macro M_CACHE_AB.
 339
 340 2006-05-04  Thiemo Seufer  <ths@mips.com>
 341             Nigel Stephens  <nigel@mips.com>
 342             David Ung  <davidu@mips.com>
 343
 344         * mips.h: Add INSN_SMARTMIPS define.
 345
 346 2006-04-30  Thiemo Seufer  <ths@mips.com>
 347             David Ung  <davidu@mips.com>
 348
 349         * mips.h: Defines udi bits and masks.  Add description of
 350         characters which may appear in the args field of udi
 351         instructions.
 352
 353 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 354
 355         * mips.h: Improve comments describing the bitfield instruction
 356         fields.
 357
 358 2006-04-26  Julian Brown  <julian@codesourcery.com>
 359
 360         * arm.h (FPU_VFP_EXT_V3): Define constant.
 361         (FPU_NEON_EXT_V1): Likewise.
 362         (FPU_VFP_HARD): Update.
 363         (FPU_VFP_V3): Define macro.
 364         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 365
 366 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 367
 368         * avr.h (AVR_ISA_PWMx): New.
 369
 370 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 371
 372         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 373         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 374         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 375         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 376         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 377
 378 2006-03-10  Paul Brook  <paul@codesourcery.com>
 379
 380         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 381
 382 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 383
 384         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 385         first.  Correct mask of bb "B" opcode.
 386
 387 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 388
 389         * i386.h (i386_optab): Support Intel Merom New Instructions.
 390
 391 2006-02-24  Paul Brook  <paul@codesourcery.com>
 392
 393         * arm.h: Add V7 feature bits.
 394
 395 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 396
 397         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 398
 399 2006-01-31  Paul Brook  <paul@codesourcery.com>
 400         Richard Earnshaw <rearnsha@arm.com>
 401
 402         * arm.h: Use ARM_CPU_FEATURE.
 403         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 404         (arm_feature_set): Change to a structure.
 405         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 406         ARM_FEATURE): New macros.
 407
 408 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 409
 410         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 411         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 412         (ADD_PC_INCR_OPCODE): Don't define.
 413
 414 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 415
 416         PR gas/1874
 417         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 418
 419 2005-11-14  David Ung  <davidu@mips.com>
 420
 421         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 422         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 423         save/restore encoding of the args field.
 424
 425 2005-10-28  Dave Brolley  <brolley@redhat.com>
 426
 427         Contribute the following changes:
 428         2005-02-16  Dave Brolley  <brolley@redhat.com>
 429
 430         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 431         cgen_isa_mask_* to cgen_bitset_*.
 432         * cgen.h: Likewise.
 433
 434         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 435
 436         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 437         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 438         (CGEN_CPU_TABLE): Make isas a ponter.
 439
 440         2003-09-29  Dave Brolley  <brolley@redhat.com>
 441
 442         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 443         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 444         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 445
 446         2002-12-13  Dave Brolley  <brolley@redhat.com>
 447
 448         * cgen.h (symcat.h): #include it.
 449         (cgen-bitset.h): #include it.
 450         (CGEN_ATTR_VALUE_TYPE): Now a union.
 451         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 452         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 453         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 454         * cgen-bitset.h: New file.
 455
 456 2005-09-30  Catherine Moore  <clm@cm00re.com>
 457
 458         * bfin.h: New file.
 459
 460 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 461
 462         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 463         indirect operands.
 464
 465 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 466
 467         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 468         Add FLAG_STRICT to pa10 ftest opcode.
 469
 470 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 471
 472         * hppa.h (pa_opcodes): Remove lha entries.
 473
 474 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 475
 476         * hppa.h (FLAG_STRICT): Revise comment.
 477         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 478         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 479         entries for "fdc".
 480
 481 2005-09-30  Catherine Moore  <clm@cm00re.com>
 482
 483         * bfin.h: New file.
 484
 485 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 486
 487         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 488
 489 2005-09-06  Chao-ying Fu  <fu@mips.com>
 490
 491         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 492         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 493         define.
 494         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 495         (INSN_ASE_MASK): Update to include INSN_MT.
 496         (INSN_MT): New define for MT ASE.
 497
 498 2005-08-25  Chao-ying Fu  <fu@mips.com>
 499
 500         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 501         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 502         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 503         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 504         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 505         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 506         instructions.
 507         (INSN_DSP): New define for DSP ASE.
 508
 509 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 510
 511         * a29k.h: Delete.
 512
 513 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 514
 515         * ppc.h (PPC_OPCODE_E300): Define.
 516
 517 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 518
 519         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 520
 521 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 522
 523         PR gas/336
 524         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 525         and pitlb.
 526
 527 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 528
 529         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 530         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 531         Add movq-s as 64-bit variants of movd-s.
 532
 533 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 534
 535         * hppa.h: Fix punctuation in comment.
 536
 537         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 538         implicit space-register addressing.  Set space-register bits on opcodes
 539         using implicit space-register addressing.  Add various missing pa20
 540         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 541         space-register addressing.  Use "fE" instead of "fe" in various
 542         fstw opcodes.
 543
 544 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 545
 546         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 547
 548 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 549
 550         * i386.h (i386_optab): Support Intel VMX Instructions.
 551
 552 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 553
 554         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 555
 556 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 557
 558         * i386.h (i386_optab): Add new insns.
 559
 560 2005-07-01  Nick Clifton  <nickc@redhat.com>
 561
 562         * sparc.h: Add typedefs to structure declarations.
 563
 564 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 565
 566         PR 1013
 567         * i386.h (i386_optab): Update comments for 64bit addressing on
 568         mov. Allow 64bit addressing for mov and movq.
 569
 570 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 571
 572         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 573         respectively, in various floating-point load and store patterns.
 574
 575 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 576
 577         * hppa.h (FLAG_STRICT): Correct comment.
 578         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 579         PA 2.0 mneumonics when equivalent.  Entries with cache control
 580         completers now require PA 1.1.  Adjust whitespace.
 581
 582 2005-05-19  Anton Blanchard  <anton@samba.org>
 583
 584         * ppc.h (PPC_OPCODE_POWER5): Define.
 585
 586 2005-05-10  Nick Clifton  <nickc@redhat.com>
 587
 588         * Update the address and phone number of the FSF organization in
 589         the GPL notices in the following files:
 590         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 591         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 592         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 593         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 594         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 595         tic54x.h, tic80.h, v850.h, vax.h
 596
 597 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 598
 599         * i386.h (i386_optab): Add ht and hnt.
 600
 601 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 602
 603         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 604         Add xcrypt-ctr.  Provide aliases without hyphens.
 605
 606 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 607
 608         Moved from ../ChangeLog
 609
 610         2005-04-12  Paul Brook  <paul@codesourcery.com>
 611         * m88k.h: Rename psr macros to avoid conflicts.
 612
 613         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 614         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 615         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 616         and ARM_ARCH_V6ZKT2.
 617
 618         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 619         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 620         Remove redundant instruction types.
 621         (struct argument): X_op - new field.
 622         (struct cst4_entry): Remove.
 623         (no_op_insn): Declare.
 624
 625         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 626         * crx.h (enum argtype): Rename types, remove unused types.
 627
 628         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 629         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 630         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 631         (enum operand_type): Rearrange operands, edit comments.
 632         replace us<N> with ui<N> for unsigned immediate.
 633         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 634         displacements (respectively).
 635         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 636         (instruction type): Add NO_TYPE_INS.
 637         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 638         (operand_entry): New field - 'flags'.
 639         (operand flags): New.
 640
 641         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 642         * crx.h (operand_type): Remove redundant types i3, i4,
 643         i5, i8, i12.
 644         Add new unsigned immediate types us3, us4, us5, us16.
 645
 646 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 647
 648         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 649         adjust them accordingly.
 650
 651 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 652
 653         * i386.h (i386_optab): Add rdtscp.
 654
 655 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 656
 657         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 658         between memory and segment register. Allow movq for moving between
 659         general-purpose register and segment register.
 660
 661 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 662
 663         PR gas/707
 664         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 665         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 666         fnstsw.
 667
 668 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 669
 670         * m68k.h (m68008, m68ec030, m68882): Remove.
 671         (m68k_mask): New.
 672         (cpu_m68k, cpu_cf): New.
 673         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 674         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 675
 676 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 677
 678         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 679         * cgen.h (enum cgen_parse_operand_type): Add
 680         CGEN_PARSE_OPERAND_SYMBOLIC.
 681
 682 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 683
 684         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 685         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 686         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 687
 688 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 689
 690         * mips.h (struct mips_opcode): Add new pinfo2 member.
 691         (INSN_ALIAS): New define for opcode table entries that are
 692         specific instances of another entry, such as 'move' for an 'or'
 693         with a zero operand.
 694         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 695         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 696
 697 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 698
 699         * mips.h (CPU_RM9000): Define.
 700         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 701
 702 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 703
 704         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 705         to/from test registers are illegal in 64-bit mode. Add missing
 706         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 707         (previously one had to explicitly encode a rex64 prefix). Re-enable
 708         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 709         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 710
 711 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 712
 713         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 714         available only with SSE2. Change the MMX additions introduced by SSE
 715         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 716         instructions by their now designated identifier (since combining i686
 717         and 3DNow! does not really imply 3DNow!A).
 718
 719 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 720
 721         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 722         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 723
 724 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 725             Vineet Sharma      <vineets@noida.hcltech.com>
 726
 727         * maxq.h: New file: Disassembly information for the maxq port.
 728
 729 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 730
 731         * i386.h (i386_optab): Put back "movzb".
 732
 733 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 734
 735         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 736         comments.  Remove member cris_ver_sim.  Add members
 737         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 738         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 739         (struct cris_support_reg, struct cris_cond15): New types.
 740         (cris_conds15): Declare.
 741         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 742         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 743         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 744         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 745         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 746         SIZE_FIELD_UNSIGNED.
 747
 748 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 749
 750         * i386.h (sldx_Suf): Remove.
 751         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 752         (q_FP): Define, implying no REX64.
 753         (x_FP, sl_FP): Imply FloatMF.
 754         (i386_optab): Split reg and mem forms of moving from segment registers
 755         so that the memory forms can ignore the 16-/32-bit operand size
 756         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 757         all non-floating-point instructions. Unite 32- and 64-bit forms of
 758         movsx, movzx, and movd. Adjust floating point operations for the above
 759         changes to the *FP macros. Add DefaultSize to floating point control
 760         insns operating on larger memory ranges. Remove left over comments
 761         hinting at certain insns being Intel-syntax ones where the ones
 762         actually meant are already gone.
 763
 764 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 765
 766         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 767         instruction type.
 768
 769 2004-09-30  Paul Brook  <paul@codesourcery.com>
 770
 771         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 772         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 773
 774 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 775
 776         * avr.h: Add support for
 777         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 778
 779 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 780
 781         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 782
 783 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 784
 785         * msp430.h (msp430_opc): Add new instructions.
 786         (msp430_rcodes): Declare new instructions.
 787         (msp430_hcodes): Likewise..
 788
 789 2004-08-13  Nick Clifton  <nickc@redhat.com>
 790
 791         PR/301
 792         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 793         processors.
 794
 795 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 796
 797         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 798
 799 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 800
 801         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 802
 803 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 804
 805         * i386.h: Adjust instruction descriptions to better match the
 806         specification.
 807
 808 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 809
 810         * arm.h: Remove all old content.  Replace with architecture defines
 811         from gas/config/tc-arm.c.
 812
 813 2004-07-09  Andreas Schwab  <schwab@suse.de>
 814
 815         * m68k.h: Fix comment.
 816
 817 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 818
 819         * crx.h: New file.
 820
 821 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 822
 823         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 824
 825 2004-05-24  Peter Barada  <peter@the-baradas.com>
 826
 827         * m68k.h: Add 'size' to m68k_opcode.
 828
 829 2004-05-05  Peter Barada  <peter@the-baradas.com>
 830
 831         * m68k.h: Switch from ColdFire chip name to core variant.
 832
 833 2004-04-22  Peter Barada  <peter@the-baradas.com>
 834
 835         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 836         descriptions for new EMAC cases.
 837         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 838         handle Motorola MAC syntax.
 839         Allow disassembly of ColdFire V4e object files.
 840
 841 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 842
 843         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 844
 845 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 846
 847         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 848
 849 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 850
 851         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 852
 853 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 854
 855         * i386.h (i386_optab): Added xstore/xcrypt insns.
 856
 857 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 858
 859         * h8300.h (32bit ldc/stc): Add relaxing support.
 860
 861 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 862
 863         * h8300.h (BITOP): Pass MEMRELAX flag.
 864
 865 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 866
 867         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 868         except for the H8S.
 869
 870 For older changes see ChangeLog-9103
 871 \f
 872 Local Variables:
 873 mode: change-log
 874 left-margin: 8
 875 fill-column: 74
 876 version-control: never
 877 End: