include/opcode/ChangeLog

   1 2009-06-11  Anthony Green  <green@moxielogic.com>
   2
   3         * moxie.h (MOXIE_F3_PCREL): Define.
   4         (moxie_form3_opc_info): Grow.
   5
   6 2009-06-06  Anthony Green  <green@moxielogic.com>
   7
   8         * moxie.h (MOXIE_F1_M): Define.
   9
  10 2009-04-15  Anthony Green  <green@moxielogic.com>
  11
  12         * moxie.h: Created.
  13
  14 2009-04-06  DJ Delorie  <dj@redhat.com>
  15
  16         * h8300.h: Add relaxation attributes to MOVA opcodes.
  17
  18 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
  19
  20         * ppc.h (ppc_parse_cpu): Declare.
  21
  22 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
  23
  24         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
  25         and _IMM11 for mbitclr and mbitset.
  26         * score-datadep.h: Update dependency information.
  27
  28 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
  29
  30         * ppc.h (PPC_OPCODE_POWER7): New.
  31
  32 2009-02-06  Doug Evans  <dje@google.com>
  33
  34         * i386.h: Add comment regarding sse* insns and prefixes.
  35
  36 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
  37
  38         * mips.h (INSN_XLR): Define.
  39         (INSN_CHIP_MASK): Update.
  40         (CPU_XLR): Define.
  41         (OPCODE_IS_MEMBER): Update.
  42         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
  43
  44 2009-01-28  Doug Evans  <dje@google.com>
  45
  46         * opcode/i386.h: Add multiple inclusion protection.
  47         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
  48         (EDI_REG_NUM): New macros.
  49         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
  50         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
  51         (REX_PREFIX_P): New macro.
  52
  53 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
  54
  55         * ppc.h (struct powerpc_opcode): New field "deprecated".
  56         (PPC_OPCODE_NOPOWER4): Delete.
  57
  58 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
  59
  60         * mips.h: Define CPU_R14000, CPU_R16000.
  61         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
  62
  63 2008-11-18  Catherine Moore  <clm@codesourcery.com>
  64
  65         * arm.h (FPU_NEON_FP16): New.
  66         (FPU_ARCH_NEON_FP16): New.
  67
  68 2008-11-06  Chao-ying Fu  <fu@mips.com>
  69
  70         * mips.h: Doucument '1' for 5-bit sync type.
  71
  72 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
  73
  74         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
  75         IA64_RS_CR.
  76
  77 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
  78
  79         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
  80
  81 2008-07-30  Michael J. Eager  <eager@eagercon.com>
  82
  83         * ppc.h (PPC_OPCODE_405): Define.
  84         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
  85
  86 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
  87
  88         * ppc.h (ppc_cpu_t): New typedef.
  89         (struct powerpc_opcode <flags>): Use it.
  90         (struct powerpc_operand <insert, extract>): Likewise.
  91         (struct powerpc_macro <flags>): Likewise.
  92
  93 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
  94
  95         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
  96         Update comment before MIPS16 field descriptors to mention MIPS16.
  97         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
  98         BBIT.
  99         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 100         New bit masks and shift counts for cins and exts.
 101
 102         * mips.h: Document new field descriptors +Q.
 103         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 104
 105 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 106
 107         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 108         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 109
 110 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 111
 112         * ppc.h: (PPC_OPCODE_E500MC): New.
 113
 114 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 115
 116         * i386.h (MAX_OPERANDS): Set to 5.
 117         (MAX_MNEM_SIZE): Changed to 20.
 118
 119 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 120
 121         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 122
 123 2008-03-09  Paul Brook  <paul@codesourcery.com>
 124
 125         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 126
 127 2008-03-04  Paul Brook  <paul@codesourcery.com>
 128
 129         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 130         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 131         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 132
 133 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 134             Nick Clifton  <nickc@redhat.com>
 135
 136         PR 3134
 137         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 138         with a 32-bit displacement but without the top bit of the 4th byte
 139         set.
 140
 141 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 142
 143         * cr16.h (cr16_num_optab): Declared.
 144
 145 2008-02-14  Hakan Ardo  <hakan@debian.org>
 146
 147         PR gas/2626
 148         * avr.h (AVR_ISA_2xxe): Define.
 149
 150 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 151
 152         * mips.h: Update copyright.
 153         (INSN_CHIP_MASK): New macro.
 154         (INSN_OCTEON): New macro.
 155         (CPU_OCTEON): New macro.
 156         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 157
 158 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 159
 160         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 161
 162 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 163
 164         * avr.h (AVR_ISA_USB162): Add new opcode set.
 165         (AVR_ISA_AVR3): Likewise.
 166
 167 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 168
 169         * mips.h (INSN_LOONGSON_2E): New.
 170         (INSN_LOONGSON_2F): New.
 171         (CPU_LOONGSON_2E): New.
 172         (CPU_LOONGSON_2F): New.
 173         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 174
 175 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 176
 177         * mips.h (INSN_ISA*): Redefine certain values as an
 178         enumeration.  Update comments.
 179         (mips_isa_table): New.
 180         (ISA_MIPS*): Redefine to match enumeration.
 181         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 182         values.
 183
 184 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 185
 186         * ppc.h (PPC_OPCODE_PPCPS): New.
 187
 188 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 189
 190         * m68k.h: Document j K & E.
 191
 192 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 193
 194         * cr16.h: New file for CR16 target.
 195
 196 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 197
 198         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 199
 200 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 201
 202         * m68k.h (mcfisa_c): New.
 203         (mcfusp, mcf_mask): Adjust.
 204
 205 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 206
 207         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 208         (num_powerpc_operands): Declare.
 209         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 210         (PPC_OPERAND_PLUS1): Define.
 211
 212 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 213
 214         * i386.h (REX_MODE64): Renamed to ...
 215         (REX_W): This.
 216         (REX_EXTX): Renamed to ...
 217         (REX_R): This.
 218         (REX_EXTY): Renamed to ...
 219         (REX_X): This.
 220         (REX_EXTZ): Renamed to ...
 221         (REX_B): This.
 222
 223 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 224
 225         * i386.h: Add entries from config/tc-i386.h and move tables
 226         to opcodes/i386-opc.h.
 227
 228 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 229
 230         * i386.h (FloatDR): Removed.
 231         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 232
 233 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 234
 235         * spu-insns.h: Add soma double-float insns.
 236
 237 2007-02-20  Thiemo Seufer  <ths@mips.com>
 238             Chao-Ying Fu  <fu@mips.com>
 239
 240         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 241         (INSN_DSPR2): Add flag for DSP R2 instructions.
 242         (M_BALIGN): New macro.
 243
 244 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 245
 246         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 247         and Seg3ShortFrom with Shortform.
 248
 249 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 250
 251         PR gas/4027
 252         * i386.h (i386_optab): Put the real "test" before the pseudo
 253         one.
 254
 255 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 256
 257         * m68k.h (m68010up): OR fido_a.
 258
 259 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 260
 261         * m68k.h (fido_a): New.
 262
 263 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 264
 265         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 266         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 267         values.
 268
 269 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 270
 271         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 272
 273 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 274
 275         * score-inst.h (enum score_insn_type): Add Insn_internal.
 276
 277 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 278             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 279             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 280             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 281             Alan Modra  <amodra@bigpond.net.au>
 282
 283         * spu-insns.h: New file.
 284         * spu.h: New file.
 285
 286 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 287
 288         * ppc.h (PPC_OPCODE_CELL): Define.
 289
 290 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 291
 292         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 293         in amdfam10 architecture.
 294
 295 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 296
 297         * i386.h: Replace CpuMNI with CpuSSSE3.
 298
 299 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 300             Joseph Myers  <joseph@codesourcery.com>
 301             Ian Lance Taylor  <ian@wasabisystems.com>
 302             Ben Elliston  <bje@wasabisystems.com>
 303
 304         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 305
 306 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 307
 308         * score-datadep.h: New file.
 309         * score-inst.h: New file.
 310
 311 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 312
 313         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 314         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 315         movdq2q and movq2dq.
 316
 317 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 318            Michael Meissner             <michael.meissner@amd.com>
 319
 320         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 321
 322 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 323
 324         * i386.h (i386_optab): Add "nop" with memory reference.
 325
 326 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 327
 328         * i386.h (i386_optab): Update comment for 64bit NOP.
 329
 330 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 331             Anton Blanchard  <anton@samba.org>
 332
 333         * ppc.h (PPC_OPCODE_POWER6): Define.
 334         Adjust whitespace.
 335
 336 2006-06-05  Thiemo Seufer  <ths@mips.com>
 337
 338         * mips.h: Improve description of MT flags.
 339
 340 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 341
 342         * m68k.h (mcf_mask): Define.
 343
 344 2006-05-05  Thiemo Seufer  <ths@mips.com>
 345             David Ung  <davidu@mips.com>
 346
 347         * mips.h (enum): Add macro M_CACHE_AB.
 348
 349 2006-05-04  Thiemo Seufer  <ths@mips.com>
 350             Nigel Stephens  <nigel@mips.com>
 351             David Ung  <davidu@mips.com>
 352
 353         * mips.h: Add INSN_SMARTMIPS define.
 354
 355 2006-04-30  Thiemo Seufer  <ths@mips.com>
 356             David Ung  <davidu@mips.com>
 357
 358         * mips.h: Defines udi bits and masks.  Add description of
 359         characters which may appear in the args field of udi
 360         instructions.
 361
 362 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 363
 364         * mips.h: Improve comments describing the bitfield instruction
 365         fields.
 366
 367 2006-04-26  Julian Brown  <julian@codesourcery.com>
 368
 369         * arm.h (FPU_VFP_EXT_V3): Define constant.
 370         (FPU_NEON_EXT_V1): Likewise.
 371         (FPU_VFP_HARD): Update.
 372         (FPU_VFP_V3): Define macro.
 373         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 374
 375 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 376
 377         * avr.h (AVR_ISA_PWMx): New.
 378
 379 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 380
 381         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 382         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 383         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 384         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 385         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 386
 387 2006-03-10  Paul Brook  <paul@codesourcery.com>
 388
 389         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 390
 391 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 392
 393         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 394         first.  Correct mask of bb "B" opcode.
 395
 396 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 397
 398         * i386.h (i386_optab): Support Intel Merom New Instructions.
 399
 400 2006-02-24  Paul Brook  <paul@codesourcery.com>
 401
 402         * arm.h: Add V7 feature bits.
 403
 404 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 405
 406         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 407
 408 2006-01-31  Paul Brook  <paul@codesourcery.com>
 409         Richard Earnshaw <rearnsha@arm.com>
 410
 411         * arm.h: Use ARM_CPU_FEATURE.
 412         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 413         (arm_feature_set): Change to a structure.
 414         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 415         ARM_FEATURE): New macros.
 416
 417 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 418
 419         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 420         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 421         (ADD_PC_INCR_OPCODE): Don't define.
 422
 423 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 424
 425         PR gas/1874
 426         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 427
 428 2005-11-14  David Ung  <davidu@mips.com>
 429
 430         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 431         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 432         save/restore encoding of the args field.
 433
 434 2005-10-28  Dave Brolley  <brolley@redhat.com>
 435
 436         Contribute the following changes:
 437         2005-02-16  Dave Brolley  <brolley@redhat.com>
 438
 439         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 440         cgen_isa_mask_* to cgen_bitset_*.
 441         * cgen.h: Likewise.
 442
 443         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 444
 445         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 446         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 447         (CGEN_CPU_TABLE): Make isas a ponter.
 448
 449         2003-09-29  Dave Brolley  <brolley@redhat.com>
 450
 451         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 452         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 453         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 454
 455         2002-12-13  Dave Brolley  <brolley@redhat.com>
 456
 457         * cgen.h (symcat.h): #include it.
 458         (cgen-bitset.h): #include it.
 459         (CGEN_ATTR_VALUE_TYPE): Now a union.
 460         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 461         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 462         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 463         * cgen-bitset.h: New file.
 464
 465 2005-09-30  Catherine Moore  <clm@cm00re.com>
 466
 467         * bfin.h: New file.
 468
 469 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 470
 471         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 472         indirect operands.
 473
 474 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 475
 476         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 477         Add FLAG_STRICT to pa10 ftest opcode.
 478
 479 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 480
 481         * hppa.h (pa_opcodes): Remove lha entries.
 482
 483 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 484
 485         * hppa.h (FLAG_STRICT): Revise comment.
 486         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 487         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 488         entries for "fdc".
 489
 490 2005-09-30  Catherine Moore  <clm@cm00re.com>
 491
 492         * bfin.h: New file.
 493
 494 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 495
 496         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 497
 498 2005-09-06  Chao-ying Fu  <fu@mips.com>
 499
 500         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 501         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 502         define.
 503         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 504         (INSN_ASE_MASK): Update to include INSN_MT.
 505         (INSN_MT): New define for MT ASE.
 506
 507 2005-08-25  Chao-ying Fu  <fu@mips.com>
 508
 509         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 510         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 511         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 512         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 513         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 514         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 515         instructions.
 516         (INSN_DSP): New define for DSP ASE.
 517
 518 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 519
 520         * a29k.h: Delete.
 521
 522 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 523
 524         * ppc.h (PPC_OPCODE_E300): Define.
 525
 526 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 527
 528         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 529
 530 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 531
 532         PR gas/336
 533         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 534         and pitlb.
 535
 536 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 537
 538         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 539         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 540         Add movq-s as 64-bit variants of movd-s.
 541
 542 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 543
 544         * hppa.h: Fix punctuation in comment.
 545
 546         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 547         implicit space-register addressing.  Set space-register bits on opcodes
 548         using implicit space-register addressing.  Add various missing pa20
 549         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 550         space-register addressing.  Use "fE" instead of "fe" in various
 551         fstw opcodes.
 552
 553 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 554
 555         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 556
 557 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 558
 559         * i386.h (i386_optab): Support Intel VMX Instructions.
 560
 561 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 562
 563         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 564
 565 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 566
 567         * i386.h (i386_optab): Add new insns.
 568
 569 2005-07-01  Nick Clifton  <nickc@redhat.com>
 570
 571         * sparc.h: Add typedefs to structure declarations.
 572
 573 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 574
 575         PR 1013
 576         * i386.h (i386_optab): Update comments for 64bit addressing on
 577         mov. Allow 64bit addressing for mov and movq.
 578
 579 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 580
 581         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 582         respectively, in various floating-point load and store patterns.
 583
 584 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 585
 586         * hppa.h (FLAG_STRICT): Correct comment.
 587         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 588         PA 2.0 mneumonics when equivalent.  Entries with cache control
 589         completers now require PA 1.1.  Adjust whitespace.
 590
 591 2005-05-19  Anton Blanchard  <anton@samba.org>
 592
 593         * ppc.h (PPC_OPCODE_POWER5): Define.
 594
 595 2005-05-10  Nick Clifton  <nickc@redhat.com>
 596
 597         * Update the address and phone number of the FSF organization in
 598         the GPL notices in the following files:
 599         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 600         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 601         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 602         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 603         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 604         tic54x.h, tic80.h, v850.h, vax.h
 605
 606 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 607
 608         * i386.h (i386_optab): Add ht and hnt.
 609
 610 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 611
 612         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 613         Add xcrypt-ctr.  Provide aliases without hyphens.
 614
 615 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 616
 617         Moved from ../ChangeLog
 618
 619         2005-04-12  Paul Brook  <paul@codesourcery.com>
 620         * m88k.h: Rename psr macros to avoid conflicts.
 621
 622         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 623         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 624         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 625         and ARM_ARCH_V6ZKT2.
 626
 627         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 628         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 629         Remove redundant instruction types.
 630         (struct argument): X_op - new field.
 631         (struct cst4_entry): Remove.
 632         (no_op_insn): Declare.
 633
 634         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 635         * crx.h (enum argtype): Rename types, remove unused types.
 636
 637         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 638         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 639         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 640         (enum operand_type): Rearrange operands, edit comments.
 641         replace us<N> with ui<N> for unsigned immediate.
 642         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 643         displacements (respectively).
 644         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 645         (instruction type): Add NO_TYPE_INS.
 646         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 647         (operand_entry): New field - 'flags'.
 648         (operand flags): New.
 649
 650         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 651         * crx.h (operand_type): Remove redundant types i3, i4,
 652         i5, i8, i12.
 653         Add new unsigned immediate types us3, us4, us5, us16.
 654
 655 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 656
 657         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 658         adjust them accordingly.
 659
 660 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 661
 662         * i386.h (i386_optab): Add rdtscp.
 663
 664 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 665
 666         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 667         between memory and segment register. Allow movq for moving between
 668         general-purpose register and segment register.
 669
 670 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 671
 672         PR gas/707
 673         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 674         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 675         fnstsw.
 676
 677 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 678
 679         * m68k.h (m68008, m68ec030, m68882): Remove.
 680         (m68k_mask): New.
 681         (cpu_m68k, cpu_cf): New.
 682         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 683         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 684
 685 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 686
 687         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 688         * cgen.h (enum cgen_parse_operand_type): Add
 689         CGEN_PARSE_OPERAND_SYMBOLIC.
 690
 691 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 692
 693         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 694         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 695         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 696
 697 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 698
 699         * mips.h (struct mips_opcode): Add new pinfo2 member.
 700         (INSN_ALIAS): New define for opcode table entries that are
 701         specific instances of another entry, such as 'move' for an 'or'
 702         with a zero operand.
 703         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 704         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 705
 706 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 707
 708         * mips.h (CPU_RM9000): Define.
 709         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 710
 711 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 712
 713         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 714         to/from test registers are illegal in 64-bit mode. Add missing
 715         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 716         (previously one had to explicitly encode a rex64 prefix). Re-enable
 717         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 718         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 719
 720 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 721
 722         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 723         available only with SSE2. Change the MMX additions introduced by SSE
 724         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 725         instructions by their now designated identifier (since combining i686
 726         and 3DNow! does not really imply 3DNow!A).
 727
 728 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 729
 730         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 731         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 732
 733 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 734             Vineet Sharma      <vineets@noida.hcltech.com>
 735
 736         * maxq.h: New file: Disassembly information for the maxq port.
 737
 738 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 739
 740         * i386.h (i386_optab): Put back "movzb".
 741
 742 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 743
 744         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 745         comments.  Remove member cris_ver_sim.  Add members
 746         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 747         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 748         (struct cris_support_reg, struct cris_cond15): New types.
 749         (cris_conds15): Declare.
 750         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 751         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 752         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 753         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 754         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 755         SIZE_FIELD_UNSIGNED.
 756
 757 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 758
 759         * i386.h (sldx_Suf): Remove.
 760         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 761         (q_FP): Define, implying no REX64.
 762         (x_FP, sl_FP): Imply FloatMF.
 763         (i386_optab): Split reg and mem forms of moving from segment registers
 764         so that the memory forms can ignore the 16-/32-bit operand size
 765         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 766         all non-floating-point instructions. Unite 32- and 64-bit forms of
 767         movsx, movzx, and movd. Adjust floating point operations for the above
 768         changes to the *FP macros. Add DefaultSize to floating point control
 769         insns operating on larger memory ranges. Remove left over comments
 770         hinting at certain insns being Intel-syntax ones where the ones
 771         actually meant are already gone.
 772
 773 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 774
 775         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 776         instruction type.
 777
 778 2004-09-30  Paul Brook  <paul@codesourcery.com>
 779
 780         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 781         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 782
 783 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 784
 785         * avr.h: Add support for
 786         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 787
 788 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 789
 790         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 791
 792 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 793
 794         * msp430.h (msp430_opc): Add new instructions.
 795         (msp430_rcodes): Declare new instructions.
 796         (msp430_hcodes): Likewise..
 797
 798 2004-08-13  Nick Clifton  <nickc@redhat.com>
 799
 800         PR/301
 801         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 802         processors.
 803
 804 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 805
 806         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 807
 808 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 809
 810         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 811
 812 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 813
 814         * i386.h: Adjust instruction descriptions to better match the
 815         specification.
 816
 817 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 818
 819         * arm.h: Remove all old content.  Replace with architecture defines
 820         from gas/config/tc-arm.c.
 821
 822 2004-07-09  Andreas Schwab  <schwab@suse.de>
 823
 824         * m68k.h: Fix comment.
 825
 826 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 827
 828         * crx.h: New file.
 829
 830 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 831
 832         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 833
 834 2004-05-24  Peter Barada  <peter@the-baradas.com>
 835
 836         * m68k.h: Add 'size' to m68k_opcode.
 837
 838 2004-05-05  Peter Barada  <peter@the-baradas.com>
 839
 840         * m68k.h: Switch from ColdFire chip name to core variant.
 841
 842 2004-04-22  Peter Barada  <peter@the-baradas.com>
 843
 844         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 845         descriptions for new EMAC cases.
 846         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 847         handle Motorola MAC syntax.
 848         Allow disassembly of ColdFire V4e object files.
 849
 850 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 851
 852         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 853
 854 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 855
 856         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 857
 858 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 859
 860         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 861
 862 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 863
 864         * i386.h (i386_optab): Added xstore/xcrypt insns.
 865
 866 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 867
 868         * h8300.h (32bit ldc/stc): Add relaxing support.
 869
 870 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 871
 872         * h8300.h (BITOP): Pass MEMRELAX flag.
 873
 874 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 875
 876         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 877         except for the H8S.
 878
 879 For older changes see ChangeLog-9103
 880 \f
 881 Local Variables:
 882 mode: change-log
 883 left-margin: 8
 884 fill-column: 74
 885 version-control: never
 886 End: