1 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
3 * aarch64.h (enum aarch64_opnd_qualifier): Add
6 2015-12-14 Yoshinori Sato <ysato@users.sourceforge.jp>
8 * rx.h: Add new instructions.
10 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
12 * aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB.
13 * aarch64-asm-2.c: Regenerate.
14 * aarch64-dis-2.c: Regenerate.
15 * aarch64-opc-2.c: Regenerate.
16 * aarch64-opc.c (aarch64_hint_options): Add "csync".
17 (aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB.
18 * aarch64-tbl.h (aarch64_feature_stat_profile): New.
20 (aarch64_opcode_table): Add "psb".
21 (AARCH64_OPERANDS): Add "BARRIER_PSB".
23 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
25 * aarch64.h (aarch64_hint_options): Declare.
26 (aarch64_opnd_info): Add field hint_option.
28 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
30 * aarch64.h (AARCH64_FEATURE_PROFILE): New.
32 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
34 * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.
36 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
38 * aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
39 (aarch64_sys_ins_reg_has_xt): Declare.
41 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
43 * aarch64.h (AARCH64_FEATURE_RAS): New.
44 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.
46 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
48 * aarch64.h (AARCH64_FEATURE_F16): Fix clash with
50 (AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC.
51 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and
54 2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
56 * arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32].
58 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
60 * aarch64.h (aarch64_op): Add OP_BFC.
62 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
64 * aarch64.h (AARCH64_FEATURE_F16): New.
65 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2
68 2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
70 * aarch64.h (AARCH64_FEATURE_V8_1): New.
71 (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.
73 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
75 * arm.h (ARM_EXT2_V8_2A): New.
76 (ARM_ARCH_V8_2A): New.
78 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
80 * aarch64.h (AARCH64_FEATURE_V8_2): New.
81 (AARCH64_ARCH_V8_2): New.
83 2015-11-11 Alan Modra <amodra@gmail.com>
84 Peter Bergner <bergner@vnet.ibm.com>
86 * ppc.h (PPC_OPCODE_POWER9): New define.
87 (PPC_OPCODE_VSX3): Likewise.
89 2015-11-02 Nick Clifton <nickc@redhat.com>
91 * rx.h (enum RX_Opcode_ID): Add more NOP opcodes.
93 2015-11-02 Nick Clifton <nickc@redhat.com>
95 * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
97 2015-10-28 Yao Qi <yao.qi@linaro.org>
99 * aarch64.h (aarch64_decode_insn): Update declaration.
101 2015-10-07 Yao Qi <yao.qi@linaro.org>
103 * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
106 2015-10-07 Yao Qi <yao.qi@linaro.org>
108 * aarch64.h [__cplusplus]: Wrap in extern "C".
110 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
111 Cupertino Miranda <cmiranda@synopsys.com>
113 * arc-func.h: New file.
116 2015-10-02 Yao Qi <yao.qi@linaro.org>
118 * aarch64.h (aarch64_zero_register_p): Move the declaration
121 2015-10-02 Yao Qi <yao.qi@linaro.org>
123 * aarch64.h (aarch64_decode_insn): Declare it.
125 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
127 * s390.h (S390_INSTR_FLAG_HTM): New flag.
128 (S390_INSTR_FLAG_VX): New flag.
129 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
131 2015-09-23 Nick Clifton <nickc@redhat.com>
133 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
136 2015-09-22 Nick Clifton <nickc@redhat.com>
138 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
140 2015-09-09 Daniel Santos <daniel.santos@pobox.com>
142 * visium.h (gen_reg_table): Make static.
143 (fp_reg_table): Likewise.
144 (cc_table): Likewise.
146 2015-07-20 Matthew Wahab <matthew.wahab@arm.com>
148 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
149 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
150 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
151 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
153 2015-07-03 Alan Modra <amodra@gmail.com>
155 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
157 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
158 Cesar Philippidis <cesar@codesourcery.com>
160 * nios2.h (enum iw_format_type): Add R2 formats.
161 (enum overflow_type): Add signed_immed12_overflow and
162 enumeration_overflow for R2.
163 (struct nios2_opcode): Document new argument letters for R2.
164 (REG_3BIT, REG_LDWM, REG_POP): Define.
165 (includes): Include nios2r2.h.
166 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
167 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
168 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
169 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
170 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
171 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
173 * nios2r2.h: New file.
175 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
177 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
178 (ppc_optional_operand_value): New inline function.
180 2015-06-04 Matthew Wahab <matthew.wahab@arm.com>
182 * aarch64.h (AARCH64_V8_1): New.
184 2015-06-03 Matthew Wahab <matthew.wahab@arm.com>
186 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
187 (ARM_ARCH_V8_1A): New.
188 (ARM_ARCH_V8_1A_FP): New.
189 (ARM_ARCH_V8_1A_SIMD): New.
190 (ARM_ARCH_V8_1A_CRYPTOV1): New.
191 (ARM_FEATURE_CORE): New.
193 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
195 * arm.h (ARM_EXT2_PAN): New.
196 (ARM_FEATURE_CORE_HIGH): New.
198 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
200 * arm.h (ARM_FEATURE_ALL): New.
202 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
204 * aarch64.h (AARCH64_FEATURE_RDMA): New.
206 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
208 * aarch64.h (AARCH64_FEATURE_LOR): New.
210 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
212 * aarch64.h (AARCH64_FEATURE_PAN): New.
213 (aarch64_sys_reg_supported_p): Declare.
214 (aarch64_pstatefield_supported_p): Declare.
216 2015-04-30 DJ Delorie <dj@redhat.com>
218 * rl78.h (RL78_Dis_Isa): New.
219 (rl78_decode_opcode): Add ISA parameter.
221 2015-03-24 Terry Guo <terry.guo@arm.com>
223 * arm.h (arm_feature_set): Extended to provide more available bits.
224 (ARM_ANY): Updated to follow above new definition.
225 (ARM_CPU_HAS_FEATURE): Likewise.
226 (ARM_CPU_IS_ANY): Likewise.
227 (ARM_MERGE_FEATURE_SETS): Likewise.
228 (ARM_CLEAR_FEATURE): Likewise.
229 (ARM_FEATURE): Likewise.
230 (ARM_FEATURE_COPY): New macro.
231 (ARM_FEATURE_EQUAL): Likewise.
232 (ARM_FEATURE_ZERO): Likewise.
233 (ARM_FEATURE_CORE_EQUAL): Likewise.
234 (ARM_FEATURE_LOW): Likewise.
235 (ARM_FEATURE_CORE_LOW): Likewise.
236 (ARM_FEATURE_CORE_COPROC): Likewise.
238 2015-02-19 Pedro Alves <palves@redhat.com>
240 * cgen.h [__cplusplus]: Wrap in extern "C".
241 * msp430-decode.h [__cplusplus]: Likewise.
242 * nios2.h [__cplusplus]: Likewise.
243 * rl78.h [__cplusplus]: Likewise.
244 * rx.h [__cplusplus]: Likewise.
245 * tilegx.h [__cplusplus]: Likewise.
247 2015-01-28 James Bowman <james.bowman@ftdichip.com>
251 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
253 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
255 2015-01-01 Alan Modra <amodra@gmail.com>
257 Update year range in copyright notice of all files.
259 2014-12-27 Anthony Green <green@moxielogic.com>
261 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
262 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
264 2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
266 * visium.h: New file.
268 2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
270 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
271 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
272 (NIOS2_INSN_OPTARG): Renumber.
274 2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
276 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
277 declaration. Fix obsolete comment.
279 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
281 * nios2.h (enum iw_format_type): New.
282 (struct nios2_opcode): Update comments. Add size and format fields.
283 (NIOS2_INSN_OPTARG): New.
284 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
285 (struct nios2_reg): Add regtype field.
286 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
287 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
288 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
289 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
290 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
291 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
292 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
293 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
294 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
295 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
296 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
297 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
298 (OP_MASK_OP, OP_SH_OP): Delete.
299 (OP_MASK_IOP, OP_SH_IOP): Delete.
300 (OP_MASK_IRD, OP_SH_IRD): Delete.
301 (OP_MASK_IRT, OP_SH_IRT): Delete.
302 (OP_MASK_IRS, OP_SH_IRS): Delete.
303 (OP_MASK_ROP, OP_SH_ROP): Delete.
304 (OP_MASK_RRD, OP_SH_RRD): Delete.
305 (OP_MASK_RRT, OP_SH_RRT): Delete.
306 (OP_MASK_RRS, OP_SH_RRS): Delete.
307 (OP_MASK_JOP, OP_SH_JOP): Delete.
308 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
309 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
310 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
311 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
312 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
313 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
314 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
315 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
316 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
317 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
318 (OP_MASK_<insn>, OP_MASK): Delete.
319 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
320 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
321 Include nios2r1.h to define new instruction opcode constants
323 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
324 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
325 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
326 (NUMOPCODES, NUMREGISTERS): Delete.
327 * nios2r1.h: New file.
329 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
331 * sparc.h (HWCAP2_VIS3B): Documentation improved.
333 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
335 * sparc.h (sparc_opcode): new field `hwcaps2'.
336 (HWCAP2_FJATHPLUS): New define.
337 (HWCAP2_VIS3B): Likewise.
338 (HWCAP2_ADP): Likewise.
339 (HWCAP2_SPARC5): Likewise.
340 (HWCAP2_MWAIT): Likewise.
341 (HWCAP2_XMPMUL): Likewise.
342 (HWCAP2_XMONT): Likewise.
343 (HWCAP2_NSEC): Likewise.
344 (HWCAP2_FJATHHPC): Likewise.
345 (HWCAP2_FJDES): Likewise.
346 (HWCAP2_FJAES): Likewise.
347 Document the new operand kind `{', corresponding to the mcdper
348 ancillary state register.
349 Document the new operand kind }, which represents frsd floating
350 point registers (double precision) which must be the same than
351 frs1 in its containing instruction.
353 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
355 * nds32.h: Add new opcode declaration.
357 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
358 Matthew Fortune <matthew.fortune@imgtec.com>
360 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
361 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
362 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
363 +I, +O, +R, +:, +\, +", +;
364 (mips_check_prev_operand): New struct.
365 (INSN2_FORBIDDEN_SLOT): New define.
366 (INSN_ISA32R6): New define.
367 (INSN_ISA64R6): New define.
368 (INSN_UPTO32R6): New define.
369 (INSN_UPTO64R6): New define.
370 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
371 (ISA_MIPS32R6): New define.
372 (ISA_MIPS64R6): New define.
373 (CPU_MIPS32R6): New define.
374 (CPU_MIPS64R6): New define.
375 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
377 2014-09-03 Jiong Wang <jiong.wang@arm.com>
379 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
380 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
381 (aarch64_insn_class): Add lse_atomic.
382 (F_LSE_SZ): New field added.
383 (opcode_has_special_coder): Recognize F_LSE_SZ.
385 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
387 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
390 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
392 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
393 (INSN_LOAD_COPROC): New define.
394 (INSN_COPROC_MOVE_DELAY): Rename to...
395 (INSN_COPROC_MOVE): New define.
397 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
398 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
399 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
400 Soundararajan <Sounderarajan.D@atmel.com>
402 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
403 (AVR_ISA_2xxxa): Define ISA without LPM.
404 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
405 Add doc for contraint used in 16 bit lds/sts.
406 Adjust ISA group for icall, ijmp, pop and push.
407 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
409 2014-05-19 Nick Clifton <nickc@redhat.com>
411 * msp430.h (struct msp430_operand_s): Add vshift field.
413 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
415 * mips.h (INSN_ISA_MASK): Updated.
416 (INSN_ISA32R3): New define.
417 (INSN_ISA32R5): New define.
418 (INSN_ISA64R3): New define.
419 (INSN_ISA64R5): New define.
420 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
421 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
422 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
424 (INSN_UPTO32R3): New define.
425 (INSN_UPTO32R5): New define.
426 (INSN_UPTO64R3): New define.
427 (INSN_UPTO64R5): New define.
428 (ISA_MIPS32R3): New define.
429 (ISA_MIPS32R5): New define.
430 (ISA_MIPS64R3): New define.
431 (ISA_MIPS64R5): New define.
432 (CPU_MIPS32R3): New define.
433 (CPU_MIPS32R5): New define.
434 (CPU_MIPS64R3): New define.
435 (CPU_MIPS64R5): New define.
437 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
439 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
441 2014-04-22 Christian Svensson <blue@cmd.nu>
445 2014-03-05 Alan Modra <amodra@gmail.com>
447 Update copyright years.
449 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
451 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
454 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
455 Wei-Cheng Wang <cole945@gmail.com>
457 * nds32.h: New file for Andes NDS32.
459 2013-12-07 Mike Frysinger <vapier@gentoo.org>
461 * bfin.h: Remove +x file mode.
463 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
465 * aarch64.h (aarch64_pstatefields): Change element type to
468 2013-11-18 Renlin Li <Renlin.Li@arm.com>
470 * arm.h (ARM_AEXT_V7VE): New define.
471 (ARM_ARCH_V7VE): New define.
472 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
474 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
478 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
480 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
481 (aarch64_sys_reg_writeonly_p): Ditto.
483 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
485 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
486 (aarch64_sys_reg_writeonly_p): Ditto.
488 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
490 * aarch64.h (aarch64_sys_reg): New typedef.
491 (aarch64_sys_regs): Change to define with the new type.
492 (aarch64_sys_reg_deprecated_p): Declare.
494 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
496 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
497 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
499 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
501 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
502 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
503 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
504 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
505 For MIPS, update extension character sequences after +.
506 (ASE_MSA): New define.
507 (ASE_MSA64): New define.
508 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
509 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
510 For microMIPS, update extension character sequences after +.
512 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
517 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
519 * mips.h: Remove references to "+I" and imm2_expr.
521 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
523 * mips.h (M_DEXT, M_DINS): Delete.
525 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
527 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
528 (mips_optional_operand_p): New function.
530 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
531 Richard Sandiford <rdsandiford@googlemail.com>
533 * mips.h: Document new VU0 operand characters.
534 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
535 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
536 (OP_REG_R5900_ACC): New mips_reg_operand_types.
537 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
538 (mips_vu0_channel_mask): Declare.
540 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
542 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
543 (mips_int_operand_min, mips_int_operand_max): New functions.
544 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
546 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
548 * mips.h (mips_decode_reg_operand): New function.
549 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
550 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
551 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
553 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
554 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
555 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
556 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
557 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
558 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
559 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
560 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
561 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
562 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
563 macros to cover the gaps.
564 (INSN2_MOD_SP): Replace with...
565 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
566 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
567 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
568 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
569 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
572 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
574 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
575 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
576 (MIPS16_INSN_COND_BRANCH): Delete.
578 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
579 Kirill Yukhin <kirill.yukhin@intel.com>
580 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
582 * i386.h (BND_PREFIX_OPCODE): New.
584 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
586 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
587 OP_SAVE_RESTORE_LIST.
588 (decode_mips16_operand): Declare.
590 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
592 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
593 (mips_operand, mips_int_operand, mips_mapped_int_operand)
594 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
595 (mips_pcrel_operand): New structures.
596 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
597 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
598 (decode_mips_operand, decode_micromips_operand): Declare.
600 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
602 * mips.h: Document MIPS16 "I" opcode.
604 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
606 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
607 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
608 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
609 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
610 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
611 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
612 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
613 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
614 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
615 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
616 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
617 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
618 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
620 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
621 (M_USD_AB): ...these.
623 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
625 * mips.h: Remove documentation of "[" and "]". Update documentation
626 of "k" and the MDMX formats.
628 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
630 * mips.h: Update documentation of "+s" and "+S".
632 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
634 * mips.h: Document "+i".
636 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
638 * mips.h: Remove "mi" documentation. Update "mh" documentation.
639 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
641 (INSN2_WRITE_GPR_MHI): Rename to...
642 (INSN2_WRITE_GPR_MH): ...this.
644 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
646 * mips.h: Remove documentation of "+D" and "+T".
648 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
650 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
651 Use "source" rather than "destination" for microMIPS "G".
653 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
655 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
658 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
660 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
662 2013-06-17 Catherine Moore <clm@codesourcery.com>
663 Maciej W. Rozycki <macro@codesourcery.com>
664 Chao-Ying Fu <fu@mips.com>
666 * mips.h (OP_SH_EVAOFFSET): Define.
667 (OP_MASK_EVAOFFSET): Define.
668 (INSN_ASE_MASK): Delete.
670 (M_CACHEE_AB, M_CACHEE_OB): New.
671 (M_LBE_OB, M_LBE_AB): New.
672 (M_LBUE_OB, M_LBUE_AB): New.
673 (M_LHE_OB, M_LHE_AB): New.
674 (M_LHUE_OB, M_LHUE_AB): New.
675 (M_LLE_AB, M_LLE_OB): New.
676 (M_LWE_OB, M_LWE_AB): New.
677 (M_LWLE_AB, M_LWLE_OB): New.
678 (M_LWRE_AB, M_LWRE_OB): New.
679 (M_PREFE_AB, M_PREFE_OB): New.
680 (M_SCE_AB, M_SCE_OB): New.
681 (M_SBE_OB, M_SBE_AB): New.
682 (M_SHE_OB, M_SHE_AB): New.
683 (M_SWE_OB, M_SWE_AB): New.
684 (M_SWLE_AB, M_SWLE_OB): New.
685 (M_SWRE_AB, M_SWRE_OB): New.
686 (MICROMIPSOP_SH_EVAOFFSET): Define.
687 (MICROMIPSOP_MASK_EVAOFFSET): Define.
689 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
691 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
693 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
695 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
697 2013-05-09 Andrew Pinski <apinski@cavium.com>
699 * mips.h (OP_MASK_CODE10): Correct definition.
700 (OP_SH_CODE10): Likewise.
701 Add a comment that "+J" is used now for OP_*CODE10.
702 (INSN_ASE_MASK): Update.
703 (INSN_VIRT): New macro.
704 (INSN_VIRT64): New macro
706 2013-05-02 Nick Clifton <nickc@redhat.com>
708 * msp430.h: Add patterns for MSP430X instructions.
710 2013-04-06 David S. Miller <davem@davemloft.net>
712 * sparc.h (F_PREFERRED): Define.
713 (F_PREF_ALIAS): Define.
715 2013-04-03 Nick Clifton <nickc@redhat.com>
717 * v850.h (V850_INVERSE_PCREL): Define.
719 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
722 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
724 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
727 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
729 * tic6xc-opcode-table.h: Add 16-bit insns.
730 * tic6x.h: Add support for 16-bit insns.
732 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
734 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
735 and mov.b/w/l Rs,@(d:32,ERd).
737 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
740 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
741 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
742 tic6x_operand_xregpair operand coding type.
743 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
744 opcode field, usu ORXREGD1324 for the src2 operand and remove the
747 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
750 * tic6x.h (enum tic6x_coding_method): Add
751 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
752 separately the msb and lsb of a register pair. This is needed to
753 encode the opcodes in the same way as TI assembler does.
754 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
755 and rsqrdp opcodes to use the new field coding types.
757 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
759 * arm.h (CRC_EXT_ARMV8): New constant.
760 (ARCH_CRC_ARMV8): New macro.
762 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
764 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
766 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
767 Andrew Jenner <andrew@codesourcery.com>
769 Based on patches from Altera Corporation.
773 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
775 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
777 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
780 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
782 2013-01-24 Nick Clifton <nickc@redhat.com>
784 * v850.h: Add e3v5 support.
786 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
788 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
790 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
792 * ppc.h (PPC_OPCODE_POWER8): New define.
793 (PPC_OPCODE_HTM): Likewise.
795 2013-01-10 Will Newton <will.newton@imgtec.com>
799 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
801 * cr16.h (make_instruction): Rename to cr16_make_instruction.
802 (match_opcode): Rename to cr16_match_opcode.
804 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
806 * mips.h: Add support for r5900 instructions including lq and sq.
808 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
810 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
811 (make_instruction,match_opcode): Added function prototypes.
812 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
814 2012-11-23 Alan Modra <amodra@gmail.com>
816 * ppc.h (ppc_parse_cpu): Update prototype.
818 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
820 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
821 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
823 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
825 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
827 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
829 * ia64.h (ia64_opnd): Add new operand types.
831 2012-08-21 David S. Miller <davem@davemloft.net>
833 * sparc.h (F3F4): New macro.
835 2012-08-13 Ian Bolton <ian.bolton@arm.com>
836 Laurent Desnogues <laurent.desnogues@arm.com>
837 Jim MacArthur <jim.macarthur@arm.com>
838 Marcus Shawcroft <marcus.shawcroft@arm.com>
839 Nigel Stephens <nigel.stephens@arm.com>
840 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
841 Richard Earnshaw <rearnsha@arm.com>
842 Sofiane Naci <sofiane.naci@arm.com>
843 Tejas Belagod <tejas.belagod@arm.com>
844 Yufeng Zhang <yufeng.zhang@arm.com>
846 * aarch64.h: New file.
848 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
849 Maciej W. Rozycki <macro@codesourcery.com>
851 * mips.h (mips_opcode): Add the exclusions field.
852 (OPCODE_IS_MEMBER): Remove macro.
853 (cpu_is_member): New inline function.
854 (opcode_is_member): Likewise.
856 2012-07-31 Chao-Ying Fu <fu@mips.com>
857 Catherine Moore <clm@codesourcery.com>
858 Maciej W. Rozycki <macro@codesourcery.com>
860 * mips.h: Document microMIPS DSP ASE usage.
861 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
862 microMIPS DSP ASE support.
863 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
864 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
865 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
866 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
867 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
868 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
869 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
871 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
873 * mips.h: Fix a typo in description.
875 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
877 * avr.h: (AVR_ISA_XCH): New define.
878 (AVR_ISA_XMEGA): Use it.
879 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
881 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
883 * m68hc11.h: Add XGate definitions.
884 (struct m68hc11_opcode): Add xg_mask field.
886 2012-05-14 Catherine Moore <clm@codesourcery.com>
887 Maciej W. Rozycki <macro@codesourcery.com>
888 Rhonda Wittels <rhonda@codesourcery.com>
890 * ppc.h (PPC_OPCODE_VLE): New definition.
891 (PPC_OP_SA): New macro.
892 (PPC_OP_SE_VLE): New macro.
893 (PPC_OP): Use a variable shift amount.
894 (powerpc_operand): Update comments.
895 (PPC_OPSHIFT_INV): New macro.
896 (PPC_OPERAND_CR): Replace with...
897 (PPC_OPERAND_CR_BIT): ...this and
898 (PPC_OPERAND_CR_REG): ...this.
901 2012-05-03 Sean Keys <skeys@ipdatasys.com>
903 * xgate.h: Header file for XGATE assembler.
905 2012-04-27 David S. Miller <davem@davemloft.net>
907 * sparc.h: Document new arg code' )' for crypto RS3
910 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
911 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
912 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
913 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
914 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
915 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
916 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
917 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
918 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
919 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
920 HWCAP_CBCOND, HWCAP_CRC32): New defines.
922 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
924 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
926 2012-02-27 Alan Modra <amodra@gmail.com>
928 * crx.h (cst4_map): Update declaration.
930 2012-02-25 Walter Lee <walt@tilera.com>
932 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
934 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
935 TILEPRO_OPC_LW_TLS_SN.
937 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
939 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
940 (XRELEASE_PREFIX_OPCODE): Likewise.
942 2011-12-08 Andrew Pinski <apinski@cavium.com>
943 Adam Nemet <anemet@caviumnetworks.com>
945 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
946 (INSN_OCTEON2): New macro.
947 (CPU_OCTEON2): New macro.
948 (OPCODE_IS_MEMBER): Add Octeon2.
950 2011-11-29 Andrew Pinski <apinski@cavium.com>
952 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
953 (INSN_OCTEONP): New macro.
954 (CPU_OCTEONP): New macro.
955 (OPCODE_IS_MEMBER): Add Octeon+.
956 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
958 2011-11-01 DJ Delorie <dj@redhat.com>
962 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
964 * mips.h: Fix a typo in description.
966 2011-09-21 David S. Miller <davem@davemloft.net>
968 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
969 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
970 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
971 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
973 2011-08-09 Chao-ying Fu <fu@mips.com>
974 Maciej W. Rozycki <macro@codesourcery.com>
976 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
977 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
978 (INSN_ASE_MASK): Add the MCU bit.
979 (INSN_MCU): New macro.
980 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
981 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
983 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
985 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
986 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
987 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
988 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
989 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
990 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
991 (INSN2_READ_GPR_MMN): Likewise.
992 (INSN2_READ_FPR_D): Change the bit used.
993 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
994 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
995 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
996 (INSN2_COND_BRANCH): Likewise.
997 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
998 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
999 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
1000 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
1001 (INSN2_MOD_GPR_MN): Likewise.
1003 2011-08-05 David S. Miller <davem@davemloft.net>
1005 * sparc.h: Document new format codes '4', '5', and '('.
1006 (OPF_LOW4, RS3): New macros.
1008 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
1010 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
1011 order of flags documented.
1013 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
1015 * mips.h: Clarify the description of microMIPS instruction
1016 manipulation macros.
1017 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
1019 2011-07-24 Chao-ying Fu <fu@mips.com>
1020 Maciej W. Rozycki <macro@codesourcery.com>
1022 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
1023 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
1024 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
1025 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
1026 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
1027 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
1028 (OP_MASK_RS3, OP_SH_RS3): Likewise.
1029 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
1030 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
1031 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
1032 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
1033 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
1034 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
1035 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
1036 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
1037 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
1038 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
1039 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
1040 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
1041 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
1042 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
1043 (INSN_WRITE_GPR_S): New macro.
1044 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
1045 (INSN2_READ_FPR_D): Likewise.
1046 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
1047 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
1048 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
1049 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
1050 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
1051 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
1052 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
1053 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
1054 (CPU_MICROMIPS): New macro.
1055 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
1056 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
1057 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
1058 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
1059 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
1060 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
1061 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
1062 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
1063 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
1064 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
1065 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
1066 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
1067 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
1068 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
1069 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
1070 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
1071 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
1072 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
1073 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
1074 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
1075 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
1076 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
1077 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
1078 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1079 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1080 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1081 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
1082 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
1083 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
1084 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
1085 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
1086 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
1087 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
1088 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
1089 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
1090 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
1091 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
1092 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
1093 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
1094 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
1095 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
1096 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
1097 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
1098 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
1099 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
1100 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
1101 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
1102 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
1103 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
1104 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
1105 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
1106 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
1107 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
1108 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1109 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1110 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1111 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1112 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1113 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1114 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1115 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1116 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1117 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1118 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1119 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1120 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1121 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1122 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1123 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1124 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1125 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1126 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1127 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1128 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1129 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1130 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1131 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1132 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1133 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1134 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1135 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1136 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1137 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1138 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1139 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1140 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1141 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1142 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1143 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1144 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1145 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1146 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1147 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1148 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1149 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1150 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1151 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1152 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1153 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1154 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1155 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1156 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1157 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1158 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1159 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1160 (micromips_opcodes): New declaration.
1161 (bfd_micromips_num_opcodes): Likewise.
1163 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1165 * mips.h (INSN_TRAP): Rename to...
1166 (INSN_NO_DELAY_SLOT): ... this.
1167 (INSN_SYNC): Remove macro.
1169 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1171 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1172 a duplicate of AVR_ISA_SPM.
1174 2011-07-01 Nick Clifton <nickc@redhat.com>
1176 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1178 2011-06-18 Robin Getz <robin.getz@analog.com>
1180 * bfin.h (is_macmod_signed): New func
1182 2011-06-18 Mike Frysinger <vapier@gentoo.org>
1184 * bfin.h (is_macmod_pmove): Add missing space before func args.
1185 (is_macmod_hmove): Likewise.
1187 2011-06-13 Walter Lee <walt@tilera.com>
1189 * tilegx.h: New file.
1190 * tilepro.h: New file.
1192 2011-05-31 Paul Brook <paul@codesourcery.com>
1194 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1196 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1198 * s390.h: Replace S390_OPERAND_REG_EVEN with
1199 S390_OPERAND_REG_PAIR.
1201 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1203 * s390.h: Add S390_OPCODE_REG_EVEN flag.
1205 2011-04-18 Julian Brown <julian@codesourcery.com>
1207 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1209 2011-04-11 Dan McDonald <dan@wellkeeper.com>
1212 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1214 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1216 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1217 New instruction set flags.
1218 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1220 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1222 * mips.h (M_PREF_AB): New enum value.
1224 2011-02-12 Mike Frysinger <vapier@gentoo.org>
1226 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1228 (is_macmod_pmove, is_macmod_hmove): New functions.
1230 2011-02-11 Mike Frysinger <vapier@gentoo.org>
1232 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1234 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1236 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1237 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1239 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1242 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1245 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1248 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1250 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1252 * mips.h: Update commentary after last commit.
1254 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1256 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1257 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1258 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1260 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1262 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1264 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1266 * mips.h: Fix previous commit.
1268 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1270 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1271 (INSN_LOONGSON_3A): Clear bit 31.
1273 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1276 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1277 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1278 (ARM_ARCH_V6M_ONLY): New define.
1280 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1282 * mips.h (INSN_LOONGSON_3A): Defined.
1283 (CPU_LOONGSON_3A): Defined.
1284 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1286 2010-10-09 Matt Rice <ratmice@gmail.com>
1288 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1289 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1291 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1293 * arm.h (ARM_EXT_VIRT): New define.
1294 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1295 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1298 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1300 * arm.h (ARM_AEXT_ADIV): New define.
1301 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1303 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1305 * arm.h (ARM_EXT_OS): New define.
1306 (ARM_AEXT_V6SM): Likewise.
1307 (ARM_ARCH_V6SM): Likewise.
1309 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1311 * arm.h (ARM_EXT_MP): Add.
1312 (ARM_ARCH_V7A_MP): Likewise.
1314 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1316 * bfin.h: Declare pseudoChr structs/defines.
1318 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1320 * bfin.h: Strip trailing whitespace.
1322 2010-07-29 DJ Delorie <dj@redhat.com>
1324 * rx.h (RX_Operand_Type): Add TwoReg.
1325 (RX_Opcode_ID): Remove ediv and ediv2.
1327 2010-07-27 DJ Delorie <dj@redhat.com>
1329 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1331 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1332 Ina Pandit <ina.pandit@kpitcummins.com>
1334 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1335 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1336 PROCESSOR_V850E2_ALL.
1337 Remove PROCESSOR_V850EA support.
1338 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1339 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1340 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1341 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1342 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1343 V850_OPERAND_PERCENT.
1344 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1346 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1349 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1351 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1352 (MIPS16_INSN_BRANCH): Rename to...
1353 (MIPS16_INSN_COND_BRANCH): ... this.
1355 2010-07-03 Alan Modra <amodra@gmail.com>
1357 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1358 Renumber other PPC_OPCODE defines.
1360 2010-07-03 Alan Modra <amodra@gmail.com>
1362 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1364 2010-06-29 Alan Modra <amodra@gmail.com>
1366 * maxq.h: Delete file.
1368 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1370 * ppc.h (PPC_OPCODE_E500): Define.
1372 2010-05-26 Catherine Moore <clm@codesourcery.com>
1374 * opcode/mips.h (INSN_MIPS16): Remove.
1376 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1378 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1380 2010-04-15 Nick Clifton <nickc@redhat.com>
1382 * alpha.h: Update copyright notice to use GPLv3.
1388 * convex.h: Likewise.
1395 * h8300.h: Likewise.
1402 * m68hc11.h: Likewise.
1408 * mn10200.h: Likewise.
1409 * mn10300.h: Likewise.
1410 * msp430.h: Likewise.
1412 * ns32k.h: Likewise.
1414 * pdp11.h: Likewise.
1421 * score-datadep.h: Likewise.
1422 * score-inst.h: Likewise.
1423 * sparc.h: Likewise.
1424 * spu-insns.h: Likewise.
1426 * tic30.h: Likewise.
1427 * tic4x.h: Likewise.
1428 * tic54x.h: Likewise.
1429 * tic80.h: Likewise.
1433 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1435 * tic6x-control-registers.h, tic6x-insn-formats.h,
1436 tic6x-opcode-table.h, tic6x.h: New.
1438 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1440 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1442 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1444 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1446 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1448 * ia64.h (ia64_find_opcode): Remove argument name.
1449 (ia64_find_next_opcode): Likewise.
1450 (ia64_dis_opcode): Likewise.
1451 (ia64_free_opcode): Likewise.
1452 (ia64_find_dependency): Likewise.
1454 2009-11-22 Doug Evans <dje@sebabeach.org>
1456 * cgen.h: Include bfd_stdint.h.
1457 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1459 2009-11-18 Paul Brook <paul@codesourcery.com>
1461 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1463 2009-11-17 Paul Brook <paul@codesourcery.com>
1464 Daniel Jacobowitz <dan@codesourcery.com>
1466 * arm.h (ARM_EXT_V6_DSP): Define.
1467 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1468 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1470 2009-11-04 DJ Delorie <dj@redhat.com>
1472 * rx.h (rx_decode_opcode) (mvtipl): Add.
1473 (mvtcp, mvfcp, opecp): Remove.
1475 2009-11-02 Paul Brook <paul@codesourcery.com>
1477 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1478 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1479 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1480 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1481 FPU_ARCH_NEON_VFP_V4): Define.
1483 2009-10-23 Doug Evans <dje@sebabeach.org>
1485 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1486 * cgen.h: Update. Improve multi-inclusion macro name.
1488 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1490 * ppc.h (PPC_OPCODE_476): Define.
1492 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1494 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1496 2009-09-29 DJ Delorie <dj@redhat.com>
1500 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1502 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1504 2009-09-21 Ben Elliston <bje@au.ibm.com>
1506 * ppc.h (PPC_OPCODE_PPCA2): New.
1508 2009-09-05 Martin Thuresson <martin@mtme.org>
1510 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1512 2009-08-29 Martin Thuresson <martin@mtme.org>
1514 * tic30.h (template): Rename type template to
1515 insn_template. Updated code to use new name.
1516 * tic54x.h (template): Rename type template to
1519 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1521 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1523 2009-06-11 Anthony Green <green@moxielogic.com>
1525 * moxie.h (MOXIE_F3_PCREL): Define.
1526 (moxie_form3_opc_info): Grow.
1528 2009-06-06 Anthony Green <green@moxielogic.com>
1530 * moxie.h (MOXIE_F1_M): Define.
1532 2009-04-15 Anthony Green <green@moxielogic.com>
1536 2009-04-06 DJ Delorie <dj@redhat.com>
1538 * h8300.h: Add relaxation attributes to MOVA opcodes.
1540 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1542 * ppc.h (ppc_parse_cpu): Declare.
1544 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1546 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1547 and _IMM11 for mbitclr and mbitset.
1548 * score-datadep.h: Update dependency information.
1550 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1552 * ppc.h (PPC_OPCODE_POWER7): New.
1554 2009-02-06 Doug Evans <dje@google.com>
1556 * i386.h: Add comment regarding sse* insns and prefixes.
1558 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1560 * mips.h (INSN_XLR): Define.
1561 (INSN_CHIP_MASK): Update.
1563 (OPCODE_IS_MEMBER): Update.
1564 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1566 2009-01-28 Doug Evans <dje@google.com>
1568 * opcode/i386.h: Add multiple inclusion protection.
1569 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1570 (EDI_REG_NUM): New macros.
1571 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1572 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1573 (REX_PREFIX_P): New macro.
1575 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1577 * ppc.h (struct powerpc_opcode): New field "deprecated".
1578 (PPC_OPCODE_NOPOWER4): Delete.
1580 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1582 * mips.h: Define CPU_R14000, CPU_R16000.
1583 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1585 2008-11-18 Catherine Moore <clm@codesourcery.com>
1587 * arm.h (FPU_NEON_FP16): New.
1588 (FPU_ARCH_NEON_FP16): New.
1590 2008-11-06 Chao-ying Fu <fu@mips.com>
1592 * mips.h: Doucument '1' for 5-bit sync type.
1594 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1596 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1599 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1601 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1603 2008-07-30 Michael J. Eager <eager@eagercon.com>
1605 * ppc.h (PPC_OPCODE_405): Define.
1606 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1608 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1610 * ppc.h (ppc_cpu_t): New typedef.
1611 (struct powerpc_opcode <flags>): Use it.
1612 (struct powerpc_operand <insert, extract>): Likewise.
1613 (struct powerpc_macro <flags>): Likewise.
1615 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1617 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1618 Update comment before MIPS16 field descriptors to mention MIPS16.
1619 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1621 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1622 New bit masks and shift counts for cins and exts.
1624 * mips.h: Document new field descriptors +Q.
1625 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1627 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1629 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1630 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1632 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1634 * ppc.h: (PPC_OPCODE_E500MC): New.
1636 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1638 * i386.h (MAX_OPERANDS): Set to 5.
1639 (MAX_MNEM_SIZE): Changed to 20.
1641 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1643 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1645 2008-03-09 Paul Brook <paul@codesourcery.com>
1647 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1649 2008-03-04 Paul Brook <paul@codesourcery.com>
1651 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1652 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1653 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1655 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1656 Nick Clifton <nickc@redhat.com>
1659 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1660 with a 32-bit displacement but without the top bit of the 4th byte
1663 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1665 * cr16.h (cr16_num_optab): Declared.
1667 2008-02-14 Hakan Ardo <hakan@debian.org>
1670 * avr.h (AVR_ISA_2xxe): Define.
1672 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1674 * mips.h: Update copyright.
1675 (INSN_CHIP_MASK): New macro.
1676 (INSN_OCTEON): New macro.
1677 (CPU_OCTEON): New macro.
1678 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1680 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1682 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1684 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1686 * avr.h (AVR_ISA_USB162): Add new opcode set.
1687 (AVR_ISA_AVR3): Likewise.
1689 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1691 * mips.h (INSN_LOONGSON_2E): New.
1692 (INSN_LOONGSON_2F): New.
1693 (CPU_LOONGSON_2E): New.
1694 (CPU_LOONGSON_2F): New.
1695 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1697 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1699 * mips.h (INSN_ISA*): Redefine certain values as an
1700 enumeration. Update comments.
1701 (mips_isa_table): New.
1702 (ISA_MIPS*): Redefine to match enumeration.
1703 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1706 2007-08-08 Ben Elliston <bje@au.ibm.com>
1708 * ppc.h (PPC_OPCODE_PPCPS): New.
1710 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1712 * m68k.h: Document j K & E.
1714 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1716 * cr16.h: New file for CR16 target.
1718 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1720 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1722 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1724 * m68k.h (mcfisa_c): New.
1725 (mcfusp, mcf_mask): Adjust.
1727 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1729 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1730 (num_powerpc_operands): Declare.
1731 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1732 (PPC_OPERAND_PLUS1): Define.
1734 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1736 * i386.h (REX_MODE64): Renamed to ...
1738 (REX_EXTX): Renamed to ...
1740 (REX_EXTY): Renamed to ...
1742 (REX_EXTZ): Renamed to ...
1745 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1747 * i386.h: Add entries from config/tc-i386.h and move tables
1748 to opcodes/i386-opc.h.
1750 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1752 * i386.h (FloatDR): Removed.
1753 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1755 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1757 * spu-insns.h: Add soma double-float insns.
1759 2007-02-20 Thiemo Seufer <ths@mips.com>
1760 Chao-Ying Fu <fu@mips.com>
1762 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1763 (INSN_DSPR2): Add flag for DSP R2 instructions.
1764 (M_BALIGN): New macro.
1766 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1768 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1769 and Seg3ShortFrom with Shortform.
1771 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1774 * i386.h (i386_optab): Put the real "test" before the pseudo
1777 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1779 * m68k.h (m68010up): OR fido_a.
1781 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1783 * m68k.h (fido_a): New.
1785 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1787 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1788 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1791 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1793 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1795 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1797 * score-inst.h (enum score_insn_type): Add Insn_internal.
1799 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1800 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1801 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1802 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1803 Alan Modra <amodra@bigpond.net.au>
1805 * spu-insns.h: New file.
1808 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1810 * ppc.h (PPC_OPCODE_CELL): Define.
1812 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1814 * i386.h : Modify opcode to support for the change in POPCNT opcode
1815 in amdfam10 architecture.
1817 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1819 * i386.h: Replace CpuMNI with CpuSSSE3.
1821 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1822 Joseph Myers <joseph@codesourcery.com>
1823 Ian Lance Taylor <ian@wasabisystems.com>
1824 Ben Elliston <bje@wasabisystems.com>
1826 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1828 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1830 * score-datadep.h: New file.
1831 * score-inst.h: New file.
1833 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1835 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1836 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1837 movdq2q and movq2dq.
1839 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1840 Michael Meissner <michael.meissner@amd.com>
1842 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1844 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1846 * i386.h (i386_optab): Add "nop" with memory reference.
1848 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1850 * i386.h (i386_optab): Update comment for 64bit NOP.
1852 2006-06-06 Ben Elliston <bje@au.ibm.com>
1853 Anton Blanchard <anton@samba.org>
1855 * ppc.h (PPC_OPCODE_POWER6): Define.
1858 2006-06-05 Thiemo Seufer <ths@mips.com>
1860 * mips.h: Improve description of MT flags.
1862 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1864 * m68k.h (mcf_mask): Define.
1866 2006-05-05 Thiemo Seufer <ths@mips.com>
1867 David Ung <davidu@mips.com>
1869 * mips.h (enum): Add macro M_CACHE_AB.
1871 2006-05-04 Thiemo Seufer <ths@mips.com>
1872 Nigel Stephens <nigel@mips.com>
1873 David Ung <davidu@mips.com>
1875 * mips.h: Add INSN_SMARTMIPS define.
1877 2006-04-30 Thiemo Seufer <ths@mips.com>
1878 David Ung <davidu@mips.com>
1880 * mips.h: Defines udi bits and masks. Add description of
1881 characters which may appear in the args field of udi
1884 2006-04-26 Thiemo Seufer <ths@networkno.de>
1886 * mips.h: Improve comments describing the bitfield instruction
1889 2006-04-26 Julian Brown <julian@codesourcery.com>
1891 * arm.h (FPU_VFP_EXT_V3): Define constant.
1892 (FPU_NEON_EXT_V1): Likewise.
1893 (FPU_VFP_HARD): Update.
1894 (FPU_VFP_V3): Define macro.
1895 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1897 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1899 * avr.h (AVR_ISA_PWMx): New.
1901 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1903 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1904 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1905 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1906 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1907 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1909 2006-03-10 Paul Brook <paul@codesourcery.com>
1911 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1913 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1915 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1916 first. Correct mask of bb "B" opcode.
1918 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1920 * i386.h (i386_optab): Support Intel Merom New Instructions.
1922 2006-02-24 Paul Brook <paul@codesourcery.com>
1924 * arm.h: Add V7 feature bits.
1926 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1928 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1930 2006-01-31 Paul Brook <paul@codesourcery.com>
1931 Richard Earnshaw <rearnsha@arm.com>
1933 * arm.h: Use ARM_CPU_FEATURE.
1934 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1935 (arm_feature_set): Change to a structure.
1936 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1937 ARM_FEATURE): New macros.
1939 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1941 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1942 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1943 (ADD_PC_INCR_OPCODE): Don't define.
1945 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1948 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1950 2005-11-14 David Ung <davidu@mips.com>
1952 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1953 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1954 save/restore encoding of the args field.
1956 2005-10-28 Dave Brolley <brolley@redhat.com>
1958 Contribute the following changes:
1959 2005-02-16 Dave Brolley <brolley@redhat.com>
1961 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1962 cgen_isa_mask_* to cgen_bitset_*.
1965 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1967 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1968 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1969 (CGEN_CPU_TABLE): Make isas a ponter.
1971 2003-09-29 Dave Brolley <brolley@redhat.com>
1973 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1974 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1975 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1977 2002-12-13 Dave Brolley <brolley@redhat.com>
1979 * cgen.h (symcat.h): #include it.
1980 (cgen-bitset.h): #include it.
1981 (CGEN_ATTR_VALUE_TYPE): Now a union.
1982 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1983 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1984 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1985 * cgen-bitset.h: New file.
1987 2005-09-30 Catherine Moore <clm@cm00re.com>
1991 2005-10-24 Jan Beulich <jbeulich@novell.com>
1993 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1996 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1998 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1999 Add FLAG_STRICT to pa10 ftest opcode.
2001 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2003 * hppa.h (pa_opcodes): Remove lha entries.
2005 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2007 * hppa.h (FLAG_STRICT): Revise comment.
2008 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
2009 before corresponding pa11 opcodes. Add strict pa10 register-immediate
2012 2005-09-30 Catherine Moore <clm@cm00re.com>
2016 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2018 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
2020 2005-09-06 Chao-ying Fu <fu@mips.com>
2022 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
2023 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
2025 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
2026 (INSN_ASE_MASK): Update to include INSN_MT.
2027 (INSN_MT): New define for MT ASE.
2029 2005-08-25 Chao-ying Fu <fu@mips.com>
2031 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
2032 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
2033 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
2034 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
2035 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
2036 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
2038 (INSN_DSP): New define for DSP ASE.
2040 2005-08-18 Alan Modra <amodra@bigpond.net.au>
2044 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
2046 * ppc.h (PPC_OPCODE_E300): Define.
2048 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
2050 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
2052 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2055 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
2058 2005-07-27 Jan Beulich <jbeulich@novell.com>
2060 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
2061 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
2062 Add movq-s as 64-bit variants of movd-s.
2064 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2066 * hppa.h: Fix punctuation in comment.
2068 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
2069 implicit space-register addressing. Set space-register bits on opcodes
2070 using implicit space-register addressing. Add various missing pa20
2071 long-immediate opcodes. Remove various opcodes using implicit 3-bit
2072 space-register addressing. Use "fE" instead of "fe" in various
2075 2005-07-18 Jan Beulich <jbeulich@novell.com>
2077 * i386.h (i386_optab): Operands of aam and aad are unsigned.
2079 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
2081 * i386.h (i386_optab): Support Intel VMX Instructions.
2083 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2085 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
2087 2005-07-05 Jan Beulich <jbeulich@novell.com>
2089 * i386.h (i386_optab): Add new insns.
2091 2005-07-01 Nick Clifton <nickc@redhat.com>
2093 * sparc.h: Add typedefs to structure declarations.
2095 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
2098 * i386.h (i386_optab): Update comments for 64bit addressing on
2099 mov. Allow 64bit addressing for mov and movq.
2101 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2103 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
2104 respectively, in various floating-point load and store patterns.
2106 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2108 * hppa.h (FLAG_STRICT): Correct comment.
2109 (pa_opcodes): Update load and store entries to allow both PA 1.X and
2110 PA 2.0 mneumonics when equivalent. Entries with cache control
2111 completers now require PA 1.1. Adjust whitespace.
2113 2005-05-19 Anton Blanchard <anton@samba.org>
2115 * ppc.h (PPC_OPCODE_POWER5): Define.
2117 2005-05-10 Nick Clifton <nickc@redhat.com>
2119 * Update the address and phone number of the FSF organization in
2120 the GPL notices in the following files:
2121 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2122 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2123 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2124 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2125 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2126 tic54x.h, tic80.h, v850.h, vax.h
2128 2005-05-09 Jan Beulich <jbeulich@novell.com>
2130 * i386.h (i386_optab): Add ht and hnt.
2132 2005-04-18 Mark Kettenis <kettenis@gnu.org>
2134 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2135 Add xcrypt-ctr. Provide aliases without hyphens.
2137 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2139 Moved from ../ChangeLog
2141 2005-04-12 Paul Brook <paul@codesourcery.com>
2142 * m88k.h: Rename psr macros to avoid conflicts.
2144 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2145 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2146 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2147 and ARM_ARCH_V6ZKT2.
2149 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2150 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2151 Remove redundant instruction types.
2152 (struct argument): X_op - new field.
2153 (struct cst4_entry): Remove.
2154 (no_op_insn): Declare.
2156 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2157 * crx.h (enum argtype): Rename types, remove unused types.
2159 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2160 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2161 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2162 (enum operand_type): Rearrange operands, edit comments.
2163 replace us<N> with ui<N> for unsigned immediate.
2164 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2165 displacements (respectively).
2166 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2167 (instruction type): Add NO_TYPE_INS.
2168 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2169 (operand_entry): New field - 'flags'.
2170 (operand flags): New.
2172 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2173 * crx.h (operand_type): Remove redundant types i3, i4,
2175 Add new unsigned immediate types us3, us4, us5, us16.
2177 2005-04-12 Mark Kettenis <kettenis@gnu.org>
2179 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2180 adjust them accordingly.
2182 2005-04-01 Jan Beulich <jbeulich@novell.com>
2184 * i386.h (i386_optab): Add rdtscp.
2186 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2188 * i386.h (i386_optab): Don't allow the `l' suffix for moving
2189 between memory and segment register. Allow movq for moving between
2190 general-purpose register and segment register.
2192 2005-02-09 Jan Beulich <jbeulich@novell.com>
2195 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2196 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2199 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2201 * m68k.h (m68008, m68ec030, m68882): Remove.
2203 (cpu_m68k, cpu_cf): New.
2204 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2205 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2207 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
2209 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2210 * cgen.h (enum cgen_parse_operand_type): Add
2211 CGEN_PARSE_OPERAND_SYMBOLIC.
2213 2005-01-21 Fred Fish <fnf@specifixinc.com>
2215 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2216 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2217 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2219 2005-01-19 Fred Fish <fnf@specifixinc.com>
2221 * mips.h (struct mips_opcode): Add new pinfo2 member.
2222 (INSN_ALIAS): New define for opcode table entries that are
2223 specific instances of another entry, such as 'move' for an 'or'
2224 with a zero operand.
2225 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2226 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2228 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2230 * mips.h (CPU_RM9000): Define.
2231 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2233 2004-11-25 Jan Beulich <jbeulich@novell.com>
2235 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2236 to/from test registers are illegal in 64-bit mode. Add missing
2237 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2238 (previously one had to explicitly encode a rex64 prefix). Re-enable
2239 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2240 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2242 2004-11-23 Jan Beulich <jbeulich@novell.com>
2244 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2245 available only with SSE2. Change the MMX additions introduced by SSE
2246 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2247 instructions by their now designated identifier (since combining i686
2248 and 3DNow! does not really imply 3DNow!A).
2250 2004-11-19 Alan Modra <amodra@bigpond.net.au>
2252 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2253 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2255 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2256 Vineet Sharma <vineets@noida.hcltech.com>
2258 * maxq.h: New file: Disassembly information for the maxq port.
2260 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2262 * i386.h (i386_optab): Put back "movzb".
2264 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
2266 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2267 comments. Remove member cris_ver_sim. Add members
2268 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2269 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2270 (struct cris_support_reg, struct cris_cond15): New types.
2271 (cris_conds15): Declare.
2272 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2273 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2274 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2275 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2276 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2277 SIZE_FIELD_UNSIGNED.
2279 2004-11-04 Jan Beulich <jbeulich@novell.com>
2281 * i386.h (sldx_Suf): Remove.
2282 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2283 (q_FP): Define, implying no REX64.
2284 (x_FP, sl_FP): Imply FloatMF.
2285 (i386_optab): Split reg and mem forms of moving from segment registers
2286 so that the memory forms can ignore the 16-/32-bit operand size
2287 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2288 all non-floating-point instructions. Unite 32- and 64-bit forms of
2289 movsx, movzx, and movd. Adjust floating point operations for the above
2290 changes to the *FP macros. Add DefaultSize to floating point control
2291 insns operating on larger memory ranges. Remove left over comments
2292 hinting at certain insns being Intel-syntax ones where the ones
2293 actually meant are already gone.
2295 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2297 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2300 2004-09-30 Paul Brook <paul@codesourcery.com>
2302 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2303 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2305 2004-09-11 Theodore A. Roth <troth@openavr.org>
2307 * avr.h: Add support for
2308 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2310 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2312 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2314 2004-08-24 Dmitry Diky <diwil@spec.ru>
2316 * msp430.h (msp430_opc): Add new instructions.
2317 (msp430_rcodes): Declare new instructions.
2318 (msp430_hcodes): Likewise..
2320 2004-08-13 Nick Clifton <nickc@redhat.com>
2323 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2326 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2328 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2330 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2332 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2334 2004-07-21 Jan Beulich <jbeulich@novell.com>
2336 * i386.h: Adjust instruction descriptions to better match the
2339 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2341 * arm.h: Remove all old content. Replace with architecture defines
2342 from gas/config/tc-arm.c.
2344 2004-07-09 Andreas Schwab <schwab@suse.de>
2346 * m68k.h: Fix comment.
2348 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2352 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2354 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2356 2004-05-24 Peter Barada <peter@the-baradas.com>
2358 * m68k.h: Add 'size' to m68k_opcode.
2360 2004-05-05 Peter Barada <peter@the-baradas.com>
2362 * m68k.h: Switch from ColdFire chip name to core variant.
2364 2004-04-22 Peter Barada <peter@the-baradas.com>
2366 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2367 descriptions for new EMAC cases.
2368 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2369 handle Motorola MAC syntax.
2370 Allow disassembly of ColdFire V4e object files.
2372 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2374 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2376 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2378 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2380 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2382 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2384 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2386 * i386.h (i386_optab): Added xstore/xcrypt insns.
2388 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2390 * h8300.h (32bit ldc/stc): Add relaxing support.
2392 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2394 * h8300.h (BITOP): Pass MEMRELAX flag.
2396 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2398 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2401 For older changes see ChangeLog-9103
2403 Copyright (C) 2004-2015 Free Software Foundation, Inc.
2405 Copying and distribution of this file, with or without modification,
2406 are permitted in any medium without royalty provided the copyright
2407 notice and this notice are preserved.
2413 version-control: never
projects / deliverable / binutils-gdb.git / blob