1 2014-12-27 Anthony Green <green@moxielogic.com>
3 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
4 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
6 2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
10 2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
12 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
13 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
14 (NIOS2_INSN_OPTARG): Renumber.
16 2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
18 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
19 declaration. Fix obsolete comment.
21 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
23 * nios2.h (enum iw_format_type): New.
24 (struct nios2_opcode): Update comments. Add size and format fields.
25 (NIOS2_INSN_OPTARG): New.
26 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
27 (struct nios2_reg): Add regtype field.
28 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
29 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
30 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
31 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
32 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
33 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
34 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
35 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
36 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
37 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
38 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
39 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
40 (OP_MASK_OP, OP_SH_OP): Delete.
41 (OP_MASK_IOP, OP_SH_IOP): Delete.
42 (OP_MASK_IRD, OP_SH_IRD): Delete.
43 (OP_MASK_IRT, OP_SH_IRT): Delete.
44 (OP_MASK_IRS, OP_SH_IRS): Delete.
45 (OP_MASK_ROP, OP_SH_ROP): Delete.
46 (OP_MASK_RRD, OP_SH_RRD): Delete.
47 (OP_MASK_RRT, OP_SH_RRT): Delete.
48 (OP_MASK_RRS, OP_SH_RRS): Delete.
49 (OP_MASK_JOP, OP_SH_JOP): Delete.
50 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
51 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
52 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
53 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
54 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
55 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
56 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
57 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
58 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
59 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
60 (OP_MASK_<insn>, OP_MASK): Delete.
61 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
62 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
63 Include nios2r1.h to define new instruction opcode constants
65 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
66 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
67 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
68 (NUMOPCODES, NUMREGISTERS): Delete.
69 * nios2r1.h: New file.
71 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
73 * sparc.h (HWCAP2_VIS3B): Documentation improved.
75 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
77 * sparc.h (sparc_opcode): new field `hwcaps2'.
78 (HWCAP2_FJATHPLUS): New define.
79 (HWCAP2_VIS3B): Likewise.
80 (HWCAP2_ADP): Likewise.
81 (HWCAP2_SPARC5): Likewise.
82 (HWCAP2_MWAIT): Likewise.
83 (HWCAP2_XMPMUL): Likewise.
84 (HWCAP2_XMONT): Likewise.
85 (HWCAP2_NSEC): Likewise.
86 (HWCAP2_FJATHHPC): Likewise.
87 (HWCAP2_FJDES): Likewise.
88 (HWCAP2_FJAES): Likewise.
89 Document the new operand kind `{', corresponding to the mcdper
90 ancillary state register.
91 Document the new operand kind }, which represents frsd floating
92 point registers (double precision) which must be the same than
93 frs1 in its containing instruction.
95 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
97 * nds32.h: Add new opcode declaration.
99 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
100 Matthew Fortune <matthew.fortune@imgtec.com>
102 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
103 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
104 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
105 +I, +O, +R, +:, +\, +", +;
106 (mips_check_prev_operand): New struct.
107 (INSN2_FORBIDDEN_SLOT): New define.
108 (INSN_ISA32R6): New define.
109 (INSN_ISA64R6): New define.
110 (INSN_UPTO32R6): New define.
111 (INSN_UPTO64R6): New define.
112 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
113 (ISA_MIPS32R6): New define.
114 (ISA_MIPS64R6): New define.
115 (CPU_MIPS32R6): New define.
116 (CPU_MIPS64R6): New define.
117 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
119 2014-09-03 Jiong Wang <jiong.wang@arm.com>
121 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
122 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
123 (aarch64_insn_class): Add lse_atomic.
124 (F_LSE_SZ): New field added.
125 (opcode_has_special_coder): Recognize F_LSE_SZ.
127 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
129 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
132 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
134 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
135 (INSN_LOAD_COPROC): New define.
136 (INSN_COPROC_MOVE_DELAY): Rename to...
137 (INSN_COPROC_MOVE): New define.
139 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
140 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
141 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
142 Soundararajan <Sounderarajan.D@atmel.com>
144 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
145 (AVR_ISA_2xxxa): Define ISA without LPM.
146 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
147 Add doc for contraint used in 16 bit lds/sts.
148 Adjust ISA group for icall, ijmp, pop and push.
149 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
151 2014-05-19 Nick Clifton <nickc@redhat.com>
153 * msp430.h (struct msp430_operand_s): Add vshift field.
155 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
157 * mips.h (INSN_ISA_MASK): Updated.
158 (INSN_ISA32R3): New define.
159 (INSN_ISA32R5): New define.
160 (INSN_ISA64R3): New define.
161 (INSN_ISA64R5): New define.
162 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
163 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
164 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
166 (INSN_UPTO32R3): New define.
167 (INSN_UPTO32R5): New define.
168 (INSN_UPTO64R3): New define.
169 (INSN_UPTO64R5): New define.
170 (ISA_MIPS32R3): New define.
171 (ISA_MIPS32R5): New define.
172 (ISA_MIPS64R3): New define.
173 (ISA_MIPS64R5): New define.
174 (CPU_MIPS32R3): New define.
175 (CPU_MIPS32R5): New define.
176 (CPU_MIPS64R3): New define.
177 (CPU_MIPS64R5): New define.
179 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
181 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
183 2014-04-22 Christian Svensson <blue@cmd.nu>
187 2014-03-05 Alan Modra <amodra@gmail.com>
189 Update copyright years.
191 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
193 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
196 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
197 Wei-Cheng Wang <cole945@gmail.com>
199 * nds32.h: New file for Andes NDS32.
201 2013-12-07 Mike Frysinger <vapier@gentoo.org>
203 * bfin.h: Remove +x file mode.
205 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
207 * aarch64.h (aarch64_pstatefields): Change element type to
210 2013-11-18 Renlin Li <Renlin.Li@arm.com>
212 * arm.h (ARM_AEXT_V7VE): New define.
213 (ARM_ARCH_V7VE): New define.
214 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
216 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
220 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
222 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
223 (aarch64_sys_reg_writeonly_p): Ditto.
225 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
227 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
228 (aarch64_sys_reg_writeonly_p): Ditto.
230 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
232 * aarch64.h (aarch64_sys_reg): New typedef.
233 (aarch64_sys_regs): Change to define with the new type.
234 (aarch64_sys_reg_deprecated_p): Declare.
236 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
238 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
239 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
241 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
243 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
244 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
245 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
246 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
247 For MIPS, update extension character sequences after +.
248 (ASE_MSA): New define.
249 (ASE_MSA64): New define.
250 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
251 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
252 For microMIPS, update extension character sequences after +.
254 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
259 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
261 * mips.h: Remove references to "+I" and imm2_expr.
263 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
265 * mips.h (M_DEXT, M_DINS): Delete.
267 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
269 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
270 (mips_optional_operand_p): New function.
272 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
273 Richard Sandiford <rdsandiford@googlemail.com>
275 * mips.h: Document new VU0 operand characters.
276 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
277 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
278 (OP_REG_R5900_ACC): New mips_reg_operand_types.
279 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
280 (mips_vu0_channel_mask): Declare.
282 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
284 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
285 (mips_int_operand_min, mips_int_operand_max): New functions.
286 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
288 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
290 * mips.h (mips_decode_reg_operand): New function.
291 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
292 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
293 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
295 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
296 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
297 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
298 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
299 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
300 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
301 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
302 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
303 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
304 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
305 macros to cover the gaps.
306 (INSN2_MOD_SP): Replace with...
307 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
308 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
309 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
310 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
311 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
314 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
316 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
317 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
318 (MIPS16_INSN_COND_BRANCH): Delete.
320 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
321 Kirill Yukhin <kirill.yukhin@intel.com>
322 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
324 * i386.h (BND_PREFIX_OPCODE): New.
326 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
328 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
329 OP_SAVE_RESTORE_LIST.
330 (decode_mips16_operand): Declare.
332 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
334 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
335 (mips_operand, mips_int_operand, mips_mapped_int_operand)
336 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
337 (mips_pcrel_operand): New structures.
338 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
339 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
340 (decode_mips_operand, decode_micromips_operand): Declare.
342 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
344 * mips.h: Document MIPS16 "I" opcode.
346 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
348 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
349 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
350 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
351 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
352 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
353 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
354 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
355 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
356 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
357 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
358 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
359 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
360 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
362 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
363 (M_USD_AB): ...these.
365 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
367 * mips.h: Remove documentation of "[" and "]". Update documentation
368 of "k" and the MDMX formats.
370 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
372 * mips.h: Update documentation of "+s" and "+S".
374 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
376 * mips.h: Document "+i".
378 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
380 * mips.h: Remove "mi" documentation. Update "mh" documentation.
381 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
383 (INSN2_WRITE_GPR_MHI): Rename to...
384 (INSN2_WRITE_GPR_MH): ...this.
386 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
388 * mips.h: Remove documentation of "+D" and "+T".
390 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
392 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
393 Use "source" rather than "destination" for microMIPS "G".
395 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
397 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
400 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
402 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
404 2013-06-17 Catherine Moore <clm@codesourcery.com>
405 Maciej W. Rozycki <macro@codesourcery.com>
406 Chao-Ying Fu <fu@mips.com>
408 * mips.h (OP_SH_EVAOFFSET): Define.
409 (OP_MASK_EVAOFFSET): Define.
410 (INSN_ASE_MASK): Delete.
412 (M_CACHEE_AB, M_CACHEE_OB): New.
413 (M_LBE_OB, M_LBE_AB): New.
414 (M_LBUE_OB, M_LBUE_AB): New.
415 (M_LHE_OB, M_LHE_AB): New.
416 (M_LHUE_OB, M_LHUE_AB): New.
417 (M_LLE_AB, M_LLE_OB): New.
418 (M_LWE_OB, M_LWE_AB): New.
419 (M_LWLE_AB, M_LWLE_OB): New.
420 (M_LWRE_AB, M_LWRE_OB): New.
421 (M_PREFE_AB, M_PREFE_OB): New.
422 (M_SCE_AB, M_SCE_OB): New.
423 (M_SBE_OB, M_SBE_AB): New.
424 (M_SHE_OB, M_SHE_AB): New.
425 (M_SWE_OB, M_SWE_AB): New.
426 (M_SWLE_AB, M_SWLE_OB): New.
427 (M_SWRE_AB, M_SWRE_OB): New.
428 (MICROMIPSOP_SH_EVAOFFSET): Define.
429 (MICROMIPSOP_MASK_EVAOFFSET): Define.
431 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
433 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
435 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
437 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
439 2013-05-09 Andrew Pinski <apinski@cavium.com>
441 * mips.h (OP_MASK_CODE10): Correct definition.
442 (OP_SH_CODE10): Likewise.
443 Add a comment that "+J" is used now for OP_*CODE10.
444 (INSN_ASE_MASK): Update.
445 (INSN_VIRT): New macro.
446 (INSN_VIRT64): New macro
448 2013-05-02 Nick Clifton <nickc@redhat.com>
450 * msp430.h: Add patterns for MSP430X instructions.
452 2013-04-06 David S. Miller <davem@davemloft.net>
454 * sparc.h (F_PREFERRED): Define.
455 (F_PREF_ALIAS): Define.
457 2013-04-03 Nick Clifton <nickc@redhat.com>
459 * v850.h (V850_INVERSE_PCREL): Define.
461 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
464 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
466 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
469 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
471 * tic6xc-opcode-table.h: Add 16-bit insns.
472 * tic6x.h: Add support for 16-bit insns.
474 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
476 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
477 and mov.b/w/l Rs,@(d:32,ERd).
479 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
482 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
483 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
484 tic6x_operand_xregpair operand coding type.
485 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
486 opcode field, usu ORXREGD1324 for the src2 operand and remove the
489 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
492 * tic6x.h (enum tic6x_coding_method): Add
493 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
494 separately the msb and lsb of a register pair. This is needed to
495 encode the opcodes in the same way as TI assembler does.
496 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
497 and rsqrdp opcodes to use the new field coding types.
499 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
501 * arm.h (CRC_EXT_ARMV8): New constant.
502 (ARCH_CRC_ARMV8): New macro.
504 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
506 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
508 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
509 Andrew Jenner <andrew@codesourcery.com>
511 Based on patches from Altera Corporation.
515 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
517 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
519 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
522 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
524 2013-01-24 Nick Clifton <nickc@redhat.com>
526 * v850.h: Add e3v5 support.
528 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
530 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
532 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
534 * ppc.h (PPC_OPCODE_POWER8): New define.
535 (PPC_OPCODE_HTM): Likewise.
537 2013-01-10 Will Newton <will.newton@imgtec.com>
541 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
543 * cr16.h (make_instruction): Rename to cr16_make_instruction.
544 (match_opcode): Rename to cr16_match_opcode.
546 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
548 * mips.h: Add support for r5900 instructions including lq and sq.
550 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
552 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
553 (make_instruction,match_opcode): Added function prototypes.
554 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
556 2012-11-23 Alan Modra <amodra@gmail.com>
558 * ppc.h (ppc_parse_cpu): Update prototype.
560 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
562 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
563 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
565 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
567 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
569 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
571 * ia64.h (ia64_opnd): Add new operand types.
573 2012-08-21 David S. Miller <davem@davemloft.net>
575 * sparc.h (F3F4): New macro.
577 2012-08-13 Ian Bolton <ian.bolton@arm.com>
578 Laurent Desnogues <laurent.desnogues@arm.com>
579 Jim MacArthur <jim.macarthur@arm.com>
580 Marcus Shawcroft <marcus.shawcroft@arm.com>
581 Nigel Stephens <nigel.stephens@arm.com>
582 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
583 Richard Earnshaw <rearnsha@arm.com>
584 Sofiane Naci <sofiane.naci@arm.com>
585 Tejas Belagod <tejas.belagod@arm.com>
586 Yufeng Zhang <yufeng.zhang@arm.com>
588 * aarch64.h: New file.
590 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
591 Maciej W. Rozycki <macro@codesourcery.com>
593 * mips.h (mips_opcode): Add the exclusions field.
594 (OPCODE_IS_MEMBER): Remove macro.
595 (cpu_is_member): New inline function.
596 (opcode_is_member): Likewise.
598 2012-07-31 Chao-Ying Fu <fu@mips.com>
599 Catherine Moore <clm@codesourcery.com>
600 Maciej W. Rozycki <macro@codesourcery.com>
602 * mips.h: Document microMIPS DSP ASE usage.
603 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
604 microMIPS DSP ASE support.
605 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
606 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
607 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
608 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
609 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
610 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
611 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
613 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
615 * mips.h: Fix a typo in description.
617 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
619 * avr.h: (AVR_ISA_XCH): New define.
620 (AVR_ISA_XMEGA): Use it.
621 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
623 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
625 * m68hc11.h: Add XGate definitions.
626 (struct m68hc11_opcode): Add xg_mask field.
628 2012-05-14 Catherine Moore <clm@codesourcery.com>
629 Maciej W. Rozycki <macro@codesourcery.com>
630 Rhonda Wittels <rhonda@codesourcery.com>
632 * ppc.h (PPC_OPCODE_VLE): New definition.
633 (PPC_OP_SA): New macro.
634 (PPC_OP_SE_VLE): New macro.
635 (PPC_OP): Use a variable shift amount.
636 (powerpc_operand): Update comments.
637 (PPC_OPSHIFT_INV): New macro.
638 (PPC_OPERAND_CR): Replace with...
639 (PPC_OPERAND_CR_BIT): ...this and
640 (PPC_OPERAND_CR_REG): ...this.
643 2012-05-03 Sean Keys <skeys@ipdatasys.com>
645 * xgate.h: Header file for XGATE assembler.
647 2012-04-27 David S. Miller <davem@davemloft.net>
649 * sparc.h: Document new arg code' )' for crypto RS3
652 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
653 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
654 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
655 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
656 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
657 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
658 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
659 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
660 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
661 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
662 HWCAP_CBCOND, HWCAP_CRC32): New defines.
664 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
666 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
668 2012-02-27 Alan Modra <amodra@gmail.com>
670 * crx.h (cst4_map): Update declaration.
672 2012-02-25 Walter Lee <walt@tilera.com>
674 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
676 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
677 TILEPRO_OPC_LW_TLS_SN.
679 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
681 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
682 (XRELEASE_PREFIX_OPCODE): Likewise.
684 2011-12-08 Andrew Pinski <apinski@cavium.com>
685 Adam Nemet <anemet@caviumnetworks.com>
687 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
688 (INSN_OCTEON2): New macro.
689 (CPU_OCTEON2): New macro.
690 (OPCODE_IS_MEMBER): Add Octeon2.
692 2011-11-29 Andrew Pinski <apinski@cavium.com>
694 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
695 (INSN_OCTEONP): New macro.
696 (CPU_OCTEONP): New macro.
697 (OPCODE_IS_MEMBER): Add Octeon+.
698 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
700 2011-11-01 DJ Delorie <dj@redhat.com>
704 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
706 * mips.h: Fix a typo in description.
708 2011-09-21 David S. Miller <davem@davemloft.net>
710 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
711 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
712 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
713 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
715 2011-08-09 Chao-ying Fu <fu@mips.com>
716 Maciej W. Rozycki <macro@codesourcery.com>
718 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
719 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
720 (INSN_ASE_MASK): Add the MCU bit.
721 (INSN_MCU): New macro.
722 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
723 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
725 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
727 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
728 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
729 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
730 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
731 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
732 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
733 (INSN2_READ_GPR_MMN): Likewise.
734 (INSN2_READ_FPR_D): Change the bit used.
735 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
736 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
737 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
738 (INSN2_COND_BRANCH): Likewise.
739 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
740 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
741 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
742 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
743 (INSN2_MOD_GPR_MN): Likewise.
745 2011-08-05 David S. Miller <davem@davemloft.net>
747 * sparc.h: Document new format codes '4', '5', and '('.
748 (OPF_LOW4, RS3): New macros.
750 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
752 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
753 order of flags documented.
755 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
757 * mips.h: Clarify the description of microMIPS instruction
759 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
761 2011-07-24 Chao-ying Fu <fu@mips.com>
762 Maciej W. Rozycki <macro@codesourcery.com>
764 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
765 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
766 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
767 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
768 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
769 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
770 (OP_MASK_RS3, OP_SH_RS3): Likewise.
771 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
772 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
773 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
774 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
775 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
776 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
777 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
778 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
779 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
780 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
781 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
782 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
783 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
784 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
785 (INSN_WRITE_GPR_S): New macro.
786 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
787 (INSN2_READ_FPR_D): Likewise.
788 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
789 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
790 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
791 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
792 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
793 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
794 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
795 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
796 (CPU_MICROMIPS): New macro.
797 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
798 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
799 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
800 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
801 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
802 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
803 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
804 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
805 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
806 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
807 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
808 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
809 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
810 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
811 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
812 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
813 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
814 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
815 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
816 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
817 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
818 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
819 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
820 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
821 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
822 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
823 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
824 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
825 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
826 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
827 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
828 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
829 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
830 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
831 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
832 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
833 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
834 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
835 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
836 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
837 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
838 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
839 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
840 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
841 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
842 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
843 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
844 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
845 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
846 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
847 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
848 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
849 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
850 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
851 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
852 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
853 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
854 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
855 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
856 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
857 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
858 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
859 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
860 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
861 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
862 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
863 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
864 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
865 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
866 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
867 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
868 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
869 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
870 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
871 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
872 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
873 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
874 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
875 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
876 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
877 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
878 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
879 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
880 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
881 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
882 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
883 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
884 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
885 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
886 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
887 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
888 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
889 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
890 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
891 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
892 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
893 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
894 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
895 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
896 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
897 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
898 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
899 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
900 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
901 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
902 (micromips_opcodes): New declaration.
903 (bfd_micromips_num_opcodes): Likewise.
905 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
907 * mips.h (INSN_TRAP): Rename to...
908 (INSN_NO_DELAY_SLOT): ... this.
909 (INSN_SYNC): Remove macro.
911 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
913 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
914 a duplicate of AVR_ISA_SPM.
916 2011-07-01 Nick Clifton <nickc@redhat.com>
918 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
920 2011-06-18 Robin Getz <robin.getz@analog.com>
922 * bfin.h (is_macmod_signed): New func
924 2011-06-18 Mike Frysinger <vapier@gentoo.org>
926 * bfin.h (is_macmod_pmove): Add missing space before func args.
927 (is_macmod_hmove): Likewise.
929 2011-06-13 Walter Lee <walt@tilera.com>
931 * tilegx.h: New file.
932 * tilepro.h: New file.
934 2011-05-31 Paul Brook <paul@codesourcery.com>
936 * arm.h (ARM_ARCH_V7R_IDIV): Define.
938 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
940 * s390.h: Replace S390_OPERAND_REG_EVEN with
941 S390_OPERAND_REG_PAIR.
943 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
945 * s390.h: Add S390_OPCODE_REG_EVEN flag.
947 2011-04-18 Julian Brown <julian@codesourcery.com>
949 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
951 2011-04-11 Dan McDonald <dan@wellkeeper.com>
954 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
956 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
958 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
959 New instruction set flags.
960 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
962 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
964 * mips.h (M_PREF_AB): New enum value.
966 2011-02-12 Mike Frysinger <vapier@gentoo.org>
968 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
970 (is_macmod_pmove, is_macmod_hmove): New functions.
972 2011-02-11 Mike Frysinger <vapier@gentoo.org>
974 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
976 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
978 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
979 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
981 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
984 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
987 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
990 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
992 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
994 * mips.h: Update commentary after last commit.
996 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
998 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
999 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1000 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1002 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1004 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1006 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1008 * mips.h: Fix previous commit.
1010 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1012 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1013 (INSN_LOONGSON_3A): Clear bit 31.
1015 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1018 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1019 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1020 (ARM_ARCH_V6M_ONLY): New define.
1022 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1024 * mips.h (INSN_LOONGSON_3A): Defined.
1025 (CPU_LOONGSON_3A): Defined.
1026 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1028 2010-10-09 Matt Rice <ratmice@gmail.com>
1030 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1031 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1033 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1035 * arm.h (ARM_EXT_VIRT): New define.
1036 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1037 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1040 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1042 * arm.h (ARM_AEXT_ADIV): New define.
1043 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1045 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1047 * arm.h (ARM_EXT_OS): New define.
1048 (ARM_AEXT_V6SM): Likewise.
1049 (ARM_ARCH_V6SM): Likewise.
1051 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1053 * arm.h (ARM_EXT_MP): Add.
1054 (ARM_ARCH_V7A_MP): Likewise.
1056 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1058 * bfin.h: Declare pseudoChr structs/defines.
1060 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1062 * bfin.h: Strip trailing whitespace.
1064 2010-07-29 DJ Delorie <dj@redhat.com>
1066 * rx.h (RX_Operand_Type): Add TwoReg.
1067 (RX_Opcode_ID): Remove ediv and ediv2.
1069 2010-07-27 DJ Delorie <dj@redhat.com>
1071 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1073 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1074 Ina Pandit <ina.pandit@kpitcummins.com>
1076 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1077 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1078 PROCESSOR_V850E2_ALL.
1079 Remove PROCESSOR_V850EA support.
1080 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1081 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1082 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1083 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1084 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1085 V850_OPERAND_PERCENT.
1086 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1088 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1091 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1093 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1094 (MIPS16_INSN_BRANCH): Rename to...
1095 (MIPS16_INSN_COND_BRANCH): ... this.
1097 2010-07-03 Alan Modra <amodra@gmail.com>
1099 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1100 Renumber other PPC_OPCODE defines.
1102 2010-07-03 Alan Modra <amodra@gmail.com>
1104 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1106 2010-06-29 Alan Modra <amodra@gmail.com>
1108 * maxq.h: Delete file.
1110 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1112 * ppc.h (PPC_OPCODE_E500): Define.
1114 2010-05-26 Catherine Moore <clm@codesourcery.com>
1116 * opcode/mips.h (INSN_MIPS16): Remove.
1118 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1120 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1122 2010-04-15 Nick Clifton <nickc@redhat.com>
1124 * alpha.h: Update copyright notice to use GPLv3.
1130 * convex.h: Likewise.
1137 * h8300.h: Likewise.
1144 * m68hc11.h: Likewise.
1150 * mn10200.h: Likewise.
1151 * mn10300.h: Likewise.
1152 * msp430.h: Likewise.
1154 * ns32k.h: Likewise.
1156 * pdp11.h: Likewise.
1163 * score-datadep.h: Likewise.
1164 * score-inst.h: Likewise.
1165 * sparc.h: Likewise.
1166 * spu-insns.h: Likewise.
1168 * tic30.h: Likewise.
1169 * tic4x.h: Likewise.
1170 * tic54x.h: Likewise.
1171 * tic80.h: Likewise.
1175 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1177 * tic6x-control-registers.h, tic6x-insn-formats.h,
1178 tic6x-opcode-table.h, tic6x.h: New.
1180 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1182 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1184 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1186 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1188 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1190 * ia64.h (ia64_find_opcode): Remove argument name.
1191 (ia64_find_next_opcode): Likewise.
1192 (ia64_dis_opcode): Likewise.
1193 (ia64_free_opcode): Likewise.
1194 (ia64_find_dependency): Likewise.
1196 2009-11-22 Doug Evans <dje@sebabeach.org>
1198 * cgen.h: Include bfd_stdint.h.
1199 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1201 2009-11-18 Paul Brook <paul@codesourcery.com>
1203 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1205 2009-11-17 Paul Brook <paul@codesourcery.com>
1206 Daniel Jacobowitz <dan@codesourcery.com>
1208 * arm.h (ARM_EXT_V6_DSP): Define.
1209 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1210 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1212 2009-11-04 DJ Delorie <dj@redhat.com>
1214 * rx.h (rx_decode_opcode) (mvtipl): Add.
1215 (mvtcp, mvfcp, opecp): Remove.
1217 2009-11-02 Paul Brook <paul@codesourcery.com>
1219 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1220 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1221 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1222 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1223 FPU_ARCH_NEON_VFP_V4): Define.
1225 2009-10-23 Doug Evans <dje@sebabeach.org>
1227 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1228 * cgen.h: Update. Improve multi-inclusion macro name.
1230 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1232 * ppc.h (PPC_OPCODE_476): Define.
1234 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1236 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1238 2009-09-29 DJ Delorie <dj@redhat.com>
1242 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1244 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1246 2009-09-21 Ben Elliston <bje@au.ibm.com>
1248 * ppc.h (PPC_OPCODE_PPCA2): New.
1250 2009-09-05 Martin Thuresson <martin@mtme.org>
1252 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1254 2009-08-29 Martin Thuresson <martin@mtme.org>
1256 * tic30.h (template): Rename type template to
1257 insn_template. Updated code to use new name.
1258 * tic54x.h (template): Rename type template to
1261 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1263 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1265 2009-06-11 Anthony Green <green@moxielogic.com>
1267 * moxie.h (MOXIE_F3_PCREL): Define.
1268 (moxie_form3_opc_info): Grow.
1270 2009-06-06 Anthony Green <green@moxielogic.com>
1272 * moxie.h (MOXIE_F1_M): Define.
1274 2009-04-15 Anthony Green <green@moxielogic.com>
1278 2009-04-06 DJ Delorie <dj@redhat.com>
1280 * h8300.h: Add relaxation attributes to MOVA opcodes.
1282 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1284 * ppc.h (ppc_parse_cpu): Declare.
1286 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1288 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1289 and _IMM11 for mbitclr and mbitset.
1290 * score-datadep.h: Update dependency information.
1292 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1294 * ppc.h (PPC_OPCODE_POWER7): New.
1296 2009-02-06 Doug Evans <dje@google.com>
1298 * i386.h: Add comment regarding sse* insns and prefixes.
1300 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1302 * mips.h (INSN_XLR): Define.
1303 (INSN_CHIP_MASK): Update.
1305 (OPCODE_IS_MEMBER): Update.
1306 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1308 2009-01-28 Doug Evans <dje@google.com>
1310 * opcode/i386.h: Add multiple inclusion protection.
1311 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1312 (EDI_REG_NUM): New macros.
1313 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1314 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1315 (REX_PREFIX_P): New macro.
1317 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1319 * ppc.h (struct powerpc_opcode): New field "deprecated".
1320 (PPC_OPCODE_NOPOWER4): Delete.
1322 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1324 * mips.h: Define CPU_R14000, CPU_R16000.
1325 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1327 2008-11-18 Catherine Moore <clm@codesourcery.com>
1329 * arm.h (FPU_NEON_FP16): New.
1330 (FPU_ARCH_NEON_FP16): New.
1332 2008-11-06 Chao-ying Fu <fu@mips.com>
1334 * mips.h: Doucument '1' for 5-bit sync type.
1336 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1338 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1341 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1343 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1345 2008-07-30 Michael J. Eager <eager@eagercon.com>
1347 * ppc.h (PPC_OPCODE_405): Define.
1348 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1350 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1352 * ppc.h (ppc_cpu_t): New typedef.
1353 (struct powerpc_opcode <flags>): Use it.
1354 (struct powerpc_operand <insert, extract>): Likewise.
1355 (struct powerpc_macro <flags>): Likewise.
1357 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1359 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1360 Update comment before MIPS16 field descriptors to mention MIPS16.
1361 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1363 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1364 New bit masks and shift counts for cins and exts.
1366 * mips.h: Document new field descriptors +Q.
1367 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1369 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1371 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1372 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1374 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1376 * ppc.h: (PPC_OPCODE_E500MC): New.
1378 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1380 * i386.h (MAX_OPERANDS): Set to 5.
1381 (MAX_MNEM_SIZE): Changed to 20.
1383 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1385 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1387 2008-03-09 Paul Brook <paul@codesourcery.com>
1389 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1391 2008-03-04 Paul Brook <paul@codesourcery.com>
1393 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1394 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1395 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1397 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1398 Nick Clifton <nickc@redhat.com>
1401 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1402 with a 32-bit displacement but without the top bit of the 4th byte
1405 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1407 * cr16.h (cr16_num_optab): Declared.
1409 2008-02-14 Hakan Ardo <hakan@debian.org>
1412 * avr.h (AVR_ISA_2xxe): Define.
1414 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1416 * mips.h: Update copyright.
1417 (INSN_CHIP_MASK): New macro.
1418 (INSN_OCTEON): New macro.
1419 (CPU_OCTEON): New macro.
1420 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1422 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1424 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1426 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1428 * avr.h (AVR_ISA_USB162): Add new opcode set.
1429 (AVR_ISA_AVR3): Likewise.
1431 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1433 * mips.h (INSN_LOONGSON_2E): New.
1434 (INSN_LOONGSON_2F): New.
1435 (CPU_LOONGSON_2E): New.
1436 (CPU_LOONGSON_2F): New.
1437 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1439 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1441 * mips.h (INSN_ISA*): Redefine certain values as an
1442 enumeration. Update comments.
1443 (mips_isa_table): New.
1444 (ISA_MIPS*): Redefine to match enumeration.
1445 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1448 2007-08-08 Ben Elliston <bje@au.ibm.com>
1450 * ppc.h (PPC_OPCODE_PPCPS): New.
1452 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1454 * m68k.h: Document j K & E.
1456 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1458 * cr16.h: New file for CR16 target.
1460 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1462 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1464 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1466 * m68k.h (mcfisa_c): New.
1467 (mcfusp, mcf_mask): Adjust.
1469 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1471 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1472 (num_powerpc_operands): Declare.
1473 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1474 (PPC_OPERAND_PLUS1): Define.
1476 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1478 * i386.h (REX_MODE64): Renamed to ...
1480 (REX_EXTX): Renamed to ...
1482 (REX_EXTY): Renamed to ...
1484 (REX_EXTZ): Renamed to ...
1487 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1489 * i386.h: Add entries from config/tc-i386.h and move tables
1490 to opcodes/i386-opc.h.
1492 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1494 * i386.h (FloatDR): Removed.
1495 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1497 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1499 * spu-insns.h: Add soma double-float insns.
1501 2007-02-20 Thiemo Seufer <ths@mips.com>
1502 Chao-Ying Fu <fu@mips.com>
1504 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1505 (INSN_DSPR2): Add flag for DSP R2 instructions.
1506 (M_BALIGN): New macro.
1508 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1510 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1511 and Seg3ShortFrom with Shortform.
1513 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1516 * i386.h (i386_optab): Put the real "test" before the pseudo
1519 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1521 * m68k.h (m68010up): OR fido_a.
1523 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1525 * m68k.h (fido_a): New.
1527 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1529 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1530 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1533 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1535 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1537 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1539 * score-inst.h (enum score_insn_type): Add Insn_internal.
1541 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1542 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1543 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1544 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1545 Alan Modra <amodra@bigpond.net.au>
1547 * spu-insns.h: New file.
1550 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1552 * ppc.h (PPC_OPCODE_CELL): Define.
1554 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1556 * i386.h : Modify opcode to support for the change in POPCNT opcode
1557 in amdfam10 architecture.
1559 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1561 * i386.h: Replace CpuMNI with CpuSSSE3.
1563 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1564 Joseph Myers <joseph@codesourcery.com>
1565 Ian Lance Taylor <ian@wasabisystems.com>
1566 Ben Elliston <bje@wasabisystems.com>
1568 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1570 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1572 * score-datadep.h: New file.
1573 * score-inst.h: New file.
1575 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1577 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1578 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1579 movdq2q and movq2dq.
1581 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1582 Michael Meissner <michael.meissner@amd.com>
1584 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1586 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1588 * i386.h (i386_optab): Add "nop" with memory reference.
1590 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1592 * i386.h (i386_optab): Update comment for 64bit NOP.
1594 2006-06-06 Ben Elliston <bje@au.ibm.com>
1595 Anton Blanchard <anton@samba.org>
1597 * ppc.h (PPC_OPCODE_POWER6): Define.
1600 2006-06-05 Thiemo Seufer <ths@mips.com>
1602 * mips.h: Improve description of MT flags.
1604 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1606 * m68k.h (mcf_mask): Define.
1608 2006-05-05 Thiemo Seufer <ths@mips.com>
1609 David Ung <davidu@mips.com>
1611 * mips.h (enum): Add macro M_CACHE_AB.
1613 2006-05-04 Thiemo Seufer <ths@mips.com>
1614 Nigel Stephens <nigel@mips.com>
1615 David Ung <davidu@mips.com>
1617 * mips.h: Add INSN_SMARTMIPS define.
1619 2006-04-30 Thiemo Seufer <ths@mips.com>
1620 David Ung <davidu@mips.com>
1622 * mips.h: Defines udi bits and masks. Add description of
1623 characters which may appear in the args field of udi
1626 2006-04-26 Thiemo Seufer <ths@networkno.de>
1628 * mips.h: Improve comments describing the bitfield instruction
1631 2006-04-26 Julian Brown <julian@codesourcery.com>
1633 * arm.h (FPU_VFP_EXT_V3): Define constant.
1634 (FPU_NEON_EXT_V1): Likewise.
1635 (FPU_VFP_HARD): Update.
1636 (FPU_VFP_V3): Define macro.
1637 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1639 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1641 * avr.h (AVR_ISA_PWMx): New.
1643 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1645 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1646 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1647 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1648 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1649 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1651 2006-03-10 Paul Brook <paul@codesourcery.com>
1653 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1655 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1657 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1658 first. Correct mask of bb "B" opcode.
1660 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1662 * i386.h (i386_optab): Support Intel Merom New Instructions.
1664 2006-02-24 Paul Brook <paul@codesourcery.com>
1666 * arm.h: Add V7 feature bits.
1668 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1670 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1672 2006-01-31 Paul Brook <paul@codesourcery.com>
1673 Richard Earnshaw <rearnsha@arm.com>
1675 * arm.h: Use ARM_CPU_FEATURE.
1676 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1677 (arm_feature_set): Change to a structure.
1678 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1679 ARM_FEATURE): New macros.
1681 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1683 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1684 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1685 (ADD_PC_INCR_OPCODE): Don't define.
1687 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1690 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1692 2005-11-14 David Ung <davidu@mips.com>
1694 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1695 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1696 save/restore encoding of the args field.
1698 2005-10-28 Dave Brolley <brolley@redhat.com>
1700 Contribute the following changes:
1701 2005-02-16 Dave Brolley <brolley@redhat.com>
1703 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1704 cgen_isa_mask_* to cgen_bitset_*.
1707 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1709 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1710 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1711 (CGEN_CPU_TABLE): Make isas a ponter.
1713 2003-09-29 Dave Brolley <brolley@redhat.com>
1715 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1716 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1717 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1719 2002-12-13 Dave Brolley <brolley@redhat.com>
1721 * cgen.h (symcat.h): #include it.
1722 (cgen-bitset.h): #include it.
1723 (CGEN_ATTR_VALUE_TYPE): Now a union.
1724 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1725 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1726 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1727 * cgen-bitset.h: New file.
1729 2005-09-30 Catherine Moore <clm@cm00re.com>
1733 2005-10-24 Jan Beulich <jbeulich@novell.com>
1735 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1738 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1740 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1741 Add FLAG_STRICT to pa10 ftest opcode.
1743 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1745 * hppa.h (pa_opcodes): Remove lha entries.
1747 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1749 * hppa.h (FLAG_STRICT): Revise comment.
1750 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1751 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1754 2005-09-30 Catherine Moore <clm@cm00re.com>
1758 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1760 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1762 2005-09-06 Chao-ying Fu <fu@mips.com>
1764 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1765 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1767 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1768 (INSN_ASE_MASK): Update to include INSN_MT.
1769 (INSN_MT): New define for MT ASE.
1771 2005-08-25 Chao-ying Fu <fu@mips.com>
1773 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1774 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1775 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1776 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1777 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1778 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1780 (INSN_DSP): New define for DSP ASE.
1782 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1786 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1788 * ppc.h (PPC_OPCODE_E300): Define.
1790 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1792 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1794 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1797 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1800 2005-07-27 Jan Beulich <jbeulich@novell.com>
1802 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1803 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1804 Add movq-s as 64-bit variants of movd-s.
1806 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1808 * hppa.h: Fix punctuation in comment.
1810 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1811 implicit space-register addressing. Set space-register bits on opcodes
1812 using implicit space-register addressing. Add various missing pa20
1813 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1814 space-register addressing. Use "fE" instead of "fe" in various
1817 2005-07-18 Jan Beulich <jbeulich@novell.com>
1819 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1821 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1823 * i386.h (i386_optab): Support Intel VMX Instructions.
1825 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1827 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1829 2005-07-05 Jan Beulich <jbeulich@novell.com>
1831 * i386.h (i386_optab): Add new insns.
1833 2005-07-01 Nick Clifton <nickc@redhat.com>
1835 * sparc.h: Add typedefs to structure declarations.
1837 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1840 * i386.h (i386_optab): Update comments for 64bit addressing on
1841 mov. Allow 64bit addressing for mov and movq.
1843 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1845 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1846 respectively, in various floating-point load and store patterns.
1848 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1850 * hppa.h (FLAG_STRICT): Correct comment.
1851 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1852 PA 2.0 mneumonics when equivalent. Entries with cache control
1853 completers now require PA 1.1. Adjust whitespace.
1855 2005-05-19 Anton Blanchard <anton@samba.org>
1857 * ppc.h (PPC_OPCODE_POWER5): Define.
1859 2005-05-10 Nick Clifton <nickc@redhat.com>
1861 * Update the address and phone number of the FSF organization in
1862 the GPL notices in the following files:
1863 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1864 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1865 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1866 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1867 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1868 tic54x.h, tic80.h, v850.h, vax.h
1870 2005-05-09 Jan Beulich <jbeulich@novell.com>
1872 * i386.h (i386_optab): Add ht and hnt.
1874 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1876 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1877 Add xcrypt-ctr. Provide aliases without hyphens.
1879 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1881 Moved from ../ChangeLog
1883 2005-04-12 Paul Brook <paul@codesourcery.com>
1884 * m88k.h: Rename psr macros to avoid conflicts.
1886 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1887 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1888 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1889 and ARM_ARCH_V6ZKT2.
1891 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1892 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1893 Remove redundant instruction types.
1894 (struct argument): X_op - new field.
1895 (struct cst4_entry): Remove.
1896 (no_op_insn): Declare.
1898 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1899 * crx.h (enum argtype): Rename types, remove unused types.
1901 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1902 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1903 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1904 (enum operand_type): Rearrange operands, edit comments.
1905 replace us<N> with ui<N> for unsigned immediate.
1906 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1907 displacements (respectively).
1908 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1909 (instruction type): Add NO_TYPE_INS.
1910 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1911 (operand_entry): New field - 'flags'.
1912 (operand flags): New.
1914 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1915 * crx.h (operand_type): Remove redundant types i3, i4,
1917 Add new unsigned immediate types us3, us4, us5, us16.
1919 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1921 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1922 adjust them accordingly.
1924 2005-04-01 Jan Beulich <jbeulich@novell.com>
1926 * i386.h (i386_optab): Add rdtscp.
1928 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1930 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1931 between memory and segment register. Allow movq for moving between
1932 general-purpose register and segment register.
1934 2005-02-09 Jan Beulich <jbeulich@novell.com>
1937 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1938 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1941 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1943 * m68k.h (m68008, m68ec030, m68882): Remove.
1945 (cpu_m68k, cpu_cf): New.
1946 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1947 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1949 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1951 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1952 * cgen.h (enum cgen_parse_operand_type): Add
1953 CGEN_PARSE_OPERAND_SYMBOLIC.
1955 2005-01-21 Fred Fish <fnf@specifixinc.com>
1957 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1958 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1959 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1961 2005-01-19 Fred Fish <fnf@specifixinc.com>
1963 * mips.h (struct mips_opcode): Add new pinfo2 member.
1964 (INSN_ALIAS): New define for opcode table entries that are
1965 specific instances of another entry, such as 'move' for an 'or'
1966 with a zero operand.
1967 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1968 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1970 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1972 * mips.h (CPU_RM9000): Define.
1973 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1975 2004-11-25 Jan Beulich <jbeulich@novell.com>
1977 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1978 to/from test registers are illegal in 64-bit mode. Add missing
1979 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1980 (previously one had to explicitly encode a rex64 prefix). Re-enable
1981 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1982 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1984 2004-11-23 Jan Beulich <jbeulich@novell.com>
1986 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1987 available only with SSE2. Change the MMX additions introduced by SSE
1988 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1989 instructions by their now designated identifier (since combining i686
1990 and 3DNow! does not really imply 3DNow!A).
1992 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1994 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1995 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1997 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1998 Vineet Sharma <vineets@noida.hcltech.com>
2000 * maxq.h: New file: Disassembly information for the maxq port.
2002 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2004 * i386.h (i386_optab): Put back "movzb".
2006 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
2008 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2009 comments. Remove member cris_ver_sim. Add members
2010 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2011 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2012 (struct cris_support_reg, struct cris_cond15): New types.
2013 (cris_conds15): Declare.
2014 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2015 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2016 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2017 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2018 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2019 SIZE_FIELD_UNSIGNED.
2021 2004-11-04 Jan Beulich <jbeulich@novell.com>
2023 * i386.h (sldx_Suf): Remove.
2024 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2025 (q_FP): Define, implying no REX64.
2026 (x_FP, sl_FP): Imply FloatMF.
2027 (i386_optab): Split reg and mem forms of moving from segment registers
2028 so that the memory forms can ignore the 16-/32-bit operand size
2029 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2030 all non-floating-point instructions. Unite 32- and 64-bit forms of
2031 movsx, movzx, and movd. Adjust floating point operations for the above
2032 changes to the *FP macros. Add DefaultSize to floating point control
2033 insns operating on larger memory ranges. Remove left over comments
2034 hinting at certain insns being Intel-syntax ones where the ones
2035 actually meant are already gone.
2037 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2039 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2042 2004-09-30 Paul Brook <paul@codesourcery.com>
2044 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2045 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2047 2004-09-11 Theodore A. Roth <troth@openavr.org>
2049 * avr.h: Add support for
2050 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2052 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2054 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2056 2004-08-24 Dmitry Diky <diwil@spec.ru>
2058 * msp430.h (msp430_opc): Add new instructions.
2059 (msp430_rcodes): Declare new instructions.
2060 (msp430_hcodes): Likewise..
2062 2004-08-13 Nick Clifton <nickc@redhat.com>
2065 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2068 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2070 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2072 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2074 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2076 2004-07-21 Jan Beulich <jbeulich@novell.com>
2078 * i386.h: Adjust instruction descriptions to better match the
2081 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2083 * arm.h: Remove all old content. Replace with architecture defines
2084 from gas/config/tc-arm.c.
2086 2004-07-09 Andreas Schwab <schwab@suse.de>
2088 * m68k.h: Fix comment.
2090 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2094 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2096 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2098 2004-05-24 Peter Barada <peter@the-baradas.com>
2100 * m68k.h: Add 'size' to m68k_opcode.
2102 2004-05-05 Peter Barada <peter@the-baradas.com>
2104 * m68k.h: Switch from ColdFire chip name to core variant.
2106 2004-04-22 Peter Barada <peter@the-baradas.com>
2108 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2109 descriptions for new EMAC cases.
2110 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2111 handle Motorola MAC syntax.
2112 Allow disassembly of ColdFire V4e object files.
2114 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2116 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2118 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2120 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2122 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2124 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2126 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2128 * i386.h (i386_optab): Added xstore/xcrypt insns.
2130 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2132 * h8300.h (32bit ldc/stc): Add relaxing support.
2134 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2136 * h8300.h (BITOP): Pass MEMRELAX flag.
2138 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2140 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2143 For older changes see ChangeLog-9103
2145 Copyright (C) 2004-2014 Free Software Foundation, Inc.
2147 Copying and distribution of this file, with or without modification,
2148 are permitted in any medium without royalty provided the copyright
2149 notice and this notice are preserved.
2155 version-control: never
projects / deliverable / binutils-gdb.git / blob