1 2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
5 2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
7 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
8 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
9 (NIOS2_INSN_OPTARG): Renumber.
11 2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
13 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
14 declaration. Fix obsolete comment.
16 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
18 * nios2.h (enum iw_format_type): New.
19 (struct nios2_opcode): Update comments. Add size and format fields.
20 (NIOS2_INSN_OPTARG): New.
21 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
22 (struct nios2_reg): Add regtype field.
23 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
24 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
25 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
26 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
27 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
28 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
29 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
30 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
31 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
32 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
33 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
34 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
35 (OP_MASK_OP, OP_SH_OP): Delete.
36 (OP_MASK_IOP, OP_SH_IOP): Delete.
37 (OP_MASK_IRD, OP_SH_IRD): Delete.
38 (OP_MASK_IRT, OP_SH_IRT): Delete.
39 (OP_MASK_IRS, OP_SH_IRS): Delete.
40 (OP_MASK_ROP, OP_SH_ROP): Delete.
41 (OP_MASK_RRD, OP_SH_RRD): Delete.
42 (OP_MASK_RRT, OP_SH_RRT): Delete.
43 (OP_MASK_RRS, OP_SH_RRS): Delete.
44 (OP_MASK_JOP, OP_SH_JOP): Delete.
45 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
46 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
47 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
48 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
49 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
50 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
51 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
52 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
53 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
54 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
55 (OP_MASK_<insn>, OP_MASK): Delete.
56 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
57 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
58 Include nios2r1.h to define new instruction opcode constants
60 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
61 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
62 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
63 (NUMOPCODES, NUMREGISTERS): Delete.
64 * nios2r1.h: New file.
66 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
68 * sparc.h (HWCAP2_VIS3B): Documentation improved.
70 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
72 * sparc.h (sparc_opcode): new field `hwcaps2'.
73 (HWCAP2_FJATHPLUS): New define.
74 (HWCAP2_VIS3B): Likewise.
75 (HWCAP2_ADP): Likewise.
76 (HWCAP2_SPARC5): Likewise.
77 (HWCAP2_MWAIT): Likewise.
78 (HWCAP2_XMPMUL): Likewise.
79 (HWCAP2_XMONT): Likewise.
80 (HWCAP2_NSEC): Likewise.
81 (HWCAP2_FJATHHPC): Likewise.
82 (HWCAP2_FJDES): Likewise.
83 (HWCAP2_FJAES): Likewise.
84 Document the new operand kind `{', corresponding to the mcdper
85 ancillary state register.
86 Document the new operand kind }, which represents frsd floating
87 point registers (double precision) which must be the same than
88 frs1 in its containing instruction.
90 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
92 * nds32.h: Add new opcode declaration.
94 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
95 Matthew Fortune <matthew.fortune@imgtec.com>
97 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
98 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
99 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
100 +I, +O, +R, +:, +\, +", +;
101 (mips_check_prev_operand): New struct.
102 (INSN2_FORBIDDEN_SLOT): New define.
103 (INSN_ISA32R6): New define.
104 (INSN_ISA64R6): New define.
105 (INSN_UPTO32R6): New define.
106 (INSN_UPTO64R6): New define.
107 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
108 (ISA_MIPS32R6): New define.
109 (ISA_MIPS64R6): New define.
110 (CPU_MIPS32R6): New define.
111 (CPU_MIPS64R6): New define.
112 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
114 2014-09-03 Jiong Wang <jiong.wang@arm.com>
116 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
117 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
118 (aarch64_insn_class): Add lse_atomic.
119 (F_LSE_SZ): New field added.
120 (opcode_has_special_coder): Recognize F_LSE_SZ.
122 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
124 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
127 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
129 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
130 (INSN_LOAD_COPROC): New define.
131 (INSN_COPROC_MOVE_DELAY): Rename to...
132 (INSN_COPROC_MOVE): New define.
134 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
135 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
136 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
137 Soundararajan <Sounderarajan.D@atmel.com>
139 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
140 (AVR_ISA_2xxxa): Define ISA without LPM.
141 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
142 Add doc for contraint used in 16 bit lds/sts.
143 Adjust ISA group for icall, ijmp, pop and push.
144 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
146 2014-05-19 Nick Clifton <nickc@redhat.com>
148 * msp430.h (struct msp430_operand_s): Add vshift field.
150 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
152 * mips.h (INSN_ISA_MASK): Updated.
153 (INSN_ISA32R3): New define.
154 (INSN_ISA32R5): New define.
155 (INSN_ISA64R3): New define.
156 (INSN_ISA64R5): New define.
157 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
158 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
159 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
161 (INSN_UPTO32R3): New define.
162 (INSN_UPTO32R5): New define.
163 (INSN_UPTO64R3): New define.
164 (INSN_UPTO64R5): New define.
165 (ISA_MIPS32R3): New define.
166 (ISA_MIPS32R5): New define.
167 (ISA_MIPS64R3): New define.
168 (ISA_MIPS64R5): New define.
169 (CPU_MIPS32R3): New define.
170 (CPU_MIPS32R5): New define.
171 (CPU_MIPS64R3): New define.
172 (CPU_MIPS64R5): New define.
174 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
176 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
178 2014-04-22 Christian Svensson <blue@cmd.nu>
182 2014-03-05 Alan Modra <amodra@gmail.com>
184 Update copyright years.
186 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
188 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
191 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
192 Wei-Cheng Wang <cole945@gmail.com>
194 * nds32.h: New file for Andes NDS32.
196 2013-12-07 Mike Frysinger <vapier@gentoo.org>
198 * bfin.h: Remove +x file mode.
200 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
202 * aarch64.h (aarch64_pstatefields): Change element type to
205 2013-11-18 Renlin Li <Renlin.Li@arm.com>
207 * arm.h (ARM_AEXT_V7VE): New define.
208 (ARM_ARCH_V7VE): New define.
209 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
211 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
215 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
217 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
218 (aarch64_sys_reg_writeonly_p): Ditto.
220 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
222 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
223 (aarch64_sys_reg_writeonly_p): Ditto.
225 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
227 * aarch64.h (aarch64_sys_reg): New typedef.
228 (aarch64_sys_regs): Change to define with the new type.
229 (aarch64_sys_reg_deprecated_p): Declare.
231 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
233 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
234 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
236 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
238 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
239 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
240 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
241 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
242 For MIPS, update extension character sequences after +.
243 (ASE_MSA): New define.
244 (ASE_MSA64): New define.
245 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
246 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
247 For microMIPS, update extension character sequences after +.
249 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
254 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
256 * mips.h: Remove references to "+I" and imm2_expr.
258 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
260 * mips.h (M_DEXT, M_DINS): Delete.
262 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
264 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
265 (mips_optional_operand_p): New function.
267 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
268 Richard Sandiford <rdsandiford@googlemail.com>
270 * mips.h: Document new VU0 operand characters.
271 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
272 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
273 (OP_REG_R5900_ACC): New mips_reg_operand_types.
274 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
275 (mips_vu0_channel_mask): Declare.
277 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
279 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
280 (mips_int_operand_min, mips_int_operand_max): New functions.
281 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
283 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
285 * mips.h (mips_decode_reg_operand): New function.
286 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
287 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
288 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
290 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
291 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
292 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
293 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
294 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
295 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
296 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
297 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
298 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
299 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
300 macros to cover the gaps.
301 (INSN2_MOD_SP): Replace with...
302 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
303 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
304 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
305 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
306 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
309 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
311 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
312 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
313 (MIPS16_INSN_COND_BRANCH): Delete.
315 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
316 Kirill Yukhin <kirill.yukhin@intel.com>
317 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
319 * i386.h (BND_PREFIX_OPCODE): New.
321 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
323 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
324 OP_SAVE_RESTORE_LIST.
325 (decode_mips16_operand): Declare.
327 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
329 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
330 (mips_operand, mips_int_operand, mips_mapped_int_operand)
331 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
332 (mips_pcrel_operand): New structures.
333 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
334 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
335 (decode_mips_operand, decode_micromips_operand): Declare.
337 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
339 * mips.h: Document MIPS16 "I" opcode.
341 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
343 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
344 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
345 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
346 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
347 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
348 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
349 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
350 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
351 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
352 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
353 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
354 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
355 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
357 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
358 (M_USD_AB): ...these.
360 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
362 * mips.h: Remove documentation of "[" and "]". Update documentation
363 of "k" and the MDMX formats.
365 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
367 * mips.h: Update documentation of "+s" and "+S".
369 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
371 * mips.h: Document "+i".
373 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
375 * mips.h: Remove "mi" documentation. Update "mh" documentation.
376 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
378 (INSN2_WRITE_GPR_MHI): Rename to...
379 (INSN2_WRITE_GPR_MH): ...this.
381 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
383 * mips.h: Remove documentation of "+D" and "+T".
385 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
387 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
388 Use "source" rather than "destination" for microMIPS "G".
390 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
392 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
395 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
397 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
399 2013-06-17 Catherine Moore <clm@codesourcery.com>
400 Maciej W. Rozycki <macro@codesourcery.com>
401 Chao-Ying Fu <fu@mips.com>
403 * mips.h (OP_SH_EVAOFFSET): Define.
404 (OP_MASK_EVAOFFSET): Define.
405 (INSN_ASE_MASK): Delete.
407 (M_CACHEE_AB, M_CACHEE_OB): New.
408 (M_LBE_OB, M_LBE_AB): New.
409 (M_LBUE_OB, M_LBUE_AB): New.
410 (M_LHE_OB, M_LHE_AB): New.
411 (M_LHUE_OB, M_LHUE_AB): New.
412 (M_LLE_AB, M_LLE_OB): New.
413 (M_LWE_OB, M_LWE_AB): New.
414 (M_LWLE_AB, M_LWLE_OB): New.
415 (M_LWRE_AB, M_LWRE_OB): New.
416 (M_PREFE_AB, M_PREFE_OB): New.
417 (M_SCE_AB, M_SCE_OB): New.
418 (M_SBE_OB, M_SBE_AB): New.
419 (M_SHE_OB, M_SHE_AB): New.
420 (M_SWE_OB, M_SWE_AB): New.
421 (M_SWLE_AB, M_SWLE_OB): New.
422 (M_SWRE_AB, M_SWRE_OB): New.
423 (MICROMIPSOP_SH_EVAOFFSET): Define.
424 (MICROMIPSOP_MASK_EVAOFFSET): Define.
426 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
428 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
430 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
432 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
434 2013-05-09 Andrew Pinski <apinski@cavium.com>
436 * mips.h (OP_MASK_CODE10): Correct definition.
437 (OP_SH_CODE10): Likewise.
438 Add a comment that "+J" is used now for OP_*CODE10.
439 (INSN_ASE_MASK): Update.
440 (INSN_VIRT): New macro.
441 (INSN_VIRT64): New macro
443 2013-05-02 Nick Clifton <nickc@redhat.com>
445 * msp430.h: Add patterns for MSP430X instructions.
447 2013-04-06 David S. Miller <davem@davemloft.net>
449 * sparc.h (F_PREFERRED): Define.
450 (F_PREF_ALIAS): Define.
452 2013-04-03 Nick Clifton <nickc@redhat.com>
454 * v850.h (V850_INVERSE_PCREL): Define.
456 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
459 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
461 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
464 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
466 * tic6xc-opcode-table.h: Add 16-bit insns.
467 * tic6x.h: Add support for 16-bit insns.
469 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
471 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
472 and mov.b/w/l Rs,@(d:32,ERd).
474 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
477 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
478 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
479 tic6x_operand_xregpair operand coding type.
480 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
481 opcode field, usu ORXREGD1324 for the src2 operand and remove the
484 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
487 * tic6x.h (enum tic6x_coding_method): Add
488 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
489 separately the msb and lsb of a register pair. This is needed to
490 encode the opcodes in the same way as TI assembler does.
491 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
492 and rsqrdp opcodes to use the new field coding types.
494 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
496 * arm.h (CRC_EXT_ARMV8): New constant.
497 (ARCH_CRC_ARMV8): New macro.
499 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
501 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
503 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
504 Andrew Jenner <andrew@codesourcery.com>
506 Based on patches from Altera Corporation.
510 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
512 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
514 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
517 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
519 2013-01-24 Nick Clifton <nickc@redhat.com>
521 * v850.h: Add e3v5 support.
523 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
525 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
527 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
529 * ppc.h (PPC_OPCODE_POWER8): New define.
530 (PPC_OPCODE_HTM): Likewise.
532 2013-01-10 Will Newton <will.newton@imgtec.com>
536 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
538 * cr16.h (make_instruction): Rename to cr16_make_instruction.
539 (match_opcode): Rename to cr16_match_opcode.
541 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
543 * mips.h: Add support for r5900 instructions including lq and sq.
545 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
547 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
548 (make_instruction,match_opcode): Added function prototypes.
549 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
551 2012-11-23 Alan Modra <amodra@gmail.com>
553 * ppc.h (ppc_parse_cpu): Update prototype.
555 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
557 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
558 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
560 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
562 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
564 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
566 * ia64.h (ia64_opnd): Add new operand types.
568 2012-08-21 David S. Miller <davem@davemloft.net>
570 * sparc.h (F3F4): New macro.
572 2012-08-13 Ian Bolton <ian.bolton@arm.com>
573 Laurent Desnogues <laurent.desnogues@arm.com>
574 Jim MacArthur <jim.macarthur@arm.com>
575 Marcus Shawcroft <marcus.shawcroft@arm.com>
576 Nigel Stephens <nigel.stephens@arm.com>
577 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
578 Richard Earnshaw <rearnsha@arm.com>
579 Sofiane Naci <sofiane.naci@arm.com>
580 Tejas Belagod <tejas.belagod@arm.com>
581 Yufeng Zhang <yufeng.zhang@arm.com>
583 * aarch64.h: New file.
585 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
586 Maciej W. Rozycki <macro@codesourcery.com>
588 * mips.h (mips_opcode): Add the exclusions field.
589 (OPCODE_IS_MEMBER): Remove macro.
590 (cpu_is_member): New inline function.
591 (opcode_is_member): Likewise.
593 2012-07-31 Chao-Ying Fu <fu@mips.com>
594 Catherine Moore <clm@codesourcery.com>
595 Maciej W. Rozycki <macro@codesourcery.com>
597 * mips.h: Document microMIPS DSP ASE usage.
598 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
599 microMIPS DSP ASE support.
600 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
601 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
602 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
603 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
604 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
605 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
606 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
608 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
610 * mips.h: Fix a typo in description.
612 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
614 * avr.h: (AVR_ISA_XCH): New define.
615 (AVR_ISA_XMEGA): Use it.
616 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
618 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
620 * m68hc11.h: Add XGate definitions.
621 (struct m68hc11_opcode): Add xg_mask field.
623 2012-05-14 Catherine Moore <clm@codesourcery.com>
624 Maciej W. Rozycki <macro@codesourcery.com>
625 Rhonda Wittels <rhonda@codesourcery.com>
627 * ppc.h (PPC_OPCODE_VLE): New definition.
628 (PPC_OP_SA): New macro.
629 (PPC_OP_SE_VLE): New macro.
630 (PPC_OP): Use a variable shift amount.
631 (powerpc_operand): Update comments.
632 (PPC_OPSHIFT_INV): New macro.
633 (PPC_OPERAND_CR): Replace with...
634 (PPC_OPERAND_CR_BIT): ...this and
635 (PPC_OPERAND_CR_REG): ...this.
638 2012-05-03 Sean Keys <skeys@ipdatasys.com>
640 * xgate.h: Header file for XGATE assembler.
642 2012-04-27 David S. Miller <davem@davemloft.net>
644 * sparc.h: Document new arg code' )' for crypto RS3
647 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
648 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
649 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
650 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
651 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
652 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
653 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
654 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
655 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
656 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
657 HWCAP_CBCOND, HWCAP_CRC32): New defines.
659 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
661 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
663 2012-02-27 Alan Modra <amodra@gmail.com>
665 * crx.h (cst4_map): Update declaration.
667 2012-02-25 Walter Lee <walt@tilera.com>
669 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
671 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
672 TILEPRO_OPC_LW_TLS_SN.
674 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
676 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
677 (XRELEASE_PREFIX_OPCODE): Likewise.
679 2011-12-08 Andrew Pinski <apinski@cavium.com>
680 Adam Nemet <anemet@caviumnetworks.com>
682 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
683 (INSN_OCTEON2): New macro.
684 (CPU_OCTEON2): New macro.
685 (OPCODE_IS_MEMBER): Add Octeon2.
687 2011-11-29 Andrew Pinski <apinski@cavium.com>
689 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
690 (INSN_OCTEONP): New macro.
691 (CPU_OCTEONP): New macro.
692 (OPCODE_IS_MEMBER): Add Octeon+.
693 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
695 2011-11-01 DJ Delorie <dj@redhat.com>
699 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
701 * mips.h: Fix a typo in description.
703 2011-09-21 David S. Miller <davem@davemloft.net>
705 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
706 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
707 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
708 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
710 2011-08-09 Chao-ying Fu <fu@mips.com>
711 Maciej W. Rozycki <macro@codesourcery.com>
713 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
714 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
715 (INSN_ASE_MASK): Add the MCU bit.
716 (INSN_MCU): New macro.
717 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
718 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
720 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
722 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
723 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
724 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
725 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
726 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
727 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
728 (INSN2_READ_GPR_MMN): Likewise.
729 (INSN2_READ_FPR_D): Change the bit used.
730 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
731 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
732 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
733 (INSN2_COND_BRANCH): Likewise.
734 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
735 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
736 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
737 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
738 (INSN2_MOD_GPR_MN): Likewise.
740 2011-08-05 David S. Miller <davem@davemloft.net>
742 * sparc.h: Document new format codes '4', '5', and '('.
743 (OPF_LOW4, RS3): New macros.
745 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
747 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
748 order of flags documented.
750 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
752 * mips.h: Clarify the description of microMIPS instruction
754 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
756 2011-07-24 Chao-ying Fu <fu@mips.com>
757 Maciej W. Rozycki <macro@codesourcery.com>
759 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
760 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
761 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
762 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
763 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
764 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
765 (OP_MASK_RS3, OP_SH_RS3): Likewise.
766 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
767 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
768 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
769 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
770 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
771 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
772 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
773 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
774 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
775 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
776 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
777 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
778 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
779 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
780 (INSN_WRITE_GPR_S): New macro.
781 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
782 (INSN2_READ_FPR_D): Likewise.
783 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
784 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
785 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
786 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
787 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
788 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
789 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
790 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
791 (CPU_MICROMIPS): New macro.
792 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
793 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
794 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
795 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
796 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
797 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
798 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
799 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
800 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
801 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
802 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
803 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
804 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
805 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
806 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
807 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
808 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
809 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
810 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
811 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
812 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
813 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
814 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
815 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
816 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
817 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
818 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
819 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
820 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
821 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
822 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
823 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
824 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
825 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
826 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
827 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
828 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
829 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
830 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
831 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
832 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
833 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
834 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
835 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
836 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
837 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
838 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
839 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
840 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
841 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
842 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
843 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
844 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
845 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
846 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
847 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
848 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
849 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
850 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
851 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
852 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
853 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
854 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
855 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
856 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
857 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
858 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
859 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
860 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
861 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
862 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
863 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
864 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
865 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
866 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
867 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
868 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
869 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
870 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
871 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
872 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
873 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
874 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
875 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
876 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
877 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
878 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
879 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
880 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
881 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
882 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
883 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
884 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
885 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
886 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
887 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
888 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
889 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
890 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
891 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
892 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
893 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
894 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
895 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
896 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
897 (micromips_opcodes): New declaration.
898 (bfd_micromips_num_opcodes): Likewise.
900 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
902 * mips.h (INSN_TRAP): Rename to...
903 (INSN_NO_DELAY_SLOT): ... this.
904 (INSN_SYNC): Remove macro.
906 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
908 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
909 a duplicate of AVR_ISA_SPM.
911 2011-07-01 Nick Clifton <nickc@redhat.com>
913 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
915 2011-06-18 Robin Getz <robin.getz@analog.com>
917 * bfin.h (is_macmod_signed): New func
919 2011-06-18 Mike Frysinger <vapier@gentoo.org>
921 * bfin.h (is_macmod_pmove): Add missing space before func args.
922 (is_macmod_hmove): Likewise.
924 2011-06-13 Walter Lee <walt@tilera.com>
926 * tilegx.h: New file.
927 * tilepro.h: New file.
929 2011-05-31 Paul Brook <paul@codesourcery.com>
931 * arm.h (ARM_ARCH_V7R_IDIV): Define.
933 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
935 * s390.h: Replace S390_OPERAND_REG_EVEN with
936 S390_OPERAND_REG_PAIR.
938 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
940 * s390.h: Add S390_OPCODE_REG_EVEN flag.
942 2011-04-18 Julian Brown <julian@codesourcery.com>
944 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
946 2011-04-11 Dan McDonald <dan@wellkeeper.com>
949 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
951 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
953 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
954 New instruction set flags.
955 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
957 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
959 * mips.h (M_PREF_AB): New enum value.
961 2011-02-12 Mike Frysinger <vapier@gentoo.org>
963 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
965 (is_macmod_pmove, is_macmod_hmove): New functions.
967 2011-02-11 Mike Frysinger <vapier@gentoo.org>
969 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
971 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
973 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
974 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
976 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
979 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
982 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
985 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
987 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
989 * mips.h: Update commentary after last commit.
991 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
993 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
994 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
995 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
997 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
999 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1001 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1003 * mips.h: Fix previous commit.
1005 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1007 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1008 (INSN_LOONGSON_3A): Clear bit 31.
1010 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1013 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1014 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1015 (ARM_ARCH_V6M_ONLY): New define.
1017 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1019 * mips.h (INSN_LOONGSON_3A): Defined.
1020 (CPU_LOONGSON_3A): Defined.
1021 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1023 2010-10-09 Matt Rice <ratmice@gmail.com>
1025 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1026 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1028 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1030 * arm.h (ARM_EXT_VIRT): New define.
1031 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1032 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1035 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1037 * arm.h (ARM_AEXT_ADIV): New define.
1038 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1040 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1042 * arm.h (ARM_EXT_OS): New define.
1043 (ARM_AEXT_V6SM): Likewise.
1044 (ARM_ARCH_V6SM): Likewise.
1046 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1048 * arm.h (ARM_EXT_MP): Add.
1049 (ARM_ARCH_V7A_MP): Likewise.
1051 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1053 * bfin.h: Declare pseudoChr structs/defines.
1055 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1057 * bfin.h: Strip trailing whitespace.
1059 2010-07-29 DJ Delorie <dj@redhat.com>
1061 * rx.h (RX_Operand_Type): Add TwoReg.
1062 (RX_Opcode_ID): Remove ediv and ediv2.
1064 2010-07-27 DJ Delorie <dj@redhat.com>
1066 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1068 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1069 Ina Pandit <ina.pandit@kpitcummins.com>
1071 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1072 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1073 PROCESSOR_V850E2_ALL.
1074 Remove PROCESSOR_V850EA support.
1075 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1076 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1077 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1078 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1079 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1080 V850_OPERAND_PERCENT.
1081 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1083 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1086 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1088 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1089 (MIPS16_INSN_BRANCH): Rename to...
1090 (MIPS16_INSN_COND_BRANCH): ... this.
1092 2010-07-03 Alan Modra <amodra@gmail.com>
1094 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1095 Renumber other PPC_OPCODE defines.
1097 2010-07-03 Alan Modra <amodra@gmail.com>
1099 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1101 2010-06-29 Alan Modra <amodra@gmail.com>
1103 * maxq.h: Delete file.
1105 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1107 * ppc.h (PPC_OPCODE_E500): Define.
1109 2010-05-26 Catherine Moore <clm@codesourcery.com>
1111 * opcode/mips.h (INSN_MIPS16): Remove.
1113 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1115 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1117 2010-04-15 Nick Clifton <nickc@redhat.com>
1119 * alpha.h: Update copyright notice to use GPLv3.
1125 * convex.h: Likewise.
1132 * h8300.h: Likewise.
1139 * m68hc11.h: Likewise.
1145 * mn10200.h: Likewise.
1146 * mn10300.h: Likewise.
1147 * msp430.h: Likewise.
1149 * ns32k.h: Likewise.
1151 * pdp11.h: Likewise.
1158 * score-datadep.h: Likewise.
1159 * score-inst.h: Likewise.
1160 * sparc.h: Likewise.
1161 * spu-insns.h: Likewise.
1163 * tic30.h: Likewise.
1164 * tic4x.h: Likewise.
1165 * tic54x.h: Likewise.
1166 * tic80.h: Likewise.
1170 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1172 * tic6x-control-registers.h, tic6x-insn-formats.h,
1173 tic6x-opcode-table.h, tic6x.h: New.
1175 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1177 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1179 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1181 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1183 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1185 * ia64.h (ia64_find_opcode): Remove argument name.
1186 (ia64_find_next_opcode): Likewise.
1187 (ia64_dis_opcode): Likewise.
1188 (ia64_free_opcode): Likewise.
1189 (ia64_find_dependency): Likewise.
1191 2009-11-22 Doug Evans <dje@sebabeach.org>
1193 * cgen.h: Include bfd_stdint.h.
1194 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1196 2009-11-18 Paul Brook <paul@codesourcery.com>
1198 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1200 2009-11-17 Paul Brook <paul@codesourcery.com>
1201 Daniel Jacobowitz <dan@codesourcery.com>
1203 * arm.h (ARM_EXT_V6_DSP): Define.
1204 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1205 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1207 2009-11-04 DJ Delorie <dj@redhat.com>
1209 * rx.h (rx_decode_opcode) (mvtipl): Add.
1210 (mvtcp, mvfcp, opecp): Remove.
1212 2009-11-02 Paul Brook <paul@codesourcery.com>
1214 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1215 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1216 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1217 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1218 FPU_ARCH_NEON_VFP_V4): Define.
1220 2009-10-23 Doug Evans <dje@sebabeach.org>
1222 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1223 * cgen.h: Update. Improve multi-inclusion macro name.
1225 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1227 * ppc.h (PPC_OPCODE_476): Define.
1229 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1231 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1233 2009-09-29 DJ Delorie <dj@redhat.com>
1237 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1239 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1241 2009-09-21 Ben Elliston <bje@au.ibm.com>
1243 * ppc.h (PPC_OPCODE_PPCA2): New.
1245 2009-09-05 Martin Thuresson <martin@mtme.org>
1247 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1249 2009-08-29 Martin Thuresson <martin@mtme.org>
1251 * tic30.h (template): Rename type template to
1252 insn_template. Updated code to use new name.
1253 * tic54x.h (template): Rename type template to
1256 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1258 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1260 2009-06-11 Anthony Green <green@moxielogic.com>
1262 * moxie.h (MOXIE_F3_PCREL): Define.
1263 (moxie_form3_opc_info): Grow.
1265 2009-06-06 Anthony Green <green@moxielogic.com>
1267 * moxie.h (MOXIE_F1_M): Define.
1269 2009-04-15 Anthony Green <green@moxielogic.com>
1273 2009-04-06 DJ Delorie <dj@redhat.com>
1275 * h8300.h: Add relaxation attributes to MOVA opcodes.
1277 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1279 * ppc.h (ppc_parse_cpu): Declare.
1281 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1283 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1284 and _IMM11 for mbitclr and mbitset.
1285 * score-datadep.h: Update dependency information.
1287 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1289 * ppc.h (PPC_OPCODE_POWER7): New.
1291 2009-02-06 Doug Evans <dje@google.com>
1293 * i386.h: Add comment regarding sse* insns and prefixes.
1295 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1297 * mips.h (INSN_XLR): Define.
1298 (INSN_CHIP_MASK): Update.
1300 (OPCODE_IS_MEMBER): Update.
1301 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1303 2009-01-28 Doug Evans <dje@google.com>
1305 * opcode/i386.h: Add multiple inclusion protection.
1306 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1307 (EDI_REG_NUM): New macros.
1308 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1309 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1310 (REX_PREFIX_P): New macro.
1312 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1314 * ppc.h (struct powerpc_opcode): New field "deprecated".
1315 (PPC_OPCODE_NOPOWER4): Delete.
1317 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1319 * mips.h: Define CPU_R14000, CPU_R16000.
1320 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1322 2008-11-18 Catherine Moore <clm@codesourcery.com>
1324 * arm.h (FPU_NEON_FP16): New.
1325 (FPU_ARCH_NEON_FP16): New.
1327 2008-11-06 Chao-ying Fu <fu@mips.com>
1329 * mips.h: Doucument '1' for 5-bit sync type.
1331 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1333 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1336 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1338 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1340 2008-07-30 Michael J. Eager <eager@eagercon.com>
1342 * ppc.h (PPC_OPCODE_405): Define.
1343 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1345 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1347 * ppc.h (ppc_cpu_t): New typedef.
1348 (struct powerpc_opcode <flags>): Use it.
1349 (struct powerpc_operand <insert, extract>): Likewise.
1350 (struct powerpc_macro <flags>): Likewise.
1352 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1354 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1355 Update comment before MIPS16 field descriptors to mention MIPS16.
1356 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1358 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1359 New bit masks and shift counts for cins and exts.
1361 * mips.h: Document new field descriptors +Q.
1362 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1364 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1366 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1367 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1369 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1371 * ppc.h: (PPC_OPCODE_E500MC): New.
1373 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1375 * i386.h (MAX_OPERANDS): Set to 5.
1376 (MAX_MNEM_SIZE): Changed to 20.
1378 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1380 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1382 2008-03-09 Paul Brook <paul@codesourcery.com>
1384 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1386 2008-03-04 Paul Brook <paul@codesourcery.com>
1388 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1389 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1390 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1392 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1393 Nick Clifton <nickc@redhat.com>
1396 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1397 with a 32-bit displacement but without the top bit of the 4th byte
1400 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1402 * cr16.h (cr16_num_optab): Declared.
1404 2008-02-14 Hakan Ardo <hakan@debian.org>
1407 * avr.h (AVR_ISA_2xxe): Define.
1409 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1411 * mips.h: Update copyright.
1412 (INSN_CHIP_MASK): New macro.
1413 (INSN_OCTEON): New macro.
1414 (CPU_OCTEON): New macro.
1415 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1417 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1419 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1421 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1423 * avr.h (AVR_ISA_USB162): Add new opcode set.
1424 (AVR_ISA_AVR3): Likewise.
1426 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1428 * mips.h (INSN_LOONGSON_2E): New.
1429 (INSN_LOONGSON_2F): New.
1430 (CPU_LOONGSON_2E): New.
1431 (CPU_LOONGSON_2F): New.
1432 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1434 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1436 * mips.h (INSN_ISA*): Redefine certain values as an
1437 enumeration. Update comments.
1438 (mips_isa_table): New.
1439 (ISA_MIPS*): Redefine to match enumeration.
1440 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1443 2007-08-08 Ben Elliston <bje@au.ibm.com>
1445 * ppc.h (PPC_OPCODE_PPCPS): New.
1447 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1449 * m68k.h: Document j K & E.
1451 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1453 * cr16.h: New file for CR16 target.
1455 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1457 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1459 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1461 * m68k.h (mcfisa_c): New.
1462 (mcfusp, mcf_mask): Adjust.
1464 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1466 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1467 (num_powerpc_operands): Declare.
1468 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1469 (PPC_OPERAND_PLUS1): Define.
1471 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1473 * i386.h (REX_MODE64): Renamed to ...
1475 (REX_EXTX): Renamed to ...
1477 (REX_EXTY): Renamed to ...
1479 (REX_EXTZ): Renamed to ...
1482 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1484 * i386.h: Add entries from config/tc-i386.h and move tables
1485 to opcodes/i386-opc.h.
1487 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1489 * i386.h (FloatDR): Removed.
1490 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1492 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1494 * spu-insns.h: Add soma double-float insns.
1496 2007-02-20 Thiemo Seufer <ths@mips.com>
1497 Chao-Ying Fu <fu@mips.com>
1499 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1500 (INSN_DSPR2): Add flag for DSP R2 instructions.
1501 (M_BALIGN): New macro.
1503 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1505 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1506 and Seg3ShortFrom with Shortform.
1508 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1511 * i386.h (i386_optab): Put the real "test" before the pseudo
1514 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1516 * m68k.h (m68010up): OR fido_a.
1518 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1520 * m68k.h (fido_a): New.
1522 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1524 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1525 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1528 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1530 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1532 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1534 * score-inst.h (enum score_insn_type): Add Insn_internal.
1536 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1537 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1538 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1539 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1540 Alan Modra <amodra@bigpond.net.au>
1542 * spu-insns.h: New file.
1545 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1547 * ppc.h (PPC_OPCODE_CELL): Define.
1549 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1551 * i386.h : Modify opcode to support for the change in POPCNT opcode
1552 in amdfam10 architecture.
1554 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1556 * i386.h: Replace CpuMNI with CpuSSSE3.
1558 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1559 Joseph Myers <joseph@codesourcery.com>
1560 Ian Lance Taylor <ian@wasabisystems.com>
1561 Ben Elliston <bje@wasabisystems.com>
1563 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1565 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1567 * score-datadep.h: New file.
1568 * score-inst.h: New file.
1570 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1572 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1573 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1574 movdq2q and movq2dq.
1576 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1577 Michael Meissner <michael.meissner@amd.com>
1579 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1581 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1583 * i386.h (i386_optab): Add "nop" with memory reference.
1585 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1587 * i386.h (i386_optab): Update comment for 64bit NOP.
1589 2006-06-06 Ben Elliston <bje@au.ibm.com>
1590 Anton Blanchard <anton@samba.org>
1592 * ppc.h (PPC_OPCODE_POWER6): Define.
1595 2006-06-05 Thiemo Seufer <ths@mips.com>
1597 * mips.h: Improve description of MT flags.
1599 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1601 * m68k.h (mcf_mask): Define.
1603 2006-05-05 Thiemo Seufer <ths@mips.com>
1604 David Ung <davidu@mips.com>
1606 * mips.h (enum): Add macro M_CACHE_AB.
1608 2006-05-04 Thiemo Seufer <ths@mips.com>
1609 Nigel Stephens <nigel@mips.com>
1610 David Ung <davidu@mips.com>
1612 * mips.h: Add INSN_SMARTMIPS define.
1614 2006-04-30 Thiemo Seufer <ths@mips.com>
1615 David Ung <davidu@mips.com>
1617 * mips.h: Defines udi bits and masks. Add description of
1618 characters which may appear in the args field of udi
1621 2006-04-26 Thiemo Seufer <ths@networkno.de>
1623 * mips.h: Improve comments describing the bitfield instruction
1626 2006-04-26 Julian Brown <julian@codesourcery.com>
1628 * arm.h (FPU_VFP_EXT_V3): Define constant.
1629 (FPU_NEON_EXT_V1): Likewise.
1630 (FPU_VFP_HARD): Update.
1631 (FPU_VFP_V3): Define macro.
1632 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1634 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1636 * avr.h (AVR_ISA_PWMx): New.
1638 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1640 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1641 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1642 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1643 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1644 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1646 2006-03-10 Paul Brook <paul@codesourcery.com>
1648 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1650 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1652 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1653 first. Correct mask of bb "B" opcode.
1655 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1657 * i386.h (i386_optab): Support Intel Merom New Instructions.
1659 2006-02-24 Paul Brook <paul@codesourcery.com>
1661 * arm.h: Add V7 feature bits.
1663 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1665 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1667 2006-01-31 Paul Brook <paul@codesourcery.com>
1668 Richard Earnshaw <rearnsha@arm.com>
1670 * arm.h: Use ARM_CPU_FEATURE.
1671 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1672 (arm_feature_set): Change to a structure.
1673 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1674 ARM_FEATURE): New macros.
1676 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1678 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1679 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1680 (ADD_PC_INCR_OPCODE): Don't define.
1682 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1685 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1687 2005-11-14 David Ung <davidu@mips.com>
1689 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1690 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1691 save/restore encoding of the args field.
1693 2005-10-28 Dave Brolley <brolley@redhat.com>
1695 Contribute the following changes:
1696 2005-02-16 Dave Brolley <brolley@redhat.com>
1698 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1699 cgen_isa_mask_* to cgen_bitset_*.
1702 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1704 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1705 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1706 (CGEN_CPU_TABLE): Make isas a ponter.
1708 2003-09-29 Dave Brolley <brolley@redhat.com>
1710 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1711 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1712 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1714 2002-12-13 Dave Brolley <brolley@redhat.com>
1716 * cgen.h (symcat.h): #include it.
1717 (cgen-bitset.h): #include it.
1718 (CGEN_ATTR_VALUE_TYPE): Now a union.
1719 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1720 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1721 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1722 * cgen-bitset.h: New file.
1724 2005-09-30 Catherine Moore <clm@cm00re.com>
1728 2005-10-24 Jan Beulich <jbeulich@novell.com>
1730 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1733 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1735 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1736 Add FLAG_STRICT to pa10 ftest opcode.
1738 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1740 * hppa.h (pa_opcodes): Remove lha entries.
1742 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1744 * hppa.h (FLAG_STRICT): Revise comment.
1745 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1746 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1749 2005-09-30 Catherine Moore <clm@cm00re.com>
1753 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1755 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1757 2005-09-06 Chao-ying Fu <fu@mips.com>
1759 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1760 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1762 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1763 (INSN_ASE_MASK): Update to include INSN_MT.
1764 (INSN_MT): New define for MT ASE.
1766 2005-08-25 Chao-ying Fu <fu@mips.com>
1768 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1769 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1770 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1771 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1772 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1773 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1775 (INSN_DSP): New define for DSP ASE.
1777 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1781 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1783 * ppc.h (PPC_OPCODE_E300): Define.
1785 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1787 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1789 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1792 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1795 2005-07-27 Jan Beulich <jbeulich@novell.com>
1797 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1798 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1799 Add movq-s as 64-bit variants of movd-s.
1801 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1803 * hppa.h: Fix punctuation in comment.
1805 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1806 implicit space-register addressing. Set space-register bits on opcodes
1807 using implicit space-register addressing. Add various missing pa20
1808 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1809 space-register addressing. Use "fE" instead of "fe" in various
1812 2005-07-18 Jan Beulich <jbeulich@novell.com>
1814 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1816 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1818 * i386.h (i386_optab): Support Intel VMX Instructions.
1820 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1822 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1824 2005-07-05 Jan Beulich <jbeulich@novell.com>
1826 * i386.h (i386_optab): Add new insns.
1828 2005-07-01 Nick Clifton <nickc@redhat.com>
1830 * sparc.h: Add typedefs to structure declarations.
1832 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1835 * i386.h (i386_optab): Update comments for 64bit addressing on
1836 mov. Allow 64bit addressing for mov and movq.
1838 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1840 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1841 respectively, in various floating-point load and store patterns.
1843 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1845 * hppa.h (FLAG_STRICT): Correct comment.
1846 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1847 PA 2.0 mneumonics when equivalent. Entries with cache control
1848 completers now require PA 1.1. Adjust whitespace.
1850 2005-05-19 Anton Blanchard <anton@samba.org>
1852 * ppc.h (PPC_OPCODE_POWER5): Define.
1854 2005-05-10 Nick Clifton <nickc@redhat.com>
1856 * Update the address and phone number of the FSF organization in
1857 the GPL notices in the following files:
1858 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1859 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1860 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1861 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1862 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1863 tic54x.h, tic80.h, v850.h, vax.h
1865 2005-05-09 Jan Beulich <jbeulich@novell.com>
1867 * i386.h (i386_optab): Add ht and hnt.
1869 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1871 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1872 Add xcrypt-ctr. Provide aliases without hyphens.
1874 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1876 Moved from ../ChangeLog
1878 2005-04-12 Paul Brook <paul@codesourcery.com>
1879 * m88k.h: Rename psr macros to avoid conflicts.
1881 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1882 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1883 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1884 and ARM_ARCH_V6ZKT2.
1886 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1887 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1888 Remove redundant instruction types.
1889 (struct argument): X_op - new field.
1890 (struct cst4_entry): Remove.
1891 (no_op_insn): Declare.
1893 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1894 * crx.h (enum argtype): Rename types, remove unused types.
1896 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1897 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1898 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1899 (enum operand_type): Rearrange operands, edit comments.
1900 replace us<N> with ui<N> for unsigned immediate.
1901 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1902 displacements (respectively).
1903 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1904 (instruction type): Add NO_TYPE_INS.
1905 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1906 (operand_entry): New field - 'flags'.
1907 (operand flags): New.
1909 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1910 * crx.h (operand_type): Remove redundant types i3, i4,
1912 Add new unsigned immediate types us3, us4, us5, us16.
1914 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1916 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1917 adjust them accordingly.
1919 2005-04-01 Jan Beulich <jbeulich@novell.com>
1921 * i386.h (i386_optab): Add rdtscp.
1923 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1925 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1926 between memory and segment register. Allow movq for moving between
1927 general-purpose register and segment register.
1929 2005-02-09 Jan Beulich <jbeulich@novell.com>
1932 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1933 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1936 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1938 * m68k.h (m68008, m68ec030, m68882): Remove.
1940 (cpu_m68k, cpu_cf): New.
1941 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1942 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1944 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1946 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1947 * cgen.h (enum cgen_parse_operand_type): Add
1948 CGEN_PARSE_OPERAND_SYMBOLIC.
1950 2005-01-21 Fred Fish <fnf@specifixinc.com>
1952 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1953 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1954 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1956 2005-01-19 Fred Fish <fnf@specifixinc.com>
1958 * mips.h (struct mips_opcode): Add new pinfo2 member.
1959 (INSN_ALIAS): New define for opcode table entries that are
1960 specific instances of another entry, such as 'move' for an 'or'
1961 with a zero operand.
1962 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1963 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1965 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1967 * mips.h (CPU_RM9000): Define.
1968 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1970 2004-11-25 Jan Beulich <jbeulich@novell.com>
1972 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1973 to/from test registers are illegal in 64-bit mode. Add missing
1974 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1975 (previously one had to explicitly encode a rex64 prefix). Re-enable
1976 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1977 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1979 2004-11-23 Jan Beulich <jbeulich@novell.com>
1981 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1982 available only with SSE2. Change the MMX additions introduced by SSE
1983 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1984 instructions by their now designated identifier (since combining i686
1985 and 3DNow! does not really imply 3DNow!A).
1987 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1989 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1990 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1992 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1993 Vineet Sharma <vineets@noida.hcltech.com>
1995 * maxq.h: New file: Disassembly information for the maxq port.
1997 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1999 * i386.h (i386_optab): Put back "movzb".
2001 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
2003 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2004 comments. Remove member cris_ver_sim. Add members
2005 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2006 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2007 (struct cris_support_reg, struct cris_cond15): New types.
2008 (cris_conds15): Declare.
2009 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2010 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2011 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2012 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2013 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2014 SIZE_FIELD_UNSIGNED.
2016 2004-11-04 Jan Beulich <jbeulich@novell.com>
2018 * i386.h (sldx_Suf): Remove.
2019 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2020 (q_FP): Define, implying no REX64.
2021 (x_FP, sl_FP): Imply FloatMF.
2022 (i386_optab): Split reg and mem forms of moving from segment registers
2023 so that the memory forms can ignore the 16-/32-bit operand size
2024 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2025 all non-floating-point instructions. Unite 32- and 64-bit forms of
2026 movsx, movzx, and movd. Adjust floating point operations for the above
2027 changes to the *FP macros. Add DefaultSize to floating point control
2028 insns operating on larger memory ranges. Remove left over comments
2029 hinting at certain insns being Intel-syntax ones where the ones
2030 actually meant are already gone.
2032 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2034 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2037 2004-09-30 Paul Brook <paul@codesourcery.com>
2039 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2040 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2042 2004-09-11 Theodore A. Roth <troth@openavr.org>
2044 * avr.h: Add support for
2045 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2047 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2049 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2051 2004-08-24 Dmitry Diky <diwil@spec.ru>
2053 * msp430.h (msp430_opc): Add new instructions.
2054 (msp430_rcodes): Declare new instructions.
2055 (msp430_hcodes): Likewise..
2057 2004-08-13 Nick Clifton <nickc@redhat.com>
2060 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2063 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2065 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2067 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2069 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2071 2004-07-21 Jan Beulich <jbeulich@novell.com>
2073 * i386.h: Adjust instruction descriptions to better match the
2076 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2078 * arm.h: Remove all old content. Replace with architecture defines
2079 from gas/config/tc-arm.c.
2081 2004-07-09 Andreas Schwab <schwab@suse.de>
2083 * m68k.h: Fix comment.
2085 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2089 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2091 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2093 2004-05-24 Peter Barada <peter@the-baradas.com>
2095 * m68k.h: Add 'size' to m68k_opcode.
2097 2004-05-05 Peter Barada <peter@the-baradas.com>
2099 * m68k.h: Switch from ColdFire chip name to core variant.
2101 2004-04-22 Peter Barada <peter@the-baradas.com>
2103 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2104 descriptions for new EMAC cases.
2105 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2106 handle Motorola MAC syntax.
2107 Allow disassembly of ColdFire V4e object files.
2109 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2111 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2113 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2115 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2117 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2119 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2121 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2123 * i386.h (i386_optab): Added xstore/xcrypt insns.
2125 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2127 * h8300.h (32bit ldc/stc): Add relaxing support.
2129 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2131 * h8300.h (BITOP): Pass MEMRELAX flag.
2133 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2135 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2138 For older changes see ChangeLog-9103
2140 Copyright (C) 2004-2014 Free Software Foundation, Inc.
2142 Copying and distribution of this file, with or without modification,
2143 are permitted in any medium without royalty provided the copyright
2144 notice and this notice are preserved.
2150 version-control: never
projects / deliverable / binutils-gdb.git / blob