1 2012-08-13 Ian Bolton <ian.bolton@arm.com>
2 Laurent Desnogues <laurent.desnogues@arm.com>
3 Jim MacArthur <jim.macarthur@arm.com>
4 Marcus Shawcroft <marcus.shawcroft@arm.com>
5 Nigel Stephens <nigel.stephens@arm.com>
6 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
7 Richard Earnshaw <rearnsha@arm.com>
8 Sofiane Naci <sofiane.naci@arm.com>
9 Tejas Belagod <tejas.belagod@arm.com>
10 Yufeng Zhang <yufeng.zhang@arm.com>
12 * aarch64.h: New file.
14 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
15 Maciej W. Rozycki <macro@codesourcery.com>
17 * mips.h (mips_opcode): Add the exclusions field.
18 (OPCODE_IS_MEMBER): Remove macro.
19 (cpu_is_member): New inline function.
20 (opcode_is_member): Likewise.
22 2012-07-31 Chao-Ying Fu <fu@mips.com>
23 Catherine Moore <clm@codesourcery.com>
24 Maciej W. Rozycki <macro@codesourcery.com>
26 * mips.h: Document microMIPS DSP ASE usage.
27 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
28 microMIPS DSP ASE support.
29 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
30 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
31 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
32 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
33 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
34 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
35 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
37 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
39 * mips.h: Fix a typo in description.
41 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
43 * avr.h: (AVR_ISA_XCH): New define.
44 (AVR_ISA_XMEGA): Use it.
45 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
47 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
49 * m68hc11.h: Add XGate definitions.
50 (struct m68hc11_opcode): Add xg_mask field.
52 2012-05-14 Catherine Moore <clm@codesourcery.com>
53 Maciej W. Rozycki <macro@codesourcery.com>
54 Rhonda Wittels <rhonda@codesourcery.com>
56 * ppc.h (PPC_OPCODE_VLE): New definition.
57 (PPC_OP_SA): New macro.
58 (PPC_OP_SE_VLE): New macro.
59 (PPC_OP): Use a variable shift amount.
60 (powerpc_operand): Update comments.
61 (PPC_OPSHIFT_INV): New macro.
62 (PPC_OPERAND_CR): Replace with...
63 (PPC_OPERAND_CR_BIT): ...this and
64 (PPC_OPERAND_CR_REG): ...this.
67 2012-05-03 Sean Keys <skeys@ipdatasys.com>
69 * xgate.h: Header file for XGATE assembler.
71 2012-04-27 David S. Miller <davem@davemloft.net>
73 * sparc.h: Document new arg code' )' for crypto RS3
76 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
77 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
78 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
79 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
80 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
81 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
82 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
83 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
84 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
85 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
86 HWCAP_CBCOND, HWCAP_CRC32): New defines.
88 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
90 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
92 2012-02-27 Alan Modra <amodra@gmail.com>
94 * crx.h (cst4_map): Update declaration.
96 2012-02-25 Walter Lee <walt@tilera.com>
98 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
100 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
101 TILEPRO_OPC_LW_TLS_SN.
103 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
105 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
106 (XRELEASE_PREFIX_OPCODE): Likewise.
108 2011-12-08 Andrew Pinski <apinski@cavium.com>
109 Adam Nemet <anemet@caviumnetworks.com>
111 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
112 (INSN_OCTEON2): New macro.
113 (CPU_OCTEON2): New macro.
114 (OPCODE_IS_MEMBER): Add Octeon2.
116 2011-11-29 Andrew Pinski <apinski@cavium.com>
118 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
119 (INSN_OCTEONP): New macro.
120 (CPU_OCTEONP): New macro.
121 (OPCODE_IS_MEMBER): Add Octeon+.
122 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
124 2011-11-01 DJ Delorie <dj@redhat.com>
128 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
130 * mips.h: Fix a typo in description.
132 2011-09-21 David S. Miller <davem@davemloft.net>
134 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
135 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
136 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
137 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
139 2011-08-09 Chao-ying Fu <fu@mips.com>
140 Maciej W. Rozycki <macro@codesourcery.com>
142 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
143 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
144 (INSN_ASE_MASK): Add the MCU bit.
145 (INSN_MCU): New macro.
146 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
147 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
149 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
151 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
152 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
153 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
154 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
155 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
156 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
157 (INSN2_READ_GPR_MMN): Likewise.
158 (INSN2_READ_FPR_D): Change the bit used.
159 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
160 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
161 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
162 (INSN2_COND_BRANCH): Likewise.
163 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
164 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
165 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
166 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
167 (INSN2_MOD_GPR_MN): Likewise.
169 2011-08-05 David S. Miller <davem@davemloft.net>
171 * sparc.h: Document new format codes '4', '5', and '('.
172 (OPF_LOW4, RS3): New macros.
174 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
176 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
177 order of flags documented.
179 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
181 * mips.h: Clarify the description of microMIPS instruction
183 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
185 2011-07-24 Chao-ying Fu <fu@mips.com>
186 Maciej W. Rozycki <macro@codesourcery.com>
188 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
189 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
190 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
191 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
192 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
193 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
194 (OP_MASK_RS3, OP_SH_RS3): Likewise.
195 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
196 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
197 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
198 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
199 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
200 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
201 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
202 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
203 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
204 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
205 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
206 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
207 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
208 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
209 (INSN_WRITE_GPR_S): New macro.
210 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
211 (INSN2_READ_FPR_D): Likewise.
212 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
213 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
214 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
215 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
216 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
217 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
218 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
219 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
220 (CPU_MICROMIPS): New macro.
221 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
222 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
223 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
224 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
225 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
226 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
227 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
228 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
229 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
230 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
231 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
232 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
233 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
234 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
235 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
236 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
237 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
238 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
239 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
240 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
241 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
242 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
243 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
244 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
245 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
246 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
247 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
248 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
249 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
250 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
251 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
252 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
253 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
254 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
255 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
256 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
257 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
258 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
259 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
260 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
261 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
262 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
263 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
264 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
265 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
266 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
267 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
268 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
269 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
270 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
271 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
272 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
273 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
274 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
275 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
276 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
277 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
278 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
279 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
280 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
281 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
282 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
283 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
284 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
285 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
286 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
287 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
288 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
289 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
290 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
291 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
292 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
293 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
294 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
295 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
296 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
297 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
298 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
299 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
300 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
301 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
302 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
303 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
304 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
305 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
306 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
307 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
308 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
309 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
310 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
311 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
312 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
313 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
314 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
315 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
316 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
317 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
318 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
319 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
320 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
321 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
322 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
323 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
324 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
325 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
326 (micromips_opcodes): New declaration.
327 (bfd_micromips_num_opcodes): Likewise.
329 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
331 * mips.h (INSN_TRAP): Rename to...
332 (INSN_NO_DELAY_SLOT): ... this.
333 (INSN_SYNC): Remove macro.
335 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
337 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
338 a duplicate of AVR_ISA_SPM.
340 2011-07-01 Nick Clifton <nickc@redhat.com>
342 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
344 2011-06-18 Robin Getz <robin.getz@analog.com>
346 * bfin.h (is_macmod_signed): New func
348 2011-06-18 Mike Frysinger <vapier@gentoo.org>
350 * bfin.h (is_macmod_pmove): Add missing space before func args.
351 (is_macmod_hmove): Likewise.
353 2011-06-13 Walter Lee <walt@tilera.com>
355 * tilegx.h: New file.
356 * tilepro.h: New file.
358 2011-05-31 Paul Brook <paul@codesourcery.com>
360 * arm.h (ARM_ARCH_V7R_IDIV): Define.
362 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
364 * s390.h: Replace S390_OPERAND_REG_EVEN with
365 S390_OPERAND_REG_PAIR.
367 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
369 * s390.h: Add S390_OPCODE_REG_EVEN flag.
371 2011-04-18 Julian Brown <julian@codesourcery.com>
373 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
375 2011-04-11 Dan McDonald <dan@wellkeeper.com>
378 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
380 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
382 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
383 New instruction set flags.
384 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
386 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
388 * mips.h (M_PREF_AB): New enum value.
390 2011-02-12 Mike Frysinger <vapier@gentoo.org>
392 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
394 (is_macmod_pmove, is_macmod_hmove): New functions.
396 2011-02-11 Mike Frysinger <vapier@gentoo.org>
398 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
400 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
402 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
403 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
405 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
408 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
411 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
414 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
416 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
418 * mips.h: Update commentary after last commit.
420 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
422 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
423 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
424 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
426 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
428 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
430 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
432 * mips.h: Fix previous commit.
434 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
436 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
437 (INSN_LOONGSON_3A): Clear bit 31.
439 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
442 * arm.h (ARM_AEXT_V6M_ONLY): New define.
443 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
444 (ARM_ARCH_V6M_ONLY): New define.
446 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
448 * mips.h (INSN_LOONGSON_3A): Defined.
449 (CPU_LOONGSON_3A): Defined.
450 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
452 2010-10-09 Matt Rice <ratmice@gmail.com>
454 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
455 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
457 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
459 * arm.h (ARM_EXT_VIRT): New define.
460 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
461 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
464 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
466 * arm.h (ARM_AEXT_ADIV): New define.
467 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
469 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
471 * arm.h (ARM_EXT_OS): New define.
472 (ARM_AEXT_V6SM): Likewise.
473 (ARM_ARCH_V6SM): Likewise.
475 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
477 * arm.h (ARM_EXT_MP): Add.
478 (ARM_ARCH_V7A_MP): Likewise.
480 2010-09-22 Mike Frysinger <vapier@gentoo.org>
482 * bfin.h: Declare pseudoChr structs/defines.
484 2010-09-21 Mike Frysinger <vapier@gentoo.org>
486 * bfin.h: Strip trailing whitespace.
488 2010-07-29 DJ Delorie <dj@redhat.com>
490 * rx.h (RX_Operand_Type): Add TwoReg.
491 (RX_Opcode_ID): Remove ediv and ediv2.
493 2010-07-27 DJ Delorie <dj@redhat.com>
495 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
497 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
498 Ina Pandit <ina.pandit@kpitcummins.com>
500 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
501 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
502 PROCESSOR_V850E2_ALL.
503 Remove PROCESSOR_V850EA support.
504 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
505 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
506 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
507 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
508 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
509 V850_OPERAND_PERCENT.
510 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
512 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
515 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
517 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
518 (MIPS16_INSN_BRANCH): Rename to...
519 (MIPS16_INSN_COND_BRANCH): ... this.
521 2010-07-03 Alan Modra <amodra@gmail.com>
523 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
524 Renumber other PPC_OPCODE defines.
526 2010-07-03 Alan Modra <amodra@gmail.com>
528 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
530 2010-06-29 Alan Modra <amodra@gmail.com>
532 * maxq.h: Delete file.
534 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
536 * ppc.h (PPC_OPCODE_E500): Define.
538 2010-05-26 Catherine Moore <clm@codesourcery.com>
540 * opcode/mips.h (INSN_MIPS16): Remove.
542 2010-04-21 Joseph Myers <joseph@codesourcery.com>
544 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
546 2010-04-15 Nick Clifton <nickc@redhat.com>
548 * alpha.h: Update copyright notice to use GPLv3.
554 * convex.h: Likewise.
568 * m68hc11.h: Likewise.
574 * mn10200.h: Likewise.
575 * mn10300.h: Likewise.
576 * msp430.h: Likewise.
587 * score-datadep.h: Likewise.
588 * score-inst.h: Likewise.
590 * spu-insns.h: Likewise.
594 * tic54x.h: Likewise.
599 2010-03-25 Joseph Myers <joseph@codesourcery.com>
601 * tic6x-control-registers.h, tic6x-insn-formats.h,
602 tic6x-opcode-table.h, tic6x.h: New.
604 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
606 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
608 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
610 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
612 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
614 * ia64.h (ia64_find_opcode): Remove argument name.
615 (ia64_find_next_opcode): Likewise.
616 (ia64_dis_opcode): Likewise.
617 (ia64_free_opcode): Likewise.
618 (ia64_find_dependency): Likewise.
620 2009-11-22 Doug Evans <dje@sebabeach.org>
622 * cgen.h: Include bfd_stdint.h.
623 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
625 2009-11-18 Paul Brook <paul@codesourcery.com>
627 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
629 2009-11-17 Paul Brook <paul@codesourcery.com>
630 Daniel Jacobowitz <dan@codesourcery.com>
632 * arm.h (ARM_EXT_V6_DSP): Define.
633 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
634 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
636 2009-11-04 DJ Delorie <dj@redhat.com>
638 * rx.h (rx_decode_opcode) (mvtipl): Add.
639 (mvtcp, mvfcp, opecp): Remove.
641 2009-11-02 Paul Brook <paul@codesourcery.com>
643 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
644 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
645 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
646 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
647 FPU_ARCH_NEON_VFP_V4): Define.
649 2009-10-23 Doug Evans <dje@sebabeach.org>
651 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
652 * cgen.h: Update. Improve multi-inclusion macro name.
654 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
656 * ppc.h (PPC_OPCODE_476): Define.
658 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
660 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
662 2009-09-29 DJ Delorie <dj@redhat.com>
666 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
668 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
670 2009-09-21 Ben Elliston <bje@au.ibm.com>
672 * ppc.h (PPC_OPCODE_PPCA2): New.
674 2009-09-05 Martin Thuresson <martin@mtme.org>
676 * ia64.h (struct ia64_operand): Renamed member class to op_class.
678 2009-08-29 Martin Thuresson <martin@mtme.org>
680 * tic30.h (template): Rename type template to
681 insn_template. Updated code to use new name.
682 * tic54x.h (template): Rename type template to
685 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
687 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
689 2009-06-11 Anthony Green <green@moxielogic.com>
691 * moxie.h (MOXIE_F3_PCREL): Define.
692 (moxie_form3_opc_info): Grow.
694 2009-06-06 Anthony Green <green@moxielogic.com>
696 * moxie.h (MOXIE_F1_M): Define.
698 2009-04-15 Anthony Green <green@moxielogic.com>
702 2009-04-06 DJ Delorie <dj@redhat.com>
704 * h8300.h: Add relaxation attributes to MOVA opcodes.
706 2009-03-10 Alan Modra <amodra@bigpond.net.au>
708 * ppc.h (ppc_parse_cpu): Declare.
710 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
712 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
713 and _IMM11 for mbitclr and mbitset.
714 * score-datadep.h: Update dependency information.
716 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
718 * ppc.h (PPC_OPCODE_POWER7): New.
720 2009-02-06 Doug Evans <dje@google.com>
722 * i386.h: Add comment regarding sse* insns and prefixes.
724 2009-02-03 Sandip Matte <sandip@rmicorp.com>
726 * mips.h (INSN_XLR): Define.
727 (INSN_CHIP_MASK): Update.
729 (OPCODE_IS_MEMBER): Update.
730 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
732 2009-01-28 Doug Evans <dje@google.com>
734 * opcode/i386.h: Add multiple inclusion protection.
735 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
736 (EDI_REG_NUM): New macros.
737 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
738 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
739 (REX_PREFIX_P): New macro.
741 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
743 * ppc.h (struct powerpc_opcode): New field "deprecated".
744 (PPC_OPCODE_NOPOWER4): Delete.
746 2008-11-28 Joshua Kinard <kumba@gentoo.org>
748 * mips.h: Define CPU_R14000, CPU_R16000.
749 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
751 2008-11-18 Catherine Moore <clm@codesourcery.com>
753 * arm.h (FPU_NEON_FP16): New.
754 (FPU_ARCH_NEON_FP16): New.
756 2008-11-06 Chao-ying Fu <fu@mips.com>
758 * mips.h: Doucument '1' for 5-bit sync type.
760 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
762 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
765 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
767 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
769 2008-07-30 Michael J. Eager <eager@eagercon.com>
771 * ppc.h (PPC_OPCODE_405): Define.
772 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
774 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
776 * ppc.h (ppc_cpu_t): New typedef.
777 (struct powerpc_opcode <flags>): Use it.
778 (struct powerpc_operand <insert, extract>): Likewise.
779 (struct powerpc_macro <flags>): Likewise.
781 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
783 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
784 Update comment before MIPS16 field descriptors to mention MIPS16.
785 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
787 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
788 New bit masks and shift counts for cins and exts.
790 * mips.h: Document new field descriptors +Q.
791 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
793 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
795 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
796 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
798 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
800 * ppc.h: (PPC_OPCODE_E500MC): New.
802 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
804 * i386.h (MAX_OPERANDS): Set to 5.
805 (MAX_MNEM_SIZE): Changed to 20.
807 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
809 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
811 2008-03-09 Paul Brook <paul@codesourcery.com>
813 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
815 2008-03-04 Paul Brook <paul@codesourcery.com>
817 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
818 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
819 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
821 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
822 Nick Clifton <nickc@redhat.com>
825 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
826 with a 32-bit displacement but without the top bit of the 4th byte
829 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
831 * cr16.h (cr16_num_optab): Declared.
833 2008-02-14 Hakan Ardo <hakan@debian.org>
836 * avr.h (AVR_ISA_2xxe): Define.
838 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
840 * mips.h: Update copyright.
841 (INSN_CHIP_MASK): New macro.
842 (INSN_OCTEON): New macro.
843 (CPU_OCTEON): New macro.
844 (OPCODE_IS_MEMBER): Handle Octeon instructions.
846 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
848 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
850 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
852 * avr.h (AVR_ISA_USB162): Add new opcode set.
853 (AVR_ISA_AVR3): Likewise.
855 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
857 * mips.h (INSN_LOONGSON_2E): New.
858 (INSN_LOONGSON_2F): New.
859 (CPU_LOONGSON_2E): New.
860 (CPU_LOONGSON_2F): New.
861 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
863 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
865 * mips.h (INSN_ISA*): Redefine certain values as an
866 enumeration. Update comments.
867 (mips_isa_table): New.
868 (ISA_MIPS*): Redefine to match enumeration.
869 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
872 2007-08-08 Ben Elliston <bje@au.ibm.com>
874 * ppc.h (PPC_OPCODE_PPCPS): New.
876 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
878 * m68k.h: Document j K & E.
880 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
882 * cr16.h: New file for CR16 target.
884 2007-05-02 Alan Modra <amodra@bigpond.net.au>
886 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
888 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
890 * m68k.h (mcfisa_c): New.
891 (mcfusp, mcf_mask): Adjust.
893 2007-04-20 Alan Modra <amodra@bigpond.net.au>
895 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
896 (num_powerpc_operands): Declare.
897 (PPC_OPERAND_SIGNED et al): Redefine as hex.
898 (PPC_OPERAND_PLUS1): Define.
900 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
902 * i386.h (REX_MODE64): Renamed to ...
904 (REX_EXTX): Renamed to ...
906 (REX_EXTY): Renamed to ...
908 (REX_EXTZ): Renamed to ...
911 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
913 * i386.h: Add entries from config/tc-i386.h and move tables
914 to opcodes/i386-opc.h.
916 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
918 * i386.h (FloatDR): Removed.
919 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
921 2007-03-01 Alan Modra <amodra@bigpond.net.au>
923 * spu-insns.h: Add soma double-float insns.
925 2007-02-20 Thiemo Seufer <ths@mips.com>
926 Chao-Ying Fu <fu@mips.com>
928 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
929 (INSN_DSPR2): Add flag for DSP R2 instructions.
930 (M_BALIGN): New macro.
932 2007-02-14 Alan Modra <amodra@bigpond.net.au>
934 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
935 and Seg3ShortFrom with Shortform.
937 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
940 * i386.h (i386_optab): Put the real "test" before the pseudo
943 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
945 * m68k.h (m68010up): OR fido_a.
947 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
949 * m68k.h (fido_a): New.
951 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
953 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
954 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
957 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
959 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
961 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
963 * score-inst.h (enum score_insn_type): Add Insn_internal.
965 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
966 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
967 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
968 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
969 Alan Modra <amodra@bigpond.net.au>
971 * spu-insns.h: New file.
974 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
976 * ppc.h (PPC_OPCODE_CELL): Define.
978 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
980 * i386.h : Modify opcode to support for the change in POPCNT opcode
981 in amdfam10 architecture.
983 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
985 * i386.h: Replace CpuMNI with CpuSSSE3.
987 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
988 Joseph Myers <joseph@codesourcery.com>
989 Ian Lance Taylor <ian@wasabisystems.com>
990 Ben Elliston <bje@wasabisystems.com>
992 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
994 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
996 * score-datadep.h: New file.
997 * score-inst.h: New file.
999 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1001 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1002 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1003 movdq2q and movq2dq.
1005 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1006 Michael Meissner <michael.meissner@amd.com>
1008 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1010 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1012 * i386.h (i386_optab): Add "nop" with memory reference.
1014 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1016 * i386.h (i386_optab): Update comment for 64bit NOP.
1018 2006-06-06 Ben Elliston <bje@au.ibm.com>
1019 Anton Blanchard <anton@samba.org>
1021 * ppc.h (PPC_OPCODE_POWER6): Define.
1024 2006-06-05 Thiemo Seufer <ths@mips.com>
1026 * mips.h: Improve description of MT flags.
1028 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1030 * m68k.h (mcf_mask): Define.
1032 2006-05-05 Thiemo Seufer <ths@mips.com>
1033 David Ung <davidu@mips.com>
1035 * mips.h (enum): Add macro M_CACHE_AB.
1037 2006-05-04 Thiemo Seufer <ths@mips.com>
1038 Nigel Stephens <nigel@mips.com>
1039 David Ung <davidu@mips.com>
1041 * mips.h: Add INSN_SMARTMIPS define.
1043 2006-04-30 Thiemo Seufer <ths@mips.com>
1044 David Ung <davidu@mips.com>
1046 * mips.h: Defines udi bits and masks. Add description of
1047 characters which may appear in the args field of udi
1050 2006-04-26 Thiemo Seufer <ths@networkno.de>
1052 * mips.h: Improve comments describing the bitfield instruction
1055 2006-04-26 Julian Brown <julian@codesourcery.com>
1057 * arm.h (FPU_VFP_EXT_V3): Define constant.
1058 (FPU_NEON_EXT_V1): Likewise.
1059 (FPU_VFP_HARD): Update.
1060 (FPU_VFP_V3): Define macro.
1061 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1063 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1065 * avr.h (AVR_ISA_PWMx): New.
1067 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1069 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1070 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1071 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1072 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1073 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1075 2006-03-10 Paul Brook <paul@codesourcery.com>
1077 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1079 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1081 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1082 first. Correct mask of bb "B" opcode.
1084 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1086 * i386.h (i386_optab): Support Intel Merom New Instructions.
1088 2006-02-24 Paul Brook <paul@codesourcery.com>
1090 * arm.h: Add V7 feature bits.
1092 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1094 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1096 2006-01-31 Paul Brook <paul@codesourcery.com>
1097 Richard Earnshaw <rearnsha@arm.com>
1099 * arm.h: Use ARM_CPU_FEATURE.
1100 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1101 (arm_feature_set): Change to a structure.
1102 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1103 ARM_FEATURE): New macros.
1105 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1107 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1108 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1109 (ADD_PC_INCR_OPCODE): Don't define.
1111 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1114 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1116 2005-11-14 David Ung <davidu@mips.com>
1118 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1119 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1120 save/restore encoding of the args field.
1122 2005-10-28 Dave Brolley <brolley@redhat.com>
1124 Contribute the following changes:
1125 2005-02-16 Dave Brolley <brolley@redhat.com>
1127 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1128 cgen_isa_mask_* to cgen_bitset_*.
1131 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1133 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1134 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1135 (CGEN_CPU_TABLE): Make isas a ponter.
1137 2003-09-29 Dave Brolley <brolley@redhat.com>
1139 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1140 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1141 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1143 2002-12-13 Dave Brolley <brolley@redhat.com>
1145 * cgen.h (symcat.h): #include it.
1146 (cgen-bitset.h): #include it.
1147 (CGEN_ATTR_VALUE_TYPE): Now a union.
1148 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1149 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1150 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1151 * cgen-bitset.h: New file.
1153 2005-09-30 Catherine Moore <clm@cm00re.com>
1157 2005-10-24 Jan Beulich <jbeulich@novell.com>
1159 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1162 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1164 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1165 Add FLAG_STRICT to pa10 ftest opcode.
1167 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1169 * hppa.h (pa_opcodes): Remove lha entries.
1171 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1173 * hppa.h (FLAG_STRICT): Revise comment.
1174 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
1175 before corresponding pa11 opcodes. Add strict pa10 register-immediate
1178 2005-09-30 Catherine Moore <clm@cm00re.com>
1182 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1184 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1186 2005-09-06 Chao-ying Fu <fu@mips.com>
1188 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1189 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
1191 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
1192 (INSN_ASE_MASK): Update to include INSN_MT.
1193 (INSN_MT): New define for MT ASE.
1195 2005-08-25 Chao-ying Fu <fu@mips.com>
1197 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1198 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
1199 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
1200 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
1201 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
1202 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
1204 (INSN_DSP): New define for DSP ASE.
1206 2005-08-18 Alan Modra <amodra@bigpond.net.au>
1210 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
1212 * ppc.h (PPC_OPCODE_E300): Define.
1214 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
1216 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1218 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1221 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1224 2005-07-27 Jan Beulich <jbeulich@novell.com>
1226 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1227 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
1228 Add movq-s as 64-bit variants of movd-s.
1230 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1232 * hppa.h: Fix punctuation in comment.
1234 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1235 implicit space-register addressing. Set space-register bits on opcodes
1236 using implicit space-register addressing. Add various missing pa20
1237 long-immediate opcodes. Remove various opcodes using implicit 3-bit
1238 space-register addressing. Use "fE" instead of "fe" in various
1241 2005-07-18 Jan Beulich <jbeulich@novell.com>
1243 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1245 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
1247 * i386.h (i386_optab): Support Intel VMX Instructions.
1249 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1251 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1253 2005-07-05 Jan Beulich <jbeulich@novell.com>
1255 * i386.h (i386_optab): Add new insns.
1257 2005-07-01 Nick Clifton <nickc@redhat.com>
1259 * sparc.h: Add typedefs to structure declarations.
1261 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
1264 * i386.h (i386_optab): Update comments for 64bit addressing on
1265 mov. Allow 64bit addressing for mov and movq.
1267 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1269 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1270 respectively, in various floating-point load and store patterns.
1272 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1274 * hppa.h (FLAG_STRICT): Correct comment.
1275 (pa_opcodes): Update load and store entries to allow both PA 1.X and
1276 PA 2.0 mneumonics when equivalent. Entries with cache control
1277 completers now require PA 1.1. Adjust whitespace.
1279 2005-05-19 Anton Blanchard <anton@samba.org>
1281 * ppc.h (PPC_OPCODE_POWER5): Define.
1283 2005-05-10 Nick Clifton <nickc@redhat.com>
1285 * Update the address and phone number of the FSF organization in
1286 the GPL notices in the following files:
1287 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1288 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1289 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1290 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1291 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1292 tic54x.h, tic80.h, v850.h, vax.h
1294 2005-05-09 Jan Beulich <jbeulich@novell.com>
1296 * i386.h (i386_optab): Add ht and hnt.
1298 2005-04-18 Mark Kettenis <kettenis@gnu.org>
1300 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1301 Add xcrypt-ctr. Provide aliases without hyphens.
1303 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
1305 Moved from ../ChangeLog
1307 2005-04-12 Paul Brook <paul@codesourcery.com>
1308 * m88k.h: Rename psr macros to avoid conflicts.
1310 2005-03-12 Zack Weinberg <zack@codesourcery.com>
1311 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1312 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
1313 and ARM_ARCH_V6ZKT2.
1315 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
1316 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1317 Remove redundant instruction types.
1318 (struct argument): X_op - new field.
1319 (struct cst4_entry): Remove.
1320 (no_op_insn): Declare.
1322 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
1323 * crx.h (enum argtype): Rename types, remove unused types.
1325 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1326 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1327 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
1328 (enum operand_type): Rearrange operands, edit comments.
1329 replace us<N> with ui<N> for unsigned immediate.
1330 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
1331 displacements (respectively).
1332 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
1333 (instruction type): Add NO_TYPE_INS.
1334 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
1335 (operand_entry): New field - 'flags'.
1336 (operand flags): New.
1338 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1339 * crx.h (operand_type): Remove redundant types i3, i4,
1341 Add new unsigned immediate types us3, us4, us5, us16.
1343 2005-04-12 Mark Kettenis <kettenis@gnu.org>
1345 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1346 adjust them accordingly.
1348 2005-04-01 Jan Beulich <jbeulich@novell.com>
1350 * i386.h (i386_optab): Add rdtscp.
1352 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
1354 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1355 between memory and segment register. Allow movq for moving between
1356 general-purpose register and segment register.
1358 2005-02-09 Jan Beulich <jbeulich@novell.com>
1361 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1362 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1365 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
1367 * m68k.h (m68008, m68ec030, m68882): Remove.
1369 (cpu_m68k, cpu_cf): New.
1370 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1371 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1373 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
1375 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
1376 * cgen.h (enum cgen_parse_operand_type): Add
1377 CGEN_PARSE_OPERAND_SYMBOLIC.
1379 2005-01-21 Fred Fish <fnf@specifixinc.com>
1381 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1382 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1383 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1385 2005-01-19 Fred Fish <fnf@specifixinc.com>
1387 * mips.h (struct mips_opcode): Add new pinfo2 member.
1388 (INSN_ALIAS): New define for opcode table entries that are
1389 specific instances of another entry, such as 'move' for an 'or'
1390 with a zero operand.
1391 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1392 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1394 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
1396 * mips.h (CPU_RM9000): Define.
1397 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1399 2004-11-25 Jan Beulich <jbeulich@novell.com>
1401 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1402 to/from test registers are illegal in 64-bit mode. Add missing
1403 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1404 (previously one had to explicitly encode a rex64 prefix). Re-enable
1405 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1406 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1408 2004-11-23 Jan Beulich <jbeulich@novell.com>
1410 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1411 available only with SSE2. Change the MMX additions introduced by SSE
1412 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1413 instructions by their now designated identifier (since combining i686
1414 and 3DNow! does not really imply 3DNow!A).
1416 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1418 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1419 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1421 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1422 Vineet Sharma <vineets@noida.hcltech.com>
1424 * maxq.h: New file: Disassembly information for the maxq port.
1426 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1428 * i386.h (i386_optab): Put back "movzb".
1430 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1432 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1433 comments. Remove member cris_ver_sim. Add members
1434 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1435 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1436 (struct cris_support_reg, struct cris_cond15): New types.
1437 (cris_conds15): Declare.
1438 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1439 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1440 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1441 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1442 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1443 SIZE_FIELD_UNSIGNED.
1445 2004-11-04 Jan Beulich <jbeulich@novell.com>
1447 * i386.h (sldx_Suf): Remove.
1448 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1449 (q_FP): Define, implying no REX64.
1450 (x_FP, sl_FP): Imply FloatMF.
1451 (i386_optab): Split reg and mem forms of moving from segment registers
1452 so that the memory forms can ignore the 16-/32-bit operand size
1453 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1454 all non-floating-point instructions. Unite 32- and 64-bit forms of
1455 movsx, movzx, and movd. Adjust floating point operations for the above
1456 changes to the *FP macros. Add DefaultSize to floating point control
1457 insns operating on larger memory ranges. Remove left over comments
1458 hinting at certain insns being Intel-syntax ones where the ones
1459 actually meant are already gone.
1461 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1463 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1466 2004-09-30 Paul Brook <paul@codesourcery.com>
1468 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1469 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1471 2004-09-11 Theodore A. Roth <troth@openavr.org>
1473 * avr.h: Add support for
1474 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1476 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1478 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1480 2004-08-24 Dmitry Diky <diwil@spec.ru>
1482 * msp430.h (msp430_opc): Add new instructions.
1483 (msp430_rcodes): Declare new instructions.
1484 (msp430_hcodes): Likewise..
1486 2004-08-13 Nick Clifton <nickc@redhat.com>
1489 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1492 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1494 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1496 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1498 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1500 2004-07-21 Jan Beulich <jbeulich@novell.com>
1502 * i386.h: Adjust instruction descriptions to better match the
1505 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1507 * arm.h: Remove all old content. Replace with architecture defines
1508 from gas/config/tc-arm.c.
1510 2004-07-09 Andreas Schwab <schwab@suse.de>
1512 * m68k.h: Fix comment.
1514 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1518 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1520 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1522 2004-05-24 Peter Barada <peter@the-baradas.com>
1524 * m68k.h: Add 'size' to m68k_opcode.
1526 2004-05-05 Peter Barada <peter@the-baradas.com>
1528 * m68k.h: Switch from ColdFire chip name to core variant.
1530 2004-04-22 Peter Barada <peter@the-baradas.com>
1532 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1533 descriptions for new EMAC cases.
1534 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1535 handle Motorola MAC syntax.
1536 Allow disassembly of ColdFire V4e object files.
1538 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1540 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1542 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1544 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1546 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1548 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1550 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1552 * i386.h (i386_optab): Added xstore/xcrypt insns.
1554 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1556 * h8300.h (32bit ldc/stc): Add relaxing support.
1558 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1560 * h8300.h (BITOP): Pass MEMRELAX flag.
1562 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1564 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1567 For older changes see ChangeLog-9103
1573 version-control: never
projects / deliverable / binutils-gdb.git / blob