1 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
3 * aarch64.h (enum aarch64_opnd_qualifier): Add
6 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
8 * aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB.
9 * aarch64-asm-2.c: Regenerate.
10 * aarch64-dis-2.c: Regenerate.
11 * aarch64-opc-2.c: Regenerate.
12 * aarch64-opc.c (aarch64_hint_options): Add "csync".
13 (aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB.
14 * aarch64-tbl.h (aarch64_feature_stat_profile): New.
16 (aarch64_opcode_table): Add "psb".
17 (AARCH64_OPERANDS): Add "BARRIER_PSB".
19 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
21 * aarch64.h (aarch64_hint_options): Declare.
22 (aarch64_opnd_info): Add field hint_option.
24 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
26 * aarch64.h (AARCH64_FEATURE_PROFILE): New.
28 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
30 * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.
32 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
34 * aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
35 (aarch64_sys_ins_reg_has_xt): Declare.
37 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
39 * aarch64.h (AARCH64_FEATURE_RAS): New.
40 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.
42 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
44 * aarch64.h (AARCH64_FEATURE_F16): Fix clash with
46 (AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC.
47 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and
50 2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
52 * arc.h (arc_reloc_equiv_tab): Replace flagcode with flags[32].
54 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
56 * aarch64.h (aarch64_op): Add OP_BFC.
58 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
60 * aarch64.h (AARCH64_FEATURE_F16): New.
61 (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2
64 2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
66 * aarch64.h (AARCH64_FEATURE_V8_1): New.
67 (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.
69 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
71 * arm.h (ARM_EXT2_V8_2A): New.
72 (ARM_ARCH_V8_2A): New.
74 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
76 * aarch64.h (AARCH64_FEATURE_V8_2): New.
77 (AARCH64_ARCH_V8_2): New.
79 2015-11-11 Alan Modra <amodra@gmail.com>
80 Peter Bergner <bergner@vnet.ibm.com>
82 * ppc.h (PPC_OPCODE_POWER9): New define.
83 (PPC_OPCODE_VSX3): Likewise.
85 2015-11-02 Nick Clifton <nickc@redhat.com>
87 * rx.h (enum RX_Opcode_ID): Add more NOP opcodes.
89 2015-11-02 Nick Clifton <nickc@redhat.com>
91 * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
93 2015-10-28 Yao Qi <yao.qi@linaro.org>
95 * aarch64.h (aarch64_decode_insn): Update declaration.
97 2015-10-07 Yao Qi <yao.qi@linaro.org>
99 * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
102 2015-10-07 Yao Qi <yao.qi@linaro.org>
104 * aarch64.h [__cplusplus]: Wrap in extern "C".
106 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
107 Cupertino Miranda <cmiranda@synopsys.com>
109 * arc-func.h: New file.
112 2015-10-02 Yao Qi <yao.qi@linaro.org>
114 * aarch64.h (aarch64_zero_register_p): Move the declaration
117 2015-10-02 Yao Qi <yao.qi@linaro.org>
119 * aarch64.h (aarch64_decode_insn): Declare it.
121 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
123 * s390.h (S390_INSTR_FLAG_HTM): New flag.
124 (S390_INSTR_FLAG_VX): New flag.
125 (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
127 2015-09-23 Nick Clifton <nickc@redhat.com>
129 * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
132 2015-09-22 Nick Clifton <nickc@redhat.com>
134 * rx.h (enum RX_Size): Add RX_Bad_Size entry.
136 2015-09-09 Daniel Santos <daniel.santos@pobox.com>
138 * visium.h (gen_reg_table): Make static.
139 (fp_reg_table): Likewise.
140 (cc_table): Likewise.
142 2015-07-20 Matthew Wahab <matthew.wahab@arm.com>
144 * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
145 (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
146 (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
147 (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
149 2015-07-03 Alan Modra <amodra@gmail.com>
151 * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
153 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
154 Cesar Philippidis <cesar@codesourcery.com>
156 * nios2.h (enum iw_format_type): Add R2 formats.
157 (enum overflow_type): Add signed_immed12_overflow and
158 enumeration_overflow for R2.
159 (struct nios2_opcode): Document new argument letters for R2.
160 (REG_3BIT, REG_LDWM, REG_POP): Define.
161 (includes): Include nios2r2.h.
162 (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
163 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
164 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
165 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
166 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
167 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
169 * nios2r2.h: New file.
171 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
173 * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
174 (ppc_optional_operand_value): New inline function.
176 2015-06-04 Matthew Wahab <matthew.wahab@arm.com>
178 * aarch64.h (AARCH64_V8_1): New.
180 2015-06-03 Matthew Wahab <matthew.wahab@arm.com>
182 * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
183 (ARM_ARCH_V8_1A): New.
184 (ARM_ARCH_V8_1A_FP): New.
185 (ARM_ARCH_V8_1A_SIMD): New.
186 (ARM_ARCH_V8_1A_CRYPTOV1): New.
187 (ARM_FEATURE_CORE): New.
189 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
191 * arm.h (ARM_EXT2_PAN): New.
192 (ARM_FEATURE_CORE_HIGH): New.
194 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
196 * arm.h (ARM_FEATURE_ALL): New.
198 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
200 * aarch64.h (AARCH64_FEATURE_RDMA): New.
202 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
204 * aarch64.h (AARCH64_FEATURE_LOR): New.
206 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
208 * aarch64.h (AARCH64_FEATURE_PAN): New.
209 (aarch64_sys_reg_supported_p): Declare.
210 (aarch64_pstatefield_supported_p): Declare.
212 2015-04-30 DJ Delorie <dj@redhat.com>
214 * rl78.h (RL78_Dis_Isa): New.
215 (rl78_decode_opcode): Add ISA parameter.
217 2015-03-24 Terry Guo <terry.guo@arm.com>
219 * arm.h (arm_feature_set): Extended to provide more available bits.
220 (ARM_ANY): Updated to follow above new definition.
221 (ARM_CPU_HAS_FEATURE): Likewise.
222 (ARM_CPU_IS_ANY): Likewise.
223 (ARM_MERGE_FEATURE_SETS): Likewise.
224 (ARM_CLEAR_FEATURE): Likewise.
225 (ARM_FEATURE): Likewise.
226 (ARM_FEATURE_COPY): New macro.
227 (ARM_FEATURE_EQUAL): Likewise.
228 (ARM_FEATURE_ZERO): Likewise.
229 (ARM_FEATURE_CORE_EQUAL): Likewise.
230 (ARM_FEATURE_LOW): Likewise.
231 (ARM_FEATURE_CORE_LOW): Likewise.
232 (ARM_FEATURE_CORE_COPROC): Likewise.
234 2015-02-19 Pedro Alves <palves@redhat.com>
236 * cgen.h [__cplusplus]: Wrap in extern "C".
237 * msp430-decode.h [__cplusplus]: Likewise.
238 * nios2.h [__cplusplus]: Likewise.
239 * rl78.h [__cplusplus]: Likewise.
240 * rx.h [__cplusplus]: Likewise.
241 * tilegx.h [__cplusplus]: Likewise.
243 2015-01-28 James Bowman <james.bowman@ftdichip.com>
247 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
249 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
251 2015-01-01 Alan Modra <amodra@gmail.com>
253 Update year range in copyright notice of all files.
255 2014-12-27 Anthony Green <green@moxielogic.com>
257 * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
258 MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
260 2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
262 * visium.h: New file.
264 2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
266 * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
267 (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
268 (NIOS2_INSN_OPTARG): Renumber.
270 2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
272 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
273 declaration. Fix obsolete comment.
275 2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
277 * nios2.h (enum iw_format_type): New.
278 (struct nios2_opcode): Update comments. Add size and format fields.
279 (NIOS2_INSN_OPTARG): New.
280 (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
281 (struct nios2_reg): Add regtype field.
282 (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
283 (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
284 (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
285 (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
286 (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
287 (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
288 (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
289 (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
290 (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
291 (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
292 (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
293 (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
294 (OP_MASK_OP, OP_SH_OP): Delete.
295 (OP_MASK_IOP, OP_SH_IOP): Delete.
296 (OP_MASK_IRD, OP_SH_IRD): Delete.
297 (OP_MASK_IRT, OP_SH_IRT): Delete.
298 (OP_MASK_IRS, OP_SH_IRS): Delete.
299 (OP_MASK_ROP, OP_SH_ROP): Delete.
300 (OP_MASK_RRD, OP_SH_RRD): Delete.
301 (OP_MASK_RRT, OP_SH_RRT): Delete.
302 (OP_MASK_RRS, OP_SH_RRS): Delete.
303 (OP_MASK_JOP, OP_SH_JOP): Delete.
304 (OP_MASK_IMM26, OP_SH_IMM26): Delete.
305 (OP_MASK_RCTL, OP_SH_RCTL): Delete.
306 (OP_MASK_IMM5, OP_SH_IMM5): Delete.
307 (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
308 (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
309 (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
310 (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
311 (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
312 (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
313 (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
314 (OP_MASK_<insn>, OP_MASK): Delete.
315 (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
316 (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
317 Include nios2r1.h to define new instruction opcode constants
319 (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
320 (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
321 (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
322 (NUMOPCODES, NUMREGISTERS): Delete.
323 * nios2r1.h: New file.
325 2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
327 * sparc.h (HWCAP2_VIS3B): Documentation improved.
329 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
331 * sparc.h (sparc_opcode): new field `hwcaps2'.
332 (HWCAP2_FJATHPLUS): New define.
333 (HWCAP2_VIS3B): Likewise.
334 (HWCAP2_ADP): Likewise.
335 (HWCAP2_SPARC5): Likewise.
336 (HWCAP2_MWAIT): Likewise.
337 (HWCAP2_XMPMUL): Likewise.
338 (HWCAP2_XMONT): Likewise.
339 (HWCAP2_NSEC): Likewise.
340 (HWCAP2_FJATHHPC): Likewise.
341 (HWCAP2_FJDES): Likewise.
342 (HWCAP2_FJAES): Likewise.
343 Document the new operand kind `{', corresponding to the mcdper
344 ancillary state register.
345 Document the new operand kind }, which represents frsd floating
346 point registers (double precision) which must be the same than
347 frs1 in its containing instruction.
349 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
351 * nds32.h: Add new opcode declaration.
353 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
354 Matthew Fortune <matthew.fortune@imgtec.com>
356 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
357 OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
358 instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
359 +I, +O, +R, +:, +\, +", +;
360 (mips_check_prev_operand): New struct.
361 (INSN2_FORBIDDEN_SLOT): New define.
362 (INSN_ISA32R6): New define.
363 (INSN_ISA64R6): New define.
364 (INSN_UPTO32R6): New define.
365 (INSN_UPTO64R6): New define.
366 (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
367 (ISA_MIPS32R6): New define.
368 (ISA_MIPS64R6): New define.
369 (CPU_MIPS32R6): New define.
370 (CPU_MIPS64R6): New define.
371 (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
373 2014-09-03 Jiong Wang <jiong.wang@arm.com>
375 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
376 (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
377 (aarch64_insn_class): Add lse_atomic.
378 (F_LSE_SZ): New field added.
379 (opcode_has_special_coder): Recognize F_LSE_SZ.
381 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
383 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
386 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
388 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
389 (INSN_LOAD_COPROC): New define.
390 (INSN_COPROC_MOVE_DELAY): Rename to...
391 (INSN_COPROC_MOVE): New define.
393 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
394 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
395 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
396 Soundararajan <Sounderarajan.D@atmel.com>
398 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
399 (AVR_ISA_2xxxa): Define ISA without LPM.
400 (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
401 Add doc for contraint used in 16 bit lds/sts.
402 Adjust ISA group for icall, ijmp, pop and push.
403 Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
405 2014-05-19 Nick Clifton <nickc@redhat.com>
407 * msp430.h (struct msp430_operand_s): Add vshift field.
409 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
411 * mips.h (INSN_ISA_MASK): Updated.
412 (INSN_ISA32R3): New define.
413 (INSN_ISA32R5): New define.
414 (INSN_ISA64R3): New define.
415 (INSN_ISA64R5): New define.
416 (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
417 INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
418 (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
420 (INSN_UPTO32R3): New define.
421 (INSN_UPTO32R5): New define.
422 (INSN_UPTO64R3): New define.
423 (INSN_UPTO64R5): New define.
424 (ISA_MIPS32R3): New define.
425 (ISA_MIPS32R5): New define.
426 (ISA_MIPS64R3): New define.
427 (ISA_MIPS64R5): New define.
428 (CPU_MIPS32R3): New define.
429 (CPU_MIPS32R5): New define.
430 (CPU_MIPS64R3): New define.
431 (CPU_MIPS64R5): New define.
433 2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
435 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
437 2014-04-22 Christian Svensson <blue@cmd.nu>
441 2014-03-05 Alan Modra <amodra@gmail.com>
443 Update copyright years.
445 2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
447 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
450 2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
451 Wei-Cheng Wang <cole945@gmail.com>
453 * nds32.h: New file for Andes NDS32.
455 2013-12-07 Mike Frysinger <vapier@gentoo.org>
457 * bfin.h: Remove +x file mode.
459 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
461 * aarch64.h (aarch64_pstatefields): Change element type to
464 2013-11-18 Renlin Li <Renlin.Li@arm.com>
466 * arm.h (ARM_AEXT_V7VE): New define.
467 (ARM_ARCH_V7VE): New define.
468 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
470 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
474 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
476 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
477 (aarch64_sys_reg_writeonly_p): Ditto.
479 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
481 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
482 (aarch64_sys_reg_writeonly_p): Ditto.
484 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
486 * aarch64.h (aarch64_sys_reg): New typedef.
487 (aarch64_sys_regs): Change to define with the new type.
488 (aarch64_sys_reg_deprecated_p): Declare.
490 2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
492 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
493 (enum aarch64_opnd): Add AARCH64_OPND_COND1.
495 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
497 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
498 (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
499 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
500 +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
501 For MIPS, update extension character sequences after +.
502 (ASE_MSA): New define.
503 (ASE_MSA64): New define.
504 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
505 +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
506 For microMIPS, update extension character sequences after +.
508 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
513 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
515 * mips.h: Remove references to "+I" and imm2_expr.
517 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
519 * mips.h (M_DEXT, M_DINS): Delete.
521 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
523 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
524 (mips_optional_operand_p): New function.
526 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
527 Richard Sandiford <rdsandiford@googlemail.com>
529 * mips.h: Document new VU0 operand characters.
530 (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
531 (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
532 (OP_REG_R5900_ACC): New mips_reg_operand_types.
533 (INSN2_VU0_CHANNEL_SUFFIX): New macro.
534 (mips_vu0_channel_mask): Declare.
536 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
538 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
539 (mips_int_operand_min, mips_int_operand_max): New functions.
540 (mips_decode_pcrel_operand): Use mips_decode_int_operand.
542 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
544 * mips.h (mips_decode_reg_operand): New function.
545 (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
546 (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
547 (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
549 (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
550 (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
551 (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
552 (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
553 (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
554 (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
555 (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
556 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
557 (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
558 (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
559 macros to cover the gaps.
560 (INSN2_MOD_SP): Replace with...
561 (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
562 (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
563 (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
564 (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
565 (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
568 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
570 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
571 (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
572 (MIPS16_INSN_COND_BRANCH): Delete.
574 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
575 Kirill Yukhin <kirill.yukhin@intel.com>
576 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
578 * i386.h (BND_PREFIX_OPCODE): New.
580 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
582 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
583 OP_SAVE_RESTORE_LIST.
584 (decode_mips16_operand): Declare.
586 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
588 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
589 (mips_operand, mips_int_operand, mips_mapped_int_operand)
590 (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
591 (mips_pcrel_operand): New structures.
592 (mips_insert_operand, mips_extract_operand, mips_signed_operand)
593 (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
594 (decode_mips_operand, decode_micromips_operand): Declare.
596 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
598 * mips.h: Document MIPS16 "I" opcode.
600 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
602 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
603 (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
604 (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
605 (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
606 (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
607 (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
608 (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
609 (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
610 (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
611 (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
612 (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
613 (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
614 (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
616 (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
617 (M_USD_AB): ...these.
619 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
621 * mips.h: Remove documentation of "[" and "]". Update documentation
622 of "k" and the MDMX formats.
624 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
626 * mips.h: Update documentation of "+s" and "+S".
628 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
630 * mips.h: Document "+i".
632 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
634 * mips.h: Remove "mi" documentation. Update "mh" documentation.
635 (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
637 (INSN2_WRITE_GPR_MHI): Rename to...
638 (INSN2_WRITE_GPR_MH): ...this.
640 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
642 * mips.h: Remove documentation of "+D" and "+T".
644 2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
646 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
647 Use "source" rather than "destination" for microMIPS "G".
649 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
651 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
654 2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
656 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
658 2013-06-17 Catherine Moore <clm@codesourcery.com>
659 Maciej W. Rozycki <macro@codesourcery.com>
660 Chao-Ying Fu <fu@mips.com>
662 * mips.h (OP_SH_EVAOFFSET): Define.
663 (OP_MASK_EVAOFFSET): Define.
664 (INSN_ASE_MASK): Delete.
666 (M_CACHEE_AB, M_CACHEE_OB): New.
667 (M_LBE_OB, M_LBE_AB): New.
668 (M_LBUE_OB, M_LBUE_AB): New.
669 (M_LHE_OB, M_LHE_AB): New.
670 (M_LHUE_OB, M_LHUE_AB): New.
671 (M_LLE_AB, M_LLE_OB): New.
672 (M_LWE_OB, M_LWE_AB): New.
673 (M_LWLE_AB, M_LWLE_OB): New.
674 (M_LWRE_AB, M_LWRE_OB): New.
675 (M_PREFE_AB, M_PREFE_OB): New.
676 (M_SCE_AB, M_SCE_OB): New.
677 (M_SBE_OB, M_SBE_AB): New.
678 (M_SHE_OB, M_SHE_AB): New.
679 (M_SWE_OB, M_SWE_AB): New.
680 (M_SWLE_AB, M_SWLE_OB): New.
681 (M_SWRE_AB, M_SWRE_OB): New.
682 (MICROMIPSOP_SH_EVAOFFSET): Define.
683 (MICROMIPSOP_MASK_EVAOFFSET): Define.
685 2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
687 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
689 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
691 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
693 2013-05-09 Andrew Pinski <apinski@cavium.com>
695 * mips.h (OP_MASK_CODE10): Correct definition.
696 (OP_SH_CODE10): Likewise.
697 Add a comment that "+J" is used now for OP_*CODE10.
698 (INSN_ASE_MASK): Update.
699 (INSN_VIRT): New macro.
700 (INSN_VIRT64): New macro
702 2013-05-02 Nick Clifton <nickc@redhat.com>
704 * msp430.h: Add patterns for MSP430X instructions.
706 2013-04-06 David S. Miller <davem@davemloft.net>
708 * sparc.h (F_PREFERRED): Define.
709 (F_PREF_ALIAS): Define.
711 2013-04-03 Nick Clifton <nickc@redhat.com>
713 * v850.h (V850_INVERSE_PCREL): Define.
715 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
718 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
720 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
723 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
725 * tic6xc-opcode-table.h: Add 16-bit insns.
726 * tic6x.h: Add support for 16-bit insns.
728 2013-03-21 Michael Schewe <michael.schewe@gmx.net>
730 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
731 and mov.b/w/l Rs,@(d:32,ERd).
733 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
736 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
737 from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
738 tic6x_operand_xregpair operand coding type.
739 Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
740 opcode field, usu ORXREGD1324 for the src2 operand and remove the
743 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
746 * tic6x.h (enum tic6x_coding_method): Add
747 tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
748 separately the msb and lsb of a register pair. This is needed to
749 encode the opcodes in the same way as TI assembler does.
750 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
751 and rsqrdp opcodes to use the new field coding types.
753 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
755 * arm.h (CRC_EXT_ARMV8): New constant.
756 (ARCH_CRC_ARMV8): New macro.
758 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
760 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
762 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
763 Andrew Jenner <andrew@codesourcery.com>
765 Based on patches from Altera Corporation.
769 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
771 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
773 2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
776 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
778 2013-01-24 Nick Clifton <nickc@redhat.com>
780 * v850.h: Add e3v5 support.
782 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
784 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
786 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
788 * ppc.h (PPC_OPCODE_POWER8): New define.
789 (PPC_OPCODE_HTM): Likewise.
791 2013-01-10 Will Newton <will.newton@imgtec.com>
795 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
797 * cr16.h (make_instruction): Rename to cr16_make_instruction.
798 (match_opcode): Rename to cr16_match_opcode.
800 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
802 * mips.h: Add support for r5900 instructions including lq and sq.
804 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
806 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
807 (make_instruction,match_opcode): Added function prototypes.
808 (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
810 2012-11-23 Alan Modra <amodra@gmail.com>
812 * ppc.h (ppc_parse_cpu): Update prototype.
814 2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
816 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
817 opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
819 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
821 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
823 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
825 * ia64.h (ia64_opnd): Add new operand types.
827 2012-08-21 David S. Miller <davem@davemloft.net>
829 * sparc.h (F3F4): New macro.
831 2012-08-13 Ian Bolton <ian.bolton@arm.com>
832 Laurent Desnogues <laurent.desnogues@arm.com>
833 Jim MacArthur <jim.macarthur@arm.com>
834 Marcus Shawcroft <marcus.shawcroft@arm.com>
835 Nigel Stephens <nigel.stephens@arm.com>
836 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
837 Richard Earnshaw <rearnsha@arm.com>
838 Sofiane Naci <sofiane.naci@arm.com>
839 Tejas Belagod <tejas.belagod@arm.com>
840 Yufeng Zhang <yufeng.zhang@arm.com>
842 * aarch64.h: New file.
844 2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
845 Maciej W. Rozycki <macro@codesourcery.com>
847 * mips.h (mips_opcode): Add the exclusions field.
848 (OPCODE_IS_MEMBER): Remove macro.
849 (cpu_is_member): New inline function.
850 (opcode_is_member): Likewise.
852 2012-07-31 Chao-Ying Fu <fu@mips.com>
853 Catherine Moore <clm@codesourcery.com>
854 Maciej W. Rozycki <macro@codesourcery.com>
856 * mips.h: Document microMIPS DSP ASE usage.
857 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
858 microMIPS DSP ASE support.
859 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
860 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
861 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
862 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
863 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
864 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
865 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
867 2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
869 * mips.h: Fix a typo in description.
871 2012-06-07 Georg-Johann Lay <avr@gjlay.de>
873 * avr.h: (AVR_ISA_XCH): New define.
874 (AVR_ISA_XMEGA): Use it.
875 (XCH, LAS, LAT, LAC): New XMEGA opcodes.
877 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
879 * m68hc11.h: Add XGate definitions.
880 (struct m68hc11_opcode): Add xg_mask field.
882 2012-05-14 Catherine Moore <clm@codesourcery.com>
883 Maciej W. Rozycki <macro@codesourcery.com>
884 Rhonda Wittels <rhonda@codesourcery.com>
886 * ppc.h (PPC_OPCODE_VLE): New definition.
887 (PPC_OP_SA): New macro.
888 (PPC_OP_SE_VLE): New macro.
889 (PPC_OP): Use a variable shift amount.
890 (powerpc_operand): Update comments.
891 (PPC_OPSHIFT_INV): New macro.
892 (PPC_OPERAND_CR): Replace with...
893 (PPC_OPERAND_CR_BIT): ...this and
894 (PPC_OPERAND_CR_REG): ...this.
897 2012-05-03 Sean Keys <skeys@ipdatasys.com>
899 * xgate.h: Header file for XGATE assembler.
901 2012-04-27 David S. Miller <davem@davemloft.net>
903 * sparc.h: Document new arg code' )' for crypto RS3
906 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
907 F_MUL32, F_DIV32, F_FDMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
908 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
909 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING, F_HWCAP_MASK): Delete.
910 (HWCAP_MUL32, HWCAP_DIV32, HWCAP_FSMULD, HWCAP_V8PLUS, HWCAP_POPC,
911 HWCAP_VIS, HWCAP_VIS2, HWCAP_ASI_BLK_INIT, HWCAP_FMAF,
912 HWCAP_VIS3, HWCAP_HPC, HWCAP_RANDOM, HWCAP_TRANS, HWCAP_FJFMAU,
913 HWCAP_IMA, HWCAP_ASI_CACHE_SPARING, HWCAP_AES, HWCAP_DES,
914 HWCAP_KASUMI, HWCAP_CAMELLIA, HWCAP_MD5, HWCAP_SHA1,
915 HWCAP_SHA256, HWCAP_SHA512, HWCAP_MPMUL, HWCAP_MONT, HWCAP_PAUSE,
916 HWCAP_CBCOND, HWCAP_CRC32): New defines.
918 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
920 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
922 2012-02-27 Alan Modra <amodra@gmail.com>
924 * crx.h (cst4_map): Update declaration.
926 2012-02-25 Walter Lee <walt@tilera.com>
928 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
930 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
931 TILEPRO_OPC_LW_TLS_SN.
933 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
935 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
936 (XRELEASE_PREFIX_OPCODE): Likewise.
938 2011-12-08 Andrew Pinski <apinski@cavium.com>
939 Adam Nemet <anemet@caviumnetworks.com>
941 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
942 (INSN_OCTEON2): New macro.
943 (CPU_OCTEON2): New macro.
944 (OPCODE_IS_MEMBER): Add Octeon2.
946 2011-11-29 Andrew Pinski <apinski@cavium.com>
948 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
949 (INSN_OCTEONP): New macro.
950 (CPU_OCTEONP): New macro.
951 (OPCODE_IS_MEMBER): Add Octeon+.
952 (M_SAA_AB, M_SAAD_AB, M_SAA_OB, M_SAAD_OB): New enum values.
954 2011-11-01 DJ Delorie <dj@redhat.com>
958 2011-10-24 Maciej W. Rozycki <macro@codesourcery.com>
960 * mips.h: Fix a typo in description.
962 2011-09-21 David S. Miller <davem@davemloft.net>
964 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
965 (F_MUL32, F_DIV32, F_FSMULD, F_V8PLUS, F_POPC, F_VIS, F_VIS2,
966 F_ASI_BLK_INIT, F_FMAF, F_VIS3, F_HPC, F_RANDOM, F_TRANS,
967 F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
969 2011-08-09 Chao-ying Fu <fu@mips.com>
970 Maciej W. Rozycki <macro@codesourcery.com>
972 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
973 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
974 (INSN_ASE_MASK): Add the MCU bit.
975 (INSN_MCU): New macro.
976 (M_ACLR_AB, M_ACLR_OB, M_ASET_AB, M_ASET_OB): New enum values.
977 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): New macros.
979 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
981 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
982 (INSN2_READ_GPR_MC, INSN2_READ_GPR_ME): Likewise.
983 (INSN2_WRITE_GPR_MF, INSN2_READ_GPR_MG): Likewise.
984 (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ): Likewise.
985 (INSN2_READ_GPR_MP, INSN2_WRITE_GPR_MP): Likewise.
986 (INSN2_READ_GPR_MQ, INSN2_WRITE_GPR_MHI): Likewise.
987 (INSN2_READ_GPR_MMN): Likewise.
988 (INSN2_READ_FPR_D): Change the bit used.
989 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_MF): Likewise.
990 (INSN2_MOD_SP, INSN2_READ_GPR_31, INSN2_READ_GP): Likewise.
991 (INSN2_READ_PC, INSN2_UNCOND_BRANCH): Likewise.
992 (INSN2_COND_BRANCH): Likewise.
993 (INSN2_WRITE_GPR_S, INSN2_MOD_GPR_MB): Remove macros.
994 (INSN2_MOD_GPR_MC, INSN2_MOD_GPR_ME, INSN2_MOD_GPR_MG): Likewise.
995 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP, INSN2_MOD_GPR_MQ): Likewise.
996 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM): Likewise.
997 (INSN2_MOD_GPR_MN): Likewise.
999 2011-08-05 David S. Miller <davem@davemloft.net>
1001 * sparc.h: Document new format codes '4', '5', and '('.
1002 (OPF_LOW4, RS3): New macros.
1004 2011-08-03 Maciej W. Rozycki <macro@codesourcery.com>
1006 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
1007 order of flags documented.
1009 2011-07-29 Maciej W. Rozycki <macro@codesourcery.com>
1011 * mips.h: Clarify the description of microMIPS instruction
1012 manipulation macros.
1013 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
1015 2011-07-24 Chao-ying Fu <fu@mips.com>
1016 Maciej W. Rozycki <macro@codesourcery.com>
1018 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
1019 (OP_MASK_STYPE, OP_SH_STYPE): Likewise.
1020 (OP_MASK_CODE10, OP_SH_CODE10): Likewise.
1021 (OP_MASK_TRAP, OP_SH_TRAP): Likewise.
1022 (OP_MASK_OFFSET12, OP_SH_OFFSET12): Likewise.
1023 (OP_MASK_OFFSET10, OP_SH_OFFSET10): Likewise.
1024 (OP_MASK_RS3, OP_SH_RS3): Likewise.
1025 (OP_MASK_MB, OP_SH_MB, OP_MASK_MC, OP_SH_MC): Likewise.
1026 (OP_MASK_MD, OP_SH_MD, OP_MASK_ME, OP_SH_ME): Likewise.
1027 (OP_MASK_MF, OP_SH_MF, OP_MASK_MG, OP_SH_MG): Likewise.
1028 (OP_MASK_MJ, OP_SH_MJ, OP_MASK_ML, OP_SH_ML): Likewise.
1029 (OP_MASK_MP, OP_SH_MP, OP_MASK_MQ, OP_SH_MQ): Likewise.
1030 (OP_MASK_IMMA, OP_SH_IMMA, OP_MASK_IMMB, OP_SH_IMMB): Likewise.
1031 (OP_MASK_IMMC, OP_SH_IMMC, OP_MASK_IMMF, OP_SH_IMMF): Likewise.
1032 (OP_MASK_IMMG, OP_SH_IMMG, OP_MASK_IMMH, OP_SH_IMMH): Likewise.
1033 (OP_MASK_IMMI, OP_SH_IMMI, OP_MASK_IMMJ, OP_SH_IMMJ): Likewise.
1034 (OP_MASK_IMML, OP_SH_IMML, OP_MASK_IMMM, OP_SH_IMMM): Likewise.
1035 (OP_MASK_IMMN, OP_SH_IMMN, OP_MASK_IMMO, OP_SH_IMMO): Likewise.
1036 (OP_MASK_IMMP, OP_SH_IMMP, OP_MASK_IMMQ, OP_SH_IMMQ): Likewise.
1037 (OP_MASK_IMMU, OP_SH_IMMU, OP_MASK_IMMW, OP_SH_IMMW): Likewise.
1038 (OP_MASK_IMMX, OP_SH_IMMX, OP_MASK_IMMY, OP_SH_IMMY): Likewise.
1039 (INSN_WRITE_GPR_S): New macro.
1040 (INSN2_BRANCH_DELAY_16BIT, INSN2_BRANCH_DELAY_32BIT): Likewise.
1041 (INSN2_READ_FPR_D): Likewise.
1042 (INSN2_MOD_GPR_MB, INSN2_MOD_GPR_MC): Likewise.
1043 (INSN2_MOD_GPR_MD, INSN2_MOD_GPR_ME): Likewise.
1044 (INSN2_MOD_GPR_MF, INSN2_MOD_GPR_MG): Likewise.
1045 (INSN2_MOD_GPR_MJ, INSN2_MOD_GPR_MP): Likewise.
1046 (INSN2_MOD_GPR_MQ, INSN2_MOD_SP): Likewise.
1047 (INSN2_READ_GPR_31, INSN2_READ_GP, INSN2_READ_PC): Likewise.
1048 (INSN2_UNCOND_BRANCH, INSN2_COND_BRANCH): Likewise.
1049 (INSN2_MOD_GPR_MHI, INSN2_MOD_GPR_MM, INSN2_MOD_GPR_MN): Likewise.
1050 (CPU_MICROMIPS): New macro.
1051 (M_BC1FL, M_BC1TL, M_BC2FL, M_BC2TL): New enum values.
1052 (M_BEQL, M_BGEZ, M_BGEZL, M_BGEZALL, M_BGTZ, M_BGTZL): Likewise.
1053 (M_BLEZ, M_BLEZL, M_BLTZ, M_BLTZL, M_BLTZALL, M_BNEL): Likewise.
1054 (M_CACHE_OB, M_JALS_1, M_JALS_2, M_JALS_A): Likewise.
1055 (M_LDC2_OB, M_LDL_OB, M_LDM_AB, M_LDM_OB): Likewise.
1056 (M_LDP_AB, M_LDP_OB, M_LDR_OB, M_LL_OB, M_LLD_OB): Likewise.
1057 (M_LWC2_OB, M_LWL_OB, M_LWM_AB, M_LWM_OB): Likewise.
1058 (M_LWP_AB, M_LWP_OB, M_LWR_OB): Likewise.
1059 (M_LWU_OB, M_PREF_OB, M_SC_OB, M_SCD_OB): Likewise.
1060 (M_SDC2_OB, M_SDL_OB, M_SDM_AB, M_SDM_OB): Likewise.
1061 (M_SDP_AB, M_SDP_OB, M_SDR_OB): Likewise.
1062 (M_SWC2_OB, M_SWL_OB, M_SWM_AB, M_SWM_OB): Likewise.
1063 (M_SWP_AB, M_SWP_OB, M_SWR_OB): Likewise.
1064 (MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): New macros.
1065 (MICROMIPSOP_MASK_IMMEDIATE, MICROMIPSOP_SH_IMMEDIATE): Likewise.
1066 (MICROMIPSOP_MASK_DELTA, MICROMIPSOP_SH_DELTA): Likewise.
1067 (MICROMIPSOP_MASK_CODE10, MICROMIPSOP_SH_CODE10): Likewise.
1068 (MICROMIPSOP_MASK_TRAP, MICROMIPSOP_SH_TRAP): Likewise.
1069 (MICROMIPSOP_MASK_SHAMT, MICROMIPSOP_SH_SHAMT): Likewise.
1070 (MICROMIPSOP_MASK_TARGET, MICROMIPSOP_SH_TARGET): Likewise.
1071 (MICROMIPSOP_MASK_EXTLSB, MICROMIPSOP_SH_EXTLSB): Likewise.
1072 (MICROMIPSOP_MASK_EXTMSBD, MICROMIPSOP_SH_EXTMSBD): Likewise.
1073 (MICROMIPSOP_MASK_INSMSB, MICROMIPSOP_SH_INSMSB): Likewise.
1074 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1075 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1076 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1077 (MICROMIPSOP_MASK_SEL, MICROMIPSOP_SH_SEL): Likewise.
1078 (MICROMIPSOP_MASK_OFFSET12, MICROMIPSOP_SH_OFFSET12): Likewise.
1079 (MICROMIPSOP_MASK_3BITPOS, MICROMIPSOP_SH_3BITPOS): Likewise.
1080 (MICROMIPSOP_MASK_STYPE, MICROMIPSOP_SH_STYPE): Likewise.
1081 (MICROMIPSOP_MASK_OFFSET10, MICROMIPSOP_SH_OFFSET10): Likewise.
1082 (MICROMIPSOP_MASK_RS, MICROMIPSOP_SH_RS): Likewise.
1083 (MICROMIPSOP_MASK_RT, MICROMIPSOP_SH_RT): Likewise.
1084 (MICROMIPSOP_MASK_RD, MICROMIPSOP_SH_RD): Likewise.
1085 (MICROMIPSOP_MASK_FS, MICROMIPSOP_SH_FS): Likewise.
1086 (MICROMIPSOP_MASK_FT, MICROMIPSOP_SH_FT): Likewise.
1087 (MICROMIPSOP_MASK_FD, MICROMIPSOP_SH_FD): Likewise.
1088 (MICROMIPSOP_MASK_FR, MICROMIPSOP_SH_FR): Likewise.
1089 (MICROMIPSOP_MASK_RS3, MICROMIPSOP_SH_RS3): Likewise.
1090 (MICROMIPSOP_MASK_PREFX, MICROMIPSOP_SH_PREFX): Likewise.
1091 (MICROMIPSOP_MASK_BCC, MICROMIPSOP_SH_BCC): Likewise.
1092 (MICROMIPSOP_MASK_CCC, MICROMIPSOP_SH_CCC): Likewise.
1093 (MICROMIPSOP_MASK_COPZ, MICROMIPSOP_SH_COPZ): Likewise.
1094 (MICROMIPSOP_MASK_MB, MICROMIPSOP_SH_MB): Likewise.
1095 (MICROMIPSOP_MASK_MC, MICROMIPSOP_SH_MC): Likewise.
1096 (MICROMIPSOP_MASK_MD, MICROMIPSOP_SH_MD): Likewise.
1097 (MICROMIPSOP_MASK_ME, MICROMIPSOP_SH_ME): Likewise.
1098 (MICROMIPSOP_MASK_MF, MICROMIPSOP_SH_MF): Likewise.
1099 (MICROMIPSOP_MASK_MG, MICROMIPSOP_SH_MG): Likewise.
1100 (MICROMIPSOP_MASK_MH, MICROMIPSOP_SH_MH): Likewise.
1101 (MICROMIPSOP_MASK_MI, MICROMIPSOP_SH_MI): Likewise.
1102 (MICROMIPSOP_MASK_MJ, MICROMIPSOP_SH_MJ): Likewise.
1103 (MICROMIPSOP_MASK_ML, MICROMIPSOP_SH_ML): Likewise.
1104 (MICROMIPSOP_MASK_MM, MICROMIPSOP_SH_MM): Likewise.
1105 (MICROMIPSOP_MASK_MN, MICROMIPSOP_SH_MN): Likewise.
1106 (MICROMIPSOP_MASK_MP, MICROMIPSOP_SH_MP): Likewise.
1107 (MICROMIPSOP_MASK_MQ, MICROMIPSOP_SH_MQ): Likewise.
1108 (MICROMIPSOP_MASK_IMMA, MICROMIPSOP_SH_IMMA): Likewise.
1109 (MICROMIPSOP_MASK_IMMB, MICROMIPSOP_SH_IMMB): Likewise.
1110 (MICROMIPSOP_MASK_IMMC, MICROMIPSOP_SH_IMMC): Likewise.
1111 (MICROMIPSOP_MASK_IMMD, MICROMIPSOP_SH_IMMD): Likewise.
1112 (MICROMIPSOP_MASK_IMME, MICROMIPSOP_SH_IMME): Likewise.
1113 (MICROMIPSOP_MASK_IMMF, MICROMIPSOP_SH_IMMF): Likewise.
1114 (MICROMIPSOP_MASK_IMMG, MICROMIPSOP_SH_IMMG): Likewise.
1115 (MICROMIPSOP_MASK_IMMH, MICROMIPSOP_SH_IMMH): Likewise.
1116 (MICROMIPSOP_MASK_IMMI, MICROMIPSOP_SH_IMMI): Likewise.
1117 (MICROMIPSOP_MASK_IMMJ, MICROMIPSOP_SH_IMMJ): Likewise.
1118 (MICROMIPSOP_MASK_IMML, MICROMIPSOP_SH_IMML): Likewise.
1119 (MICROMIPSOP_MASK_IMMM, MICROMIPSOP_SH_IMMM): Likewise.
1120 (MICROMIPSOP_MASK_IMMN, MICROMIPSOP_SH_IMMN): Likewise.
1121 (MICROMIPSOP_MASK_IMMO, MICROMIPSOP_SH_IMMO): Likewise.
1122 (MICROMIPSOP_MASK_IMMP, MICROMIPSOP_SH_IMMP): Likewise.
1123 (MICROMIPSOP_MASK_IMMQ, MICROMIPSOP_SH_IMMQ): Likewise.
1124 (MICROMIPSOP_MASK_IMMU, MICROMIPSOP_SH_IMMU): Likewise.
1125 (MICROMIPSOP_MASK_IMMW, MICROMIPSOP_SH_IMMW): Likewise.
1126 (MICROMIPSOP_MASK_IMMX, MICROMIPSOP_SH_IMMX): Likewise.
1127 (MICROMIPSOP_MASK_IMMY, MICROMIPSOP_SH_IMMY): Likewise.
1128 (MICROMIPSOP_MASK_CODE, MICROMIPSOP_SH_CODE): Likewise.
1129 (MICROMIPSOP_MASK_CODE2, MICROMIPSOP_SH_CODE2): Likewise.
1130 (MICROMIPSOP_MASK_CACHE, MICROMIPSOP_SH_CACHE): Likewise.
1131 (MICROMIPSOP_MASK_CODE20, MICROMIPSOP_SH_CODE20): Likewise.
1132 (MICROMIPSOP_MASK_PERFREG, MICROMIPSOP_SH_PERFREG): Likewise.
1133 (MICROMIPSOP_MASK_CODE19, MICROMIPSOP_SH_CODE19): Likewise.
1134 (MICROMIPSOP_MASK_ALN, MICROMIPSOP_SH_ALN): Likewise.
1135 (MICROMIPSOP_MASK_VECBYTE, MICROMIPSOP_SH_VECBYTE): Likewise.
1136 (MICROMIPSOP_MASK_VECALIGN, MICROMIPSOP_SH_VECALIGN): Likewise.
1137 (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Likewise.
1138 (MICROMIPSOP_MASK_DSPACC_S, MICROMIPSOP_SH_DSPACC_S): Likewise.
1139 (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
1140 (MICROMIPSOP_MASK_DSPSFT_7, MICROMIPSOP_SH_DSPSFT_7): Likewise.
1141 (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
1142 (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
1143 (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
1144 (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
1145 (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
1146 (MICROMIPSOP_MASK_RDDSP, MICROMIPSOP_SH_RDDSP): Likewise.
1147 (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
1148 (MICROMIPSOP_MASK_MT_U, MICROMIPSOP_SH_MT_U): Likewise.
1149 (MICROMIPSOP_MASK_MT_H, MICROMIPSOP_SH_MT_H): Likewise.
1150 (MICROMIPSOP_MASK_MTACC_T, MICROMIPSOP_SH_MTACC_T): Likewise.
1151 (MICROMIPSOP_MASK_MTACC_D, MICROMIPSOP_SH_MTACC_D): Likewise.
1152 (MICROMIPSOP_MASK_BBITIND, MICROMIPSOP_SH_BBITIND): Likewise.
1153 (MICROMIPSOP_MASK_CINSPOS, MICROMIPSOP_SH_CINSPOS): Likewise.
1154 (MICROMIPSOP_MASK_CINSLM1, MICROMIPSOP_SH_CINSLM1): Likewise.
1155 (MICROMIPSOP_MASK_SEQI, MICROMIPSOP_SH_SEQI): Likewise.
1156 (micromips_opcodes): New declaration.
1157 (bfd_micromips_num_opcodes): Likewise.
1159 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
1161 * mips.h (INSN_TRAP): Rename to...
1162 (INSN_NO_DELAY_SLOT): ... this.
1163 (INSN_SYNC): Remove macro.
1165 2011-07-01 Eric B. Weddington <eric.weddington@atmel.com>
1167 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
1168 a duplicate of AVR_ISA_SPM.
1170 2011-07-01 Nick Clifton <nickc@redhat.com>
1172 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
1174 2011-06-18 Robin Getz <robin.getz@analog.com>
1176 * bfin.h (is_macmod_signed): New func
1178 2011-06-18 Mike Frysinger <vapier@gentoo.org>
1180 * bfin.h (is_macmod_pmove): Add missing space before func args.
1181 (is_macmod_hmove): Likewise.
1183 2011-06-13 Walter Lee <walt@tilera.com>
1185 * tilegx.h: New file.
1186 * tilepro.h: New file.
1188 2011-05-31 Paul Brook <paul@codesourcery.com>
1190 * arm.h (ARM_ARCH_V7R_IDIV): Define.
1192 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1194 * s390.h: Replace S390_OPERAND_REG_EVEN with
1195 S390_OPERAND_REG_PAIR.
1197 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1199 * s390.h: Add S390_OPCODE_REG_EVEN flag.
1201 2011-04-18 Julian Brown <julian@codesourcery.com>
1203 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
1205 2011-04-11 Dan McDonald <dan@wellkeeper.com>
1208 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
1210 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
1212 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
1213 New instruction set flags.
1214 (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
1216 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
1218 * mips.h (M_PREF_AB): New enum value.
1220 2011-02-12 Mike Frysinger <vapier@gentoo.org>
1222 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
1224 (is_macmod_pmove, is_macmod_hmove): New functions.
1226 2011-02-11 Mike Frysinger <vapier@gentoo.org>
1228 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
1230 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
1232 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
1233 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
1235 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1238 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
1241 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1244 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
1246 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
1248 * mips.h: Update commentary after last commit.
1250 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
1252 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
1253 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
1254 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
1256 2010-11-25 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
1258 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
1260 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
1262 * mips.h: Fix previous commit.
1264 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
1266 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1267 (INSN_LOONGSON_3A): Clear bit 31.
1269 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1272 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1273 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
1274 (ARM_ARCH_V6M_ONLY): New define.
1276 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
1278 * mips.h (INSN_LOONGSON_3A): Defined.
1279 (CPU_LOONGSON_3A): Defined.
1280 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
1282 2010-10-09 Matt Rice <ratmice@gmail.com>
1284 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1285 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
1287 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1289 * arm.h (ARM_EXT_VIRT): New define.
1290 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
1291 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
1294 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1296 * arm.h (ARM_AEXT_ADIV): New define.
1297 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
1299 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1301 * arm.h (ARM_EXT_OS): New define.
1302 (ARM_AEXT_V6SM): Likewise.
1303 (ARM_ARCH_V6SM): Likewise.
1305 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
1307 * arm.h (ARM_EXT_MP): Add.
1308 (ARM_ARCH_V7A_MP): Likewise.
1310 2010-09-22 Mike Frysinger <vapier@gentoo.org>
1312 * bfin.h: Declare pseudoChr structs/defines.
1314 2010-09-21 Mike Frysinger <vapier@gentoo.org>
1316 * bfin.h: Strip trailing whitespace.
1318 2010-07-29 DJ Delorie <dj@redhat.com>
1320 * rx.h (RX_Operand_Type): Add TwoReg.
1321 (RX_Opcode_ID): Remove ediv and ediv2.
1323 2010-07-27 DJ Delorie <dj@redhat.com>
1325 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1327 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
1328 Ina Pandit <ina.pandit@kpitcummins.com>
1330 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1331 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
1332 PROCESSOR_V850E2_ALL.
1333 Remove PROCESSOR_V850EA support.
1334 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
1335 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
1336 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
1337 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
1338 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
1339 V850_OPERAND_PERCENT.
1340 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
1342 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
1345 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
1347 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1348 (MIPS16_INSN_BRANCH): Rename to...
1349 (MIPS16_INSN_COND_BRANCH): ... this.
1351 2010-07-03 Alan Modra <amodra@gmail.com>
1353 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1354 Renumber other PPC_OPCODE defines.
1356 2010-07-03 Alan Modra <amodra@gmail.com>
1358 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1360 2010-06-29 Alan Modra <amodra@gmail.com>
1362 * maxq.h: Delete file.
1364 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
1366 * ppc.h (PPC_OPCODE_E500): Define.
1368 2010-05-26 Catherine Moore <clm@codesourcery.com>
1370 * opcode/mips.h (INSN_MIPS16): Remove.
1372 2010-04-21 Joseph Myers <joseph@codesourcery.com>
1374 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1376 2010-04-15 Nick Clifton <nickc@redhat.com>
1378 * alpha.h: Update copyright notice to use GPLv3.
1384 * convex.h: Likewise.
1391 * h8300.h: Likewise.
1398 * m68hc11.h: Likewise.
1404 * mn10200.h: Likewise.
1405 * mn10300.h: Likewise.
1406 * msp430.h: Likewise.
1408 * ns32k.h: Likewise.
1410 * pdp11.h: Likewise.
1417 * score-datadep.h: Likewise.
1418 * score-inst.h: Likewise.
1419 * sparc.h: Likewise.
1420 * spu-insns.h: Likewise.
1422 * tic30.h: Likewise.
1423 * tic4x.h: Likewise.
1424 * tic54x.h: Likewise.
1425 * tic80.h: Likewise.
1429 2010-03-25 Joseph Myers <joseph@codesourcery.com>
1431 * tic6x-control-registers.h, tic6x-insn-formats.h,
1432 tic6x-opcode-table.h, tic6x.h: New.
1434 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
1436 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1438 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
1440 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1442 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
1444 * ia64.h (ia64_find_opcode): Remove argument name.
1445 (ia64_find_next_opcode): Likewise.
1446 (ia64_dis_opcode): Likewise.
1447 (ia64_free_opcode): Likewise.
1448 (ia64_find_dependency): Likewise.
1450 2009-11-22 Doug Evans <dje@sebabeach.org>
1452 * cgen.h: Include bfd_stdint.h.
1453 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
1455 2009-11-18 Paul Brook <paul@codesourcery.com>
1457 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1459 2009-11-17 Paul Brook <paul@codesourcery.com>
1460 Daniel Jacobowitz <dan@codesourcery.com>
1462 * arm.h (ARM_EXT_V6_DSP): Define.
1463 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
1464 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
1466 2009-11-04 DJ Delorie <dj@redhat.com>
1468 * rx.h (rx_decode_opcode) (mvtipl): Add.
1469 (mvtcp, mvfcp, opecp): Remove.
1471 2009-11-02 Paul Brook <paul@codesourcery.com>
1473 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1474 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
1475 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
1476 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
1477 FPU_ARCH_NEON_VFP_V4): Define.
1479 2009-10-23 Doug Evans <dje@sebabeach.org>
1481 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1482 * cgen.h: Update. Improve multi-inclusion macro name.
1484 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
1486 * ppc.h (PPC_OPCODE_476): Define.
1488 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
1490 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1492 2009-09-29 DJ Delorie <dj@redhat.com>
1496 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
1498 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1500 2009-09-21 Ben Elliston <bje@au.ibm.com>
1502 * ppc.h (PPC_OPCODE_PPCA2): New.
1504 2009-09-05 Martin Thuresson <martin@mtme.org>
1506 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1508 2009-08-29 Martin Thuresson <martin@mtme.org>
1510 * tic30.h (template): Rename type template to
1511 insn_template. Updated code to use new name.
1512 * tic54x.h (template): Rename type template to
1515 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
1517 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1519 2009-06-11 Anthony Green <green@moxielogic.com>
1521 * moxie.h (MOXIE_F3_PCREL): Define.
1522 (moxie_form3_opc_info): Grow.
1524 2009-06-06 Anthony Green <green@moxielogic.com>
1526 * moxie.h (MOXIE_F1_M): Define.
1528 2009-04-15 Anthony Green <green@moxielogic.com>
1532 2009-04-06 DJ Delorie <dj@redhat.com>
1534 * h8300.h: Add relaxation attributes to MOVA opcodes.
1536 2009-03-10 Alan Modra <amodra@bigpond.net.au>
1538 * ppc.h (ppc_parse_cpu): Declare.
1540 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
1542 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1543 and _IMM11 for mbitclr and mbitset.
1544 * score-datadep.h: Update dependency information.
1546 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
1548 * ppc.h (PPC_OPCODE_POWER7): New.
1550 2009-02-06 Doug Evans <dje@google.com>
1552 * i386.h: Add comment regarding sse* insns and prefixes.
1554 2009-02-03 Sandip Matte <sandip@rmicorp.com>
1556 * mips.h (INSN_XLR): Define.
1557 (INSN_CHIP_MASK): Update.
1559 (OPCODE_IS_MEMBER): Update.
1560 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
1562 2009-01-28 Doug Evans <dje@google.com>
1564 * opcode/i386.h: Add multiple inclusion protection.
1565 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
1566 (EDI_REG_NUM): New macros.
1567 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
1568 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
1569 (REX_PREFIX_P): New macro.
1571 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
1573 * ppc.h (struct powerpc_opcode): New field "deprecated".
1574 (PPC_OPCODE_NOPOWER4): Delete.
1576 2008-11-28 Joshua Kinard <kumba@gentoo.org>
1578 * mips.h: Define CPU_R14000, CPU_R16000.
1579 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
1581 2008-11-18 Catherine Moore <clm@codesourcery.com>
1583 * arm.h (FPU_NEON_FP16): New.
1584 (FPU_ARCH_NEON_FP16): New.
1586 2008-11-06 Chao-ying Fu <fu@mips.com>
1588 * mips.h: Doucument '1' for 5-bit sync type.
1590 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
1592 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1595 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
1597 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1599 2008-07-30 Michael J. Eager <eager@eagercon.com>
1601 * ppc.h (PPC_OPCODE_405): Define.
1602 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
1604 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
1606 * ppc.h (ppc_cpu_t): New typedef.
1607 (struct powerpc_opcode <flags>): Use it.
1608 (struct powerpc_operand <insert, extract>): Likewise.
1609 (struct powerpc_macro <flags>): Likewise.
1611 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
1613 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1614 Update comment before MIPS16 field descriptors to mention MIPS16.
1615 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
1617 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
1618 New bit masks and shift counts for cins and exts.
1620 * mips.h: Document new field descriptors +Q.
1621 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
1623 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
1625 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1626 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
1628 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
1630 * ppc.h: (PPC_OPCODE_E500MC): New.
1632 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
1634 * i386.h (MAX_OPERANDS): Set to 5.
1635 (MAX_MNEM_SIZE): Changed to 20.
1637 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
1639 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1641 2008-03-09 Paul Brook <paul@codesourcery.com>
1643 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1645 2008-03-04 Paul Brook <paul@codesourcery.com>
1647 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1648 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
1649 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
1651 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
1652 Nick Clifton <nickc@redhat.com>
1655 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1656 with a 32-bit displacement but without the top bit of the 4th byte
1659 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1661 * cr16.h (cr16_num_optab): Declared.
1663 2008-02-14 Hakan Ardo <hakan@debian.org>
1666 * avr.h (AVR_ISA_2xxe): Define.
1668 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
1670 * mips.h: Update copyright.
1671 (INSN_CHIP_MASK): New macro.
1672 (INSN_OCTEON): New macro.
1673 (CPU_OCTEON): New macro.
1674 (OPCODE_IS_MEMBER): Handle Octeon instructions.
1676 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
1678 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1680 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
1682 * avr.h (AVR_ISA_USB162): Add new opcode set.
1683 (AVR_ISA_AVR3): Likewise.
1685 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1687 * mips.h (INSN_LOONGSON_2E): New.
1688 (INSN_LOONGSON_2F): New.
1689 (CPU_LOONGSON_2E): New.
1690 (CPU_LOONGSON_2F): New.
1691 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
1693 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
1695 * mips.h (INSN_ISA*): Redefine certain values as an
1696 enumeration. Update comments.
1697 (mips_isa_table): New.
1698 (ISA_MIPS*): Redefine to match enumeration.
1699 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
1702 2007-08-08 Ben Elliston <bje@au.ibm.com>
1704 * ppc.h (PPC_OPCODE_PPCPS): New.
1706 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
1708 * m68k.h: Document j K & E.
1710 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
1712 * cr16.h: New file for CR16 target.
1714 2007-05-02 Alan Modra <amodra@bigpond.net.au>
1716 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1718 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
1720 * m68k.h (mcfisa_c): New.
1721 (mcfusp, mcf_mask): Adjust.
1723 2007-04-20 Alan Modra <amodra@bigpond.net.au>
1725 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1726 (num_powerpc_operands): Declare.
1727 (PPC_OPERAND_SIGNED et al): Redefine as hex.
1728 (PPC_OPERAND_PLUS1): Define.
1730 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
1732 * i386.h (REX_MODE64): Renamed to ...
1734 (REX_EXTX): Renamed to ...
1736 (REX_EXTY): Renamed to ...
1738 (REX_EXTZ): Renamed to ...
1741 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
1743 * i386.h: Add entries from config/tc-i386.h and move tables
1744 to opcodes/i386-opc.h.
1746 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
1748 * i386.h (FloatDR): Removed.
1749 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
1751 2007-03-01 Alan Modra <amodra@bigpond.net.au>
1753 * spu-insns.h: Add soma double-float insns.
1755 2007-02-20 Thiemo Seufer <ths@mips.com>
1756 Chao-Ying Fu <fu@mips.com>
1758 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1759 (INSN_DSPR2): Add flag for DSP R2 instructions.
1760 (M_BALIGN): New macro.
1762 2007-02-14 Alan Modra <amodra@bigpond.net.au>
1764 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1765 and Seg3ShortFrom with Shortform.
1767 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
1770 * i386.h (i386_optab): Put the real "test" before the pseudo
1773 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
1775 * m68k.h (m68010up): OR fido_a.
1777 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
1779 * m68k.h (fido_a): New.
1781 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
1783 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1784 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
1787 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
1789 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1791 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
1793 * score-inst.h (enum score_insn_type): Add Insn_internal.
1795 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
1796 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
1797 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
1798 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
1799 Alan Modra <amodra@bigpond.net.au>
1801 * spu-insns.h: New file.
1804 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
1806 * ppc.h (PPC_OPCODE_CELL): Define.
1808 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1810 * i386.h : Modify opcode to support for the change in POPCNT opcode
1811 in amdfam10 architecture.
1813 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
1815 * i386.h: Replace CpuMNI with CpuSSSE3.
1817 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
1818 Joseph Myers <joseph@codesourcery.com>
1819 Ian Lance Taylor <ian@wasabisystems.com>
1820 Ben Elliston <bje@wasabisystems.com>
1822 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1824 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
1826 * score-datadep.h: New file.
1827 * score-inst.h: New file.
1829 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
1831 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1832 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
1833 movdq2q and movq2dq.
1835 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
1836 Michael Meissner <michael.meissner@amd.com>
1838 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1840 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1842 * i386.h (i386_optab): Add "nop" with memory reference.
1844 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
1846 * i386.h (i386_optab): Update comment for 64bit NOP.
1848 2006-06-06 Ben Elliston <bje@au.ibm.com>
1849 Anton Blanchard <anton@samba.org>
1851 * ppc.h (PPC_OPCODE_POWER6): Define.
1854 2006-06-05 Thiemo Seufer <ths@mips.com>
1856 * mips.h: Improve description of MT flags.
1858 2006-05-25 Richard Sandiford <richard@codesourcery.com>
1860 * m68k.h (mcf_mask): Define.
1862 2006-05-05 Thiemo Seufer <ths@mips.com>
1863 David Ung <davidu@mips.com>
1865 * mips.h (enum): Add macro M_CACHE_AB.
1867 2006-05-04 Thiemo Seufer <ths@mips.com>
1868 Nigel Stephens <nigel@mips.com>
1869 David Ung <davidu@mips.com>
1871 * mips.h: Add INSN_SMARTMIPS define.
1873 2006-04-30 Thiemo Seufer <ths@mips.com>
1874 David Ung <davidu@mips.com>
1876 * mips.h: Defines udi bits and masks. Add description of
1877 characters which may appear in the args field of udi
1880 2006-04-26 Thiemo Seufer <ths@networkno.de>
1882 * mips.h: Improve comments describing the bitfield instruction
1885 2006-04-26 Julian Brown <julian@codesourcery.com>
1887 * arm.h (FPU_VFP_EXT_V3): Define constant.
1888 (FPU_NEON_EXT_V1): Likewise.
1889 (FPU_VFP_HARD): Update.
1890 (FPU_VFP_V3): Define macro.
1891 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
1893 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
1895 * avr.h (AVR_ISA_PWMx): New.
1897 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
1899 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1900 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
1901 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
1902 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
1903 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
1905 2006-03-10 Paul Brook <paul@codesourcery.com>
1907 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1909 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1911 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1912 first. Correct mask of bb "B" opcode.
1914 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
1916 * i386.h (i386_optab): Support Intel Merom New Instructions.
1918 2006-02-24 Paul Brook <paul@codesourcery.com>
1920 * arm.h: Add V7 feature bits.
1922 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
1924 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1926 2006-01-31 Paul Brook <paul@codesourcery.com>
1927 Richard Earnshaw <rearnsha@arm.com>
1929 * arm.h: Use ARM_CPU_FEATURE.
1930 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
1931 (arm_feature_set): Change to a structure.
1932 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
1933 ARM_FEATURE): New macros.
1935 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
1937 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1938 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
1939 (ADD_PC_INCR_OPCODE): Don't define.
1941 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
1944 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1946 2005-11-14 David Ung <davidu@mips.com>
1948 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1949 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
1950 save/restore encoding of the args field.
1952 2005-10-28 Dave Brolley <brolley@redhat.com>
1954 Contribute the following changes:
1955 2005-02-16 Dave Brolley <brolley@redhat.com>
1957 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1958 cgen_isa_mask_* to cgen_bitset_*.
1961 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
1963 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1964 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
1965 (CGEN_CPU_TABLE): Make isas a ponter.
1967 2003-09-29 Dave Brolley <brolley@redhat.com>
1969 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1970 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
1971 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
1973 2002-12-13 Dave Brolley <brolley@redhat.com>
1975 * cgen.h (symcat.h): #include it.
1976 (cgen-bitset.h): #include it.
1977 (CGEN_ATTR_VALUE_TYPE): Now a union.
1978 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1979 (CGEN_ATTR_ENTRY): 'value' now unsigned.
1980 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
1981 * cgen-bitset.h: New file.
1983 2005-09-30 Catherine Moore <clm@cm00re.com>
1987 2005-10-24 Jan Beulich <jbeulich@novell.com>
1989 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1992 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1994 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1995 Add FLAG_STRICT to pa10 ftest opcode.
1997 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1999 * hppa.h (pa_opcodes): Remove lha entries.
2001 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2003 * hppa.h (FLAG_STRICT): Revise comment.
2004 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
2005 before corresponding pa11 opcodes. Add strict pa10 register-immediate
2008 2005-09-30 Catherine Moore <clm@cm00re.com>
2012 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2014 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
2016 2005-09-06 Chao-ying Fu <fu@mips.com>
2018 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
2019 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
2021 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
2022 (INSN_ASE_MASK): Update to include INSN_MT.
2023 (INSN_MT): New define for MT ASE.
2025 2005-08-25 Chao-ying Fu <fu@mips.com>
2027 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
2028 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
2029 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
2030 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
2031 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
2032 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
2034 (INSN_DSP): New define for DSP ASE.
2036 2005-08-18 Alan Modra <amodra@bigpond.net.au>
2040 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
2042 * ppc.h (PPC_OPCODE_E300): Define.
2044 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
2046 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
2048 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2051 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
2054 2005-07-27 Jan Beulich <jbeulich@novell.com>
2056 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
2057 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
2058 Add movq-s as 64-bit variants of movd-s.
2060 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2062 * hppa.h: Fix punctuation in comment.
2064 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
2065 implicit space-register addressing. Set space-register bits on opcodes
2066 using implicit space-register addressing. Add various missing pa20
2067 long-immediate opcodes. Remove various opcodes using implicit 3-bit
2068 space-register addressing. Use "fE" instead of "fe" in various
2071 2005-07-18 Jan Beulich <jbeulich@novell.com>
2073 * i386.h (i386_optab): Operands of aam and aad are unsigned.
2075 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
2077 * i386.h (i386_optab): Support Intel VMX Instructions.
2079 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2081 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
2083 2005-07-05 Jan Beulich <jbeulich@novell.com>
2085 * i386.h (i386_optab): Add new insns.
2087 2005-07-01 Nick Clifton <nickc@redhat.com>
2089 * sparc.h: Add typedefs to structure declarations.
2091 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
2094 * i386.h (i386_optab): Update comments for 64bit addressing on
2095 mov. Allow 64bit addressing for mov and movq.
2097 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2099 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
2100 respectively, in various floating-point load and store patterns.
2102 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
2104 * hppa.h (FLAG_STRICT): Correct comment.
2105 (pa_opcodes): Update load and store entries to allow both PA 1.X and
2106 PA 2.0 mneumonics when equivalent. Entries with cache control
2107 completers now require PA 1.1. Adjust whitespace.
2109 2005-05-19 Anton Blanchard <anton@samba.org>
2111 * ppc.h (PPC_OPCODE_POWER5): Define.
2113 2005-05-10 Nick Clifton <nickc@redhat.com>
2115 * Update the address and phone number of the FSF organization in
2116 the GPL notices in the following files:
2117 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
2118 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
2119 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
2120 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
2121 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
2122 tic54x.h, tic80.h, v850.h, vax.h
2124 2005-05-09 Jan Beulich <jbeulich@novell.com>
2126 * i386.h (i386_optab): Add ht and hnt.
2128 2005-04-18 Mark Kettenis <kettenis@gnu.org>
2130 * i386.h: Insert hyphens into selected VIA PadLock extensions.
2131 Add xcrypt-ctr. Provide aliases without hyphens.
2133 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
2135 Moved from ../ChangeLog
2137 2005-04-12 Paul Brook <paul@codesourcery.com>
2138 * m88k.h: Rename psr macros to avoid conflicts.
2140 2005-03-12 Zack Weinberg <zack@codesourcery.com>
2141 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
2142 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
2143 and ARM_ARCH_V6ZKT2.
2145 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
2146 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
2147 Remove redundant instruction types.
2148 (struct argument): X_op - new field.
2149 (struct cst4_entry): Remove.
2150 (no_op_insn): Declare.
2152 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
2153 * crx.h (enum argtype): Rename types, remove unused types.
2155 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
2156 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
2157 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
2158 (enum operand_type): Rearrange operands, edit comments.
2159 replace us<N> with ui<N> for unsigned immediate.
2160 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
2161 displacements (respectively).
2162 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
2163 (instruction type): Add NO_TYPE_INS.
2164 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
2165 (operand_entry): New field - 'flags'.
2166 (operand flags): New.
2168 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
2169 * crx.h (operand_type): Remove redundant types i3, i4,
2171 Add new unsigned immediate types us3, us4, us5, us16.
2173 2005-04-12 Mark Kettenis <kettenis@gnu.org>
2175 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
2176 adjust them accordingly.
2178 2005-04-01 Jan Beulich <jbeulich@novell.com>
2180 * i386.h (i386_optab): Add rdtscp.
2182 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
2184 * i386.h (i386_optab): Don't allow the `l' suffix for moving
2185 between memory and segment register. Allow movq for moving between
2186 general-purpose register and segment register.
2188 2005-02-09 Jan Beulich <jbeulich@novell.com>
2191 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
2192 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
2195 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
2197 * m68k.h (m68008, m68ec030, m68882): Remove.
2199 (cpu_m68k, cpu_cf): New.
2200 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
2201 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
2203 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
2205 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
2206 * cgen.h (enum cgen_parse_operand_type): Add
2207 CGEN_PARSE_OPERAND_SYMBOLIC.
2209 2005-01-21 Fred Fish <fnf@specifixinc.com>
2211 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
2212 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
2213 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
2215 2005-01-19 Fred Fish <fnf@specifixinc.com>
2217 * mips.h (struct mips_opcode): Add new pinfo2 member.
2218 (INSN_ALIAS): New define for opcode table entries that are
2219 specific instances of another entry, such as 'move' for an 'or'
2220 with a zero operand.
2221 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
2222 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
2224 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
2226 * mips.h (CPU_RM9000): Define.
2227 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
2229 2004-11-25 Jan Beulich <jbeulich@novell.com>
2231 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
2232 to/from test registers are illegal in 64-bit mode. Add missing
2233 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
2234 (previously one had to explicitly encode a rex64 prefix). Re-enable
2235 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
2236 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
2238 2004-11-23 Jan Beulich <jbeulich@novell.com>
2240 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
2241 available only with SSE2. Change the MMX additions introduced by SSE
2242 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
2243 instructions by their now designated identifier (since combining i686
2244 and 3DNow! does not really imply 3DNow!A).
2246 2004-11-19 Alan Modra <amodra@bigpond.net.au>
2248 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
2249 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
2251 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
2252 Vineet Sharma <vineets@noida.hcltech.com>
2254 * maxq.h: New file: Disassembly information for the maxq port.
2256 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
2258 * i386.h (i386_optab): Put back "movzb".
2260 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
2262 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2263 comments. Remove member cris_ver_sim. Add members
2264 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
2265 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
2266 (struct cris_support_reg, struct cris_cond15): New types.
2267 (cris_conds15): Declare.
2268 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
2269 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
2270 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
2271 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
2272 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
2273 SIZE_FIELD_UNSIGNED.
2275 2004-11-04 Jan Beulich <jbeulich@novell.com>
2277 * i386.h (sldx_Suf): Remove.
2278 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
2279 (q_FP): Define, implying no REX64.
2280 (x_FP, sl_FP): Imply FloatMF.
2281 (i386_optab): Split reg and mem forms of moving from segment registers
2282 so that the memory forms can ignore the 16-/32-bit operand size
2283 distinction. Adjust a few others for Intel mode. Remove *FP uses from
2284 all non-floating-point instructions. Unite 32- and 64-bit forms of
2285 movsx, movzx, and movd. Adjust floating point operations for the above
2286 changes to the *FP macros. Add DefaultSize to floating point control
2287 insns operating on larger memory ranges. Remove left over comments
2288 hinting at certain insns being Intel-syntax ones where the ones
2289 actually meant are already gone.
2291 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
2293 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2296 2004-09-30 Paul Brook <paul@codesourcery.com>
2298 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2299 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
2301 2004-09-11 Theodore A. Roth <troth@openavr.org>
2303 * avr.h: Add support for
2304 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
2306 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
2308 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2310 2004-08-24 Dmitry Diky <diwil@spec.ru>
2312 * msp430.h (msp430_opc): Add new instructions.
2313 (msp430_rcodes): Declare new instructions.
2314 (msp430_hcodes): Likewise..
2316 2004-08-13 Nick Clifton <nickc@redhat.com>
2319 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2322 2004-08-30 Michal Ludvig <mludvig@suse.cz>
2324 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2326 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
2328 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2330 2004-07-21 Jan Beulich <jbeulich@novell.com>
2332 * i386.h: Adjust instruction descriptions to better match the
2335 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
2337 * arm.h: Remove all old content. Replace with architecture defines
2338 from gas/config/tc-arm.c.
2340 2004-07-09 Andreas Schwab <schwab@suse.de>
2342 * m68k.h: Fix comment.
2344 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2348 2004-06-24 Alan Modra <amodra@bigpond.net.au>
2350 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2352 2004-05-24 Peter Barada <peter@the-baradas.com>
2354 * m68k.h: Add 'size' to m68k_opcode.
2356 2004-05-05 Peter Barada <peter@the-baradas.com>
2358 * m68k.h: Switch from ColdFire chip name to core variant.
2360 2004-04-22 Peter Barada <peter@the-baradas.com>
2362 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2363 descriptions for new EMAC cases.
2364 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
2365 handle Motorola MAC syntax.
2366 Allow disassembly of ColdFire V4e object files.
2368 2004-03-16 Alan Modra <amodra@bigpond.net.au>
2370 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2372 2004-03-12 Jakub Jelinek <jakub@redhat.com>
2374 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2376 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2378 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2380 2004-03-12 Michal Ludvig <mludvig@suse.cz>
2382 * i386.h (i386_optab): Added xstore/xcrypt insns.
2384 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
2386 * h8300.h (32bit ldc/stc): Add relaxing support.
2388 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
2390 * h8300.h (BITOP): Pass MEMRELAX flag.
2392 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
2394 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
2397 For older changes see ChangeLog-9103
2399 Copyright (C) 2004-2015 Free Software Foundation, Inc.
2401 Copying and distribution of this file, with or without modification,
2402 are permitted in any medium without royalty provided the copyright
2403 notice and this notice are preserved.
2409 version-control: never
projects / deliverable / binutils-gdb.git / blob