include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright 2009, 2010, 2011, 2012  Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 /* The offset for pc-relative addressing is currently defined to be 0.  */
  31 #define AARCH64_PCREL_OFFSET            0
  32
  33 typedef uint32_t aarch64_insn;
  34
  35 /* The following bitmasks control CPU features.  */
  36 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  37 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  38 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  39 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  40
  41 /* Architectures are the sum of the base and extensions.  */
  42 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  43                                                  AARCH64_FEATURE_FP  \
  44                                                  | AARCH64_FEATURE_SIMD)
  45 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
  46 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
  47
  48 /* CPU-specific features.  */
  49 typedef unsigned long aarch64_feature_set;
  50
  51 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
  52   (((CPU) & (FEAT)) != 0)
  53
  54 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
  55   do                                            \
  56     {                                           \
  57       (TARG) = (F1) | (F2);                     \
  58     }                                           \
  59   while (0)
  60
  61 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
  62   do                                            \
  63     {                                           \
  64       (TARG) = (F1) &~ (F2);                    \
  65     }                                           \
  66   while (0)
  67
  68 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
  69
  70 #define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT)    \
  71   (((OPC) & (FEAT)) != 0)
  72
  73 enum aarch64_operand_class
  74 {
  75   AARCH64_OPND_CLASS_NIL,
  76   AARCH64_OPND_CLASS_INT_REG,
  77   AARCH64_OPND_CLASS_MODIFIED_REG,
  78   AARCH64_OPND_CLASS_FP_REG,
  79   AARCH64_OPND_CLASS_SIMD_REG,
  80   AARCH64_OPND_CLASS_SIMD_ELEMENT,
  81   AARCH64_OPND_CLASS_SISD_REG,
  82   AARCH64_OPND_CLASS_SIMD_REGLIST,
  83   AARCH64_OPND_CLASS_CP_REG,
  84   AARCH64_OPND_CLASS_ADDRESS,
  85   AARCH64_OPND_CLASS_IMMEDIATE,
  86   AARCH64_OPND_CLASS_SYSTEM,
  87 };
  88
  89 /* Operand code that helps both parsing and coding.
  90    Keep AARCH64_OPERANDS synced.  */
  91
  92 enum aarch64_opnd
  93 {
  94   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
  95
  96   AARCH64_OPND_Rd,      /* Integer register as destination.  */
  97   AARCH64_OPND_Rn,      /* Integer register as source.  */
  98   AARCH64_OPND_Rm,      /* Integer register as source.  */
  99   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 100   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 101   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 102   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 103   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 104
 105   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 106   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 107   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 108   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 109
 110   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 111   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 112   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 113   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 114   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 115   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 116
 117   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 118   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 119   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 120
 121   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 122   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 123   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 124   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 125   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 126   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 127   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 128   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 129   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 130   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 131   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 132                            structure to all lanes.  */
 133   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 134
 135   AARCH64_OPND_Cn,      /* Co-processor register in CRn field.  */
 136   AARCH64_OPND_Cm,      /* Co-processor register in CRm field.  */
 137
 138   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 139   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 140   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 141   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 142   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 143   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 144   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 145                            (no encoding).  */
 146   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 147   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 148   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 149   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 150   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 151   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 152   AARCH64_OPND_IMM,     /* Immediate.  */
 153   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 154   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 155   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 156   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 157   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 158   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 159   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 160   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 161                            each condition flag.  */
 162
 163   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 164   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 165   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 166   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 167   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 168
 169   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 170
 171   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 172   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 173   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 174   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 175   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 176
 177   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 178   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 179   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 180   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 181   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 182                                    negative or unaligned and there is
 183                                    no writeback allowed.  This operand code
 184                                    is only used to support the programmer-
 185                                    friendly feature of using LDR/STR as the
 186                                    the mnemonic name for LDUR/STUR instructions
 187                                    wherever there is no ambiguity.  */
 188   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 189   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 190   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 191
 192   AARCH64_OPND_SYSREG,          /* System register operand.  */
 193   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 194   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 195   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 196   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 197   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 198   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 199   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 200   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 201 };
 202
 203 /* Qualifier constrains an operand.  It either specifies a variant of an
 204    operand type or limits values available to an operand type.
 205
 206    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 207
 208 enum aarch64_opnd_qualifier
 209 {
 210   /* Indicating no further qualification on an operand.  */
 211   AARCH64_OPND_QLF_NIL,
 212
 213   /* Qualifying an operand which is a general purpose (integer) register;
 214      indicating the operand data size or a specific register.  */
 215   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 216   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 217   AARCH64_OPND_QLF_WSP, /* WSP.  */
 218   AARCH64_OPND_QLF_SP,  /* SP.  */
 219
 220   /* Qualifying an operand which is a floating-point register, a SIMD
 221      vector element or a SIMD vector element list; indicating operand data
 222      size or the size of each SIMD vector element in the case of a SIMD
 223      vector element list.
 224      These qualifiers are also used to qualify an address operand to
 225      indicate the size of data element a load/store instruction is
 226      accessing.
 227      They are also used for the immediate shift operand in e.g. SSHR.  Such
 228      a use is only for the ease of operand encoding/decoding and qualifier
 229      sequence matching; such a use should not be applied widely; use the value
 230      constraint qualifiers for immediate operands wherever possible.  */
 231   AARCH64_OPND_QLF_S_B,
 232   AARCH64_OPND_QLF_S_H,
 233   AARCH64_OPND_QLF_S_S,
 234   AARCH64_OPND_QLF_S_D,
 235   AARCH64_OPND_QLF_S_Q,
 236
 237   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 238      register list; indicating register shape.
 239      They are also used for the immediate shift operand in e.g. SSHR.  Such
 240      a use is only for the ease of operand encoding/decoding and qualifier
 241      sequence matching; such a use should not be applied widely; use the value
 242      constraint qualifiers for immediate operands wherever possible.  */
 243   AARCH64_OPND_QLF_V_8B,
 244   AARCH64_OPND_QLF_V_16B,
 245   AARCH64_OPND_QLF_V_4H,
 246   AARCH64_OPND_QLF_V_8H,
 247   AARCH64_OPND_QLF_V_2S,
 248   AARCH64_OPND_QLF_V_4S,
 249   AARCH64_OPND_QLF_V_1D,
 250   AARCH64_OPND_QLF_V_2D,
 251   AARCH64_OPND_QLF_V_1Q,
 252
 253   /* Constraint on value.  */
 254   AARCH64_OPND_QLF_imm_0_7,
 255   AARCH64_OPND_QLF_imm_0_15,
 256   AARCH64_OPND_QLF_imm_0_31,
 257   AARCH64_OPND_QLF_imm_0_63,
 258   AARCH64_OPND_QLF_imm_1_32,
 259   AARCH64_OPND_QLF_imm_1_64,
 260
 261   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 262      or shift-ones.  */
 263   AARCH64_OPND_QLF_LSL,
 264   AARCH64_OPND_QLF_MSL,
 265
 266   /* Special qualifier helping retrieve qualifier information during the
 267      decoding time (currently not in use).  */
 268   AARCH64_OPND_QLF_RETRIEVE,
 269 };
 270 \f
 271 /* Instruction class.  */
 272
 273 enum aarch64_insn_class
 274 {
 275   addsub_carry,
 276   addsub_ext,
 277   addsub_imm,
 278   addsub_shift,
 279   asimdall,
 280   asimddiff,
 281   asimdelem,
 282   asimdext,
 283   asimdimm,
 284   asimdins,
 285   asimdmisc,
 286   asimdperm,
 287   asimdsame,
 288   asimdshf,
 289   asimdtbl,
 290   asisddiff,
 291   asisdelem,
 292   asisdlse,
 293   asisdlsep,
 294   asisdlso,
 295   asisdlsop,
 296   asisdmisc,
 297   asisdone,
 298   asisdpair,
 299   asisdsame,
 300   asisdshf,
 301   bitfield,
 302   branch_imm,
 303   branch_reg,
 304   compbranch,
 305   condbranch,
 306   condcmp_imm,
 307   condcmp_reg,
 308   condsel,
 309   cryptoaes,
 310   cryptosha2,
 311   cryptosha3,
 312   dp_1src,
 313   dp_2src,
 314   dp_3src,
 315   exception,
 316   extract,
 317   float2fix,
 318   float2int,
 319   floatccmp,
 320   floatcmp,
 321   floatdp1,
 322   floatdp2,
 323   floatdp3,
 324   floatimm,
 325   floatsel,
 326   ldst_immpost,
 327   ldst_immpre,
 328   ldst_imm9,    /* immpost or immpre */
 329   ldst_pos,
 330   ldst_regoff,
 331   ldst_unpriv,
 332   ldst_unscaled,
 333   ldstexcl,
 334   ldstnapair_offs,
 335   ldstpair_off,
 336   ldstpair_indexed,
 337   loadlit,
 338   log_imm,
 339   log_shift,
 340   movewide,
 341   pcreladdr,
 342   ic_system,
 343   testbranch,
 344 };
 345
 346 /* Opcode enumerators.  */
 347
 348 enum aarch64_op
 349 {
 350   OP_NIL,
 351   OP_STRB_POS,
 352   OP_LDRB_POS,
 353   OP_LDRSB_POS,
 354   OP_STRH_POS,
 355   OP_LDRH_POS,
 356   OP_LDRSH_POS,
 357   OP_STR_POS,
 358   OP_LDR_POS,
 359   OP_STRF_POS,
 360   OP_LDRF_POS,
 361   OP_LDRSW_POS,
 362   OP_PRFM_POS,
 363
 364   OP_STURB,
 365   OP_LDURB,
 366   OP_LDURSB,
 367   OP_STURH,
 368   OP_LDURH,
 369   OP_LDURSH,
 370   OP_STUR,
 371   OP_LDUR,
 372   OP_STURV,
 373   OP_LDURV,
 374   OP_LDURSW,
 375   OP_PRFUM,
 376
 377   OP_LDR_LIT,
 378   OP_LDRV_LIT,
 379   OP_LDRSW_LIT,
 380   OP_PRFM_LIT,
 381
 382   OP_ADD,
 383   OP_B,
 384   OP_BL,
 385
 386   OP_MOVN,
 387   OP_MOVZ,
 388   OP_MOVK,
 389
 390   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 391   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 392   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 393
 394   OP_MOV_V,             /* MOV alias for moving vector register.  */
 395
 396   OP_ASR_IMM,
 397   OP_LSR_IMM,
 398   OP_LSL_IMM,
 399
 400   OP_BIC,
 401
 402   OP_UBFX,
 403   OP_BFXIL,
 404   OP_SBFX,
 405   OP_SBFIZ,
 406   OP_BFI,
 407   OP_UBFIZ,
 408   OP_UXTB,
 409   OP_UXTH,
 410   OP_UXTW,
 411
 412   OP_V_MOVI_B,
 413
 414   OP_CINC,
 415   OP_CINV,
 416   OP_CNEG,
 417   OP_CSET,
 418   OP_CSETM,
 419
 420   OP_FCVT,
 421   OP_FCVTN,
 422   OP_FCVTN2,
 423   OP_FCVTL,
 424   OP_FCVTL2,
 425   OP_FCVTXN_S,          /* Scalar version.  */
 426
 427   OP_ROR_IMM,
 428
 429   OP_TOTAL_NUM,         /* Pseudo.  */
 430 };
 431
 432 /* Maximum number of operands an instruction can have.  */
 433 #define AARCH64_MAX_OPND_NUM 6
 434 /* Maximum number of qualifier sequences an instruction can have.  */
 435 #define AARCH64_MAX_QLF_SEQ_NUM 10
 436 /* Operand qualifier typedef; optimized for the size.  */
 437 typedef unsigned char aarch64_opnd_qualifier_t;
 438 /* Operand qualifier sequence typedef.  */
 439 typedef aarch64_opnd_qualifier_t        \
 440           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 441
 442 /* FIXME: improve the efficiency.  */
 443 static inline bfd_boolean
 444 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 445 {
 446   int i;
 447   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 448     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 449       return FALSE;
 450   return TRUE;
 451 }
 452
 453 /* This structure holds information for a particular opcode.  */
 454
 455 struct aarch64_opcode
 456 {
 457   /* The name of the mnemonic.  */
 458   const char *name;
 459
 460   /* The opcode itself.  Those bits which will be filled in with
 461      operands are zeroes.  */
 462   aarch64_insn opcode;
 463
 464   /* The opcode mask.  This is used by the disassembler.  This is a
 465      mask containing ones indicating those bits which must match the
 466      opcode field, and zeroes indicating those bits which need not
 467      match (and are presumably filled in by operands).  */
 468   aarch64_insn mask;
 469
 470   /* Instruction class.  */
 471   enum aarch64_insn_class iclass;
 472
 473   /* Enumerator identifier.  */
 474   enum aarch64_op op;
 475
 476   /* Which architecture variant provides this instruction.  */
 477   const aarch64_feature_set *avariant;
 478
 479   /* An array of operand codes.  Each code is an index into the
 480      operand table.  They appear in the order which the operands must
 481      appear in assembly code, and are terminated by a zero.  */
 482   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 483
 484   /* A list of operand qualifier code sequence.  Each operand qualifier
 485      code qualifies the corresponding operand code.  Each operand
 486      qualifier sequence specifies a valid opcode variant and related
 487      constraint on operands.  */
 488   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 489
 490   /* Flags providing information about this instruction */
 491   uint32_t flags;
 492 };
 493
 494 typedef struct aarch64_opcode aarch64_opcode;
 495
 496 /* Table describing all the AArch64 opcodes.  */
 497 extern aarch64_opcode aarch64_opcode_table[];
 498
 499 /* Opcode flags.  */
 500 #define F_ALIAS (1 << 0)
 501 #define F_HAS_ALIAS (1 << 1)
 502 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 503    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 504 #define F_P1 (1 << 2)
 505 #define F_P2 (2 << 2)
 506 #define F_P3 (3 << 2)
 507 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 508 #define F_COND (1 << 4)
 509 /* Instruction has the field of 'sf'.  */
 510 #define F_SF (1 << 5)
 511 /* Instruction has the field of 'size:Q'.  */
 512 #define F_SIZEQ (1 << 6)
 513 /* Floating-point instruction has the field of 'type'.  */
 514 #define F_FPTYPE (1 << 7)
 515 /* AdvSIMD scalar instruction has the field of 'size'.  */
 516 #define F_SSIZE (1 << 8)
 517 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 518 #define F_T (1 << 9)
 519 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 520 #define F_GPRSIZE_IN_Q (1 << 10)
 521 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 522 #define F_LDS_SIZE (1 << 11)
 523 /* Optional operand; assume maximum of 1 operand can be optional.  */
 524 #define F_OPD0_OPT (1 << 12)
 525 #define F_OPD1_OPT (2 << 12)
 526 #define F_OPD2_OPT (3 << 12)
 527 #define F_OPD3_OPT (4 << 12)
 528 #define F_OPD4_OPT (5 << 12)
 529 /* Default value for the optional operand when omitted from the assembly.  */
 530 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 531 /* Instruction that is an alias of another instruction needs to be
 532    encoded/decoded by converting it to/from the real form, followed by
 533    the encoding/decoding according to the rules of the real opcode.
 534    This compares to the direct coding using the alias's information.
 535    N.B. this flag requires F_ALIAS to be used together.  */
 536 #define F_CONV (1 << 20)
 537 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 538    friendly pseudo instruction available only in the assembly code (thus will
 539    not show up in the disassembly).  */
 540 #define F_PSEUDO (1 << 21)
 541 /* Instruction has miscellaneous encoding/decoding rules.  */
 542 #define F_MISC (1 << 22)
 543 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 544 #define F_N (1 << 23)
 545 /* Opcode dependent field.  */
 546 #define F_OD(X) (((X) & 0x7) << 24)
 547 /* Next bit is 27.  */
 548
 549 static inline bfd_boolean
 550 alias_opcode_p (const aarch64_opcode *opcode)
 551 {
 552   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 553 }
 554
 555 static inline bfd_boolean
 556 opcode_has_alias (const aarch64_opcode *opcode)
 557 {
 558   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 559 }
 560
 561 /* Priority for disassembling preference.  */
 562 static inline int
 563 opcode_priority (const aarch64_opcode *opcode)
 564 {
 565   return (opcode->flags >> 2) & 0x3;
 566 }
 567
 568 static inline bfd_boolean
 569 pseudo_opcode_p (const aarch64_opcode *opcode)
 570 {
 571   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 572 }
 573
 574 static inline bfd_boolean
 575 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 576 {
 577   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 578     ? TRUE : FALSE;
 579 }
 580
 581 static inline aarch64_insn
 582 get_optional_operand_default_value (const aarch64_opcode *opcode)
 583 {
 584   return (opcode->flags >> 15) & 0x1f;
 585 }
 586
 587 static inline unsigned int
 588 get_opcode_dependent_value (const aarch64_opcode *opcode)
 589 {
 590   return (opcode->flags >> 24) & 0x7;
 591 }
 592
 593 static inline bfd_boolean
 594 opcode_has_special_coder (const aarch64_opcode *opcode)
 595 {
 596   return (opcode->flags & (F_SF | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 597           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 598     : FALSE;
 599 }
 600 \f
 601 struct aarch64_name_value_pair
 602 {
 603   const char *  name;
 604   aarch64_insn  value;
 605 };
 606
 607 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 608 extern const struct aarch64_name_value_pair aarch64_sys_regs [];
 609 extern const struct aarch64_name_value_pair aarch64_pstatefields [];
 610 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 611 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 612
 613 typedef struct
 614 {
 615   const char *template;
 616   uint32_t value;
 617   int has_xt;
 618 } aarch64_sys_ins_reg;
 619
 620 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 621 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 622 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 623 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 624
 625 /* Shift/extending operator kinds.
 626    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 627 enum aarch64_modifier_kind
 628 {
 629   AARCH64_MOD_NONE,
 630   AARCH64_MOD_MSL,
 631   AARCH64_MOD_ROR,
 632   AARCH64_MOD_ASR,
 633   AARCH64_MOD_LSR,
 634   AARCH64_MOD_LSL,
 635   AARCH64_MOD_UXTB,
 636   AARCH64_MOD_UXTH,
 637   AARCH64_MOD_UXTW,
 638   AARCH64_MOD_UXTX,
 639   AARCH64_MOD_SXTB,
 640   AARCH64_MOD_SXTH,
 641   AARCH64_MOD_SXTW,
 642   AARCH64_MOD_SXTX,
 643 };
 644
 645 bfd_boolean
 646 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 647
 648 enum aarch64_modifier_kind
 649 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 650 /* Condition.  */
 651
 652 typedef struct
 653 {
 654   /* A list of names with the first one as the disassembly preference;
 655      terminated by NULL if fewer than 3.  */
 656   const char *names[3];
 657   aarch64_insn value;
 658 } aarch64_cond;
 659
 660 extern const aarch64_cond aarch64_conds[16];
 661
 662 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 663 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 664 \f
 665 /* Structure representing an operand.  */
 666
 667 struct aarch64_opnd_info
 668 {
 669   enum aarch64_opnd type;
 670   aarch64_opnd_qualifier_t qualifier;
 671   int idx;
 672
 673   union
 674     {
 675       struct
 676         {
 677           unsigned regno;
 678         } reg;
 679       struct
 680         {
 681           unsigned regno : 5;
 682           unsigned index : 4;
 683         } reglane;
 684       /* e.g. LVn.  */
 685       struct
 686         {
 687           unsigned first_regno : 5;
 688           unsigned num_regs : 3;
 689           /* 1 if it is a list of reg element.  */
 690           unsigned has_index : 1;
 691           /* Lane index; valid only when has_index is 1.  */
 692           unsigned index : 4;
 693         } reglist;
 694       /* e.g. immediate or pc relative address offset.  */
 695       struct
 696         {
 697           int64_t value;
 698           unsigned is_fp : 1;
 699         } imm;
 700       /* e.g. address in STR (register offset).  */
 701       struct
 702         {
 703           unsigned base_regno;
 704           struct
 705             {
 706               union
 707                 {
 708                   int imm;
 709                   unsigned regno;
 710                 };
 711               unsigned is_reg;
 712             } offset;
 713           unsigned pcrel : 1;           /* PC-relative.  */
 714           unsigned writeback : 1;
 715           unsigned preind : 1;          /* Pre-indexed.  */
 716           unsigned postind : 1;         /* Post-indexed.  */
 717         } addr;
 718       const aarch64_cond *cond;
 719       /* The encoding of the system register.  */
 720       aarch64_insn sysreg;
 721       /* The encoding of the PSTATE field.  */
 722       aarch64_insn pstatefield;
 723       const aarch64_sys_ins_reg *sysins_op;
 724       const struct aarch64_name_value_pair *barrier;
 725       const struct aarch64_name_value_pair *prfop;
 726     };
 727
 728   /* Operand shifter; in use when the operand is a register offset address,
 729      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
 730   struct
 731     {
 732       enum aarch64_modifier_kind kind;
 733       int amount;
 734       unsigned operator_present: 1;     /* Only valid during encoding.  */
 735       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
 736       unsigned amount_present: 1;
 737     } shifter;
 738
 739   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
 740                            to be done on it.  In some (but not all) of these
 741                            cases, we need to tell libopcodes to skip the
 742                            constraint checking and the encoding for this
 743                            operand, so that the libopcodes can pick up the
 744                            right opcode before the operand is fixed-up.  This
 745                            flag should only be used during the
 746                            assembling/encoding.  */
 747   unsigned present:1;   /* Whether this operand is present in the assembly
 748                            line; not used during the disassembly.  */
 749 };
 750
 751 typedef struct aarch64_opnd_info aarch64_opnd_info;
 752
 753 /* Structure representing an instruction.
 754
 755    It is used during both the assembling and disassembling.  The assembler
 756    fills an aarch64_inst after a successful parsing and then passes it to the
 757    encoding routine to do the encoding.  During the disassembling, the
 758    disassembler calls the decoding routine to decode a binary instruction; on a
 759    successful return, such a structure will be filled with information of the
 760    instruction; then the disassembler uses the information to print out the
 761    instruction.  */
 762
 763 struct aarch64_inst
 764 {
 765   /* The value of the binary instruction.  */
 766   aarch64_insn value;
 767
 768   /* Corresponding opcode entry.  */
 769   const aarch64_opcode *opcode;
 770
 771   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
 772   const aarch64_cond *cond;
 773
 774   /* Operands information.  */
 775   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
 776 };
 777
 778 typedef struct aarch64_inst aarch64_inst;
 779 \f
 780 /* Diagnosis related declaration and interface.  */
 781
 782 /* Operand error kind enumerators.
 783
 784    AARCH64_OPDE_RECOVERABLE
 785      Less severe error found during the parsing, very possibly because that
 786      GAS has picked up a wrong instruction template for the parsing.
 787
 788    AARCH64_OPDE_SYNTAX_ERROR
 789      General syntax error; it can be either a user error, or simply because
 790      that GAS is trying a wrong instruction template.
 791
 792    AARCH64_OPDE_FATAL_SYNTAX_ERROR
 793      Definitely a user syntax error.
 794
 795    AARCH64_OPDE_INVALID_VARIANT
 796      No syntax error, but the operands are not a valid combination, e.g.
 797      FMOV D0,S0
 798
 799    AARCH64_OPDE_OUT_OF_RANGE
 800      Error about some immediate value out of a valid range.
 801
 802    AARCH64_OPDE_UNALIGNED
 803      Error about some immediate value not properly aligned (i.e. not being a
 804      multiple times of a certain value).
 805
 806    AARCH64_OPDE_REG_LIST
 807      Error about the register list operand having unexpected number of
 808      registers.
 809
 810    AARCH64_OPDE_OTHER_ERROR
 811      Error of the highest severity and used for any severe issue that does not
 812      fall into any of the above categories.
 813
 814    The enumerators are only interesting to GAS.  They are declared here (in
 815    libopcodes) because that some errors are detected (and then notified to GAS)
 816    by libopcodes (rather than by GAS solely).
 817
 818    The first three errors are only deteced by GAS while the
 819    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
 820    only libopcodes has the information about the valid variants of each
 821    instruction.
 822
 823    The enumerators have an increasing severity.  This is helpful when there are
 824    multiple instruction templates available for a given mnemonic name (e.g.
 825    FMOV); this mechanism will help choose the most suitable template from which
 826    the generated diagnostics can most closely describe the issues, if any.  */
 827
 828 enum aarch64_operand_error_kind
 829 {
 830   AARCH64_OPDE_NIL,
 831   AARCH64_OPDE_RECOVERABLE,
 832   AARCH64_OPDE_SYNTAX_ERROR,
 833   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
 834   AARCH64_OPDE_INVALID_VARIANT,
 835   AARCH64_OPDE_OUT_OF_RANGE,
 836   AARCH64_OPDE_UNALIGNED,
 837   AARCH64_OPDE_REG_LIST,
 838   AARCH64_OPDE_OTHER_ERROR
 839 };
 840
 841 /* N.B. GAS assumes that this structure work well with shallow copy.  */
 842 struct aarch64_operand_error
 843 {
 844   enum aarch64_operand_error_kind kind;
 845   int index;
 846   const char *error;
 847   int data[3];  /* Some data for extra information.  */
 848 };
 849
 850 typedef struct aarch64_operand_error aarch64_operand_error;
 851
 852 /* Encoding entrypoint.  */
 853
 854 extern int
 855 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
 856                        aarch64_insn *, aarch64_opnd_qualifier_t *,
 857                        aarch64_operand_error *);
 858
 859 extern const aarch64_opcode *
 860 aarch64_replace_opcode (struct aarch64_inst *,
 861                         const aarch64_opcode *);
 862
 863 /* Given the opcode enumerator OP, return the pointer to the corresponding
 864    opcode entry.  */
 865
 866 extern const aarch64_opcode *
 867 aarch64_get_opcode (enum aarch64_op);
 868
 869 /* Generate the string representation of an operand.  */
 870 extern void
 871 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
 872                        const aarch64_opnd_info *, int, int *, bfd_vma *);
 873
 874 /* Miscellaneous interface.  */
 875
 876 extern int
 877 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
 878
 879 extern aarch64_opnd_qualifier_t
 880 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
 881                                 const aarch64_opnd_qualifier_t, int);
 882
 883 extern int
 884 aarch64_num_of_operands (const aarch64_opcode *);
 885
 886 extern int
 887 aarch64_stack_pointer_p (const aarch64_opnd_info *);
 888
 889 extern
 890 int aarch64_zero_register_p (const aarch64_opnd_info *);
 891
 892 /* Given an operand qualifier, return the expected data element size
 893    of a qualified operand.  */
 894 extern unsigned char
 895 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
 896
 897 extern enum aarch64_operand_class
 898 aarch64_get_operand_class (enum aarch64_opnd);
 899
 900 extern const char *
 901 aarch64_get_operand_name (enum aarch64_opnd);
 902
 903 extern const char *
 904 aarch64_get_operand_desc (enum aarch64_opnd);
 905
 906 #ifdef DEBUG_AARCH64
 907 extern int debug_dump;
 908
 909 extern void
 910 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
 911
 912 #define DEBUG_TRACE(M, ...)                                     \
 913   {                                                             \
 914     if (debug_dump)                                             \
 915       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
 916   }
 917
 918 #define DEBUG_TRACE_IF(C, M, ...)                               \
 919   {                                                             \
 920     if (debug_dump && (C))                                      \
 921       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
 922   }
 923 #else  /* !DEBUG_AARCH64 */
 924 #define DEBUG_TRACE(M, ...) ;
 925 #define DEBUG_TRACE_IF(C, M, ...) ;
 926 #endif /* DEBUG_AARCH64 */
 927
 928 #endif /* OPCODE_AARCH64_H */