include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2017 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_SHA2    0x200000000ULL  /* SHA2 instructions.  */
  41 #define AARCH64_FEATURE_AES     0x800000000ULL  /* AES instructions.  */
  42 #define AARCH64_FEATURE_V8_4    0x000000800ULL  /* ARMv8.4 processors.  */
  43 #define AARCH64_FEATURE_SM4     0x100000000ULL  /* SM3 & SM4 instructions.  */
  44 #define AARCH64_FEATURE_SHA3    0x400000000ULL  /* SHA3 instructions.  */
  45 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  46 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  47 #define AARCH64_FEATURE_V8_3    0x00000040      /* ARMv8.3 processors.  */
  48 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  49 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  50 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  51 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  52 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  53 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  54 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  55 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  56 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  57 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  58 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  59 #define AARCH64_FEATURE_PROFILE 0x08000000      /* Statistical Profiling.  */
  60 #define AARCH64_FEATURE_SVE     0x10000000      /* SVE instructions.  */
  61 #define AARCH64_FEATURE_RCPC    0x20000000      /* RCPC instructions.  */
  62 #define AARCH64_FEATURE_COMPNUM 0x40000000      /* Complex # instructions.  */
  63 #define AARCH64_FEATURE_DOTPROD 0x080000000     /* Dot Product instructions.  */
  64 #define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins.  */
  65
  66 /* Architectures are the sum of the base and extensions.  */
  67 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  68                                                  AARCH64_FEATURE_FP  \
  69                                                  | AARCH64_FEATURE_SIMD)
  70 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_ARCH_V8, \
  71                                                  AARCH64_FEATURE_CRC    \
  72                                                  | AARCH64_FEATURE_V8_1 \
  73                                                  | AARCH64_FEATURE_LSE  \
  74                                                  | AARCH64_FEATURE_PAN  \
  75                                                  | AARCH64_FEATURE_LOR  \
  76                                                  | AARCH64_FEATURE_RDMA)
  77 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_ARCH_V8_1,     \
  78                                                  AARCH64_FEATURE_V8_2   \
  79                                                  | AARCH64_FEATURE_RAS)
  80 #define AARCH64_ARCH_V8_3       AARCH64_FEATURE (AARCH64_ARCH_V8_2,     \
  81                                                  AARCH64_FEATURE_V8_3   \
  82                                                  | AARCH64_FEATURE_RCPC \
  83                                                  | AARCH64_FEATURE_COMPNUM)
  84 #define AARCH64_ARCH_V8_4       AARCH64_FEATURE (AARCH64_ARCH_V8_3,     \
  85                                                  AARCH64_FEATURE_V8_4   \
  86                                                  | AARCH64_FEATURE_DOTPROD \
  87                                                  | AARCH64_FEATURE_F16_FML)
  88
  89 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
  90 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
  91
  92 /* CPU-specific features.  */
  93 typedef unsigned long long aarch64_feature_set;
  94
  95 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
  96   ((~(CPU) & (FEAT)) == 0)
  97
  98 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
  99   (((CPU) & (FEAT)) != 0)
 100
 101 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
 102   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
 103
 104 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
 105   do                                            \
 106     {                                           \
 107       (TARG) = (F1) | (F2);                     \
 108     }                                           \
 109   while (0)
 110
 111 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 112   do                                            \
 113     {                                           \
 114       (TARG) = (F1) &~ (F2);                    \
 115     }                                           \
 116   while (0)
 117
 118 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 119
 120 enum aarch64_operand_class
 121 {
 122   AARCH64_OPND_CLASS_NIL,
 123   AARCH64_OPND_CLASS_INT_REG,
 124   AARCH64_OPND_CLASS_MODIFIED_REG,
 125   AARCH64_OPND_CLASS_FP_REG,
 126   AARCH64_OPND_CLASS_SIMD_REG,
 127   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 128   AARCH64_OPND_CLASS_SISD_REG,
 129   AARCH64_OPND_CLASS_SIMD_REGLIST,
 130   AARCH64_OPND_CLASS_SVE_REG,
 131   AARCH64_OPND_CLASS_PRED_REG,
 132   AARCH64_OPND_CLASS_ADDRESS,
 133   AARCH64_OPND_CLASS_IMMEDIATE,
 134   AARCH64_OPND_CLASS_SYSTEM,
 135   AARCH64_OPND_CLASS_COND,
 136 };
 137
 138 /* Operand code that helps both parsing and coding.
 139    Keep AARCH64_OPERANDS synced.  */
 140
 141 enum aarch64_opnd
 142 {
 143   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 144
 145   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 146   AARCH64_OPND_Rn,      /* Integer register as source.  */
 147   AARCH64_OPND_Rm,      /* Integer register as source.  */
 148   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 149   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 150   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 151   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 152   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 153
 154   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 155   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 156   AARCH64_OPND_Rm_SP,   /* Integer Rm or SP.  */
 157   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 158   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 159   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 160
 161   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 162   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 163   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 164   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 165   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 166   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 167
 168   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 169   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 170   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 171
 172   AARCH64_OPND_Va,      /* AdvSIMD Vector Va.  */
 173   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 174   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 175   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 176   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 177   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 178   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 179   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 180   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 181   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 182   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 183   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 184                            structure to all lanes.  */
 185   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 186
 187   AARCH64_OPND_CRn,     /* Co-processor register in CRn field.  */
 188   AARCH64_OPND_CRm,     /* Co-processor register in CRm field.  */
 189
 190   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 191   AARCH64_OPND_MASK,    /* AdvSIMD EXT index operand.  */
 192   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 193   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 194   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 195   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 196   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 197   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 198                            (no encoding).  */
 199   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 200   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 201   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 202   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 203   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 204   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 205   AARCH64_OPND_IMM,     /* Immediate.  */
 206   AARCH64_OPND_IMM_2,   /* Immediate.  */
 207   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 208   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 209   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 210   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 211   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 212   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 213   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 214   AARCH64_OPND_SIMM5,   /* 5-bit signed immediate in the imm5 field.  */
 215   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 216                            each condition flag.  */
 217
 218   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 219   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 220   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 221   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 222   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 223   AARCH64_OPND_IMM_ROT1,        /* Immediate rotate operand for FCMLA.  */
 224   AARCH64_OPND_IMM_ROT2,        /* Immediate rotate operand for indexed FCMLA.  */
 225   AARCH64_OPND_IMM_ROT3,        /* Immediate rotate operand for FCADD.  */
 226
 227   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 228   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 229
 230   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 231   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 232   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 233   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 234   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 235
 236   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 237   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 238   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 239   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 240   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 241                                    negative or unaligned and there is
 242                                    no writeback allowed.  This operand code
 243                                    is only used to support the programmer-
 244                                    friendly feature of using LDR/STR as the
 245                                    the mnemonic name for LDUR/STUR instructions
 246                                    wherever there is no ambiguity.  */
 247   AARCH64_OPND_ADDR_SIMM10,     /* Address of signed 10-bit immediate.  */
 248   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 249   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 250   AARCH64_OPND_ADDR_OFFSET,     /* Address with an optional 9-bit immediate.  */
 251   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 252
 253   AARCH64_OPND_SYSREG,          /* System register operand.  */
 254   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 255   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 256   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 257   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 258   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 259   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 260   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 261   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 262   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 263
 264   AARCH64_OPND_SVE_ADDR_RI_S4x16,   /* SVE [<Xn|SP>, #<simm4>*16].  */
 265   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
 266   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
 267   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
 268   AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL].  */
 269   AARCH64_OPND_SVE_ADDR_RI_S6xVL,   /* SVE [<Xn|SP>, #<simm6>, MUL VL].  */
 270   AARCH64_OPND_SVE_ADDR_RI_S9xVL,   /* SVE [<Xn|SP>, #<simm9>, MUL VL].  */
 271   AARCH64_OPND_SVE_ADDR_RI_U6,      /* SVE [<Xn|SP>, #<uimm6>].  */
 272   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
 273   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
 274   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
 275   AARCH64_OPND_SVE_ADDR_RR,         /* SVE [<Xn|SP>, <Xm|XZR>].  */
 276   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
 277   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
 278   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
 279   AARCH64_OPND_SVE_ADDR_RX,         /* SVE [<Xn|SP>, <Xm>].  */
 280   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
 281   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
 282   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
 283   AARCH64_OPND_SVE_ADDR_RZ,         /* SVE [<Xn|SP>, Zm.D].  */
 284   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
 285   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
 286   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
 287   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 288                                        Bit 14 controls S/U choice.  */
 289   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 290                                        Bit 22 controls S/U choice.  */
 291   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 292                                        Bit 14 controls S/U choice.  */
 293   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 294                                        Bit 22 controls S/U choice.  */
 295   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 296                                        Bit 14 controls S/U choice.  */
 297   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 298                                        Bit 22 controls S/U choice.  */
 299   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 300                                        Bit 14 controls S/U choice.  */
 301   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 302                                        Bit 22 controls S/U choice.  */
 303   AARCH64_OPND_SVE_ADDR_ZI_U5,      /* SVE [Zn.<T>, #<uimm5>].  */
 304   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
 305   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
 306   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
 307   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
 308   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
 309   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
 310   AARCH64_OPND_SVE_AIMM,        /* SVE unsigned arithmetic immediate.  */
 311   AARCH64_OPND_SVE_ASIMM,       /* SVE signed arithmetic immediate.  */
 312   AARCH64_OPND_SVE_FPIMM8,      /* SVE 8-bit floating-point immediate.  */
 313   AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0.  */
 314   AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0.  */
 315   AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0.  */
 316   AARCH64_OPND_SVE_IMM_ROT1,    /* SVE 1-bit rotate operand (90 or 270).  */
 317   AARCH64_OPND_SVE_IMM_ROT2,    /* SVE 2-bit rotate operand (N*90).  */
 318   AARCH64_OPND_SVE_INV_LIMM,    /* SVE inverted logical immediate.  */
 319   AARCH64_OPND_SVE_LIMM,        /* SVE logical immediate.  */
 320   AARCH64_OPND_SVE_LIMM_MOV,    /* SVE logical immediate for MOV.  */
 321   AARCH64_OPND_SVE_PATTERN,     /* SVE vector pattern enumeration.  */
 322   AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor.  */
 323   AARCH64_OPND_SVE_PRFOP,       /* SVE prefetch operation.  */
 324   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 325   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 326   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 327   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 328   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 329   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 330   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 331   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 332   AARCH64_OPND_SVE_Rm,          /* Integer Rm or ZR, alt. SVE position.  */
 333   AARCH64_OPND_SVE_Rn_SP,       /* Integer Rn or SP, alt. SVE position.  */
 334   AARCH64_OPND_SVE_SHLIMM_PRED,   /* SVE shift left amount (predicated).  */
 335   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
 336   AARCH64_OPND_SVE_SHRIMM_PRED,   /* SVE shift right amount (predicated).  */
 337   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
 338   AARCH64_OPND_SVE_SIMM5,       /* SVE signed 5-bit immediate.  */
 339   AARCH64_OPND_SVE_SIMM5B,      /* SVE secondary signed 5-bit immediate.  */
 340   AARCH64_OPND_SVE_SIMM6,       /* SVE signed 6-bit immediate.  */
 341   AARCH64_OPND_SVE_SIMM8,       /* SVE signed 8-bit immediate.  */
 342   AARCH64_OPND_SVE_UIMM3,       /* SVE unsigned 3-bit immediate.  */
 343   AARCH64_OPND_SVE_UIMM7,       /* SVE unsigned 7-bit immediate.  */
 344   AARCH64_OPND_SVE_UIMM8,       /* SVE unsigned 8-bit immediate.  */
 345   AARCH64_OPND_SVE_UIMM8_53,    /* SVE split unsigned 8-bit immediate.  */
 346   AARCH64_OPND_SVE_VZn,         /* Scalar SIMD&FP register in Zn field.  */
 347   AARCH64_OPND_SVE_Vd,          /* Scalar SIMD&FP register in Vd.  */
 348   AARCH64_OPND_SVE_Vm,          /* Scalar SIMD&FP register in Vm.  */
 349   AARCH64_OPND_SVE_Vn,          /* Scalar SIMD&FP register in Vn.  */
 350   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 351   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 352   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 353   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 354   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 355   AARCH64_OPND_SVE_Zm3_INDEX,   /* z0-z7[0-3] in Zm, bits [20,16].  */
 356   AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22.  */
 357   AARCH64_OPND_SVE_Zm4_INDEX,   /* z0-z15[0-1] in Zm, bits [20,16].  */
 358   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 359   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 360   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 361   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 362   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 363   AARCH64_OPND_SM3_IMM2,        /* SM3 encodes lane in bits [13, 14].  */
 364 };
 365
 366 /* Qualifier constrains an operand.  It either specifies a variant of an
 367    operand type or limits values available to an operand type.
 368
 369    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 370
 371 enum aarch64_opnd_qualifier
 372 {
 373   /* Indicating no further qualification on an operand.  */
 374   AARCH64_OPND_QLF_NIL,
 375
 376   /* Qualifying an operand which is a general purpose (integer) register;
 377      indicating the operand data size or a specific register.  */
 378   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 379   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 380   AARCH64_OPND_QLF_WSP, /* WSP.  */
 381   AARCH64_OPND_QLF_SP,  /* SP.  */
 382
 383   /* Qualifying an operand which is a floating-point register, a SIMD
 384      vector element or a SIMD vector element list; indicating operand data
 385      size or the size of each SIMD vector element in the case of a SIMD
 386      vector element list.
 387      These qualifiers are also used to qualify an address operand to
 388      indicate the size of data element a load/store instruction is
 389      accessing.
 390      They are also used for the immediate shift operand in e.g. SSHR.  Such
 391      a use is only for the ease of operand encoding/decoding and qualifier
 392      sequence matching; such a use should not be applied widely; use the value
 393      constraint qualifiers for immediate operands wherever possible.  */
 394   AARCH64_OPND_QLF_S_B,
 395   AARCH64_OPND_QLF_S_H,
 396   AARCH64_OPND_QLF_S_S,
 397   AARCH64_OPND_QLF_S_D,
 398   AARCH64_OPND_QLF_S_Q,
 399
 400   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 401      register list; indicating register shape.
 402      They are also used for the immediate shift operand in e.g. SSHR.  Such
 403      a use is only for the ease of operand encoding/decoding and qualifier
 404      sequence matching; such a use should not be applied widely; use the value
 405      constraint qualifiers for immediate operands wherever possible.  */
 406   AARCH64_OPND_QLF_V_8B,
 407   AARCH64_OPND_QLF_V_16B,
 408   AARCH64_OPND_QLF_V_2H,
 409   AARCH64_OPND_QLF_V_4H,
 410   AARCH64_OPND_QLF_V_8H,
 411   AARCH64_OPND_QLF_V_2S,
 412   AARCH64_OPND_QLF_V_4S,
 413   AARCH64_OPND_QLF_V_1D,
 414   AARCH64_OPND_QLF_V_2D,
 415   AARCH64_OPND_QLF_V_1Q,
 416
 417   AARCH64_OPND_QLF_P_Z,
 418   AARCH64_OPND_QLF_P_M,
 419
 420   /* Constraint on value.  */
 421   AARCH64_OPND_QLF_CR,          /* CRn, CRm. */
 422   AARCH64_OPND_QLF_imm_0_7,
 423   AARCH64_OPND_QLF_imm_0_15,
 424   AARCH64_OPND_QLF_imm_0_31,
 425   AARCH64_OPND_QLF_imm_0_63,
 426   AARCH64_OPND_QLF_imm_1_32,
 427   AARCH64_OPND_QLF_imm_1_64,
 428
 429   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 430      or shift-ones.  */
 431   AARCH64_OPND_QLF_LSL,
 432   AARCH64_OPND_QLF_MSL,
 433
 434   /* Special qualifier helping retrieve qualifier information during the
 435      decoding time (currently not in use).  */
 436   AARCH64_OPND_QLF_RETRIEVE,
 437 };
 438 \f
 439 /* Instruction class.  */
 440
 441 enum aarch64_insn_class
 442 {
 443   addsub_carry,
 444   addsub_ext,
 445   addsub_imm,
 446   addsub_shift,
 447   asimdall,
 448   asimddiff,
 449   asimdelem,
 450   asimdext,
 451   asimdimm,
 452   asimdins,
 453   asimdmisc,
 454   asimdperm,
 455   asimdsame,
 456   asimdshf,
 457   asimdtbl,
 458   asisddiff,
 459   asisdelem,
 460   asisdlse,
 461   asisdlsep,
 462   asisdlso,
 463   asisdlsop,
 464   asisdmisc,
 465   asisdone,
 466   asisdpair,
 467   asisdsame,
 468   asisdshf,
 469   bitfield,
 470   branch_imm,
 471   branch_reg,
 472   compbranch,
 473   condbranch,
 474   condcmp_imm,
 475   condcmp_reg,
 476   condsel,
 477   cryptoaes,
 478   cryptosha2,
 479   cryptosha3,
 480   dp_1src,
 481   dp_2src,
 482   dp_3src,
 483   exception,
 484   extract,
 485   float2fix,
 486   float2int,
 487   floatccmp,
 488   floatcmp,
 489   floatdp1,
 490   floatdp2,
 491   floatdp3,
 492   floatimm,
 493   floatsel,
 494   ldst_immpost,
 495   ldst_immpre,
 496   ldst_imm9,    /* immpost or immpre */
 497   ldst_imm10,   /* LDRAA/LDRAB */
 498   ldst_pos,
 499   ldst_regoff,
 500   ldst_unpriv,
 501   ldst_unscaled,
 502   ldstexcl,
 503   ldstnapair_offs,
 504   ldstpair_off,
 505   ldstpair_indexed,
 506   loadlit,
 507   log_imm,
 508   log_shift,
 509   lse_atomic,
 510   movewide,
 511   pcreladdr,
 512   ic_system,
 513   sve_cpy,
 514   sve_index,
 515   sve_limm,
 516   sve_misc,
 517   sve_movprfx,
 518   sve_pred_zm,
 519   sve_shift_pred,
 520   sve_shift_unpred,
 521   sve_size_bhs,
 522   sve_size_bhsd,
 523   sve_size_hsd,
 524   sve_size_sd,
 525   testbranch,
 526   cryptosm3,
 527   cryptosm4,
 528   dotproduct,
 529 };
 530
 531 /* Opcode enumerators.  */
 532
 533 enum aarch64_op
 534 {
 535   OP_NIL,
 536   OP_STRB_POS,
 537   OP_LDRB_POS,
 538   OP_LDRSB_POS,
 539   OP_STRH_POS,
 540   OP_LDRH_POS,
 541   OP_LDRSH_POS,
 542   OP_STR_POS,
 543   OP_LDR_POS,
 544   OP_STRF_POS,
 545   OP_LDRF_POS,
 546   OP_LDRSW_POS,
 547   OP_PRFM_POS,
 548
 549   OP_STURB,
 550   OP_LDURB,
 551   OP_LDURSB,
 552   OP_STURH,
 553   OP_LDURH,
 554   OP_LDURSH,
 555   OP_STUR,
 556   OP_LDUR,
 557   OP_STURV,
 558   OP_LDURV,
 559   OP_LDURSW,
 560   OP_PRFUM,
 561
 562   OP_LDR_LIT,
 563   OP_LDRV_LIT,
 564   OP_LDRSW_LIT,
 565   OP_PRFM_LIT,
 566
 567   OP_ADD,
 568   OP_B,
 569   OP_BL,
 570
 571   OP_MOVN,
 572   OP_MOVZ,
 573   OP_MOVK,
 574
 575   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 576   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 577   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 578
 579   OP_MOV_V,             /* MOV alias for moving vector register.  */
 580
 581   OP_ASR_IMM,
 582   OP_LSR_IMM,
 583   OP_LSL_IMM,
 584
 585   OP_BIC,
 586
 587   OP_UBFX,
 588   OP_BFXIL,
 589   OP_SBFX,
 590   OP_SBFIZ,
 591   OP_BFI,
 592   OP_BFC,               /* ARMv8.2.  */
 593   OP_UBFIZ,
 594   OP_UXTB,
 595   OP_UXTH,
 596   OP_UXTW,
 597
 598   OP_CINC,
 599   OP_CINV,
 600   OP_CNEG,
 601   OP_CSET,
 602   OP_CSETM,
 603
 604   OP_FCVT,
 605   OP_FCVTN,
 606   OP_FCVTN2,
 607   OP_FCVTL,
 608   OP_FCVTL2,
 609   OP_FCVTXN_S,          /* Scalar version.  */
 610
 611   OP_ROR_IMM,
 612
 613   OP_SXTL,
 614   OP_SXTL2,
 615   OP_UXTL,
 616   OP_UXTL2,
 617
 618   OP_MOV_P_P,
 619   OP_MOV_Z_P_Z,
 620   OP_MOV_Z_V,
 621   OP_MOV_Z_Z,
 622   OP_MOV_Z_Zi,
 623   OP_MOVM_P_P_P,
 624   OP_MOVS_P_P,
 625   OP_MOVZS_P_P_P,
 626   OP_MOVZ_P_P_P,
 627   OP_NOTS_P_P_P_Z,
 628   OP_NOT_P_P_P_Z,
 629
 630   OP_FCMLA_ELEM,        /* ARMv8.3, indexed element version.  */
 631
 632   OP_TOTAL_NUM,         /* Pseudo.  */
 633 };
 634
 635 /* Maximum number of operands an instruction can have.  */
 636 #define AARCH64_MAX_OPND_NUM 6
 637 /* Maximum number of qualifier sequences an instruction can have.  */
 638 #define AARCH64_MAX_QLF_SEQ_NUM 10
 639 /* Operand qualifier typedef; optimized for the size.  */
 640 typedef unsigned char aarch64_opnd_qualifier_t;
 641 /* Operand qualifier sequence typedef.  */
 642 typedef aarch64_opnd_qualifier_t        \
 643           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 644
 645 /* FIXME: improve the efficiency.  */
 646 static inline bfd_boolean
 647 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 648 {
 649   int i;
 650   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 651     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 652       return FALSE;
 653   return TRUE;
 654 }
 655
 656 /* This structure holds information for a particular opcode.  */
 657
 658 struct aarch64_opcode
 659 {
 660   /* The name of the mnemonic.  */
 661   const char *name;
 662
 663   /* The opcode itself.  Those bits which will be filled in with
 664      operands are zeroes.  */
 665   aarch64_insn opcode;
 666
 667   /* The opcode mask.  This is used by the disassembler.  This is a
 668      mask containing ones indicating those bits which must match the
 669      opcode field, and zeroes indicating those bits which need not
 670      match (and are presumably filled in by operands).  */
 671   aarch64_insn mask;
 672
 673   /* Instruction class.  */
 674   enum aarch64_insn_class iclass;
 675
 676   /* Enumerator identifier.  */
 677   enum aarch64_op op;
 678
 679   /* Which architecture variant provides this instruction.  */
 680   const aarch64_feature_set *avariant;
 681
 682   /* An array of operand codes.  Each code is an index into the
 683      operand table.  They appear in the order which the operands must
 684      appear in assembly code, and are terminated by a zero.  */
 685   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 686
 687   /* A list of operand qualifier code sequence.  Each operand qualifier
 688      code qualifies the corresponding operand code.  Each operand
 689      qualifier sequence specifies a valid opcode variant and related
 690      constraint on operands.  */
 691   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 692
 693   /* Flags providing information about this instruction */
 694   uint32_t flags;
 695
 696   /* If nonzero, this operand and operand 0 are both registers and
 697      are required to have the same register number.  */
 698   unsigned char tied_operand;
 699
 700   /* If non-NULL, a function to verify that a given instruction is valid.  */
 701   bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
 702 };
 703
 704 typedef struct aarch64_opcode aarch64_opcode;
 705
 706 /* Table describing all the AArch64 opcodes.  */
 707 extern aarch64_opcode aarch64_opcode_table[];
 708
 709 /* Opcode flags.  */
 710 #define F_ALIAS (1 << 0)
 711 #define F_HAS_ALIAS (1 << 1)
 712 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 713    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 714 #define F_P1 (1 << 2)
 715 #define F_P2 (2 << 2)
 716 #define F_P3 (3 << 2)
 717 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 718 #define F_COND (1 << 4)
 719 /* Instruction has the field of 'sf'.  */
 720 #define F_SF (1 << 5)
 721 /* Instruction has the field of 'size:Q'.  */
 722 #define F_SIZEQ (1 << 6)
 723 /* Floating-point instruction has the field of 'type'.  */
 724 #define F_FPTYPE (1 << 7)
 725 /* AdvSIMD scalar instruction has the field of 'size'.  */
 726 #define F_SSIZE (1 << 8)
 727 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 728 #define F_T (1 << 9)
 729 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 730 #define F_GPRSIZE_IN_Q (1 << 10)
 731 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 732 #define F_LDS_SIZE (1 << 11)
 733 /* Optional operand; assume maximum of 1 operand can be optional.  */
 734 #define F_OPD0_OPT (1 << 12)
 735 #define F_OPD1_OPT (2 << 12)
 736 #define F_OPD2_OPT (3 << 12)
 737 #define F_OPD3_OPT (4 << 12)
 738 #define F_OPD4_OPT (5 << 12)
 739 /* Default value for the optional operand when omitted from the assembly.  */
 740 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 741 /* Instruction that is an alias of another instruction needs to be
 742    encoded/decoded by converting it to/from the real form, followed by
 743    the encoding/decoding according to the rules of the real opcode.
 744    This compares to the direct coding using the alias's information.
 745    N.B. this flag requires F_ALIAS to be used together.  */
 746 #define F_CONV (1 << 20)
 747 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 748    friendly pseudo instruction available only in the assembly code (thus will
 749    not show up in the disassembly).  */
 750 #define F_PSEUDO (1 << 21)
 751 /* Instruction has miscellaneous encoding/decoding rules.  */
 752 #define F_MISC (1 << 22)
 753 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 754 #define F_N (1 << 23)
 755 /* Opcode dependent field.  */
 756 #define F_OD(X) (((X) & 0x7) << 24)
 757 /* Instruction has the field of 'sz'.  */
 758 #define F_LSE_SZ (1 << 27)
 759 /* Require an exact qualifier match, even for NIL qualifiers.  */
 760 #define F_STRICT (1ULL << 28)
 761 /* Next bit is 29.  */
 762
 763 static inline bfd_boolean
 764 alias_opcode_p (const aarch64_opcode *opcode)
 765 {
 766   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 767 }
 768
 769 static inline bfd_boolean
 770 opcode_has_alias (const aarch64_opcode *opcode)
 771 {
 772   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 773 }
 774
 775 /* Priority for disassembling preference.  */
 776 static inline int
 777 opcode_priority (const aarch64_opcode *opcode)
 778 {
 779   return (opcode->flags >> 2) & 0x3;
 780 }
 781
 782 static inline bfd_boolean
 783 pseudo_opcode_p (const aarch64_opcode *opcode)
 784 {
 785   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 786 }
 787
 788 static inline bfd_boolean
 789 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 790 {
 791   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 792     ? TRUE : FALSE;
 793 }
 794
 795 static inline aarch64_insn
 796 get_optional_operand_default_value (const aarch64_opcode *opcode)
 797 {
 798   return (opcode->flags >> 15) & 0x1f;
 799 }
 800
 801 static inline unsigned int
 802 get_opcode_dependent_value (const aarch64_opcode *opcode)
 803 {
 804   return (opcode->flags >> 24) & 0x7;
 805 }
 806
 807 static inline bfd_boolean
 808 opcode_has_special_coder (const aarch64_opcode *opcode)
 809 {
 810   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 811           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 812     : FALSE;
 813 }
 814 \f
 815 struct aarch64_name_value_pair
 816 {
 817   const char *  name;
 818   aarch64_insn  value;
 819 };
 820
 821 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 822 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 823 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 824 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 825
 826 typedef struct
 827 {
 828   const char *  name;
 829   aarch64_insn  value;
 830   uint32_t      flags;
 831 } aarch64_sys_reg;
 832
 833 extern const aarch64_sys_reg aarch64_sys_regs [];
 834 extern const aarch64_sys_reg aarch64_pstatefields [];
 835 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 836 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 837                                                 const aarch64_sys_reg *);
 838 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 839                                                     const aarch64_sys_reg *);
 840
 841 typedef struct
 842 {
 843   const char *name;
 844   uint32_t value;
 845   uint32_t flags ;
 846 } aarch64_sys_ins_reg;
 847
 848 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 849 extern bfd_boolean
 850 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 851                                  const aarch64_sys_ins_reg *);
 852
 853 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 854 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 855 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 856 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 857
 858 /* Shift/extending operator kinds.
 859    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 860 enum aarch64_modifier_kind
 861 {
 862   AARCH64_MOD_NONE,
 863   AARCH64_MOD_MSL,
 864   AARCH64_MOD_ROR,
 865   AARCH64_MOD_ASR,
 866   AARCH64_MOD_LSR,
 867   AARCH64_MOD_LSL,
 868   AARCH64_MOD_UXTB,
 869   AARCH64_MOD_UXTH,
 870   AARCH64_MOD_UXTW,
 871   AARCH64_MOD_UXTX,
 872   AARCH64_MOD_SXTB,
 873   AARCH64_MOD_SXTH,
 874   AARCH64_MOD_SXTW,
 875   AARCH64_MOD_SXTX,
 876   AARCH64_MOD_MUL,
 877   AARCH64_MOD_MUL_VL,
 878 };
 879
 880 bfd_boolean
 881 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 882
 883 enum aarch64_modifier_kind
 884 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 885 /* Condition.  */
 886
 887 typedef struct
 888 {
 889   /* A list of names with the first one as the disassembly preference;
 890      terminated by NULL if fewer than 3.  */
 891   const char *names[4];
 892   aarch64_insn value;
 893 } aarch64_cond;
 894
 895 extern const aarch64_cond aarch64_conds[16];
 896
 897 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 898 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 899 \f
 900 /* Structure representing an operand.  */
 901
 902 struct aarch64_opnd_info
 903 {
 904   enum aarch64_opnd type;
 905   aarch64_opnd_qualifier_t qualifier;
 906   int idx;
 907
 908   union
 909     {
 910       struct
 911         {
 912           unsigned regno;
 913         } reg;
 914       struct
 915         {
 916           unsigned int regno;
 917           int64_t index;
 918         } reglane;
 919       /* e.g. LVn.  */
 920       struct
 921         {
 922           unsigned first_regno : 5;
 923           unsigned num_regs : 3;
 924           /* 1 if it is a list of reg element.  */
 925           unsigned has_index : 1;
 926           /* Lane index; valid only when has_index is 1.  */
 927           int64_t index;
 928         } reglist;
 929       /* e.g. immediate or pc relative address offset.  */
 930       struct
 931         {
 932           int64_t value;
 933           unsigned is_fp : 1;
 934         } imm;
 935       /* e.g. address in STR (register offset).  */
 936       struct
 937         {
 938           unsigned base_regno;
 939           struct
 940             {
 941               union
 942                 {
 943                   int imm;
 944                   unsigned regno;
 945                 };
 946               unsigned is_reg;
 947             } offset;
 948           unsigned pcrel : 1;           /* PC-relative.  */
 949           unsigned writeback : 1;
 950           unsigned preind : 1;          /* Pre-indexed.  */
 951           unsigned postind : 1;         /* Post-indexed.  */
 952         } addr;
 953       const aarch64_cond *cond;
 954       /* The encoding of the system register.  */
 955       aarch64_insn sysreg;
 956       /* The encoding of the PSTATE field.  */
 957       aarch64_insn pstatefield;
 958       const aarch64_sys_ins_reg *sysins_op;
 959       const struct aarch64_name_value_pair *barrier;
 960       const struct aarch64_name_value_pair *hint_option;
 961       const struct aarch64_name_value_pair *prfop;
 962     };
 963
 964   /* Operand shifter; in use when the operand is a register offset address,
 965      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
 966   struct
 967     {
 968       enum aarch64_modifier_kind kind;
 969       unsigned operator_present: 1;     /* Only valid during encoding.  */
 970       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
 971       unsigned amount_present: 1;
 972       int64_t amount;
 973     } shifter;
 974
 975   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
 976                            to be done on it.  In some (but not all) of these
 977                            cases, we need to tell libopcodes to skip the
 978                            constraint checking and the encoding for this
 979                            operand, so that the libopcodes can pick up the
 980                            right opcode before the operand is fixed-up.  This
 981                            flag should only be used during the
 982                            assembling/encoding.  */
 983   unsigned present:1;   /* Whether this operand is present in the assembly
 984                            line; not used during the disassembly.  */
 985 };
 986
 987 typedef struct aarch64_opnd_info aarch64_opnd_info;
 988
 989 /* Structure representing an instruction.
 990
 991    It is used during both the assembling and disassembling.  The assembler
 992    fills an aarch64_inst after a successful parsing and then passes it to the
 993    encoding routine to do the encoding.  During the disassembling, the
 994    disassembler calls the decoding routine to decode a binary instruction; on a
 995    successful return, such a structure will be filled with information of the
 996    instruction; then the disassembler uses the information to print out the
 997    instruction.  */
 998
 999 struct aarch64_inst
1000 {
1001   /* The value of the binary instruction.  */
1002   aarch64_insn value;
1003
1004   /* Corresponding opcode entry.  */
1005   const aarch64_opcode *opcode;
1006
1007   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
1008   const aarch64_cond *cond;
1009
1010   /* Operands information.  */
1011   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1012 };
1013
1014 typedef struct aarch64_inst aarch64_inst;
1015 \f
1016 /* Diagnosis related declaration and interface.  */
1017
1018 /* Operand error kind enumerators.
1019
1020    AARCH64_OPDE_RECOVERABLE
1021      Less severe error found during the parsing, very possibly because that
1022      GAS has picked up a wrong instruction template for the parsing.
1023
1024    AARCH64_OPDE_SYNTAX_ERROR
1025      General syntax error; it can be either a user error, or simply because
1026      that GAS is trying a wrong instruction template.
1027
1028    AARCH64_OPDE_FATAL_SYNTAX_ERROR
1029      Definitely a user syntax error.
1030
1031    AARCH64_OPDE_INVALID_VARIANT
1032      No syntax error, but the operands are not a valid combination, e.g.
1033      FMOV D0,S0
1034
1035    AARCH64_OPDE_UNTIED_OPERAND
1036      The asm failed to use the same register for a destination operand
1037      and a tied source operand.
1038
1039    AARCH64_OPDE_OUT_OF_RANGE
1040      Error about some immediate value out of a valid range.
1041
1042    AARCH64_OPDE_UNALIGNED
1043      Error about some immediate value not properly aligned (i.e. not being a
1044      multiple times of a certain value).
1045
1046    AARCH64_OPDE_REG_LIST
1047      Error about the register list operand having unexpected number of
1048      registers.
1049
1050    AARCH64_OPDE_OTHER_ERROR
1051      Error of the highest severity and used for any severe issue that does not
1052      fall into any of the above categories.
1053
1054    The enumerators are only interesting to GAS.  They are declared here (in
1055    libopcodes) because that some errors are detected (and then notified to GAS)
1056    by libopcodes (rather than by GAS solely).
1057
1058    The first three errors are only deteced by GAS while the
1059    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1060    only libopcodes has the information about the valid variants of each
1061    instruction.
1062
1063    The enumerators have an increasing severity.  This is helpful when there are
1064    multiple instruction templates available for a given mnemonic name (e.g.
1065    FMOV); this mechanism will help choose the most suitable template from which
1066    the generated diagnostics can most closely describe the issues, if any.  */
1067
1068 enum aarch64_operand_error_kind
1069 {
1070   AARCH64_OPDE_NIL,
1071   AARCH64_OPDE_RECOVERABLE,
1072   AARCH64_OPDE_SYNTAX_ERROR,
1073   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1074   AARCH64_OPDE_INVALID_VARIANT,
1075   AARCH64_OPDE_UNTIED_OPERAND,
1076   AARCH64_OPDE_OUT_OF_RANGE,
1077   AARCH64_OPDE_UNALIGNED,
1078   AARCH64_OPDE_REG_LIST,
1079   AARCH64_OPDE_OTHER_ERROR
1080 };
1081
1082 /* N.B. GAS assumes that this structure work well with shallow copy.  */
1083 struct aarch64_operand_error
1084 {
1085   enum aarch64_operand_error_kind kind;
1086   int index;
1087   const char *error;
1088   int data[3];  /* Some data for extra information.  */
1089 };
1090
1091 typedef struct aarch64_operand_error aarch64_operand_error;
1092
1093 /* Encoding entrypoint.  */
1094
1095 extern int
1096 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1097                        aarch64_insn *, aarch64_opnd_qualifier_t *,
1098                        aarch64_operand_error *);
1099
1100 extern const aarch64_opcode *
1101 aarch64_replace_opcode (struct aarch64_inst *,
1102                         const aarch64_opcode *);
1103
1104 /* Given the opcode enumerator OP, return the pointer to the corresponding
1105    opcode entry.  */
1106
1107 extern const aarch64_opcode *
1108 aarch64_get_opcode (enum aarch64_op);
1109
1110 /* Generate the string representation of an operand.  */
1111 extern void
1112 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1113                        const aarch64_opnd_info *, int, int *, bfd_vma *);
1114
1115 /* Miscellaneous interface.  */
1116
1117 extern int
1118 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1119
1120 extern aarch64_opnd_qualifier_t
1121 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1122                                 const aarch64_opnd_qualifier_t, int);
1123
1124 extern int
1125 aarch64_num_of_operands (const aarch64_opcode *);
1126
1127 extern int
1128 aarch64_stack_pointer_p (const aarch64_opnd_info *);
1129
1130 extern int
1131 aarch64_zero_register_p (const aarch64_opnd_info *);
1132
1133 extern int
1134 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
1135
1136 /* Given an operand qualifier, return the expected data element size
1137    of a qualified operand.  */
1138 extern unsigned char
1139 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1140
1141 extern enum aarch64_operand_class
1142 aarch64_get_operand_class (enum aarch64_opnd);
1143
1144 extern const char *
1145 aarch64_get_operand_name (enum aarch64_opnd);
1146
1147 extern const char *
1148 aarch64_get_operand_desc (enum aarch64_opnd);
1149
1150 extern bfd_boolean
1151 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1152
1153 #ifdef DEBUG_AARCH64
1154 extern int debug_dump;
1155
1156 extern void
1157 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1158
1159 #define DEBUG_TRACE(M, ...)                                     \
1160   {                                                             \
1161     if (debug_dump)                                             \
1162       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1163   }
1164
1165 #define DEBUG_TRACE_IF(C, M, ...)                               \
1166   {                                                             \
1167     if (debug_dump && (C))                                      \
1168       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1169   }
1170 #else  /* !DEBUG_AARCH64 */
1171 #define DEBUG_TRACE(M, ...) ;
1172 #define DEBUG_TRACE_IF(C, M, ...) ;
1173 #endif /* DEBUG_AARCH64 */
1174
1175 extern const char *const aarch64_sve_pattern_array[32];
1176 extern const char *const aarch64_sve_prfop_array[16];
1177
1178 #ifdef __cplusplus
1179 }
1180 #endif
1181
1182 #endif /* OPCODE_AARCH64_H */