include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2016 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  41 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  42 #define AARCH64_FEATURE_V8_3    0x00000040      /* ARMv8.3 processors.  */
  43 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  44 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  45 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  46 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  47 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  48 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  49 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  50 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  51 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  52 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  53 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  54 #define AARCH64_FEATURE_PROFILE 0x08000000      /* Statistical Profiling.  */
  55 #define AARCH64_FEATURE_SVE     0x10000000      /* SVE instructions.  */
  56
  57 /* Architectures are the sum of the base and extensions.  */
  58 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  59                                                  AARCH64_FEATURE_FP  \
  60                                                  | AARCH64_FEATURE_SIMD)
  61 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_ARCH_V8, \
  62                                                  AARCH64_FEATURE_CRC    \
  63                                                  | AARCH64_FEATURE_V8_1 \
  64                                                  | AARCH64_FEATURE_LSE  \
  65                                                  | AARCH64_FEATURE_PAN  \
  66                                                  | AARCH64_FEATURE_LOR  \
  67                                                  | AARCH64_FEATURE_RDMA)
  68 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_ARCH_V8_1,     \
  69                                                  AARCH64_FEATURE_V8_2   \
  70                                                  | AARCH64_FEATURE_F16  \
  71                                                  | AARCH64_FEATURE_RAS)
  72 #define AARCH64_ARCH_V8_3       AARCH64_FEATURE (AARCH64_ARCH_V8_2,     \
  73                                                  AARCH64_FEATURE_V8_3)
  74
  75 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
  76 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
  77
  78 /* CPU-specific features.  */
  79 typedef unsigned long aarch64_feature_set;
  80
  81 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
  82   ((~(CPU) & (FEAT)) == 0)
  83
  84 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
  85   (((CPU) & (FEAT)) != 0)
  86
  87 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
  88   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
  89
  90 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
  91   do                                            \
  92     {                                           \
  93       (TARG) = (F1) | (F2);                     \
  94     }                                           \
  95   while (0)
  96
  97 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
  98   do                                            \
  99     {                                           \
 100       (TARG) = (F1) &~ (F2);                    \
 101     }                                           \
 102   while (0)
 103
 104 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 105
 106 enum aarch64_operand_class
 107 {
 108   AARCH64_OPND_CLASS_NIL,
 109   AARCH64_OPND_CLASS_INT_REG,
 110   AARCH64_OPND_CLASS_MODIFIED_REG,
 111   AARCH64_OPND_CLASS_FP_REG,
 112   AARCH64_OPND_CLASS_SIMD_REG,
 113   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 114   AARCH64_OPND_CLASS_SISD_REG,
 115   AARCH64_OPND_CLASS_SIMD_REGLIST,
 116   AARCH64_OPND_CLASS_CP_REG,
 117   AARCH64_OPND_CLASS_SVE_REG,
 118   AARCH64_OPND_CLASS_PRED_REG,
 119   AARCH64_OPND_CLASS_ADDRESS,
 120   AARCH64_OPND_CLASS_IMMEDIATE,
 121   AARCH64_OPND_CLASS_SYSTEM,
 122   AARCH64_OPND_CLASS_COND,
 123 };
 124
 125 /* Operand code that helps both parsing and coding.
 126    Keep AARCH64_OPERANDS synced.  */
 127
 128 enum aarch64_opnd
 129 {
 130   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 131
 132   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 133   AARCH64_OPND_Rn,      /* Integer register as source.  */
 134   AARCH64_OPND_Rm,      /* Integer register as source.  */
 135   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 136   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 137   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 138   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 139   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 140
 141   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 142   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 143   AARCH64_OPND_Rm_SP,   /* Integer Rm or SP.  */
 144   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 145   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 146   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 147
 148   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 149   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 150   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 151   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 152   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 153   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 154
 155   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 156   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 157   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 158
 159   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 160   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 161   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 162   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 163   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 164   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 165   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 166   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 167   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 168   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 169   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 170                            structure to all lanes.  */
 171   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 172
 173   AARCH64_OPND_Cn,      /* Co-processor register in CRn field.  */
 174   AARCH64_OPND_Cm,      /* Co-processor register in CRm field.  */
 175
 176   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 177   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 178   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 179   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 180   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 181   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 182   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 183                            (no encoding).  */
 184   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 185   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 186   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 187   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 188   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 189   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 190   AARCH64_OPND_IMM,     /* Immediate.  */
 191   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 192   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 193   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 194   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 195   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 196   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 197   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 198   AARCH64_OPND_SIMM5,   /* 5-bit signed immediate in the imm5 field.  */
 199   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 200                            each condition flag.  */
 201
 202   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 203   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 204   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 205   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 206   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 207
 208   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 209   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 210
 211   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 212   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 213   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 214   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 215   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 216
 217   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 218   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 219   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 220   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 221   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 222                                    negative or unaligned and there is
 223                                    no writeback allowed.  This operand code
 224                                    is only used to support the programmer-
 225                                    friendly feature of using LDR/STR as the
 226                                    the mnemonic name for LDUR/STUR instructions
 227                                    wherever there is no ambiguity.  */
 228   AARCH64_OPND_ADDR_SIMM10,     /* Address of signed 10-bit immediate.  */
 229   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 230   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 231   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 232
 233   AARCH64_OPND_SYSREG,          /* System register operand.  */
 234   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 235   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 236   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 237   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 238   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 239   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 240   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 241   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 242   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 243
 244   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
 245   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
 246   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
 247   AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL].  */
 248   AARCH64_OPND_SVE_ADDR_RI_S6xVL,   /* SVE [<Xn|SP>, #<simm6>, MUL VL].  */
 249   AARCH64_OPND_SVE_ADDR_RI_S9xVL,   /* SVE [<Xn|SP>, #<simm9>, MUL VL].  */
 250   AARCH64_OPND_SVE_ADDR_RI_U6,      /* SVE [<Xn|SP>, #<uimm6>].  */
 251   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
 252   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
 253   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
 254   AARCH64_OPND_SVE_ADDR_RR,         /* SVE [<Xn|SP>, <Xm|XZR>].  */
 255   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
 256   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
 257   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
 258   AARCH64_OPND_SVE_ADDR_RX,         /* SVE [<Xn|SP>, <Xm>].  */
 259   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
 260   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
 261   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
 262   AARCH64_OPND_SVE_ADDR_RZ,         /* SVE [<Xn|SP>, Zm.D].  */
 263   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
 264   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
 265   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
 266   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 267                                        Bit 14 controls S/U choice.  */
 268   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 269                                        Bit 22 controls S/U choice.  */
 270   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 271                                        Bit 14 controls S/U choice.  */
 272   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 273                                        Bit 22 controls S/U choice.  */
 274   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 275                                        Bit 14 controls S/U choice.  */
 276   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 277                                        Bit 22 controls S/U choice.  */
 278   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 279                                        Bit 14 controls S/U choice.  */
 280   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 281                                        Bit 22 controls S/U choice.  */
 282   AARCH64_OPND_SVE_ADDR_ZI_U5,      /* SVE [Zn.<T>, #<uimm5>].  */
 283   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
 284   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
 285   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
 286   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
 287   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
 288   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
 289   AARCH64_OPND_SVE_AIMM,        /* SVE unsigned arithmetic immediate.  */
 290   AARCH64_OPND_SVE_ASIMM,       /* SVE signed arithmetic immediate.  */
 291   AARCH64_OPND_SVE_FPIMM8,      /* SVE 8-bit floating-point immediate.  */
 292   AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0.  */
 293   AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0.  */
 294   AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0.  */
 295   AARCH64_OPND_SVE_INV_LIMM,    /* SVE inverted logical immediate.  */
 296   AARCH64_OPND_SVE_LIMM,        /* SVE logical immediate.  */
 297   AARCH64_OPND_SVE_LIMM_MOV,    /* SVE logical immediate for MOV.  */
 298   AARCH64_OPND_SVE_PATTERN,     /* SVE vector pattern enumeration.  */
 299   AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor.  */
 300   AARCH64_OPND_SVE_PRFOP,       /* SVE prefetch operation.  */
 301   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 302   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 303   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 304   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 305   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 306   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 307   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 308   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 309   AARCH64_OPND_SVE_Rm,          /* Integer Rm or ZR, alt. SVE position.  */
 310   AARCH64_OPND_SVE_Rn_SP,       /* Integer Rn or SP, alt. SVE position.  */
 311   AARCH64_OPND_SVE_SHLIMM_PRED,   /* SVE shift left amount (predicated).  */
 312   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
 313   AARCH64_OPND_SVE_SHRIMM_PRED,   /* SVE shift right amount (predicated).  */
 314   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
 315   AARCH64_OPND_SVE_SIMM5,       /* SVE signed 5-bit immediate.  */
 316   AARCH64_OPND_SVE_SIMM5B,      /* SVE secondary signed 5-bit immediate.  */
 317   AARCH64_OPND_SVE_SIMM6,       /* SVE signed 6-bit immediate.  */
 318   AARCH64_OPND_SVE_SIMM8,       /* SVE signed 8-bit immediate.  */
 319   AARCH64_OPND_SVE_UIMM3,       /* SVE unsigned 3-bit immediate.  */
 320   AARCH64_OPND_SVE_UIMM7,       /* SVE unsigned 7-bit immediate.  */
 321   AARCH64_OPND_SVE_UIMM8,       /* SVE unsigned 8-bit immediate.  */
 322   AARCH64_OPND_SVE_UIMM8_53,    /* SVE split unsigned 8-bit immediate.  */
 323   AARCH64_OPND_SVE_VZn,         /* Scalar SIMD&FP register in Zn field.  */
 324   AARCH64_OPND_SVE_Vd,          /* Scalar SIMD&FP register in Vd.  */
 325   AARCH64_OPND_SVE_Vm,          /* Scalar SIMD&FP register in Vm.  */
 326   AARCH64_OPND_SVE_Vn,          /* Scalar SIMD&FP register in Vn.  */
 327   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 328   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 329   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 330   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 331   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 332   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 333   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 334   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 335   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 336   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 337 };
 338
 339 /* Qualifier constrains an operand.  It either specifies a variant of an
 340    operand type or limits values available to an operand type.
 341
 342    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 343
 344 enum aarch64_opnd_qualifier
 345 {
 346   /* Indicating no further qualification on an operand.  */
 347   AARCH64_OPND_QLF_NIL,
 348
 349   /* Qualifying an operand which is a general purpose (integer) register;
 350      indicating the operand data size or a specific register.  */
 351   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 352   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 353   AARCH64_OPND_QLF_WSP, /* WSP.  */
 354   AARCH64_OPND_QLF_SP,  /* SP.  */
 355
 356   /* Qualifying an operand which is a floating-point register, a SIMD
 357      vector element or a SIMD vector element list; indicating operand data
 358      size or the size of each SIMD vector element in the case of a SIMD
 359      vector element list.
 360      These qualifiers are also used to qualify an address operand to
 361      indicate the size of data element a load/store instruction is
 362      accessing.
 363      They are also used for the immediate shift operand in e.g. SSHR.  Such
 364      a use is only for the ease of operand encoding/decoding and qualifier
 365      sequence matching; such a use should not be applied widely; use the value
 366      constraint qualifiers for immediate operands wherever possible.  */
 367   AARCH64_OPND_QLF_S_B,
 368   AARCH64_OPND_QLF_S_H,
 369   AARCH64_OPND_QLF_S_S,
 370   AARCH64_OPND_QLF_S_D,
 371   AARCH64_OPND_QLF_S_Q,
 372
 373   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 374      register list; indicating register shape.
 375      They are also used for the immediate shift operand in e.g. SSHR.  Such
 376      a use is only for the ease of operand encoding/decoding and qualifier
 377      sequence matching; such a use should not be applied widely; use the value
 378      constraint qualifiers for immediate operands wherever possible.  */
 379   AARCH64_OPND_QLF_V_8B,
 380   AARCH64_OPND_QLF_V_16B,
 381   AARCH64_OPND_QLF_V_2H,
 382   AARCH64_OPND_QLF_V_4H,
 383   AARCH64_OPND_QLF_V_8H,
 384   AARCH64_OPND_QLF_V_2S,
 385   AARCH64_OPND_QLF_V_4S,
 386   AARCH64_OPND_QLF_V_1D,
 387   AARCH64_OPND_QLF_V_2D,
 388   AARCH64_OPND_QLF_V_1Q,
 389
 390   AARCH64_OPND_QLF_P_Z,
 391   AARCH64_OPND_QLF_P_M,
 392
 393   /* Constraint on value.  */
 394   AARCH64_OPND_QLF_imm_0_7,
 395   AARCH64_OPND_QLF_imm_0_15,
 396   AARCH64_OPND_QLF_imm_0_31,
 397   AARCH64_OPND_QLF_imm_0_63,
 398   AARCH64_OPND_QLF_imm_1_32,
 399   AARCH64_OPND_QLF_imm_1_64,
 400
 401   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 402      or shift-ones.  */
 403   AARCH64_OPND_QLF_LSL,
 404   AARCH64_OPND_QLF_MSL,
 405
 406   /* Special qualifier helping retrieve qualifier information during the
 407      decoding time (currently not in use).  */
 408   AARCH64_OPND_QLF_RETRIEVE,
 409 };
 410 \f
 411 /* Instruction class.  */
 412
 413 enum aarch64_insn_class
 414 {
 415   addsub_carry,
 416   addsub_ext,
 417   addsub_imm,
 418   addsub_shift,
 419   asimdall,
 420   asimddiff,
 421   asimdelem,
 422   asimdext,
 423   asimdimm,
 424   asimdins,
 425   asimdmisc,
 426   asimdperm,
 427   asimdsame,
 428   asimdshf,
 429   asimdtbl,
 430   asisddiff,
 431   asisdelem,
 432   asisdlse,
 433   asisdlsep,
 434   asisdlso,
 435   asisdlsop,
 436   asisdmisc,
 437   asisdone,
 438   asisdpair,
 439   asisdsame,
 440   asisdshf,
 441   bitfield,
 442   branch_imm,
 443   branch_reg,
 444   compbranch,
 445   condbranch,
 446   condcmp_imm,
 447   condcmp_reg,
 448   condsel,
 449   cryptoaes,
 450   cryptosha2,
 451   cryptosha3,
 452   dp_1src,
 453   dp_2src,
 454   dp_3src,
 455   exception,
 456   extract,
 457   float2fix,
 458   float2int,
 459   floatccmp,
 460   floatcmp,
 461   floatdp1,
 462   floatdp2,
 463   floatdp3,
 464   floatimm,
 465   floatsel,
 466   ldst_immpost,
 467   ldst_immpre,
 468   ldst_imm9,    /* immpost or immpre */
 469   ldst_imm10,   /* LDRAA/LDRAB */
 470   ldst_pos,
 471   ldst_regoff,
 472   ldst_unpriv,
 473   ldst_unscaled,
 474   ldstexcl,
 475   ldstnapair_offs,
 476   ldstpair_off,
 477   ldstpair_indexed,
 478   loadlit,
 479   log_imm,
 480   log_shift,
 481   lse_atomic,
 482   movewide,
 483   pcreladdr,
 484   ic_system,
 485   sve_cpy,
 486   sve_index,
 487   sve_limm,
 488   sve_misc,
 489   sve_movprfx,
 490   sve_pred_zm,
 491   sve_shift_pred,
 492   sve_shift_unpred,
 493   sve_size_bhs,
 494   sve_size_bhsd,
 495   sve_size_hsd,
 496   sve_size_sd,
 497   testbranch,
 498 };
 499
 500 /* Opcode enumerators.  */
 501
 502 enum aarch64_op
 503 {
 504   OP_NIL,
 505   OP_STRB_POS,
 506   OP_LDRB_POS,
 507   OP_LDRSB_POS,
 508   OP_STRH_POS,
 509   OP_LDRH_POS,
 510   OP_LDRSH_POS,
 511   OP_STR_POS,
 512   OP_LDR_POS,
 513   OP_STRF_POS,
 514   OP_LDRF_POS,
 515   OP_LDRSW_POS,
 516   OP_PRFM_POS,
 517
 518   OP_STURB,
 519   OP_LDURB,
 520   OP_LDURSB,
 521   OP_STURH,
 522   OP_LDURH,
 523   OP_LDURSH,
 524   OP_STUR,
 525   OP_LDUR,
 526   OP_STURV,
 527   OP_LDURV,
 528   OP_LDURSW,
 529   OP_PRFUM,
 530
 531   OP_LDR_LIT,
 532   OP_LDRV_LIT,
 533   OP_LDRSW_LIT,
 534   OP_PRFM_LIT,
 535
 536   OP_ADD,
 537   OP_B,
 538   OP_BL,
 539
 540   OP_MOVN,
 541   OP_MOVZ,
 542   OP_MOVK,
 543
 544   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 545   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 546   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 547
 548   OP_MOV_V,             /* MOV alias for moving vector register.  */
 549
 550   OP_ASR_IMM,
 551   OP_LSR_IMM,
 552   OP_LSL_IMM,
 553
 554   OP_BIC,
 555
 556   OP_UBFX,
 557   OP_BFXIL,
 558   OP_SBFX,
 559   OP_SBFIZ,
 560   OP_BFI,
 561   OP_BFC,               /* ARMv8.2.  */
 562   OP_UBFIZ,
 563   OP_UXTB,
 564   OP_UXTH,
 565   OP_UXTW,
 566
 567   OP_CINC,
 568   OP_CINV,
 569   OP_CNEG,
 570   OP_CSET,
 571   OP_CSETM,
 572
 573   OP_FCVT,
 574   OP_FCVTN,
 575   OP_FCVTN2,
 576   OP_FCVTL,
 577   OP_FCVTL2,
 578   OP_FCVTXN_S,          /* Scalar version.  */
 579
 580   OP_ROR_IMM,
 581
 582   OP_SXTL,
 583   OP_SXTL2,
 584   OP_UXTL,
 585   OP_UXTL2,
 586
 587   OP_MOV_P_P,
 588   OP_MOV_Z_P_Z,
 589   OP_MOV_Z_V,
 590   OP_MOV_Z_Z,
 591   OP_MOV_Z_Zi,
 592   OP_MOVM_P_P_P,
 593   OP_MOVS_P_P,
 594   OP_MOVZS_P_P_P,
 595   OP_MOVZ_P_P_P,
 596   OP_NOTS_P_P_P_Z,
 597   OP_NOT_P_P_P_Z,
 598
 599   OP_TOTAL_NUM,         /* Pseudo.  */
 600 };
 601
 602 /* Maximum number of operands an instruction can have.  */
 603 #define AARCH64_MAX_OPND_NUM 6
 604 /* Maximum number of qualifier sequences an instruction can have.  */
 605 #define AARCH64_MAX_QLF_SEQ_NUM 10
 606 /* Operand qualifier typedef; optimized for the size.  */
 607 typedef unsigned char aarch64_opnd_qualifier_t;
 608 /* Operand qualifier sequence typedef.  */
 609 typedef aarch64_opnd_qualifier_t        \
 610           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 611
 612 /* FIXME: improve the efficiency.  */
 613 static inline bfd_boolean
 614 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 615 {
 616   int i;
 617   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 618     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 619       return FALSE;
 620   return TRUE;
 621 }
 622
 623 /* This structure holds information for a particular opcode.  */
 624
 625 struct aarch64_opcode
 626 {
 627   /* The name of the mnemonic.  */
 628   const char *name;
 629
 630   /* The opcode itself.  Those bits which will be filled in with
 631      operands are zeroes.  */
 632   aarch64_insn opcode;
 633
 634   /* The opcode mask.  This is used by the disassembler.  This is a
 635      mask containing ones indicating those bits which must match the
 636      opcode field, and zeroes indicating those bits which need not
 637      match (and are presumably filled in by operands).  */
 638   aarch64_insn mask;
 639
 640   /* Instruction class.  */
 641   enum aarch64_insn_class iclass;
 642
 643   /* Enumerator identifier.  */
 644   enum aarch64_op op;
 645
 646   /* Which architecture variant provides this instruction.  */
 647   const aarch64_feature_set *avariant;
 648
 649   /* An array of operand codes.  Each code is an index into the
 650      operand table.  They appear in the order which the operands must
 651      appear in assembly code, and are terminated by a zero.  */
 652   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 653
 654   /* A list of operand qualifier code sequence.  Each operand qualifier
 655      code qualifies the corresponding operand code.  Each operand
 656      qualifier sequence specifies a valid opcode variant and related
 657      constraint on operands.  */
 658   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 659
 660   /* Flags providing information about this instruction */
 661   uint32_t flags;
 662
 663   /* If nonzero, this operand and operand 0 are both registers and
 664      are required to have the same register number.  */
 665   unsigned char tied_operand;
 666
 667   /* If non-NULL, a function to verify that a given instruction is valid.  */
 668   bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
 669 };
 670
 671 typedef struct aarch64_opcode aarch64_opcode;
 672
 673 /* Table describing all the AArch64 opcodes.  */
 674 extern aarch64_opcode aarch64_opcode_table[];
 675
 676 /* Opcode flags.  */
 677 #define F_ALIAS (1 << 0)
 678 #define F_HAS_ALIAS (1 << 1)
 679 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 680    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 681 #define F_P1 (1 << 2)
 682 #define F_P2 (2 << 2)
 683 #define F_P3 (3 << 2)
 684 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 685 #define F_COND (1 << 4)
 686 /* Instruction has the field of 'sf'.  */
 687 #define F_SF (1 << 5)
 688 /* Instruction has the field of 'size:Q'.  */
 689 #define F_SIZEQ (1 << 6)
 690 /* Floating-point instruction has the field of 'type'.  */
 691 #define F_FPTYPE (1 << 7)
 692 /* AdvSIMD scalar instruction has the field of 'size'.  */
 693 #define F_SSIZE (1 << 8)
 694 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 695 #define F_T (1 << 9)
 696 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 697 #define F_GPRSIZE_IN_Q (1 << 10)
 698 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 699 #define F_LDS_SIZE (1 << 11)
 700 /* Optional operand; assume maximum of 1 operand can be optional.  */
 701 #define F_OPD0_OPT (1 << 12)
 702 #define F_OPD1_OPT (2 << 12)
 703 #define F_OPD2_OPT (3 << 12)
 704 #define F_OPD3_OPT (4 << 12)
 705 #define F_OPD4_OPT (5 << 12)
 706 /* Default value for the optional operand when omitted from the assembly.  */
 707 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 708 /* Instruction that is an alias of another instruction needs to be
 709    encoded/decoded by converting it to/from the real form, followed by
 710    the encoding/decoding according to the rules of the real opcode.
 711    This compares to the direct coding using the alias's information.
 712    N.B. this flag requires F_ALIAS to be used together.  */
 713 #define F_CONV (1 << 20)
 714 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 715    friendly pseudo instruction available only in the assembly code (thus will
 716    not show up in the disassembly).  */
 717 #define F_PSEUDO (1 << 21)
 718 /* Instruction has miscellaneous encoding/decoding rules.  */
 719 #define F_MISC (1 << 22)
 720 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 721 #define F_N (1 << 23)
 722 /* Opcode dependent field.  */
 723 #define F_OD(X) (((X) & 0x7) << 24)
 724 /* Instruction has the field of 'sz'.  */
 725 #define F_LSE_SZ (1 << 27)
 726 /* Require an exact qualifier match, even for NIL qualifiers.  */
 727 #define F_STRICT (1ULL << 28)
 728 /* Next bit is 29.  */
 729
 730 static inline bfd_boolean
 731 alias_opcode_p (const aarch64_opcode *opcode)
 732 {
 733   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 734 }
 735
 736 static inline bfd_boolean
 737 opcode_has_alias (const aarch64_opcode *opcode)
 738 {
 739   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 740 }
 741
 742 /* Priority for disassembling preference.  */
 743 static inline int
 744 opcode_priority (const aarch64_opcode *opcode)
 745 {
 746   return (opcode->flags >> 2) & 0x3;
 747 }
 748
 749 static inline bfd_boolean
 750 pseudo_opcode_p (const aarch64_opcode *opcode)
 751 {
 752   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 753 }
 754
 755 static inline bfd_boolean
 756 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 757 {
 758   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 759     ? TRUE : FALSE;
 760 }
 761
 762 static inline aarch64_insn
 763 get_optional_operand_default_value (const aarch64_opcode *opcode)
 764 {
 765   return (opcode->flags >> 15) & 0x1f;
 766 }
 767
 768 static inline unsigned int
 769 get_opcode_dependent_value (const aarch64_opcode *opcode)
 770 {
 771   return (opcode->flags >> 24) & 0x7;
 772 }
 773
 774 static inline bfd_boolean
 775 opcode_has_special_coder (const aarch64_opcode *opcode)
 776 {
 777   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 778           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 779     : FALSE;
 780 }
 781 \f
 782 struct aarch64_name_value_pair
 783 {
 784   const char *  name;
 785   aarch64_insn  value;
 786 };
 787
 788 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 789 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 790 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 791 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 792
 793 typedef struct
 794 {
 795   const char *  name;
 796   aarch64_insn  value;
 797   uint32_t      flags;
 798 } aarch64_sys_reg;
 799
 800 extern const aarch64_sys_reg aarch64_sys_regs [];
 801 extern const aarch64_sys_reg aarch64_pstatefields [];
 802 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 803 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 804                                                 const aarch64_sys_reg *);
 805 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 806                                                     const aarch64_sys_reg *);
 807
 808 typedef struct
 809 {
 810   const char *name;
 811   uint32_t value;
 812   uint32_t flags ;
 813 } aarch64_sys_ins_reg;
 814
 815 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 816 extern bfd_boolean
 817 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 818                                  const aarch64_sys_ins_reg *);
 819
 820 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 821 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 822 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 823 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 824
 825 /* Shift/extending operator kinds.
 826    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 827 enum aarch64_modifier_kind
 828 {
 829   AARCH64_MOD_NONE,
 830   AARCH64_MOD_MSL,
 831   AARCH64_MOD_ROR,
 832   AARCH64_MOD_ASR,
 833   AARCH64_MOD_LSR,
 834   AARCH64_MOD_LSL,
 835   AARCH64_MOD_UXTB,
 836   AARCH64_MOD_UXTH,
 837   AARCH64_MOD_UXTW,
 838   AARCH64_MOD_UXTX,
 839   AARCH64_MOD_SXTB,
 840   AARCH64_MOD_SXTH,
 841   AARCH64_MOD_SXTW,
 842   AARCH64_MOD_SXTX,
 843   AARCH64_MOD_MUL,
 844   AARCH64_MOD_MUL_VL,
 845 };
 846
 847 bfd_boolean
 848 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 849
 850 enum aarch64_modifier_kind
 851 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 852 /* Condition.  */
 853
 854 typedef struct
 855 {
 856   /* A list of names with the first one as the disassembly preference;
 857      terminated by NULL if fewer than 3.  */
 858   const char *names[4];
 859   aarch64_insn value;
 860 } aarch64_cond;
 861
 862 extern const aarch64_cond aarch64_conds[16];
 863
 864 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 865 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 866 \f
 867 /* Structure representing an operand.  */
 868
 869 struct aarch64_opnd_info
 870 {
 871   enum aarch64_opnd type;
 872   aarch64_opnd_qualifier_t qualifier;
 873   int idx;
 874
 875   union
 876     {
 877       struct
 878         {
 879           unsigned regno;
 880         } reg;
 881       struct
 882         {
 883           unsigned int regno;
 884           int64_t index;
 885         } reglane;
 886       /* e.g. LVn.  */
 887       struct
 888         {
 889           unsigned first_regno : 5;
 890           unsigned num_regs : 3;
 891           /* 1 if it is a list of reg element.  */
 892           unsigned has_index : 1;
 893           /* Lane index; valid only when has_index is 1.  */
 894           int64_t index;
 895         } reglist;
 896       /* e.g. immediate or pc relative address offset.  */
 897       struct
 898         {
 899           int64_t value;
 900           unsigned is_fp : 1;
 901         } imm;
 902       /* e.g. address in STR (register offset).  */
 903       struct
 904         {
 905           unsigned base_regno;
 906           struct
 907             {
 908               union
 909                 {
 910                   int imm;
 911                   unsigned regno;
 912                 };
 913               unsigned is_reg;
 914             } offset;
 915           unsigned pcrel : 1;           /* PC-relative.  */
 916           unsigned writeback : 1;
 917           unsigned preind : 1;          /* Pre-indexed.  */
 918           unsigned postind : 1;         /* Post-indexed.  */
 919         } addr;
 920       const aarch64_cond *cond;
 921       /* The encoding of the system register.  */
 922       aarch64_insn sysreg;
 923       /* The encoding of the PSTATE field.  */
 924       aarch64_insn pstatefield;
 925       const aarch64_sys_ins_reg *sysins_op;
 926       const struct aarch64_name_value_pair *barrier;
 927       const struct aarch64_name_value_pair *hint_option;
 928       const struct aarch64_name_value_pair *prfop;
 929     };
 930
 931   /* Operand shifter; in use when the operand is a register offset address,
 932      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
 933   struct
 934     {
 935       enum aarch64_modifier_kind kind;
 936       unsigned operator_present: 1;     /* Only valid during encoding.  */
 937       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
 938       unsigned amount_present: 1;
 939       int64_t amount;
 940     } shifter;
 941
 942   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
 943                            to be done on it.  In some (but not all) of these
 944                            cases, we need to tell libopcodes to skip the
 945                            constraint checking and the encoding for this
 946                            operand, so that the libopcodes can pick up the
 947                            right opcode before the operand is fixed-up.  This
 948                            flag should only be used during the
 949                            assembling/encoding.  */
 950   unsigned present:1;   /* Whether this operand is present in the assembly
 951                            line; not used during the disassembly.  */
 952 };
 953
 954 typedef struct aarch64_opnd_info aarch64_opnd_info;
 955
 956 /* Structure representing an instruction.
 957
 958    It is used during both the assembling and disassembling.  The assembler
 959    fills an aarch64_inst after a successful parsing and then passes it to the
 960    encoding routine to do the encoding.  During the disassembling, the
 961    disassembler calls the decoding routine to decode a binary instruction; on a
 962    successful return, such a structure will be filled with information of the
 963    instruction; then the disassembler uses the information to print out the
 964    instruction.  */
 965
 966 struct aarch64_inst
 967 {
 968   /* The value of the binary instruction.  */
 969   aarch64_insn value;
 970
 971   /* Corresponding opcode entry.  */
 972   const aarch64_opcode *opcode;
 973
 974   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
 975   const aarch64_cond *cond;
 976
 977   /* Operands information.  */
 978   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
 979 };
 980
 981 typedef struct aarch64_inst aarch64_inst;
 982 \f
 983 /* Diagnosis related declaration and interface.  */
 984
 985 /* Operand error kind enumerators.
 986
 987    AARCH64_OPDE_RECOVERABLE
 988      Less severe error found during the parsing, very possibly because that
 989      GAS has picked up a wrong instruction template for the parsing.
 990
 991    AARCH64_OPDE_SYNTAX_ERROR
 992      General syntax error; it can be either a user error, or simply because
 993      that GAS is trying a wrong instruction template.
 994
 995    AARCH64_OPDE_FATAL_SYNTAX_ERROR
 996      Definitely a user syntax error.
 997
 998    AARCH64_OPDE_INVALID_VARIANT
 999      No syntax error, but the operands are not a valid combination, e.g.
1000      FMOV D0,S0
1001
1002    AARCH64_OPDE_UNTIED_OPERAND
1003      The asm failed to use the same register for a destination operand
1004      and a tied source operand.
1005
1006    AARCH64_OPDE_OUT_OF_RANGE
1007      Error about some immediate value out of a valid range.
1008
1009    AARCH64_OPDE_UNALIGNED
1010      Error about some immediate value not properly aligned (i.e. not being a
1011      multiple times of a certain value).
1012
1013    AARCH64_OPDE_REG_LIST
1014      Error about the register list operand having unexpected number of
1015      registers.
1016
1017    AARCH64_OPDE_OTHER_ERROR
1018      Error of the highest severity and used for any severe issue that does not
1019      fall into any of the above categories.
1020
1021    The enumerators are only interesting to GAS.  They are declared here (in
1022    libopcodes) because that some errors are detected (and then notified to GAS)
1023    by libopcodes (rather than by GAS solely).
1024
1025    The first three errors are only deteced by GAS while the
1026    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1027    only libopcodes has the information about the valid variants of each
1028    instruction.
1029
1030    The enumerators have an increasing severity.  This is helpful when there are
1031    multiple instruction templates available for a given mnemonic name (e.g.
1032    FMOV); this mechanism will help choose the most suitable template from which
1033    the generated diagnostics can most closely describe the issues, if any.  */
1034
1035 enum aarch64_operand_error_kind
1036 {
1037   AARCH64_OPDE_NIL,
1038   AARCH64_OPDE_RECOVERABLE,
1039   AARCH64_OPDE_SYNTAX_ERROR,
1040   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1041   AARCH64_OPDE_INVALID_VARIANT,
1042   AARCH64_OPDE_UNTIED_OPERAND,
1043   AARCH64_OPDE_OUT_OF_RANGE,
1044   AARCH64_OPDE_UNALIGNED,
1045   AARCH64_OPDE_REG_LIST,
1046   AARCH64_OPDE_OTHER_ERROR
1047 };
1048
1049 /* N.B. GAS assumes that this structure work well with shallow copy.  */
1050 struct aarch64_operand_error
1051 {
1052   enum aarch64_operand_error_kind kind;
1053   int index;
1054   const char *error;
1055   int data[3];  /* Some data for extra information.  */
1056 };
1057
1058 typedef struct aarch64_operand_error aarch64_operand_error;
1059
1060 /* Encoding entrypoint.  */
1061
1062 extern int
1063 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1064                        aarch64_insn *, aarch64_opnd_qualifier_t *,
1065                        aarch64_operand_error *);
1066
1067 extern const aarch64_opcode *
1068 aarch64_replace_opcode (struct aarch64_inst *,
1069                         const aarch64_opcode *);
1070
1071 /* Given the opcode enumerator OP, return the pointer to the corresponding
1072    opcode entry.  */
1073
1074 extern const aarch64_opcode *
1075 aarch64_get_opcode (enum aarch64_op);
1076
1077 /* Generate the string representation of an operand.  */
1078 extern void
1079 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1080                        const aarch64_opnd_info *, int, int *, bfd_vma *);
1081
1082 /* Miscellaneous interface.  */
1083
1084 extern int
1085 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1086
1087 extern aarch64_opnd_qualifier_t
1088 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1089                                 const aarch64_opnd_qualifier_t, int);
1090
1091 extern int
1092 aarch64_num_of_operands (const aarch64_opcode *);
1093
1094 extern int
1095 aarch64_stack_pointer_p (const aarch64_opnd_info *);
1096
1097 extern int
1098 aarch64_zero_register_p (const aarch64_opnd_info *);
1099
1100 extern int
1101 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
1102
1103 /* Given an operand qualifier, return the expected data element size
1104    of a qualified operand.  */
1105 extern unsigned char
1106 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1107
1108 extern enum aarch64_operand_class
1109 aarch64_get_operand_class (enum aarch64_opnd);
1110
1111 extern const char *
1112 aarch64_get_operand_name (enum aarch64_opnd);
1113
1114 extern const char *
1115 aarch64_get_operand_desc (enum aarch64_opnd);
1116
1117 extern bfd_boolean
1118 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1119
1120 #ifdef DEBUG_AARCH64
1121 extern int debug_dump;
1122
1123 extern void
1124 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1125
1126 #define DEBUG_TRACE(M, ...)                                     \
1127   {                                                             \
1128     if (debug_dump)                                             \
1129       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1130   }
1131
1132 #define DEBUG_TRACE_IF(C, M, ...)                               \
1133   {                                                             \
1134     if (debug_dump && (C))                                      \
1135       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1136   }
1137 #else  /* !DEBUG_AARCH64 */
1138 #define DEBUG_TRACE(M, ...) ;
1139 #define DEBUG_TRACE_IF(C, M, ...) ;
1140 #endif /* DEBUG_AARCH64 */
1141
1142 extern const char *const aarch64_sve_pattern_array[32];
1143 extern const char *const aarch64_sve_prfop_array[16];
1144
1145 #ifdef __cplusplus
1146 }
1147 #endif
1148
1149 #endif /* OPCODE_AARCH64_H */