include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2016 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  41 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  42 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  43 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  44 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  45 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  46 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  47 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  48 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  49 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  50 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  51 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  52 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  53 #define AARCH64_FEATURE_PROFILE 0x08000000      /* Statistical Profiling.  */
  54
  55 /* Architectures are the sum of the base and extensions.  */
  56 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  57                                                  AARCH64_FEATURE_FP  \
  58                                                  | AARCH64_FEATURE_SIMD)
  59 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  60                                                  AARCH64_FEATURE_FP  \
  61                                                  | AARCH64_FEATURE_SIMD \
  62                                                  | AARCH64_FEATURE_CRC  \
  63                                                  | AARCH64_FEATURE_V8_1 \
  64                                                  | AARCH64_FEATURE_LSE  \
  65                                                  | AARCH64_FEATURE_PAN  \
  66                                                  | AARCH64_FEATURE_LOR  \
  67                                                  | AARCH64_FEATURE_RDMA)
  68 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_FEATURE_V8,    \
  69                                                  AARCH64_FEATURE_V8_2   \
  70                                                  | AARCH64_FEATURE_F16  \
  71                                                  | AARCH64_FEATURE_RAS  \
  72                                                  | AARCH64_FEATURE_FP   \
  73                                                  | AARCH64_FEATURE_SIMD \
  74                                                  | AARCH64_FEATURE_CRC  \
  75                                                  | AARCH64_FEATURE_V8_1 \
  76                                                  | AARCH64_FEATURE_LSE  \
  77                                                  | AARCH64_FEATURE_PAN  \
  78                                                  | AARCH64_FEATURE_LOR  \
  79                                                  | AARCH64_FEATURE_RDMA)
  80
  81 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
  82 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
  83
  84 /* CPU-specific features.  */
  85 typedef unsigned long aarch64_feature_set;
  86
  87 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
  88   (((CPU) & (FEAT)) != 0)
  89
  90 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
  91   do                                            \
  92     {                                           \
  93       (TARG) = (F1) | (F2);                     \
  94     }                                           \
  95   while (0)
  96
  97 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
  98   do                                            \
  99     {                                           \
 100       (TARG) = (F1) &~ (F2);                    \
 101     }                                           \
 102   while (0)
 103
 104 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 105
 106 #define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT)    \
 107   (((OPC) & (FEAT)) != 0)
 108
 109 enum aarch64_operand_class
 110 {
 111   AARCH64_OPND_CLASS_NIL,
 112   AARCH64_OPND_CLASS_INT_REG,
 113   AARCH64_OPND_CLASS_MODIFIED_REG,
 114   AARCH64_OPND_CLASS_FP_REG,
 115   AARCH64_OPND_CLASS_SIMD_REG,
 116   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 117   AARCH64_OPND_CLASS_SISD_REG,
 118   AARCH64_OPND_CLASS_SIMD_REGLIST,
 119   AARCH64_OPND_CLASS_CP_REG,
 120   AARCH64_OPND_CLASS_ADDRESS,
 121   AARCH64_OPND_CLASS_IMMEDIATE,
 122   AARCH64_OPND_CLASS_SYSTEM,
 123   AARCH64_OPND_CLASS_COND,
 124 };
 125
 126 /* Operand code that helps both parsing and coding.
 127    Keep AARCH64_OPERANDS synced.  */
 128
 129 enum aarch64_opnd
 130 {
 131   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 132
 133   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 134   AARCH64_OPND_Rn,      /* Integer register as source.  */
 135   AARCH64_OPND_Rm,      /* Integer register as source.  */
 136   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 137   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 138   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 139   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 140   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 141
 142   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 143   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 144   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 145   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 146   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 147
 148   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 149   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 150   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 151   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 152   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 153   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 154
 155   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 156   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 157   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 158
 159   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 160   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 161   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 162   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 163   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 164   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 165   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 166   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 167   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 168   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 169   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 170                            structure to all lanes.  */
 171   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 172
 173   AARCH64_OPND_Cn,      /* Co-processor register in CRn field.  */
 174   AARCH64_OPND_Cm,      /* Co-processor register in CRm field.  */
 175
 176   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 177   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 178   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 179   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 180   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 181   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 182   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 183                            (no encoding).  */
 184   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 185   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 186   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 187   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 188   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 189   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 190   AARCH64_OPND_IMM,     /* Immediate.  */
 191   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 192   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 193   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 194   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 195   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 196   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 197   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 198   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 199                            each condition flag.  */
 200
 201   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 202   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 203   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 204   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 205   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 206
 207   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 208   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 209
 210   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 211   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 212   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 213   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 214   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 215
 216   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 217   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 218   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 219   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 220   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 221                                    negative or unaligned and there is
 222                                    no writeback allowed.  This operand code
 223                                    is only used to support the programmer-
 224                                    friendly feature of using LDR/STR as the
 225                                    the mnemonic name for LDUR/STUR instructions
 226                                    wherever there is no ambiguity.  */
 227   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 228   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 229   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 230
 231   AARCH64_OPND_SYSREG,          /* System register operand.  */
 232   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 233   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 234   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 235   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 236   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 237   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 238   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 239   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 240   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 241 };
 242
 243 /* Qualifier constrains an operand.  It either specifies a variant of an
 244    operand type or limits values available to an operand type.
 245
 246    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 247
 248 enum aarch64_opnd_qualifier
 249 {
 250   /* Indicating no further qualification on an operand.  */
 251   AARCH64_OPND_QLF_NIL,
 252
 253   /* Qualifying an operand which is a general purpose (integer) register;
 254      indicating the operand data size or a specific register.  */
 255   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 256   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 257   AARCH64_OPND_QLF_WSP, /* WSP.  */
 258   AARCH64_OPND_QLF_SP,  /* SP.  */
 259
 260   /* Qualifying an operand which is a floating-point register, a SIMD
 261      vector element or a SIMD vector element list; indicating operand data
 262      size or the size of each SIMD vector element in the case of a SIMD
 263      vector element list.
 264      These qualifiers are also used to qualify an address operand to
 265      indicate the size of data element a load/store instruction is
 266      accessing.
 267      They are also used for the immediate shift operand in e.g. SSHR.  Such
 268      a use is only for the ease of operand encoding/decoding and qualifier
 269      sequence matching; such a use should not be applied widely; use the value
 270      constraint qualifiers for immediate operands wherever possible.  */
 271   AARCH64_OPND_QLF_S_B,
 272   AARCH64_OPND_QLF_S_H,
 273   AARCH64_OPND_QLF_S_S,
 274   AARCH64_OPND_QLF_S_D,
 275   AARCH64_OPND_QLF_S_Q,
 276
 277   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 278      register list; indicating register shape.
 279      They are also used for the immediate shift operand in e.g. SSHR.  Such
 280      a use is only for the ease of operand encoding/decoding and qualifier
 281      sequence matching; such a use should not be applied widely; use the value
 282      constraint qualifiers for immediate operands wherever possible.  */
 283   AARCH64_OPND_QLF_V_8B,
 284   AARCH64_OPND_QLF_V_16B,
 285   AARCH64_OPND_QLF_V_2H,
 286   AARCH64_OPND_QLF_V_4H,
 287   AARCH64_OPND_QLF_V_8H,
 288   AARCH64_OPND_QLF_V_2S,
 289   AARCH64_OPND_QLF_V_4S,
 290   AARCH64_OPND_QLF_V_1D,
 291   AARCH64_OPND_QLF_V_2D,
 292   AARCH64_OPND_QLF_V_1Q,
 293
 294   /* Constraint on value.  */
 295   AARCH64_OPND_QLF_imm_0_7,
 296   AARCH64_OPND_QLF_imm_0_15,
 297   AARCH64_OPND_QLF_imm_0_31,
 298   AARCH64_OPND_QLF_imm_0_63,
 299   AARCH64_OPND_QLF_imm_1_32,
 300   AARCH64_OPND_QLF_imm_1_64,
 301
 302   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 303      or shift-ones.  */
 304   AARCH64_OPND_QLF_LSL,
 305   AARCH64_OPND_QLF_MSL,
 306
 307   /* Special qualifier helping retrieve qualifier information during the
 308      decoding time (currently not in use).  */
 309   AARCH64_OPND_QLF_RETRIEVE,
 310 };
 311 \f
 312 /* Instruction class.  */
 313
 314 enum aarch64_insn_class
 315 {
 316   addsub_carry,
 317   addsub_ext,
 318   addsub_imm,
 319   addsub_shift,
 320   asimdall,
 321   asimddiff,
 322   asimdelem,
 323   asimdext,
 324   asimdimm,
 325   asimdins,
 326   asimdmisc,
 327   asimdperm,
 328   asimdsame,
 329   asimdshf,
 330   asimdtbl,
 331   asisddiff,
 332   asisdelem,
 333   asisdlse,
 334   asisdlsep,
 335   asisdlso,
 336   asisdlsop,
 337   asisdmisc,
 338   asisdone,
 339   asisdpair,
 340   asisdsame,
 341   asisdshf,
 342   bitfield,
 343   branch_imm,
 344   branch_reg,
 345   compbranch,
 346   condbranch,
 347   condcmp_imm,
 348   condcmp_reg,
 349   condsel,
 350   cryptoaes,
 351   cryptosha2,
 352   cryptosha3,
 353   dp_1src,
 354   dp_2src,
 355   dp_3src,
 356   exception,
 357   extract,
 358   float2fix,
 359   float2int,
 360   floatccmp,
 361   floatcmp,
 362   floatdp1,
 363   floatdp2,
 364   floatdp3,
 365   floatimm,
 366   floatsel,
 367   ldst_immpost,
 368   ldst_immpre,
 369   ldst_imm9,    /* immpost or immpre */
 370   ldst_pos,
 371   ldst_regoff,
 372   ldst_unpriv,
 373   ldst_unscaled,
 374   ldstexcl,
 375   ldstnapair_offs,
 376   ldstpair_off,
 377   ldstpair_indexed,
 378   loadlit,
 379   log_imm,
 380   log_shift,
 381   lse_atomic,
 382   movewide,
 383   pcreladdr,
 384   ic_system,
 385   testbranch,
 386 };
 387
 388 /* Opcode enumerators.  */
 389
 390 enum aarch64_op
 391 {
 392   OP_NIL,
 393   OP_STRB_POS,
 394   OP_LDRB_POS,
 395   OP_LDRSB_POS,
 396   OP_STRH_POS,
 397   OP_LDRH_POS,
 398   OP_LDRSH_POS,
 399   OP_STR_POS,
 400   OP_LDR_POS,
 401   OP_STRF_POS,
 402   OP_LDRF_POS,
 403   OP_LDRSW_POS,
 404   OP_PRFM_POS,
 405
 406   OP_STURB,
 407   OP_LDURB,
 408   OP_LDURSB,
 409   OP_STURH,
 410   OP_LDURH,
 411   OP_LDURSH,
 412   OP_STUR,
 413   OP_LDUR,
 414   OP_STURV,
 415   OP_LDURV,
 416   OP_LDURSW,
 417   OP_PRFUM,
 418
 419   OP_LDR_LIT,
 420   OP_LDRV_LIT,
 421   OP_LDRSW_LIT,
 422   OP_PRFM_LIT,
 423
 424   OP_ADD,
 425   OP_B,
 426   OP_BL,
 427
 428   OP_MOVN,
 429   OP_MOVZ,
 430   OP_MOVK,
 431
 432   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 433   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 434   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 435
 436   OP_MOV_V,             /* MOV alias for moving vector register.  */
 437
 438   OP_ASR_IMM,
 439   OP_LSR_IMM,
 440   OP_LSL_IMM,
 441
 442   OP_BIC,
 443
 444   OP_UBFX,
 445   OP_BFXIL,
 446   OP_SBFX,
 447   OP_SBFIZ,
 448   OP_BFI,
 449   OP_BFC,               /* ARMv8.2.  */
 450   OP_UBFIZ,
 451   OP_UXTB,
 452   OP_UXTH,
 453   OP_UXTW,
 454
 455   OP_CINC,
 456   OP_CINV,
 457   OP_CNEG,
 458   OP_CSET,
 459   OP_CSETM,
 460
 461   OP_FCVT,
 462   OP_FCVTN,
 463   OP_FCVTN2,
 464   OP_FCVTL,
 465   OP_FCVTL2,
 466   OP_FCVTXN_S,          /* Scalar version.  */
 467
 468   OP_ROR_IMM,
 469
 470   OP_SXTL,
 471   OP_SXTL2,
 472   OP_UXTL,
 473   OP_UXTL2,
 474
 475   OP_TOTAL_NUM,         /* Pseudo.  */
 476 };
 477
 478 /* Maximum number of operands an instruction can have.  */
 479 #define AARCH64_MAX_OPND_NUM 6
 480 /* Maximum number of qualifier sequences an instruction can have.  */
 481 #define AARCH64_MAX_QLF_SEQ_NUM 10
 482 /* Operand qualifier typedef; optimized for the size.  */
 483 typedef unsigned char aarch64_opnd_qualifier_t;
 484 /* Operand qualifier sequence typedef.  */
 485 typedef aarch64_opnd_qualifier_t        \
 486           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 487
 488 /* FIXME: improve the efficiency.  */
 489 static inline bfd_boolean
 490 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 491 {
 492   int i;
 493   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 494     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 495       return FALSE;
 496   return TRUE;
 497 }
 498
 499 /* This structure holds information for a particular opcode.  */
 500
 501 struct aarch64_opcode
 502 {
 503   /* The name of the mnemonic.  */
 504   const char *name;
 505
 506   /* The opcode itself.  Those bits which will be filled in with
 507      operands are zeroes.  */
 508   aarch64_insn opcode;
 509
 510   /* The opcode mask.  This is used by the disassembler.  This is a
 511      mask containing ones indicating those bits which must match the
 512      opcode field, and zeroes indicating those bits which need not
 513      match (and are presumably filled in by operands).  */
 514   aarch64_insn mask;
 515
 516   /* Instruction class.  */
 517   enum aarch64_insn_class iclass;
 518
 519   /* Enumerator identifier.  */
 520   enum aarch64_op op;
 521
 522   /* Which architecture variant provides this instruction.  */
 523   const aarch64_feature_set *avariant;
 524
 525   /* An array of operand codes.  Each code is an index into the
 526      operand table.  They appear in the order which the operands must
 527      appear in assembly code, and are terminated by a zero.  */
 528   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 529
 530   /* A list of operand qualifier code sequence.  Each operand qualifier
 531      code qualifies the corresponding operand code.  Each operand
 532      qualifier sequence specifies a valid opcode variant and related
 533      constraint on operands.  */
 534   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 535
 536   /* Flags providing information about this instruction */
 537   uint32_t flags;
 538
 539   /* If non-NULL, a function to verify that a given instruction is valid.  */
 540   bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
 541 };
 542
 543 typedef struct aarch64_opcode aarch64_opcode;
 544
 545 /* Table describing all the AArch64 opcodes.  */
 546 extern aarch64_opcode aarch64_opcode_table[];
 547
 548 /* Opcode flags.  */
 549 #define F_ALIAS (1 << 0)
 550 #define F_HAS_ALIAS (1 << 1)
 551 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 552    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 553 #define F_P1 (1 << 2)
 554 #define F_P2 (2 << 2)
 555 #define F_P3 (3 << 2)
 556 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 557 #define F_COND (1 << 4)
 558 /* Instruction has the field of 'sf'.  */
 559 #define F_SF (1 << 5)
 560 /* Instruction has the field of 'size:Q'.  */
 561 #define F_SIZEQ (1 << 6)
 562 /* Floating-point instruction has the field of 'type'.  */
 563 #define F_FPTYPE (1 << 7)
 564 /* AdvSIMD scalar instruction has the field of 'size'.  */
 565 #define F_SSIZE (1 << 8)
 566 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 567 #define F_T (1 << 9)
 568 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 569 #define F_GPRSIZE_IN_Q (1 << 10)
 570 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 571 #define F_LDS_SIZE (1 << 11)
 572 /* Optional operand; assume maximum of 1 operand can be optional.  */
 573 #define F_OPD0_OPT (1 << 12)
 574 #define F_OPD1_OPT (2 << 12)
 575 #define F_OPD2_OPT (3 << 12)
 576 #define F_OPD3_OPT (4 << 12)
 577 #define F_OPD4_OPT (5 << 12)
 578 /* Default value for the optional operand when omitted from the assembly.  */
 579 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 580 /* Instruction that is an alias of another instruction needs to be
 581    encoded/decoded by converting it to/from the real form, followed by
 582    the encoding/decoding according to the rules of the real opcode.
 583    This compares to the direct coding using the alias's information.
 584    N.B. this flag requires F_ALIAS to be used together.  */
 585 #define F_CONV (1 << 20)
 586 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 587    friendly pseudo instruction available only in the assembly code (thus will
 588    not show up in the disassembly).  */
 589 #define F_PSEUDO (1 << 21)
 590 /* Instruction has miscellaneous encoding/decoding rules.  */
 591 #define F_MISC (1 << 22)
 592 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 593 #define F_N (1 << 23)
 594 /* Opcode dependent field.  */
 595 #define F_OD(X) (((X) & 0x7) << 24)
 596 /* Instruction has the field of 'sz'.  */
 597 #define F_LSE_SZ (1 << 27)
 598 /* Next bit is 28.  */
 599
 600 static inline bfd_boolean
 601 alias_opcode_p (const aarch64_opcode *opcode)
 602 {
 603   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 604 }
 605
 606 static inline bfd_boolean
 607 opcode_has_alias (const aarch64_opcode *opcode)
 608 {
 609   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 610 }
 611
 612 /* Priority for disassembling preference.  */
 613 static inline int
 614 opcode_priority (const aarch64_opcode *opcode)
 615 {
 616   return (opcode->flags >> 2) & 0x3;
 617 }
 618
 619 static inline bfd_boolean
 620 pseudo_opcode_p (const aarch64_opcode *opcode)
 621 {
 622   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 623 }
 624
 625 static inline bfd_boolean
 626 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 627 {
 628   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 629     ? TRUE : FALSE;
 630 }
 631
 632 static inline aarch64_insn
 633 get_optional_operand_default_value (const aarch64_opcode *opcode)
 634 {
 635   return (opcode->flags >> 15) & 0x1f;
 636 }
 637
 638 static inline unsigned int
 639 get_opcode_dependent_value (const aarch64_opcode *opcode)
 640 {
 641   return (opcode->flags >> 24) & 0x7;
 642 }
 643
 644 static inline bfd_boolean
 645 opcode_has_special_coder (const aarch64_opcode *opcode)
 646 {
 647   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 648           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 649     : FALSE;
 650 }
 651 \f
 652 struct aarch64_name_value_pair
 653 {
 654   const char *  name;
 655   aarch64_insn  value;
 656 };
 657
 658 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 659 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 660 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 661 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 662
 663 typedef struct
 664 {
 665   const char *  name;
 666   aarch64_insn  value;
 667   uint32_t      flags;
 668 } aarch64_sys_reg;
 669
 670 extern const aarch64_sys_reg aarch64_sys_regs [];
 671 extern const aarch64_sys_reg aarch64_pstatefields [];
 672 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 673 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 674                                                 const aarch64_sys_reg *);
 675 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 676                                                     const aarch64_sys_reg *);
 677
 678 typedef struct
 679 {
 680   const char *name;
 681   uint32_t value;
 682   uint32_t flags ;
 683 } aarch64_sys_ins_reg;
 684
 685 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 686 extern bfd_boolean
 687 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 688                                  const aarch64_sys_ins_reg *);
 689
 690 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 691 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 692 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 693 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 694
 695 /* Shift/extending operator kinds.
 696    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 697 enum aarch64_modifier_kind
 698 {
 699   AARCH64_MOD_NONE,
 700   AARCH64_MOD_MSL,
 701   AARCH64_MOD_ROR,
 702   AARCH64_MOD_ASR,
 703   AARCH64_MOD_LSR,
 704   AARCH64_MOD_LSL,
 705   AARCH64_MOD_UXTB,
 706   AARCH64_MOD_UXTH,
 707   AARCH64_MOD_UXTW,
 708   AARCH64_MOD_UXTX,
 709   AARCH64_MOD_SXTB,
 710   AARCH64_MOD_SXTH,
 711   AARCH64_MOD_SXTW,
 712   AARCH64_MOD_SXTX,
 713 };
 714
 715 bfd_boolean
 716 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 717
 718 enum aarch64_modifier_kind
 719 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 720 /* Condition.  */
 721
 722 typedef struct
 723 {
 724   /* A list of names with the first one as the disassembly preference;
 725      terminated by NULL if fewer than 3.  */
 726   const char *names[3];
 727   aarch64_insn value;
 728 } aarch64_cond;
 729
 730 extern const aarch64_cond aarch64_conds[16];
 731
 732 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 733 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 734 \f
 735 /* Structure representing an operand.  */
 736
 737 struct aarch64_opnd_info
 738 {
 739   enum aarch64_opnd type;
 740   aarch64_opnd_qualifier_t qualifier;
 741   int idx;
 742
 743   union
 744     {
 745       struct
 746         {
 747           unsigned regno;
 748         } reg;
 749       struct
 750         {
 751           unsigned int regno;
 752           int64_t index;
 753         } reglane;
 754       /* e.g. LVn.  */
 755       struct
 756         {
 757           unsigned first_regno : 5;
 758           unsigned num_regs : 3;
 759           /* 1 if it is a list of reg element.  */
 760           unsigned has_index : 1;
 761           /* Lane index; valid only when has_index is 1.  */
 762           int64_t index;
 763         } reglist;
 764       /* e.g. immediate or pc relative address offset.  */
 765       struct
 766         {
 767           int64_t value;
 768           unsigned is_fp : 1;
 769         } imm;
 770       /* e.g. address in STR (register offset).  */
 771       struct
 772         {
 773           unsigned base_regno;
 774           struct
 775             {
 776               union
 777                 {
 778                   int imm;
 779                   unsigned regno;
 780                 };
 781               unsigned is_reg;
 782             } offset;
 783           unsigned pcrel : 1;           /* PC-relative.  */
 784           unsigned writeback : 1;
 785           unsigned preind : 1;          /* Pre-indexed.  */
 786           unsigned postind : 1;         /* Post-indexed.  */
 787         } addr;
 788       const aarch64_cond *cond;
 789       /* The encoding of the system register.  */
 790       aarch64_insn sysreg;
 791       /* The encoding of the PSTATE field.  */
 792       aarch64_insn pstatefield;
 793       const aarch64_sys_ins_reg *sysins_op;
 794       const struct aarch64_name_value_pair *barrier;
 795       const struct aarch64_name_value_pair *hint_option;
 796       const struct aarch64_name_value_pair *prfop;
 797     };
 798
 799   /* Operand shifter; in use when the operand is a register offset address,
 800      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
 801   struct
 802     {
 803       enum aarch64_modifier_kind kind;
 804       int amount;
 805       unsigned operator_present: 1;     /* Only valid during encoding.  */
 806       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
 807       unsigned amount_present: 1;
 808     } shifter;
 809
 810   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
 811                            to be done on it.  In some (but not all) of these
 812                            cases, we need to tell libopcodes to skip the
 813                            constraint checking and the encoding for this
 814                            operand, so that the libopcodes can pick up the
 815                            right opcode before the operand is fixed-up.  This
 816                            flag should only be used during the
 817                            assembling/encoding.  */
 818   unsigned present:1;   /* Whether this operand is present in the assembly
 819                            line; not used during the disassembly.  */
 820 };
 821
 822 typedef struct aarch64_opnd_info aarch64_opnd_info;
 823
 824 /* Structure representing an instruction.
 825
 826    It is used during both the assembling and disassembling.  The assembler
 827    fills an aarch64_inst after a successful parsing and then passes it to the
 828    encoding routine to do the encoding.  During the disassembling, the
 829    disassembler calls the decoding routine to decode a binary instruction; on a
 830    successful return, such a structure will be filled with information of the
 831    instruction; then the disassembler uses the information to print out the
 832    instruction.  */
 833
 834 struct aarch64_inst
 835 {
 836   /* The value of the binary instruction.  */
 837   aarch64_insn value;
 838
 839   /* Corresponding opcode entry.  */
 840   const aarch64_opcode *opcode;
 841
 842   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
 843   const aarch64_cond *cond;
 844
 845   /* Operands information.  */
 846   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
 847 };
 848
 849 typedef struct aarch64_inst aarch64_inst;
 850 \f
 851 /* Diagnosis related declaration and interface.  */
 852
 853 /* Operand error kind enumerators.
 854
 855    AARCH64_OPDE_RECOVERABLE
 856      Less severe error found during the parsing, very possibly because that
 857      GAS has picked up a wrong instruction template for the parsing.
 858
 859    AARCH64_OPDE_SYNTAX_ERROR
 860      General syntax error; it can be either a user error, or simply because
 861      that GAS is trying a wrong instruction template.
 862
 863    AARCH64_OPDE_FATAL_SYNTAX_ERROR
 864      Definitely a user syntax error.
 865
 866    AARCH64_OPDE_INVALID_VARIANT
 867      No syntax error, but the operands are not a valid combination, e.g.
 868      FMOV D0,S0
 869
 870    AARCH64_OPDE_OUT_OF_RANGE
 871      Error about some immediate value out of a valid range.
 872
 873    AARCH64_OPDE_UNALIGNED
 874      Error about some immediate value not properly aligned (i.e. not being a
 875      multiple times of a certain value).
 876
 877    AARCH64_OPDE_REG_LIST
 878      Error about the register list operand having unexpected number of
 879      registers.
 880
 881    AARCH64_OPDE_OTHER_ERROR
 882      Error of the highest severity and used for any severe issue that does not
 883      fall into any of the above categories.
 884
 885    The enumerators are only interesting to GAS.  They are declared here (in
 886    libopcodes) because that some errors are detected (and then notified to GAS)
 887    by libopcodes (rather than by GAS solely).
 888
 889    The first three errors are only deteced by GAS while the
 890    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
 891    only libopcodes has the information about the valid variants of each
 892    instruction.
 893
 894    The enumerators have an increasing severity.  This is helpful when there are
 895    multiple instruction templates available for a given mnemonic name (e.g.
 896    FMOV); this mechanism will help choose the most suitable template from which
 897    the generated diagnostics can most closely describe the issues, if any.  */
 898
 899 enum aarch64_operand_error_kind
 900 {
 901   AARCH64_OPDE_NIL,
 902   AARCH64_OPDE_RECOVERABLE,
 903   AARCH64_OPDE_SYNTAX_ERROR,
 904   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
 905   AARCH64_OPDE_INVALID_VARIANT,
 906   AARCH64_OPDE_OUT_OF_RANGE,
 907   AARCH64_OPDE_UNALIGNED,
 908   AARCH64_OPDE_REG_LIST,
 909   AARCH64_OPDE_OTHER_ERROR
 910 };
 911
 912 /* N.B. GAS assumes that this structure work well with shallow copy.  */
 913 struct aarch64_operand_error
 914 {
 915   enum aarch64_operand_error_kind kind;
 916   int index;
 917   const char *error;
 918   int data[3];  /* Some data for extra information.  */
 919 };
 920
 921 typedef struct aarch64_operand_error aarch64_operand_error;
 922
 923 /* Encoding entrypoint.  */
 924
 925 extern int
 926 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
 927                        aarch64_insn *, aarch64_opnd_qualifier_t *,
 928                        aarch64_operand_error *);
 929
 930 extern const aarch64_opcode *
 931 aarch64_replace_opcode (struct aarch64_inst *,
 932                         const aarch64_opcode *);
 933
 934 /* Given the opcode enumerator OP, return the pointer to the corresponding
 935    opcode entry.  */
 936
 937 extern const aarch64_opcode *
 938 aarch64_get_opcode (enum aarch64_op);
 939
 940 /* Generate the string representation of an operand.  */
 941 extern void
 942 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
 943                        const aarch64_opnd_info *, int, int *, bfd_vma *);
 944
 945 /* Miscellaneous interface.  */
 946
 947 extern int
 948 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
 949
 950 extern aarch64_opnd_qualifier_t
 951 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
 952                                 const aarch64_opnd_qualifier_t, int);
 953
 954 extern int
 955 aarch64_num_of_operands (const aarch64_opcode *);
 956
 957 extern int
 958 aarch64_stack_pointer_p (const aarch64_opnd_info *);
 959
 960 extern int
 961 aarch64_zero_register_p (const aarch64_opnd_info *);
 962
 963 extern int
 964 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
 965
 966 /* Given an operand qualifier, return the expected data element size
 967    of a qualified operand.  */
 968 extern unsigned char
 969 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
 970
 971 extern enum aarch64_operand_class
 972 aarch64_get_operand_class (enum aarch64_opnd);
 973
 974 extern const char *
 975 aarch64_get_operand_name (enum aarch64_opnd);
 976
 977 extern const char *
 978 aarch64_get_operand_desc (enum aarch64_opnd);
 979
 980 #ifdef DEBUG_AARCH64
 981 extern int debug_dump;
 982
 983 extern void
 984 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
 985
 986 #define DEBUG_TRACE(M, ...)                                     \
 987   {                                                             \
 988     if (debug_dump)                                             \
 989       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
 990   }
 991
 992 #define DEBUG_TRACE_IF(C, M, ...)                               \
 993   {                                                             \
 994     if (debug_dump && (C))                                      \
 995       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
 996   }
 997 #else  /* !DEBUG_AARCH64 */
 998 #define DEBUG_TRACE(M, ...) ;
 999 #define DEBUG_TRACE_IF(C, M, ...) ;
1000 #endif /* DEBUG_AARCH64 */
1001
1002 #ifdef __cplusplus
1003 }
1004 #endif
1005
1006 #endif /* OPCODE_AARCH64_H */