include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2017 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  41 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  42 #define AARCH64_FEATURE_V8_3    0x00000040      /* ARMv8.3 processors.  */
  43 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  44 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  45 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  46 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  47 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  48 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  49 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  50 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  51 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  52 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  53 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  54 #define AARCH64_FEATURE_PROFILE 0x08000000      /* Statistical Profiling.  */
  55 #define AARCH64_FEATURE_SVE     0x10000000      /* SVE instructions.  */
  56 #define AARCH64_FEATURE_RCPC    0x20000000      /* RCPC instructions.  */
  57 #define AARCH64_FEATURE_COMPNUM 0x40000000      /* Complex # instructions.  */
  58 #define AARCH64_FEATURE_DOTPROD 0x080000000     /* Dot Product instructions.  */
  59
  60 /* Architectures are the sum of the base and extensions.  */
  61 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  62                                                  AARCH64_FEATURE_FP  \
  63                                                  | AARCH64_FEATURE_SIMD)
  64 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_ARCH_V8, \
  65                                                  AARCH64_FEATURE_CRC    \
  66                                                  | AARCH64_FEATURE_V8_1 \
  67                                                  | AARCH64_FEATURE_LSE  \
  68                                                  | AARCH64_FEATURE_PAN  \
  69                                                  | AARCH64_FEATURE_LOR  \
  70                                                  | AARCH64_FEATURE_RDMA)
  71 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_ARCH_V8_1,     \
  72                                                  AARCH64_FEATURE_V8_2   \
  73                                                  | AARCH64_FEATURE_F16  \
  74                                                  | AARCH64_FEATURE_RAS)
  75 #define AARCH64_ARCH_V8_3       AARCH64_FEATURE (AARCH64_ARCH_V8_2,     \
  76                                                  AARCH64_FEATURE_V8_3   \
  77                                                  | AARCH64_FEATURE_RCPC \
  78                                                  | AARCH64_FEATURE_COMPNUM)
  79
  80 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
  81 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
  82
  83 /* CPU-specific features.  */
  84 typedef unsigned long aarch64_feature_set;
  85
  86 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
  87   ((~(CPU) & (FEAT)) == 0)
  88
  89 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
  90   (((CPU) & (FEAT)) != 0)
  91
  92 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
  93   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
  94
  95 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
  96   do                                            \
  97     {                                           \
  98       (TARG) = (F1) | (F2);                     \
  99     }                                           \
 100   while (0)
 101
 102 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 103   do                                            \
 104     {                                           \
 105       (TARG) = (F1) &~ (F2);                    \
 106     }                                           \
 107   while (0)
 108
 109 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 110
 111 enum aarch64_operand_class
 112 {
 113   AARCH64_OPND_CLASS_NIL,
 114   AARCH64_OPND_CLASS_INT_REG,
 115   AARCH64_OPND_CLASS_MODIFIED_REG,
 116   AARCH64_OPND_CLASS_FP_REG,
 117   AARCH64_OPND_CLASS_SIMD_REG,
 118   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 119   AARCH64_OPND_CLASS_SISD_REG,
 120   AARCH64_OPND_CLASS_SIMD_REGLIST,
 121   AARCH64_OPND_CLASS_SVE_REG,
 122   AARCH64_OPND_CLASS_PRED_REG,
 123   AARCH64_OPND_CLASS_ADDRESS,
 124   AARCH64_OPND_CLASS_IMMEDIATE,
 125   AARCH64_OPND_CLASS_SYSTEM,
 126   AARCH64_OPND_CLASS_COND,
 127 };
 128
 129 /* Operand code that helps both parsing and coding.
 130    Keep AARCH64_OPERANDS synced.  */
 131
 132 enum aarch64_opnd
 133 {
 134   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 135
 136   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 137   AARCH64_OPND_Rn,      /* Integer register as source.  */
 138   AARCH64_OPND_Rm,      /* Integer register as source.  */
 139   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 140   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 141   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 142   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 143   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 144
 145   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 146   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 147   AARCH64_OPND_Rm_SP,   /* Integer Rm or SP.  */
 148   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 149   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 150   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 151
 152   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 153   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 154   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 155   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 156   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 157   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 158
 159   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 160   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 161   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 162
 163   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 164   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 165   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 166   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 167   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 168   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 169   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 170   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 171   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 172   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 173   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 174                            structure to all lanes.  */
 175   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 176
 177   AARCH64_OPND_CRn,     /* Co-processor register in CRn field.  */
 178   AARCH64_OPND_CRm,     /* Co-processor register in CRm field.  */
 179
 180   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 181   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 182   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 183   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 184   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 185   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 186   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 187                            (no encoding).  */
 188   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 189   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 190   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 191   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 192   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 193   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 194   AARCH64_OPND_IMM,     /* Immediate.  */
 195   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 196   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 197   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 198   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 199   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 200   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 201   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 202   AARCH64_OPND_SIMM5,   /* 5-bit signed immediate in the imm5 field.  */
 203   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 204                            each condition flag.  */
 205
 206   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 207   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 208   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 209   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 210   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 211   AARCH64_OPND_IMM_ROT1,        /* Immediate rotate operand for FCMLA.  */
 212   AARCH64_OPND_IMM_ROT2,        /* Immediate rotate operand for indexed FCMLA.  */
 213   AARCH64_OPND_IMM_ROT3,        /* Immediate rotate operand for FCADD.  */
 214
 215   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 216   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 217
 218   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 219   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 220   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 221   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 222   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 223
 224   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 225   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 226   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 227   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 228   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 229                                    negative or unaligned and there is
 230                                    no writeback allowed.  This operand code
 231                                    is only used to support the programmer-
 232                                    friendly feature of using LDR/STR as the
 233                                    the mnemonic name for LDUR/STUR instructions
 234                                    wherever there is no ambiguity.  */
 235   AARCH64_OPND_ADDR_SIMM10,     /* Address of signed 10-bit immediate.  */
 236   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 237   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 238   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 239
 240   AARCH64_OPND_SYSREG,          /* System register operand.  */
 241   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 242   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 243   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 244   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 245   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 246   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 247   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 248   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 249   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 250
 251   AARCH64_OPND_SVE_ADDR_RI_S4x16,   /* SVE [<Xn|SP>, #<simm4>*16].  */
 252   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
 253   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
 254   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
 255   AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL].  */
 256   AARCH64_OPND_SVE_ADDR_RI_S6xVL,   /* SVE [<Xn|SP>, #<simm6>, MUL VL].  */
 257   AARCH64_OPND_SVE_ADDR_RI_S9xVL,   /* SVE [<Xn|SP>, #<simm9>, MUL VL].  */
 258   AARCH64_OPND_SVE_ADDR_RI_U6,      /* SVE [<Xn|SP>, #<uimm6>].  */
 259   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
 260   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
 261   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
 262   AARCH64_OPND_SVE_ADDR_RR,         /* SVE [<Xn|SP>, <Xm|XZR>].  */
 263   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
 264   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
 265   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
 266   AARCH64_OPND_SVE_ADDR_RX,         /* SVE [<Xn|SP>, <Xm>].  */
 267   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
 268   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
 269   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
 270   AARCH64_OPND_SVE_ADDR_RZ,         /* SVE [<Xn|SP>, Zm.D].  */
 271   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
 272   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
 273   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
 274   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 275                                        Bit 14 controls S/U choice.  */
 276   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 277                                        Bit 22 controls S/U choice.  */
 278   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 279                                        Bit 14 controls S/U choice.  */
 280   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 281                                        Bit 22 controls S/U choice.  */
 282   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 283                                        Bit 14 controls S/U choice.  */
 284   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 285                                        Bit 22 controls S/U choice.  */
 286   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 287                                        Bit 14 controls S/U choice.  */
 288   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 289                                        Bit 22 controls S/U choice.  */
 290   AARCH64_OPND_SVE_ADDR_ZI_U5,      /* SVE [Zn.<T>, #<uimm5>].  */
 291   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
 292   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
 293   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
 294   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
 295   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
 296   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
 297   AARCH64_OPND_SVE_AIMM,        /* SVE unsigned arithmetic immediate.  */
 298   AARCH64_OPND_SVE_ASIMM,       /* SVE signed arithmetic immediate.  */
 299   AARCH64_OPND_SVE_FPIMM8,      /* SVE 8-bit floating-point immediate.  */
 300   AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0.  */
 301   AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0.  */
 302   AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0.  */
 303   AARCH64_OPND_SVE_IMM_ROT1,    /* SVE 1-bit rotate operand (90 or 270).  */
 304   AARCH64_OPND_SVE_IMM_ROT2,    /* SVE 2-bit rotate operand (N*90).  */
 305   AARCH64_OPND_SVE_INV_LIMM,    /* SVE inverted logical immediate.  */
 306   AARCH64_OPND_SVE_LIMM,        /* SVE logical immediate.  */
 307   AARCH64_OPND_SVE_LIMM_MOV,    /* SVE logical immediate for MOV.  */
 308   AARCH64_OPND_SVE_PATTERN,     /* SVE vector pattern enumeration.  */
 309   AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor.  */
 310   AARCH64_OPND_SVE_PRFOP,       /* SVE prefetch operation.  */
 311   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 312   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 313   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 314   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 315   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 316   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 317   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 318   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 319   AARCH64_OPND_SVE_Rm,          /* Integer Rm or ZR, alt. SVE position.  */
 320   AARCH64_OPND_SVE_Rn_SP,       /* Integer Rn or SP, alt. SVE position.  */
 321   AARCH64_OPND_SVE_SHLIMM_PRED,   /* SVE shift left amount (predicated).  */
 322   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
 323   AARCH64_OPND_SVE_SHRIMM_PRED,   /* SVE shift right amount (predicated).  */
 324   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
 325   AARCH64_OPND_SVE_SIMM5,       /* SVE signed 5-bit immediate.  */
 326   AARCH64_OPND_SVE_SIMM5B,      /* SVE secondary signed 5-bit immediate.  */
 327   AARCH64_OPND_SVE_SIMM6,       /* SVE signed 6-bit immediate.  */
 328   AARCH64_OPND_SVE_SIMM8,       /* SVE signed 8-bit immediate.  */
 329   AARCH64_OPND_SVE_UIMM3,       /* SVE unsigned 3-bit immediate.  */
 330   AARCH64_OPND_SVE_UIMM7,       /* SVE unsigned 7-bit immediate.  */
 331   AARCH64_OPND_SVE_UIMM8,       /* SVE unsigned 8-bit immediate.  */
 332   AARCH64_OPND_SVE_UIMM8_53,    /* SVE split unsigned 8-bit immediate.  */
 333   AARCH64_OPND_SVE_VZn,         /* Scalar SIMD&FP register in Zn field.  */
 334   AARCH64_OPND_SVE_Vd,          /* Scalar SIMD&FP register in Vd.  */
 335   AARCH64_OPND_SVE_Vm,          /* Scalar SIMD&FP register in Vm.  */
 336   AARCH64_OPND_SVE_Vn,          /* Scalar SIMD&FP register in Vn.  */
 337   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 338   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 339   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 340   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 341   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 342   AARCH64_OPND_SVE_Zm3_INDEX,   /* z0-z7[0-3] in Zm, bits [20,16].  */
 343   AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22.  */
 344   AARCH64_OPND_SVE_Zm4_INDEX,   /* z0-z15[0-1] in Zm, bits [20,16].  */
 345   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 346   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 347   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 348   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 349   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 350 };
 351
 352 /* Qualifier constrains an operand.  It either specifies a variant of an
 353    operand type or limits values available to an operand type.
 354
 355    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 356
 357 enum aarch64_opnd_qualifier
 358 {
 359   /* Indicating no further qualification on an operand.  */
 360   AARCH64_OPND_QLF_NIL,
 361
 362   /* Qualifying an operand which is a general purpose (integer) register;
 363      indicating the operand data size or a specific register.  */
 364   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 365   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 366   AARCH64_OPND_QLF_WSP, /* WSP.  */
 367   AARCH64_OPND_QLF_SP,  /* SP.  */
 368
 369   /* Qualifying an operand which is a floating-point register, a SIMD
 370      vector element or a SIMD vector element list; indicating operand data
 371      size or the size of each SIMD vector element in the case of a SIMD
 372      vector element list.
 373      These qualifiers are also used to qualify an address operand to
 374      indicate the size of data element a load/store instruction is
 375      accessing.
 376      They are also used for the immediate shift operand in e.g. SSHR.  Such
 377      a use is only for the ease of operand encoding/decoding and qualifier
 378      sequence matching; such a use should not be applied widely; use the value
 379      constraint qualifiers for immediate operands wherever possible.  */
 380   AARCH64_OPND_QLF_S_B,
 381   AARCH64_OPND_QLF_S_H,
 382   AARCH64_OPND_QLF_S_S,
 383   AARCH64_OPND_QLF_S_D,
 384   AARCH64_OPND_QLF_S_Q,
 385
 386   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 387      register list; indicating register shape.
 388      They are also used for the immediate shift operand in e.g. SSHR.  Such
 389      a use is only for the ease of operand encoding/decoding and qualifier
 390      sequence matching; such a use should not be applied widely; use the value
 391      constraint qualifiers for immediate operands wherever possible.  */
 392   AARCH64_OPND_QLF_V_8B,
 393   AARCH64_OPND_QLF_V_16B,
 394   AARCH64_OPND_QLF_V_2H,
 395   AARCH64_OPND_QLF_V_4H,
 396   AARCH64_OPND_QLF_V_8H,
 397   AARCH64_OPND_QLF_V_2S,
 398   AARCH64_OPND_QLF_V_4S,
 399   AARCH64_OPND_QLF_V_1D,
 400   AARCH64_OPND_QLF_V_2D,
 401   AARCH64_OPND_QLF_V_1Q,
 402
 403   AARCH64_OPND_QLF_P_Z,
 404   AARCH64_OPND_QLF_P_M,
 405
 406   /* Constraint on value.  */
 407   AARCH64_OPND_QLF_CR,          /* CRn, CRm. */
 408   AARCH64_OPND_QLF_imm_0_7,
 409   AARCH64_OPND_QLF_imm_0_15,
 410   AARCH64_OPND_QLF_imm_0_31,
 411   AARCH64_OPND_QLF_imm_0_63,
 412   AARCH64_OPND_QLF_imm_1_32,
 413   AARCH64_OPND_QLF_imm_1_64,
 414
 415   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 416      or shift-ones.  */
 417   AARCH64_OPND_QLF_LSL,
 418   AARCH64_OPND_QLF_MSL,
 419
 420   /* Special qualifier helping retrieve qualifier information during the
 421      decoding time (currently not in use).  */
 422   AARCH64_OPND_QLF_RETRIEVE,
 423 };
 424 \f
 425 /* Instruction class.  */
 426
 427 enum aarch64_insn_class
 428 {
 429   addsub_carry,
 430   addsub_ext,
 431   addsub_imm,
 432   addsub_shift,
 433   asimdall,
 434   asimddiff,
 435   asimdelem,
 436   asimdext,
 437   asimdimm,
 438   asimdins,
 439   asimdmisc,
 440   asimdperm,
 441   asimdsame,
 442   asimdshf,
 443   asimdtbl,
 444   asisddiff,
 445   asisdelem,
 446   asisdlse,
 447   asisdlsep,
 448   asisdlso,
 449   asisdlsop,
 450   asisdmisc,
 451   asisdone,
 452   asisdpair,
 453   asisdsame,
 454   asisdshf,
 455   bitfield,
 456   branch_imm,
 457   branch_reg,
 458   compbranch,
 459   condbranch,
 460   condcmp_imm,
 461   condcmp_reg,
 462   condsel,
 463   cryptoaes,
 464   cryptosha2,
 465   cryptosha3,
 466   dp_1src,
 467   dp_2src,
 468   dp_3src,
 469   exception,
 470   extract,
 471   float2fix,
 472   float2int,
 473   floatccmp,
 474   floatcmp,
 475   floatdp1,
 476   floatdp2,
 477   floatdp3,
 478   floatimm,
 479   floatsel,
 480   ldst_immpost,
 481   ldst_immpre,
 482   ldst_imm9,    /* immpost or immpre */
 483   ldst_imm10,   /* LDRAA/LDRAB */
 484   ldst_pos,
 485   ldst_regoff,
 486   ldst_unpriv,
 487   ldst_unscaled,
 488   ldstexcl,
 489   ldstnapair_offs,
 490   ldstpair_off,
 491   ldstpair_indexed,
 492   loadlit,
 493   log_imm,
 494   log_shift,
 495   lse_atomic,
 496   movewide,
 497   pcreladdr,
 498   ic_system,
 499   sve_cpy,
 500   sve_index,
 501   sve_limm,
 502   sve_misc,
 503   sve_movprfx,
 504   sve_pred_zm,
 505   sve_shift_pred,
 506   sve_shift_unpred,
 507   sve_size_bhs,
 508   sve_size_bhsd,
 509   sve_size_hsd,
 510   sve_size_sd,
 511   testbranch,
 512   dotproduct,
 513 };
 514
 515 /* Opcode enumerators.  */
 516
 517 enum aarch64_op
 518 {
 519   OP_NIL,
 520   OP_STRB_POS,
 521   OP_LDRB_POS,
 522   OP_LDRSB_POS,
 523   OP_STRH_POS,
 524   OP_LDRH_POS,
 525   OP_LDRSH_POS,
 526   OP_STR_POS,
 527   OP_LDR_POS,
 528   OP_STRF_POS,
 529   OP_LDRF_POS,
 530   OP_LDRSW_POS,
 531   OP_PRFM_POS,
 532
 533   OP_STURB,
 534   OP_LDURB,
 535   OP_LDURSB,
 536   OP_STURH,
 537   OP_LDURH,
 538   OP_LDURSH,
 539   OP_STUR,
 540   OP_LDUR,
 541   OP_STURV,
 542   OP_LDURV,
 543   OP_LDURSW,
 544   OP_PRFUM,
 545
 546   OP_LDR_LIT,
 547   OP_LDRV_LIT,
 548   OP_LDRSW_LIT,
 549   OP_PRFM_LIT,
 550
 551   OP_ADD,
 552   OP_B,
 553   OP_BL,
 554
 555   OP_MOVN,
 556   OP_MOVZ,
 557   OP_MOVK,
 558
 559   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 560   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 561   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 562
 563   OP_MOV_V,             /* MOV alias for moving vector register.  */
 564
 565   OP_ASR_IMM,
 566   OP_LSR_IMM,
 567   OP_LSL_IMM,
 568
 569   OP_BIC,
 570
 571   OP_UBFX,
 572   OP_BFXIL,
 573   OP_SBFX,
 574   OP_SBFIZ,
 575   OP_BFI,
 576   OP_BFC,               /* ARMv8.2.  */
 577   OP_UBFIZ,
 578   OP_UXTB,
 579   OP_UXTH,
 580   OP_UXTW,
 581
 582   OP_CINC,
 583   OP_CINV,
 584   OP_CNEG,
 585   OP_CSET,
 586   OP_CSETM,
 587
 588   OP_FCVT,
 589   OP_FCVTN,
 590   OP_FCVTN2,
 591   OP_FCVTL,
 592   OP_FCVTL2,
 593   OP_FCVTXN_S,          /* Scalar version.  */
 594
 595   OP_ROR_IMM,
 596
 597   OP_SXTL,
 598   OP_SXTL2,
 599   OP_UXTL,
 600   OP_UXTL2,
 601
 602   OP_MOV_P_P,
 603   OP_MOV_Z_P_Z,
 604   OP_MOV_Z_V,
 605   OP_MOV_Z_Z,
 606   OP_MOV_Z_Zi,
 607   OP_MOVM_P_P_P,
 608   OP_MOVS_P_P,
 609   OP_MOVZS_P_P_P,
 610   OP_MOVZ_P_P_P,
 611   OP_NOTS_P_P_P_Z,
 612   OP_NOT_P_P_P_Z,
 613
 614   OP_FCMLA_ELEM,        /* ARMv8.3, indexed element version.  */
 615
 616   OP_TOTAL_NUM,         /* Pseudo.  */
 617 };
 618
 619 /* Maximum number of operands an instruction can have.  */
 620 #define AARCH64_MAX_OPND_NUM 6
 621 /* Maximum number of qualifier sequences an instruction can have.  */
 622 #define AARCH64_MAX_QLF_SEQ_NUM 10
 623 /* Operand qualifier typedef; optimized for the size.  */
 624 typedef unsigned char aarch64_opnd_qualifier_t;
 625 /* Operand qualifier sequence typedef.  */
 626 typedef aarch64_opnd_qualifier_t        \
 627           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 628
 629 /* FIXME: improve the efficiency.  */
 630 static inline bfd_boolean
 631 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 632 {
 633   int i;
 634   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 635     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 636       return FALSE;
 637   return TRUE;
 638 }
 639
 640 /* This structure holds information for a particular opcode.  */
 641
 642 struct aarch64_opcode
 643 {
 644   /* The name of the mnemonic.  */
 645   const char *name;
 646
 647   /* The opcode itself.  Those bits which will be filled in with
 648      operands are zeroes.  */
 649   aarch64_insn opcode;
 650
 651   /* The opcode mask.  This is used by the disassembler.  This is a
 652      mask containing ones indicating those bits which must match the
 653      opcode field, and zeroes indicating those bits which need not
 654      match (and are presumably filled in by operands).  */
 655   aarch64_insn mask;
 656
 657   /* Instruction class.  */
 658   enum aarch64_insn_class iclass;
 659
 660   /* Enumerator identifier.  */
 661   enum aarch64_op op;
 662
 663   /* Which architecture variant provides this instruction.  */
 664   const aarch64_feature_set *avariant;
 665
 666   /* An array of operand codes.  Each code is an index into the
 667      operand table.  They appear in the order which the operands must
 668      appear in assembly code, and are terminated by a zero.  */
 669   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 670
 671   /* A list of operand qualifier code sequence.  Each operand qualifier
 672      code qualifies the corresponding operand code.  Each operand
 673      qualifier sequence specifies a valid opcode variant and related
 674      constraint on operands.  */
 675   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 676
 677   /* Flags providing information about this instruction */
 678   uint32_t flags;
 679
 680   /* If nonzero, this operand and operand 0 are both registers and
 681      are required to have the same register number.  */
 682   unsigned char tied_operand;
 683
 684   /* If non-NULL, a function to verify that a given instruction is valid.  */
 685   bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
 686 };
 687
 688 typedef struct aarch64_opcode aarch64_opcode;
 689
 690 /* Table describing all the AArch64 opcodes.  */
 691 extern aarch64_opcode aarch64_opcode_table[];
 692
 693 /* Opcode flags.  */
 694 #define F_ALIAS (1 << 0)
 695 #define F_HAS_ALIAS (1 << 1)
 696 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 697    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 698 #define F_P1 (1 << 2)
 699 #define F_P2 (2 << 2)
 700 #define F_P3 (3 << 2)
 701 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 702 #define F_COND (1 << 4)
 703 /* Instruction has the field of 'sf'.  */
 704 #define F_SF (1 << 5)
 705 /* Instruction has the field of 'size:Q'.  */
 706 #define F_SIZEQ (1 << 6)
 707 /* Floating-point instruction has the field of 'type'.  */
 708 #define F_FPTYPE (1 << 7)
 709 /* AdvSIMD scalar instruction has the field of 'size'.  */
 710 #define F_SSIZE (1 << 8)
 711 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 712 #define F_T (1 << 9)
 713 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 714 #define F_GPRSIZE_IN_Q (1 << 10)
 715 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 716 #define F_LDS_SIZE (1 << 11)
 717 /* Optional operand; assume maximum of 1 operand can be optional.  */
 718 #define F_OPD0_OPT (1 << 12)
 719 #define F_OPD1_OPT (2 << 12)
 720 #define F_OPD2_OPT (3 << 12)
 721 #define F_OPD3_OPT (4 << 12)
 722 #define F_OPD4_OPT (5 << 12)
 723 /* Default value for the optional operand when omitted from the assembly.  */
 724 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 725 /* Instruction that is an alias of another instruction needs to be
 726    encoded/decoded by converting it to/from the real form, followed by
 727    the encoding/decoding according to the rules of the real opcode.
 728    This compares to the direct coding using the alias's information.
 729    N.B. this flag requires F_ALIAS to be used together.  */
 730 #define F_CONV (1 << 20)
 731 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 732    friendly pseudo instruction available only in the assembly code (thus will
 733    not show up in the disassembly).  */
 734 #define F_PSEUDO (1 << 21)
 735 /* Instruction has miscellaneous encoding/decoding rules.  */
 736 #define F_MISC (1 << 22)
 737 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 738 #define F_N (1 << 23)
 739 /* Opcode dependent field.  */
 740 #define F_OD(X) (((X) & 0x7) << 24)
 741 /* Instruction has the field of 'sz'.  */
 742 #define F_LSE_SZ (1 << 27)
 743 /* Require an exact qualifier match, even for NIL qualifiers.  */
 744 #define F_STRICT (1ULL << 28)
 745 /* Next bit is 29.  */
 746
 747 static inline bfd_boolean
 748 alias_opcode_p (const aarch64_opcode *opcode)
 749 {
 750   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 751 }
 752
 753 static inline bfd_boolean
 754 opcode_has_alias (const aarch64_opcode *opcode)
 755 {
 756   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 757 }
 758
 759 /* Priority for disassembling preference.  */
 760 static inline int
 761 opcode_priority (const aarch64_opcode *opcode)
 762 {
 763   return (opcode->flags >> 2) & 0x3;
 764 }
 765
 766 static inline bfd_boolean
 767 pseudo_opcode_p (const aarch64_opcode *opcode)
 768 {
 769   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 770 }
 771
 772 static inline bfd_boolean
 773 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 774 {
 775   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 776     ? TRUE : FALSE;
 777 }
 778
 779 static inline aarch64_insn
 780 get_optional_operand_default_value (const aarch64_opcode *opcode)
 781 {
 782   return (opcode->flags >> 15) & 0x1f;
 783 }
 784
 785 static inline unsigned int
 786 get_opcode_dependent_value (const aarch64_opcode *opcode)
 787 {
 788   return (opcode->flags >> 24) & 0x7;
 789 }
 790
 791 static inline bfd_boolean
 792 opcode_has_special_coder (const aarch64_opcode *opcode)
 793 {
 794   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 795           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 796     : FALSE;
 797 }
 798 \f
 799 struct aarch64_name_value_pair
 800 {
 801   const char *  name;
 802   aarch64_insn  value;
 803 };
 804
 805 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 806 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 807 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 808 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 809
 810 typedef struct
 811 {
 812   const char *  name;
 813   aarch64_insn  value;
 814   uint32_t      flags;
 815 } aarch64_sys_reg;
 816
 817 extern const aarch64_sys_reg aarch64_sys_regs [];
 818 extern const aarch64_sys_reg aarch64_pstatefields [];
 819 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 820 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 821                                                 const aarch64_sys_reg *);
 822 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 823                                                     const aarch64_sys_reg *);
 824
 825 typedef struct
 826 {
 827   const char *name;
 828   uint32_t value;
 829   uint32_t flags ;
 830 } aarch64_sys_ins_reg;
 831
 832 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 833 extern bfd_boolean
 834 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 835                                  const aarch64_sys_ins_reg *);
 836
 837 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 838 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 839 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 840 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 841
 842 /* Shift/extending operator kinds.
 843    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 844 enum aarch64_modifier_kind
 845 {
 846   AARCH64_MOD_NONE,
 847   AARCH64_MOD_MSL,
 848   AARCH64_MOD_ROR,
 849   AARCH64_MOD_ASR,
 850   AARCH64_MOD_LSR,
 851   AARCH64_MOD_LSL,
 852   AARCH64_MOD_UXTB,
 853   AARCH64_MOD_UXTH,
 854   AARCH64_MOD_UXTW,
 855   AARCH64_MOD_UXTX,
 856   AARCH64_MOD_SXTB,
 857   AARCH64_MOD_SXTH,
 858   AARCH64_MOD_SXTW,
 859   AARCH64_MOD_SXTX,
 860   AARCH64_MOD_MUL,
 861   AARCH64_MOD_MUL_VL,
 862 };
 863
 864 bfd_boolean
 865 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 866
 867 enum aarch64_modifier_kind
 868 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 869 /* Condition.  */
 870
 871 typedef struct
 872 {
 873   /* A list of names with the first one as the disassembly preference;
 874      terminated by NULL if fewer than 3.  */
 875   const char *names[4];
 876   aarch64_insn value;
 877 } aarch64_cond;
 878
 879 extern const aarch64_cond aarch64_conds[16];
 880
 881 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 882 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 883 \f
 884 /* Structure representing an operand.  */
 885
 886 struct aarch64_opnd_info
 887 {
 888   enum aarch64_opnd type;
 889   aarch64_opnd_qualifier_t qualifier;
 890   int idx;
 891
 892   union
 893     {
 894       struct
 895         {
 896           unsigned regno;
 897         } reg;
 898       struct
 899         {
 900           unsigned int regno;
 901           int64_t index;
 902         } reglane;
 903       /* e.g. LVn.  */
 904       struct
 905         {
 906           unsigned first_regno : 5;
 907           unsigned num_regs : 3;
 908           /* 1 if it is a list of reg element.  */
 909           unsigned has_index : 1;
 910           /* Lane index; valid only when has_index is 1.  */
 911           int64_t index;
 912         } reglist;
 913       /* e.g. immediate or pc relative address offset.  */
 914       struct
 915         {
 916           int64_t value;
 917           unsigned is_fp : 1;
 918         } imm;
 919       /* e.g. address in STR (register offset).  */
 920       struct
 921         {
 922           unsigned base_regno;
 923           struct
 924             {
 925               union
 926                 {
 927                   int imm;
 928                   unsigned regno;
 929                 };
 930               unsigned is_reg;
 931             } offset;
 932           unsigned pcrel : 1;           /* PC-relative.  */
 933           unsigned writeback : 1;
 934           unsigned preind : 1;          /* Pre-indexed.  */
 935           unsigned postind : 1;         /* Post-indexed.  */
 936         } addr;
 937       const aarch64_cond *cond;
 938       /* The encoding of the system register.  */
 939       aarch64_insn sysreg;
 940       /* The encoding of the PSTATE field.  */
 941       aarch64_insn pstatefield;
 942       const aarch64_sys_ins_reg *sysins_op;
 943       const struct aarch64_name_value_pair *barrier;
 944       const struct aarch64_name_value_pair *hint_option;
 945       const struct aarch64_name_value_pair *prfop;
 946     };
 947
 948   /* Operand shifter; in use when the operand is a register offset address,
 949      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
 950   struct
 951     {
 952       enum aarch64_modifier_kind kind;
 953       unsigned operator_present: 1;     /* Only valid during encoding.  */
 954       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
 955       unsigned amount_present: 1;
 956       int64_t amount;
 957     } shifter;
 958
 959   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
 960                            to be done on it.  In some (but not all) of these
 961                            cases, we need to tell libopcodes to skip the
 962                            constraint checking and the encoding for this
 963                            operand, so that the libopcodes can pick up the
 964                            right opcode before the operand is fixed-up.  This
 965                            flag should only be used during the
 966                            assembling/encoding.  */
 967   unsigned present:1;   /* Whether this operand is present in the assembly
 968                            line; not used during the disassembly.  */
 969 };
 970
 971 typedef struct aarch64_opnd_info aarch64_opnd_info;
 972
 973 /* Structure representing an instruction.
 974
 975    It is used during both the assembling and disassembling.  The assembler
 976    fills an aarch64_inst after a successful parsing and then passes it to the
 977    encoding routine to do the encoding.  During the disassembling, the
 978    disassembler calls the decoding routine to decode a binary instruction; on a
 979    successful return, such a structure will be filled with information of the
 980    instruction; then the disassembler uses the information to print out the
 981    instruction.  */
 982
 983 struct aarch64_inst
 984 {
 985   /* The value of the binary instruction.  */
 986   aarch64_insn value;
 987
 988   /* Corresponding opcode entry.  */
 989   const aarch64_opcode *opcode;
 990
 991   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
 992   const aarch64_cond *cond;
 993
 994   /* Operands information.  */
 995   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
 996 };
 997
 998 typedef struct aarch64_inst aarch64_inst;
 999 \f
1000 /* Diagnosis related declaration and interface.  */
1001
1002 /* Operand error kind enumerators.
1003
1004    AARCH64_OPDE_RECOVERABLE
1005      Less severe error found during the parsing, very possibly because that
1006      GAS has picked up a wrong instruction template for the parsing.
1007
1008    AARCH64_OPDE_SYNTAX_ERROR
1009      General syntax error; it can be either a user error, or simply because
1010      that GAS is trying a wrong instruction template.
1011
1012    AARCH64_OPDE_FATAL_SYNTAX_ERROR
1013      Definitely a user syntax error.
1014
1015    AARCH64_OPDE_INVALID_VARIANT
1016      No syntax error, but the operands are not a valid combination, e.g.
1017      FMOV D0,S0
1018
1019    AARCH64_OPDE_UNTIED_OPERAND
1020      The asm failed to use the same register for a destination operand
1021      and a tied source operand.
1022
1023    AARCH64_OPDE_OUT_OF_RANGE
1024      Error about some immediate value out of a valid range.
1025
1026    AARCH64_OPDE_UNALIGNED
1027      Error about some immediate value not properly aligned (i.e. not being a
1028      multiple times of a certain value).
1029
1030    AARCH64_OPDE_REG_LIST
1031      Error about the register list operand having unexpected number of
1032      registers.
1033
1034    AARCH64_OPDE_OTHER_ERROR
1035      Error of the highest severity and used for any severe issue that does not
1036      fall into any of the above categories.
1037
1038    The enumerators are only interesting to GAS.  They are declared here (in
1039    libopcodes) because that some errors are detected (and then notified to GAS)
1040    by libopcodes (rather than by GAS solely).
1041
1042    The first three errors are only deteced by GAS while the
1043    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1044    only libopcodes has the information about the valid variants of each
1045    instruction.
1046
1047    The enumerators have an increasing severity.  This is helpful when there are
1048    multiple instruction templates available for a given mnemonic name (e.g.
1049    FMOV); this mechanism will help choose the most suitable template from which
1050    the generated diagnostics can most closely describe the issues, if any.  */
1051
1052 enum aarch64_operand_error_kind
1053 {
1054   AARCH64_OPDE_NIL,
1055   AARCH64_OPDE_RECOVERABLE,
1056   AARCH64_OPDE_SYNTAX_ERROR,
1057   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1058   AARCH64_OPDE_INVALID_VARIANT,
1059   AARCH64_OPDE_UNTIED_OPERAND,
1060   AARCH64_OPDE_OUT_OF_RANGE,
1061   AARCH64_OPDE_UNALIGNED,
1062   AARCH64_OPDE_REG_LIST,
1063   AARCH64_OPDE_OTHER_ERROR
1064 };
1065
1066 /* N.B. GAS assumes that this structure work well with shallow copy.  */
1067 struct aarch64_operand_error
1068 {
1069   enum aarch64_operand_error_kind kind;
1070   int index;
1071   const char *error;
1072   int data[3];  /* Some data for extra information.  */
1073 };
1074
1075 typedef struct aarch64_operand_error aarch64_operand_error;
1076
1077 /* Encoding entrypoint.  */
1078
1079 extern int
1080 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1081                        aarch64_insn *, aarch64_opnd_qualifier_t *,
1082                        aarch64_operand_error *);
1083
1084 extern const aarch64_opcode *
1085 aarch64_replace_opcode (struct aarch64_inst *,
1086                         const aarch64_opcode *);
1087
1088 /* Given the opcode enumerator OP, return the pointer to the corresponding
1089    opcode entry.  */
1090
1091 extern const aarch64_opcode *
1092 aarch64_get_opcode (enum aarch64_op);
1093
1094 /* Generate the string representation of an operand.  */
1095 extern void
1096 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1097                        const aarch64_opnd_info *, int, int *, bfd_vma *);
1098
1099 /* Miscellaneous interface.  */
1100
1101 extern int
1102 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1103
1104 extern aarch64_opnd_qualifier_t
1105 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1106                                 const aarch64_opnd_qualifier_t, int);
1107
1108 extern int
1109 aarch64_num_of_operands (const aarch64_opcode *);
1110
1111 extern int
1112 aarch64_stack_pointer_p (const aarch64_opnd_info *);
1113
1114 extern int
1115 aarch64_zero_register_p (const aarch64_opnd_info *);
1116
1117 extern int
1118 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
1119
1120 /* Given an operand qualifier, return the expected data element size
1121    of a qualified operand.  */
1122 extern unsigned char
1123 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1124
1125 extern enum aarch64_operand_class
1126 aarch64_get_operand_class (enum aarch64_opnd);
1127
1128 extern const char *
1129 aarch64_get_operand_name (enum aarch64_opnd);
1130
1131 extern const char *
1132 aarch64_get_operand_desc (enum aarch64_opnd);
1133
1134 extern bfd_boolean
1135 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1136
1137 #ifdef DEBUG_AARCH64
1138 extern int debug_dump;
1139
1140 extern void
1141 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1142
1143 #define DEBUG_TRACE(M, ...)                                     \
1144   {                                                             \
1145     if (debug_dump)                                             \
1146       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1147   }
1148
1149 #define DEBUG_TRACE_IF(C, M, ...)                               \
1150   {                                                             \
1151     if (debug_dump && (C))                                      \
1152       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1153   }
1154 #else  /* !DEBUG_AARCH64 */
1155 #define DEBUG_TRACE(M, ...) ;
1156 #define DEBUG_TRACE_IF(C, M, ...) ;
1157 #endif /* DEBUG_AARCH64 */
1158
1159 extern const char *const aarch64_sve_pattern_array[32];
1160 extern const char *const aarch64_sve_prfop_array[16];
1161
1162 #ifdef __cplusplus
1163 }
1164 #endif
1165
1166 #endif /* OPCODE_AARCH64_H */