include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2019 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_SHA2    0x200000000ULL  /* SHA2 instructions.  */
  41 #define AARCH64_FEATURE_AES     0x800000000ULL  /* AES instructions.  */
  42 #define AARCH64_FEATURE_V8_4    0x000000800ULL  /* ARMv8.4 processors.  */
  43 #define AARCH64_FEATURE_SM4     0x100000000ULL  /* SM3 & SM4 instructions.  */
  44 #define AARCH64_FEATURE_SHA3    0x400000000ULL  /* SHA3 instructions.  */
  45 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  46 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  47 #define AARCH64_FEATURE_V8_3    0x00000040      /* ARMv8.3 processors.  */
  48 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  49 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  50 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  51 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  52 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  53 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  54 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  55 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  56 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  57 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  58 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  59 #define AARCH64_FEATURE_PROFILE 0x08000000      /* Statistical Profiling.  */
  60 #define AARCH64_FEATURE_SVE     0x10000000      /* SVE instructions.  */
  61 #define AARCH64_FEATURE_RCPC    0x20000000      /* RCPC instructions.  */
  62 #define AARCH64_FEATURE_COMPNUM 0x40000000      /* Complex # instructions.  */
  63 #define AARCH64_FEATURE_DOTPROD 0x080000000     /* Dot Product instructions.  */
  64 #define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins.  */
  65 #define AARCH64_FEATURE_V8_5    0x2000000000ULL /* ARMv8.5 processors.  */
  66 #define AARCH64_FEATURE_V8_6    0x00000002      /* ARMv8.6 processors.  */
  67 #define AARCH64_FEATURE_BFLOAT16        0x00000004      /* Bfloat16 insns.  */
  68
  69 /* Flag Manipulation insns.  */
  70 #define AARCH64_FEATURE_FLAGMANIP       0x4000000000ULL
  71 /* FRINT[32,64][Z,X] insns.  */
  72 #define AARCH64_FEATURE_FRINTTS         0x8000000000ULL
  73 /* SB instruction.  */
  74 #define AARCH64_FEATURE_SB              0x10000000000ULL
  75 /* Execution and Data Prediction Restriction instructions.  */
  76 #define AARCH64_FEATURE_PREDRES         0x20000000000ULL
  77 /* DC CVADP.  */
  78 #define AARCH64_FEATURE_CVADP           0x40000000000ULL
  79 /* Random Number instructions.  */
  80 #define AARCH64_FEATURE_RNG             0x80000000000ULL
  81 /* BTI instructions.  */
  82 #define AARCH64_FEATURE_BTI             0x100000000000ULL
  83 /* SCXTNUM_ELx.  */
  84 #define AARCH64_FEATURE_SCXTNUM         0x200000000000ULL
  85 /* ID_PFR2 instructions.  */
  86 #define AARCH64_FEATURE_ID_PFR2         0x400000000000ULL
  87 /* SSBS mechanism enabled.  */
  88 #define AARCH64_FEATURE_SSBS            0x800000000000ULL
  89 /* Memory Tagging Extension.  */
  90 #define AARCH64_FEATURE_MEMTAG          0x1000000000000ULL
  91 /* Transactional Memory Extension.  */
  92 #define AARCH64_FEATURE_TME             0x2000000000000ULL
  93
  94 /* Matrix Multiply instructions */
  95 #define AARCH64_FEATURE_I8MM            0x10000000000000ULL
  96 #define AARCH64_FEATURE_F32MM           0x20000000000000ULL
  97 #define AARCH64_FEATURE_F64MM           0x40000000000000ULL
  98
  99 /* SVE2 instructions.  */
 100 #define AARCH64_FEATURE_SVE2            0x000000010
 101 #define AARCH64_FEATURE_SVE2_AES                0x000000080
 102 #define AARCH64_FEATURE_SVE2_BITPERM    0x000000100
 103 #define AARCH64_FEATURE_SVE2_SM4                0x000000200
 104 #define AARCH64_FEATURE_SVE2_SHA3       0x000000400
 105
 106 /* Architectures are the sum of the base and extensions.  */
 107 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
 108                                                  AARCH64_FEATURE_FP  \
 109                                                  | AARCH64_FEATURE_SIMD)
 110 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_ARCH_V8, \
 111                                                  AARCH64_FEATURE_CRC    \
 112                                                  | AARCH64_FEATURE_V8_1 \
 113                                                  | AARCH64_FEATURE_LSE  \
 114                                                  | AARCH64_FEATURE_PAN  \
 115                                                  | AARCH64_FEATURE_LOR  \
 116                                                  | AARCH64_FEATURE_RDMA)
 117 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_ARCH_V8_1,     \
 118                                                  AARCH64_FEATURE_V8_2   \
 119                                                  | AARCH64_FEATURE_RAS)
 120 #define AARCH64_ARCH_V8_3       AARCH64_FEATURE (AARCH64_ARCH_V8_2,     \
 121                                                  AARCH64_FEATURE_V8_3   \
 122                                                  | AARCH64_FEATURE_RCPC \
 123                                                  | AARCH64_FEATURE_COMPNUM)
 124 #define AARCH64_ARCH_V8_4       AARCH64_FEATURE (AARCH64_ARCH_V8_3,     \
 125                                                  AARCH64_FEATURE_V8_4   \
 126                                                  | AARCH64_FEATURE_DOTPROD \
 127                                                  | AARCH64_FEATURE_F16_FML)
 128 #define AARCH64_ARCH_V8_5       AARCH64_FEATURE (AARCH64_ARCH_V8_4,     \
 129                                                  AARCH64_FEATURE_V8_5   \
 130                                                  | AARCH64_FEATURE_FLAGMANIP \
 131                                                  | AARCH64_FEATURE_FRINTTS \
 132                                                  | AARCH64_FEATURE_SB   \
 133                                                  | AARCH64_FEATURE_PREDRES \
 134                                                  | AARCH64_FEATURE_CVADP \
 135                                                  | AARCH64_FEATURE_BTI  \
 136                                                  | AARCH64_FEATURE_SCXTNUM \
 137                                                  | AARCH64_FEATURE_ID_PFR2 \
 138                                                  | AARCH64_FEATURE_SSBS)
 139 #define AARCH64_ARCH_V8_6       AARCH64_FEATURE (AARCH64_ARCH_V8_5,     \
 140                                                  AARCH64_FEATURE_V8_6   \
 141                                                  | AARCH64_FEATURE_BFLOAT16 \
 142                                                  | AARCH64_FEATURE_I8MM)
 143
 144 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
 145 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
 146
 147 /* CPU-specific features.  */
 148 typedef unsigned long long aarch64_feature_set;
 149
 150 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
 151   ((~(CPU) & (FEAT)) == 0)
 152
 153 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
 154   (((CPU) & (FEAT)) != 0)
 155
 156 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
 157   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
 158
 159 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
 160   do                                            \
 161     {                                           \
 162       (TARG) = (F1) | (F2);                     \
 163     }                                           \
 164   while (0)
 165
 166 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 167   do                                            \
 168     {                                           \
 169       (TARG) = (F1) &~ (F2);                    \
 170     }                                           \
 171   while (0)
 172
 173 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 174
 175 enum aarch64_operand_class
 176 {
 177   AARCH64_OPND_CLASS_NIL,
 178   AARCH64_OPND_CLASS_INT_REG,
 179   AARCH64_OPND_CLASS_MODIFIED_REG,
 180   AARCH64_OPND_CLASS_FP_REG,
 181   AARCH64_OPND_CLASS_SIMD_REG,
 182   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 183   AARCH64_OPND_CLASS_SISD_REG,
 184   AARCH64_OPND_CLASS_SIMD_REGLIST,
 185   AARCH64_OPND_CLASS_SVE_REG,
 186   AARCH64_OPND_CLASS_PRED_REG,
 187   AARCH64_OPND_CLASS_ADDRESS,
 188   AARCH64_OPND_CLASS_IMMEDIATE,
 189   AARCH64_OPND_CLASS_SYSTEM,
 190   AARCH64_OPND_CLASS_COND,
 191 };
 192
 193 /* Operand code that helps both parsing and coding.
 194    Keep AARCH64_OPERANDS synced.  */
 195
 196 enum aarch64_opnd
 197 {
 198   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 199
 200   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 201   AARCH64_OPND_Rn,      /* Integer register as source.  */
 202   AARCH64_OPND_Rm,      /* Integer register as source.  */
 203   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 204   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 205   AARCH64_OPND_Rt_SP,   /* Integer Rt or SP used in STG instructions.  */
 206   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 207   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 208   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 209
 210   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 211   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 212   AARCH64_OPND_Rm_SP,   /* Integer Rm or SP.  */
 213   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 214   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 215   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 216
 217   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 218   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 219   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 220   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 221   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 222   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 223
 224   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 225   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 226   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 227
 228   AARCH64_OPND_Va,      /* AdvSIMD Vector Va.  */
 229   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 230   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 231   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 232   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 233   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 234   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 235   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 236   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 237   AARCH64_OPND_Em16,    /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
 238                            qualifier is S_H.  */
 239   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 240   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 241   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 242                            structure to all lanes.  */
 243   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 244
 245   AARCH64_OPND_CRn,     /* Co-processor register in CRn field.  */
 246   AARCH64_OPND_CRm,     /* Co-processor register in CRm field.  */
 247
 248   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 249   AARCH64_OPND_MASK,    /* AdvSIMD EXT index operand.  */
 250   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 251   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 252   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 253   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 254   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 255   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 256                            (no encoding).  */
 257   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 258   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 259   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 260   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 261   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 262   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 263   AARCH64_OPND_IMM,     /* Immediate.  */
 264   AARCH64_OPND_IMM_2,   /* Immediate.  */
 265   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 266   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 267   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 268   AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg.  */
 269   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 270   AARCH64_OPND_UIMM10,  /* Unsigned 10-bit immediate in addg/subg.  */
 271   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 272   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 273   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 274   AARCH64_OPND_SIMM5,   /* 5-bit signed immediate in the imm5 field.  */
 275   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 276                            each condition flag.  */
 277
 278   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 279   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 280   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 281   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 282   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 283   AARCH64_OPND_IMM_ROT1,        /* Immediate rotate operand for FCMLA.  */
 284   AARCH64_OPND_IMM_ROT2,        /* Immediate rotate operand for indexed FCMLA.  */
 285   AARCH64_OPND_IMM_ROT3,        /* Immediate rotate operand for FCADD.  */
 286
 287   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 288   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 289
 290   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 291   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 292   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 293   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 294   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 295
 296   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 297   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 298   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 299   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 300   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 301                                    negative or unaligned and there is
 302                                    no writeback allowed.  This operand code
 303                                    is only used to support the programmer-
 304                                    friendly feature of using LDR/STR as the
 305                                    the mnemonic name for LDUR/STUR instructions
 306                                    wherever there is no ambiguity.  */
 307   AARCH64_OPND_ADDR_SIMM10,     /* Address of signed 10-bit immediate.  */
 308   AARCH64_OPND_ADDR_SIMM11,     /* Address with a signed 11-bit (multiple of
 309                                    16) immediate.  */
 310   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 311   AARCH64_OPND_ADDR_SIMM13,     /* Address with a signed 13-bit (multiple of
 312                                    16) immediate.  */
 313   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 314   AARCH64_OPND_ADDR_OFFSET,     /* Address with an optional 9-bit immediate.  */
 315   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 316
 317   AARCH64_OPND_SYSREG,          /* System register operand.  */
 318   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 319   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 320   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 321   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 322   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 323   AARCH64_OPND_SYSREG_SR,       /* System register RCTX operand.  */
 324   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 325   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 326   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 327   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 328   AARCH64_OPND_BTI_TARGET,      /* BTI {<target>}.  */
 329
 330   AARCH64_OPND_SVE_ADDR_RI_S4x16,   /* SVE [<Xn|SP>, #<simm4>*16].  */
 331   AARCH64_OPND_SVE_ADDR_RI_S4x32,   /* SVE [<Xn|SP>, #<simm4>*32].  */
 332   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
 333   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
 334   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
 335   AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL].  */
 336   AARCH64_OPND_SVE_ADDR_RI_S6xVL,   /* SVE [<Xn|SP>, #<simm6>, MUL VL].  */
 337   AARCH64_OPND_SVE_ADDR_RI_S9xVL,   /* SVE [<Xn|SP>, #<simm9>, MUL VL].  */
 338   AARCH64_OPND_SVE_ADDR_RI_U6,      /* SVE [<Xn|SP>, #<uimm6>].  */
 339   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
 340   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
 341   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
 342   AARCH64_OPND_SVE_ADDR_R,          /* SVE [<Xn|SP>].  */
 343   AARCH64_OPND_SVE_ADDR_RR,         /* SVE [<Xn|SP>, <Xm|XZR>].  */
 344   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
 345   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
 346   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
 347   AARCH64_OPND_SVE_ADDR_RX,         /* SVE [<Xn|SP>, <Xm>].  */
 348   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
 349   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
 350   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
 351   AARCH64_OPND_SVE_ADDR_ZX,         /* SVE [Zn.<T>{, <Xm>}].  */
 352   AARCH64_OPND_SVE_ADDR_RZ,         /* SVE [<Xn|SP>, Zm.D].  */
 353   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
 354   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
 355   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
 356   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 357                                        Bit 14 controls S/U choice.  */
 358   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 359                                        Bit 22 controls S/U choice.  */
 360   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 361                                        Bit 14 controls S/U choice.  */
 362   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 363                                        Bit 22 controls S/U choice.  */
 364   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 365                                        Bit 14 controls S/U choice.  */
 366   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 367                                        Bit 22 controls S/U choice.  */
 368   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 369                                        Bit 14 controls S/U choice.  */
 370   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 371                                        Bit 22 controls S/U choice.  */
 372   AARCH64_OPND_SVE_ADDR_ZI_U5,      /* SVE [Zn.<T>, #<uimm5>].  */
 373   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
 374   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
 375   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
 376   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
 377   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
 378   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
 379   AARCH64_OPND_SVE_AIMM,        /* SVE unsigned arithmetic immediate.  */
 380   AARCH64_OPND_SVE_ASIMM,       /* SVE signed arithmetic immediate.  */
 381   AARCH64_OPND_SVE_FPIMM8,      /* SVE 8-bit floating-point immediate.  */
 382   AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0.  */
 383   AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0.  */
 384   AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0.  */
 385   AARCH64_OPND_SVE_IMM_ROT1,    /* SVE 1-bit rotate operand (90 or 270).  */
 386   AARCH64_OPND_SVE_IMM_ROT2,    /* SVE 2-bit rotate operand (N*90).  */
 387   AARCH64_OPND_SVE_IMM_ROT3,    /* SVE cadd 1-bit rotate (90 or 270).  */
 388   AARCH64_OPND_SVE_INV_LIMM,    /* SVE inverted logical immediate.  */
 389   AARCH64_OPND_SVE_LIMM,        /* SVE logical immediate.  */
 390   AARCH64_OPND_SVE_LIMM_MOV,    /* SVE logical immediate for MOV.  */
 391   AARCH64_OPND_SVE_PATTERN,     /* SVE vector pattern enumeration.  */
 392   AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor.  */
 393   AARCH64_OPND_SVE_PRFOP,       /* SVE prefetch operation.  */
 394   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 395   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 396   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 397   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 398   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 399   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 400   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 401   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 402   AARCH64_OPND_SVE_Rm,          /* Integer Rm or ZR, alt. SVE position.  */
 403   AARCH64_OPND_SVE_Rn_SP,       /* Integer Rn or SP, alt. SVE position.  */
 404   AARCH64_OPND_SVE_SHLIMM_PRED,   /* SVE shift left amount (predicated).  */
 405   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
 406   AARCH64_OPND_SVE_SHLIMM_UNPRED_22,    /* SVE 3 bit shift left unpred.  */
 407   AARCH64_OPND_SVE_SHRIMM_PRED,   /* SVE shift right amount (predicated).  */
 408   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
 409   AARCH64_OPND_SVE_SHRIMM_UNPRED_22,    /* SVE 3 bit shift right unpred.  */
 410   AARCH64_OPND_SVE_SIMM5,       /* SVE signed 5-bit immediate.  */
 411   AARCH64_OPND_SVE_SIMM5B,      /* SVE secondary signed 5-bit immediate.  */
 412   AARCH64_OPND_SVE_SIMM6,       /* SVE signed 6-bit immediate.  */
 413   AARCH64_OPND_SVE_SIMM8,       /* SVE signed 8-bit immediate.  */
 414   AARCH64_OPND_SVE_UIMM3,       /* SVE unsigned 3-bit immediate.  */
 415   AARCH64_OPND_SVE_UIMM7,       /* SVE unsigned 7-bit immediate.  */
 416   AARCH64_OPND_SVE_UIMM8,       /* SVE unsigned 8-bit immediate.  */
 417   AARCH64_OPND_SVE_UIMM8_53,    /* SVE split unsigned 8-bit immediate.  */
 418   AARCH64_OPND_SVE_VZn,         /* Scalar SIMD&FP register in Zn field.  */
 419   AARCH64_OPND_SVE_Vd,          /* Scalar SIMD&FP register in Vd.  */
 420   AARCH64_OPND_SVE_Vm,          /* Scalar SIMD&FP register in Vm.  */
 421   AARCH64_OPND_SVE_Vn,          /* Scalar SIMD&FP register in Vn.  */
 422   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 423   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 424   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 425   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 426   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 427   AARCH64_OPND_SVE_Zm3_INDEX,   /* z0-z7[0-3] in Zm, bits [20,16].  */
 428   AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22.  */
 429   AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11.  */
 430   AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11.  */
 431   AARCH64_OPND_SVE_Zm4_INDEX,   /* z0-z15[0-1] in Zm, bits [20,16].  */
 432   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 433   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 434   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 435   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 436   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 437   AARCH64_OPND_TME_UIMM16,      /* TME unsigned 16-bit immediate.  */
 438   AARCH64_OPND_SM3_IMM2,        /* SM3 encodes lane in bits [13, 14].  */
 439 };
 440
 441 /* Qualifier constrains an operand.  It either specifies a variant of an
 442    operand type or limits values available to an operand type.
 443
 444    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 445
 446 enum aarch64_opnd_qualifier
 447 {
 448   /* Indicating no further qualification on an operand.  */
 449   AARCH64_OPND_QLF_NIL,
 450
 451   /* Qualifying an operand which is a general purpose (integer) register;
 452      indicating the operand data size or a specific register.  */
 453   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 454   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 455   AARCH64_OPND_QLF_WSP, /* WSP.  */
 456   AARCH64_OPND_QLF_SP,  /* SP.  */
 457
 458   /* Qualifying an operand which is a floating-point register, a SIMD
 459      vector element or a SIMD vector element list; indicating operand data
 460      size or the size of each SIMD vector element in the case of a SIMD
 461      vector element list.
 462      These qualifiers are also used to qualify an address operand to
 463      indicate the size of data element a load/store instruction is
 464      accessing.
 465      They are also used for the immediate shift operand in e.g. SSHR.  Such
 466      a use is only for the ease of operand encoding/decoding and qualifier
 467      sequence matching; such a use should not be applied widely; use the value
 468      constraint qualifiers for immediate operands wherever possible.  */
 469   AARCH64_OPND_QLF_S_B,
 470   AARCH64_OPND_QLF_S_H,
 471   AARCH64_OPND_QLF_S_S,
 472   AARCH64_OPND_QLF_S_D,
 473   AARCH64_OPND_QLF_S_Q,
 474   /* These type qualifiers have a special meaning in that they mean 4 x 1 byte
 475      or 2 x 2 byte are selected by the instruction.  Other than that they have
 476      no difference with AARCH64_OPND_QLF_S_B in encoding.  They are here purely
 477      for syntactical reasons and is an exception from normal AArch64
 478      disassembly scheme.  */
 479   AARCH64_OPND_QLF_S_4B,
 480   AARCH64_OPND_QLF_S_2H,
 481
 482   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 483      register list; indicating register shape.
 484      They are also used for the immediate shift operand in e.g. SSHR.  Such
 485      a use is only for the ease of operand encoding/decoding and qualifier
 486      sequence matching; such a use should not be applied widely; use the value
 487      constraint qualifiers for immediate operands wherever possible.  */
 488   AARCH64_OPND_QLF_V_4B,
 489   AARCH64_OPND_QLF_V_8B,
 490   AARCH64_OPND_QLF_V_16B,
 491   AARCH64_OPND_QLF_V_2H,
 492   AARCH64_OPND_QLF_V_4H,
 493   AARCH64_OPND_QLF_V_8H,
 494   AARCH64_OPND_QLF_V_2S,
 495   AARCH64_OPND_QLF_V_4S,
 496   AARCH64_OPND_QLF_V_1D,
 497   AARCH64_OPND_QLF_V_2D,
 498   AARCH64_OPND_QLF_V_1Q,
 499
 500   AARCH64_OPND_QLF_P_Z,
 501   AARCH64_OPND_QLF_P_M,
 502
 503   /* Used in scaled signed immediate that are scaled by a Tag granule
 504      like in stg, st2g, etc.   */
 505   AARCH64_OPND_QLF_imm_tag,
 506
 507   /* Constraint on value.  */
 508   AARCH64_OPND_QLF_CR,          /* CRn, CRm. */
 509   AARCH64_OPND_QLF_imm_0_7,
 510   AARCH64_OPND_QLF_imm_0_15,
 511   AARCH64_OPND_QLF_imm_0_31,
 512   AARCH64_OPND_QLF_imm_0_63,
 513   AARCH64_OPND_QLF_imm_1_32,
 514   AARCH64_OPND_QLF_imm_1_64,
 515
 516   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 517      or shift-ones.  */
 518   AARCH64_OPND_QLF_LSL,
 519   AARCH64_OPND_QLF_MSL,
 520
 521   /* Special qualifier helping retrieve qualifier information during the
 522      decoding time (currently not in use).  */
 523   AARCH64_OPND_QLF_RETRIEVE,
 524 };
 525 \f
 526 /* Instruction class.  */
 527
 528 enum aarch64_insn_class
 529 {
 530   aarch64_misc,
 531   addsub_carry,
 532   addsub_ext,
 533   addsub_imm,
 534   addsub_shift,
 535   asimdall,
 536   asimddiff,
 537   asimdelem,
 538   asimdext,
 539   asimdimm,
 540   asimdins,
 541   asimdmisc,
 542   asimdperm,
 543   asimdsame,
 544   asimdshf,
 545   asimdtbl,
 546   asisddiff,
 547   asisdelem,
 548   asisdlse,
 549   asisdlsep,
 550   asisdlso,
 551   asisdlsop,
 552   asisdmisc,
 553   asisdone,
 554   asisdpair,
 555   asisdsame,
 556   asisdshf,
 557   bitfield,
 558   branch_imm,
 559   branch_reg,
 560   compbranch,
 561   condbranch,
 562   condcmp_imm,
 563   condcmp_reg,
 564   condsel,
 565   cryptoaes,
 566   cryptosha2,
 567   cryptosha3,
 568   dp_1src,
 569   dp_2src,
 570   dp_3src,
 571   exception,
 572   extract,
 573   float2fix,
 574   float2int,
 575   floatccmp,
 576   floatcmp,
 577   floatdp1,
 578   floatdp2,
 579   floatdp3,
 580   floatimm,
 581   floatsel,
 582   ldst_immpost,
 583   ldst_immpre,
 584   ldst_imm9,    /* immpost or immpre */
 585   ldst_imm10,   /* LDRAA/LDRAB */
 586   ldst_pos,
 587   ldst_regoff,
 588   ldst_unpriv,
 589   ldst_unscaled,
 590   ldstexcl,
 591   ldstnapair_offs,
 592   ldstpair_off,
 593   ldstpair_indexed,
 594   loadlit,
 595   log_imm,
 596   log_shift,
 597   lse_atomic,
 598   movewide,
 599   pcreladdr,
 600   ic_system,
 601   sve_cpy,
 602   sve_index,
 603   sve_limm,
 604   sve_misc,
 605   sve_movprfx,
 606   sve_pred_zm,
 607   sve_shift_pred,
 608   sve_shift_unpred,
 609   sve_size_bhs,
 610   sve_size_bhsd,
 611   sve_size_hsd,
 612   sve_size_hsd2,
 613   sve_size_sd,
 614   sve_size_bh,
 615   sve_size_sd2,
 616   sve_size_13,
 617   sve_shift_tsz_hsd,
 618   sve_shift_tsz_bhsd,
 619   sve_size_tsz_bhs,
 620   testbranch,
 621   cryptosm3,
 622   cryptosm4,
 623   dotproduct,
 624   bfloat16,
 625 };
 626
 627 /* Opcode enumerators.  */
 628
 629 enum aarch64_op
 630 {
 631   OP_NIL,
 632   OP_STRB_POS,
 633   OP_LDRB_POS,
 634   OP_LDRSB_POS,
 635   OP_STRH_POS,
 636   OP_LDRH_POS,
 637   OP_LDRSH_POS,
 638   OP_STR_POS,
 639   OP_LDR_POS,
 640   OP_STRF_POS,
 641   OP_LDRF_POS,
 642   OP_LDRSW_POS,
 643   OP_PRFM_POS,
 644
 645   OP_STURB,
 646   OP_LDURB,
 647   OP_LDURSB,
 648   OP_STURH,
 649   OP_LDURH,
 650   OP_LDURSH,
 651   OP_STUR,
 652   OP_LDUR,
 653   OP_STURV,
 654   OP_LDURV,
 655   OP_LDURSW,
 656   OP_PRFUM,
 657
 658   OP_LDR_LIT,
 659   OP_LDRV_LIT,
 660   OP_LDRSW_LIT,
 661   OP_PRFM_LIT,
 662
 663   OP_ADD,
 664   OP_B,
 665   OP_BL,
 666
 667   OP_MOVN,
 668   OP_MOVZ,
 669   OP_MOVK,
 670
 671   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 672   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 673   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 674
 675   OP_MOV_V,             /* MOV alias for moving vector register.  */
 676
 677   OP_ASR_IMM,
 678   OP_LSR_IMM,
 679   OP_LSL_IMM,
 680
 681   OP_BIC,
 682
 683   OP_UBFX,
 684   OP_BFXIL,
 685   OP_SBFX,
 686   OP_SBFIZ,
 687   OP_BFI,
 688   OP_BFC,               /* ARMv8.2.  */
 689   OP_UBFIZ,
 690   OP_UXTB,
 691   OP_UXTH,
 692   OP_UXTW,
 693
 694   OP_CINC,
 695   OP_CINV,
 696   OP_CNEG,
 697   OP_CSET,
 698   OP_CSETM,
 699
 700   OP_FCVT,
 701   OP_FCVTN,
 702   OP_FCVTN2,
 703   OP_FCVTL,
 704   OP_FCVTL2,
 705   OP_FCVTXN_S,          /* Scalar version.  */
 706
 707   OP_ROR_IMM,
 708
 709   OP_SXTL,
 710   OP_SXTL2,
 711   OP_UXTL,
 712   OP_UXTL2,
 713
 714   OP_MOV_P_P,
 715   OP_MOV_Z_P_Z,
 716   OP_MOV_Z_V,
 717   OP_MOV_Z_Z,
 718   OP_MOV_Z_Zi,
 719   OP_MOVM_P_P_P,
 720   OP_MOVS_P_P,
 721   OP_MOVZS_P_P_P,
 722   OP_MOVZ_P_P_P,
 723   OP_NOTS_P_P_P_Z,
 724   OP_NOT_P_P_P_Z,
 725
 726   OP_FCMLA_ELEM,        /* ARMv8.3, indexed element version.  */
 727
 728   OP_TOTAL_NUM,         /* Pseudo.  */
 729 };
 730
 731 /* Error types.  */
 732 enum err_type
 733 {
 734   ERR_OK,
 735   ERR_UND,
 736   ERR_UNP,
 737   ERR_NYI,
 738   ERR_VFI,
 739   ERR_NR_ENTRIES
 740 };
 741
 742 /* Maximum number of operands an instruction can have.  */
 743 #define AARCH64_MAX_OPND_NUM 6
 744 /* Maximum number of qualifier sequences an instruction can have.  */
 745 #define AARCH64_MAX_QLF_SEQ_NUM 10
 746 /* Operand qualifier typedef; optimized for the size.  */
 747 typedef unsigned char aarch64_opnd_qualifier_t;
 748 /* Operand qualifier sequence typedef.  */
 749 typedef aarch64_opnd_qualifier_t        \
 750           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 751
 752 /* FIXME: improve the efficiency.  */
 753 static inline bfd_boolean
 754 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 755 {
 756   int i;
 757   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 758     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 759       return FALSE;
 760   return TRUE;
 761 }
 762
 763 /*  Forward declare error reporting type.  */
 764 typedef struct aarch64_operand_error aarch64_operand_error;
 765 /* Forward declare instruction sequence type.  */
 766 typedef struct aarch64_instr_sequence aarch64_instr_sequence;
 767 /* Forward declare instruction definition.  */
 768 typedef struct aarch64_inst aarch64_inst;
 769
 770 /* This structure holds information for a particular opcode.  */
 771
 772 struct aarch64_opcode
 773 {
 774   /* The name of the mnemonic.  */
 775   const char *name;
 776
 777   /* The opcode itself.  Those bits which will be filled in with
 778      operands are zeroes.  */
 779   aarch64_insn opcode;
 780
 781   /* The opcode mask.  This is used by the disassembler.  This is a
 782      mask containing ones indicating those bits which must match the
 783      opcode field, and zeroes indicating those bits which need not
 784      match (and are presumably filled in by operands).  */
 785   aarch64_insn mask;
 786
 787   /* Instruction class.  */
 788   enum aarch64_insn_class iclass;
 789
 790   /* Enumerator identifier.  */
 791   enum aarch64_op op;
 792
 793   /* Which architecture variant provides this instruction.  */
 794   const aarch64_feature_set *avariant;
 795
 796   /* An array of operand codes.  Each code is an index into the
 797      operand table.  They appear in the order which the operands must
 798      appear in assembly code, and are terminated by a zero.  */
 799   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 800
 801   /* A list of operand qualifier code sequence.  Each operand qualifier
 802      code qualifies the corresponding operand code.  Each operand
 803      qualifier sequence specifies a valid opcode variant and related
 804      constraint on operands.  */
 805   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 806
 807   /* Flags providing information about this instruction */
 808   uint64_t flags;
 809
 810   /* Extra constraints on the instruction that the verifier checks.  */
 811   uint32_t constraints;
 812
 813   /* If nonzero, this operand and operand 0 are both registers and
 814      are required to have the same register number.  */
 815   unsigned char tied_operand;
 816
 817   /* If non-NULL, a function to verify that a given instruction is valid.  */
 818   enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
 819                               bfd_vma, bfd_boolean, aarch64_operand_error *,
 820                               struct aarch64_instr_sequence *);
 821 };
 822
 823 typedef struct aarch64_opcode aarch64_opcode;
 824
 825 /* Table describing all the AArch64 opcodes.  */
 826 extern aarch64_opcode aarch64_opcode_table[];
 827
 828 /* Opcode flags.  */
 829 #define F_ALIAS (1 << 0)
 830 #define F_HAS_ALIAS (1 << 1)
 831 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 832    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 833 #define F_P1 (1 << 2)
 834 #define F_P2 (2 << 2)
 835 #define F_P3 (3 << 2)
 836 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 837 #define F_COND (1 << 4)
 838 /* Instruction has the field of 'sf'.  */
 839 #define F_SF (1 << 5)
 840 /* Instruction has the field of 'size:Q'.  */
 841 #define F_SIZEQ (1 << 6)
 842 /* Floating-point instruction has the field of 'type'.  */
 843 #define F_FPTYPE (1 << 7)
 844 /* AdvSIMD scalar instruction has the field of 'size'.  */
 845 #define F_SSIZE (1 << 8)
 846 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 847 #define F_T (1 << 9)
 848 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 849 #define F_GPRSIZE_IN_Q (1 << 10)
 850 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 851 #define F_LDS_SIZE (1 << 11)
 852 /* Optional operand; assume maximum of 1 operand can be optional.  */
 853 #define F_OPD0_OPT (1 << 12)
 854 #define F_OPD1_OPT (2 << 12)
 855 #define F_OPD2_OPT (3 << 12)
 856 #define F_OPD3_OPT (4 << 12)
 857 #define F_OPD4_OPT (5 << 12)
 858 /* Default value for the optional operand when omitted from the assembly.  */
 859 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 860 /* Instruction that is an alias of another instruction needs to be
 861    encoded/decoded by converting it to/from the real form, followed by
 862    the encoding/decoding according to the rules of the real opcode.
 863    This compares to the direct coding using the alias's information.
 864    N.B. this flag requires F_ALIAS to be used together.  */
 865 #define F_CONV (1 << 20)
 866 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 867    friendly pseudo instruction available only in the assembly code (thus will
 868    not show up in the disassembly).  */
 869 #define F_PSEUDO (1 << 21)
 870 /* Instruction has miscellaneous encoding/decoding rules.  */
 871 #define F_MISC (1 << 22)
 872 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 873 #define F_N (1 << 23)
 874 /* Opcode dependent field.  */
 875 #define F_OD(X) (((X) & 0x7) << 24)
 876 /* Instruction has the field of 'sz'.  */
 877 #define F_LSE_SZ (1 << 27)
 878 /* Require an exact qualifier match, even for NIL qualifiers.  */
 879 #define F_STRICT (1ULL << 28)
 880 /* This system instruction is used to read system registers.  */
 881 #define F_SYS_READ (1ULL << 29)
 882 /* This system instruction is used to write system registers.  */
 883 #define F_SYS_WRITE (1ULL << 30)
 884 /* This instruction has an extra constraint on it that imposes a requirement on
 885    subsequent instructions.  */
 886 #define F_SCAN (1ULL << 31)
 887 /* Next bit is 32.  */
 888
 889 /* Instruction constraints.  */
 890 /* This instruction has a predication constraint on the instruction at PC+4.  */
 891 #define C_SCAN_MOVPRFX (1U << 0)
 892 /* This instruction's operation width is determined by the operand with the
 893    largest element size.  */
 894 #define C_MAX_ELEM (1U << 1)
 895 /* Next bit is 2.  */
 896
 897 static inline bfd_boolean
 898 alias_opcode_p (const aarch64_opcode *opcode)
 899 {
 900   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 901 }
 902
 903 static inline bfd_boolean
 904 opcode_has_alias (const aarch64_opcode *opcode)
 905 {
 906   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 907 }
 908
 909 /* Priority for disassembling preference.  */
 910 static inline int
 911 opcode_priority (const aarch64_opcode *opcode)
 912 {
 913   return (opcode->flags >> 2) & 0x3;
 914 }
 915
 916 static inline bfd_boolean
 917 pseudo_opcode_p (const aarch64_opcode *opcode)
 918 {
 919   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 920 }
 921
 922 static inline bfd_boolean
 923 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 924 {
 925   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 926     ? TRUE : FALSE;
 927 }
 928
 929 static inline aarch64_insn
 930 get_optional_operand_default_value (const aarch64_opcode *opcode)
 931 {
 932   return (opcode->flags >> 15) & 0x1f;
 933 }
 934
 935 static inline unsigned int
 936 get_opcode_dependent_value (const aarch64_opcode *opcode)
 937 {
 938   return (opcode->flags >> 24) & 0x7;
 939 }
 940
 941 static inline bfd_boolean
 942 opcode_has_special_coder (const aarch64_opcode *opcode)
 943 {
 944   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 945           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 946     : FALSE;
 947 }
 948 \f
 949 struct aarch64_name_value_pair
 950 {
 951   const char *  name;
 952   aarch64_insn  value;
 953 };
 954
 955 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 956 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 957 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 958 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 959
 960 typedef struct
 961 {
 962   const char *  name;
 963   aarch64_insn  value;
 964   uint32_t      flags;
 965 } aarch64_sys_reg;
 966
 967 extern const aarch64_sys_reg aarch64_sys_regs [];
 968 extern const aarch64_sys_reg aarch64_pstatefields [];
 969 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 970 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 971                                                 const aarch64_sys_reg *);
 972 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 973                                                     const aarch64_sys_reg *);
 974
 975 typedef struct
 976 {
 977   const char *name;
 978   uint32_t value;
 979   uint32_t flags ;
 980 } aarch64_sys_ins_reg;
 981
 982 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 983 extern bfd_boolean
 984 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 985                                  const aarch64_sys_ins_reg *);
 986
 987 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 988 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 989 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 990 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 991 extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
 992
 993 /* Shift/extending operator kinds.
 994    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 995 enum aarch64_modifier_kind
 996 {
 997   AARCH64_MOD_NONE,
 998   AARCH64_MOD_MSL,
 999   AARCH64_MOD_ROR,
1000   AARCH64_MOD_ASR,
1001   AARCH64_MOD_LSR,
1002   AARCH64_MOD_LSL,
1003   AARCH64_MOD_UXTB,
1004   AARCH64_MOD_UXTH,
1005   AARCH64_MOD_UXTW,
1006   AARCH64_MOD_UXTX,
1007   AARCH64_MOD_SXTB,
1008   AARCH64_MOD_SXTH,
1009   AARCH64_MOD_SXTW,
1010   AARCH64_MOD_SXTX,
1011   AARCH64_MOD_MUL,
1012   AARCH64_MOD_MUL_VL,
1013 };
1014
1015 bfd_boolean
1016 aarch64_extend_operator_p (enum aarch64_modifier_kind);
1017
1018 enum aarch64_modifier_kind
1019 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
1020 /* Condition.  */
1021
1022 typedef struct
1023 {
1024   /* A list of names with the first one as the disassembly preference;
1025      terminated by NULL if fewer than 3.  */
1026   const char *names[4];
1027   aarch64_insn value;
1028 } aarch64_cond;
1029
1030 extern const aarch64_cond aarch64_conds[16];
1031
1032 const aarch64_cond* get_cond_from_value (aarch64_insn value);
1033 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
1034 \f
1035 /* Structure representing an operand.  */
1036
1037 struct aarch64_opnd_info
1038 {
1039   enum aarch64_opnd type;
1040   aarch64_opnd_qualifier_t qualifier;
1041   int idx;
1042
1043   union
1044     {
1045       struct
1046         {
1047           unsigned regno;
1048         } reg;
1049       struct
1050         {
1051           unsigned int regno;
1052           int64_t index;
1053         } reglane;
1054       /* e.g. LVn.  */
1055       struct
1056         {
1057           unsigned first_regno : 5;
1058           unsigned num_regs : 3;
1059           /* 1 if it is a list of reg element.  */
1060           unsigned has_index : 1;
1061           /* Lane index; valid only when has_index is 1.  */
1062           int64_t index;
1063         } reglist;
1064       /* e.g. immediate or pc relative address offset.  */
1065       struct
1066         {
1067           int64_t value;
1068           unsigned is_fp : 1;
1069         } imm;
1070       /* e.g. address in STR (register offset).  */
1071       struct
1072         {
1073           unsigned base_regno;
1074           struct
1075             {
1076               union
1077                 {
1078                   int imm;
1079                   unsigned regno;
1080                 };
1081               unsigned is_reg;
1082             } offset;
1083           unsigned pcrel : 1;           /* PC-relative.  */
1084           unsigned writeback : 1;
1085           unsigned preind : 1;          /* Pre-indexed.  */
1086           unsigned postind : 1;         /* Post-indexed.  */
1087         } addr;
1088
1089       struct
1090         {
1091           /* The encoding of the system register.  */
1092           aarch64_insn value;
1093
1094           /* The system register flags.  */
1095           uint32_t flags;
1096         } sysreg;
1097
1098       const aarch64_cond *cond;
1099       /* The encoding of the PSTATE field.  */
1100       aarch64_insn pstatefield;
1101       const aarch64_sys_ins_reg *sysins_op;
1102       const struct aarch64_name_value_pair *barrier;
1103       const struct aarch64_name_value_pair *hint_option;
1104       const struct aarch64_name_value_pair *prfop;
1105     };
1106
1107   /* Operand shifter; in use when the operand is a register offset address,
1108      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
1109   struct
1110     {
1111       enum aarch64_modifier_kind kind;
1112       unsigned operator_present: 1;     /* Only valid during encoding.  */
1113       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
1114       unsigned amount_present: 1;
1115       int64_t amount;
1116     } shifter;
1117
1118   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
1119                            to be done on it.  In some (but not all) of these
1120                            cases, we need to tell libopcodes to skip the
1121                            constraint checking and the encoding for this
1122                            operand, so that the libopcodes can pick up the
1123                            right opcode before the operand is fixed-up.  This
1124                            flag should only be used during the
1125                            assembling/encoding.  */
1126   unsigned present:1;   /* Whether this operand is present in the assembly
1127                            line; not used during the disassembly.  */
1128 };
1129
1130 typedef struct aarch64_opnd_info aarch64_opnd_info;
1131
1132 /* Structure representing an instruction.
1133
1134    It is used during both the assembling and disassembling.  The assembler
1135    fills an aarch64_inst after a successful parsing and then passes it to the
1136    encoding routine to do the encoding.  During the disassembling, the
1137    disassembler calls the decoding routine to decode a binary instruction; on a
1138    successful return, such a structure will be filled with information of the
1139    instruction; then the disassembler uses the information to print out the
1140    instruction.  */
1141
1142 struct aarch64_inst
1143 {
1144   /* The value of the binary instruction.  */
1145   aarch64_insn value;
1146
1147   /* Corresponding opcode entry.  */
1148   const aarch64_opcode *opcode;
1149
1150   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
1151   const aarch64_cond *cond;
1152
1153   /* Operands information.  */
1154   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1155 };
1156
1157 /* Defining the HINT #imm values for the aarch64_hint_options.  */
1158 #define HINT_OPD_CSYNC  0x11
1159 #define HINT_OPD_C      0x22
1160 #define HINT_OPD_J      0x24
1161 #define HINT_OPD_JC     0x26
1162 #define HINT_OPD_NULL   0x00
1163
1164 \f
1165 /* Diagnosis related declaration and interface.  */
1166
1167 /* Operand error kind enumerators.
1168
1169    AARCH64_OPDE_RECOVERABLE
1170      Less severe error found during the parsing, very possibly because that
1171      GAS has picked up a wrong instruction template for the parsing.
1172
1173    AARCH64_OPDE_SYNTAX_ERROR
1174      General syntax error; it can be either a user error, or simply because
1175      that GAS is trying a wrong instruction template.
1176
1177    AARCH64_OPDE_FATAL_SYNTAX_ERROR
1178      Definitely a user syntax error.
1179
1180    AARCH64_OPDE_INVALID_VARIANT
1181      No syntax error, but the operands are not a valid combination, e.g.
1182      FMOV D0,S0
1183
1184    AARCH64_OPDE_UNTIED_OPERAND
1185      The asm failed to use the same register for a destination operand
1186      and a tied source operand.
1187
1188    AARCH64_OPDE_OUT_OF_RANGE
1189      Error about some immediate value out of a valid range.
1190
1191    AARCH64_OPDE_UNALIGNED
1192      Error about some immediate value not properly aligned (i.e. not being a
1193      multiple times of a certain value).
1194
1195    AARCH64_OPDE_REG_LIST
1196      Error about the register list operand having unexpected number of
1197      registers.
1198
1199    AARCH64_OPDE_OTHER_ERROR
1200      Error of the highest severity and used for any severe issue that does not
1201      fall into any of the above categories.
1202
1203    The enumerators are only interesting to GAS.  They are declared here (in
1204    libopcodes) because that some errors are detected (and then notified to GAS)
1205    by libopcodes (rather than by GAS solely).
1206
1207    The first three errors are only deteced by GAS while the
1208    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1209    only libopcodes has the information about the valid variants of each
1210    instruction.
1211
1212    The enumerators have an increasing severity.  This is helpful when there are
1213    multiple instruction templates available for a given mnemonic name (e.g.
1214    FMOV); this mechanism will help choose the most suitable template from which
1215    the generated diagnostics can most closely describe the issues, if any.  */
1216
1217 enum aarch64_operand_error_kind
1218 {
1219   AARCH64_OPDE_NIL,
1220   AARCH64_OPDE_RECOVERABLE,
1221   AARCH64_OPDE_SYNTAX_ERROR,
1222   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1223   AARCH64_OPDE_INVALID_VARIANT,
1224   AARCH64_OPDE_UNTIED_OPERAND,
1225   AARCH64_OPDE_OUT_OF_RANGE,
1226   AARCH64_OPDE_UNALIGNED,
1227   AARCH64_OPDE_REG_LIST,
1228   AARCH64_OPDE_OTHER_ERROR
1229 };
1230
1231 /* N.B. GAS assumes that this structure work well with shallow copy.  */
1232 struct aarch64_operand_error
1233 {
1234   enum aarch64_operand_error_kind kind;
1235   int index;
1236   const char *error;
1237   int data[3];  /* Some data for extra information.  */
1238   bfd_boolean non_fatal;
1239 };
1240
1241 /* AArch64 sequence structure used to track instructions with F_SCAN
1242    dependencies for both assembler and disassembler.  */
1243 struct aarch64_instr_sequence
1244 {
1245   /* The instruction that caused this sequence to be opened.  */
1246   aarch64_inst *instr;
1247   /* The number of instructions the above instruction allows to be kept in the
1248      sequence before an automatic close is done.  */
1249   int num_insns;
1250   /* The instructions currently added to the sequence.  */
1251   aarch64_inst **current_insns;
1252   /* The number of instructions already in the sequence.  */
1253   int next_insn;
1254 };
1255
1256 /* Encoding entrypoint.  */
1257
1258 extern int
1259 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1260                        aarch64_insn *, aarch64_opnd_qualifier_t *,
1261                        aarch64_operand_error *, aarch64_instr_sequence *);
1262
1263 extern const aarch64_opcode *
1264 aarch64_replace_opcode (struct aarch64_inst *,
1265                         const aarch64_opcode *);
1266
1267 /* Given the opcode enumerator OP, return the pointer to the corresponding
1268    opcode entry.  */
1269
1270 extern const aarch64_opcode *
1271 aarch64_get_opcode (enum aarch64_op);
1272
1273 /* Generate the string representation of an operand.  */
1274 extern void
1275 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1276                        const aarch64_opnd_info *, int, int *, bfd_vma *,
1277                        char **);
1278
1279 /* Miscellaneous interface.  */
1280
1281 extern int
1282 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1283
1284 extern aarch64_opnd_qualifier_t
1285 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1286                                 const aarch64_opnd_qualifier_t, int);
1287
1288 extern bfd_boolean
1289 aarch64_is_destructive_by_operands (const aarch64_opcode *);
1290
1291 extern int
1292 aarch64_num_of_operands (const aarch64_opcode *);
1293
1294 extern int
1295 aarch64_stack_pointer_p (const aarch64_opnd_info *);
1296
1297 extern int
1298 aarch64_zero_register_p (const aarch64_opnd_info *);
1299
1300 extern enum err_type
1301 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
1302                      aarch64_operand_error *);
1303
1304 extern void
1305 init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
1306
1307 /* Given an operand qualifier, return the expected data element size
1308    of a qualified operand.  */
1309 extern unsigned char
1310 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1311
1312 extern enum aarch64_operand_class
1313 aarch64_get_operand_class (enum aarch64_opnd);
1314
1315 extern const char *
1316 aarch64_get_operand_name (enum aarch64_opnd);
1317
1318 extern const char *
1319 aarch64_get_operand_desc (enum aarch64_opnd);
1320
1321 extern bfd_boolean
1322 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1323
1324 #ifdef DEBUG_AARCH64
1325 extern int debug_dump;
1326
1327 extern void
1328 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1329
1330 #define DEBUG_TRACE(M, ...)                                     \
1331   {                                                             \
1332     if (debug_dump)                                             \
1333       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1334   }
1335
1336 #define DEBUG_TRACE_IF(C, M, ...)                               \
1337   {                                                             \
1338     if (debug_dump && (C))                                      \
1339       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1340   }
1341 #else  /* !DEBUG_AARCH64 */
1342 #define DEBUG_TRACE(M, ...) ;
1343 #define DEBUG_TRACE_IF(C, M, ...) ;
1344 #endif /* DEBUG_AARCH64 */
1345
1346 extern const char *const aarch64_sve_pattern_array[32];
1347 extern const char *const aarch64_sve_prfop_array[16];
1348
1349 #ifdef __cplusplus
1350 }
1351 #endif
1352
1353 #endif /* OPCODE_AARCH64_H */