include/opcode/crx.h

   1 /* crx.h -- Header file for CRX opcode and register tables.
   2    Copyright 2004 Free Software Foundation, Inc.
   3    Contributed by Tomer Levi, NSC, Israel.
   4    Originally written for GAS 2.12 by Tomer Levi, NSC, Israel.
   5    Updates, BFDizing, GNUifying and ELF support by Tomer Levi.
   6
   7    This file is part of GAS, GDB and the GNU binutils.
   8
   9    GAS, GDB, and GNU binutils is free software; you can redistribute it
  10    and/or modify it under the terms of the GNU General Public License as
  11    published by the Free Software Foundation; either version 2, or (at your
  12    option) any later version.
  13
  14    GAS, GDB, and GNU binutils are distributed in the hope that they will be
  15    useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this program; if not, write to the Free Software
  21    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  22
  23 #ifndef _CRX_H_
  24 #define _CRX_H_
  25
  26 /* CRX core/debug Registers :
  27    The enums are used as indices to CRX registers table (crx_regtab).
  28    Therefore, order MUST be preserved.  */
  29
  30 typedef enum
  31   {
  32     /* 32-bit general purpose registers.  */
  33     r0, r1, r2, r3, r4, r5, r6, r7, r8, r9,
  34     r10, r11, r12, r13, r14, r15, ra, sp,
  35     /* 32-bit user registers.  */
  36     u0, u1, u2, u3, u4, u5, u6, u7, u8, u9,
  37     u10, u11, u12, u13, u14, u15, ura, usp,
  38     /* hi and lo registers.  */
  39     hi, lo,
  40     /* hi and lo user registers.  */
  41     uhi, ulo,
  42     /* Processor Status Register.  */
  43     psr,
  44     /* Configuration Register.  */
  45     cfg,
  46     /* Coprocessor Configuration Register.  */
  47     cpcfg,
  48     /* Cashe Configuration Register.  */
  49     ccfg,
  50     /* Interrupt Base Register.  */
  51     intbase,
  52     /* Interrupt Stack Pointer Register.  */
  53     isp,
  54     /* Coprocessor Enable Register.  */
  55     cen,
  56     /* Program Counter Register.  */
  57     pc,
  58     /* Not a register.  */
  59     nullregister,
  60     MAX_REG
  61   }
  62 reg;
  63
  64 /* CRX Coprocessor registers and special registers :
  65    The enums are used as indices to CRX coprocessor registers table
  66    (crx_copregtab). Therefore, order MUST be preserved.  */
  67
  68 typedef enum
  69   {
  70     /* Coprocessor registers.  */
  71     c0 = MAX_REG, c1, c2, c3, c4, c5, c6, c7, c8,
  72     c9, c10, c11, c12, c13, c14, c15,
  73     /* Coprocessor special registers.  */
  74     cs0, cs1 ,cs2, cs3, cs4, cs5, cs6, cs7, cs8,
  75     cs9, cs10, cs11, cs12, cs13, cs14, cs15,
  76     /* Not a Coprocessor register.  */
  77     nullcopregister,
  78     MAX_COPREG
  79   }
  80 copreg;
  81
  82 /* CRX Register types. */
  83
  84 typedef enum
  85   {
  86     CRX_PC_REGTYPE,   /*  pc type */
  87     CRX_R_REGTYPE,    /*  r<N>    */
  88     CRX_U_REGTYPE,    /*  u<N>    */
  89     CRX_C_REGTYPE,    /*  c<N>    */
  90     CRX_CS_REGTYPE,   /*  cs<N>   */
  91     CRX_MTPR_REGTYPE, /*  mtpr    */
  92     CRX_CFG_REGTYPE   /*  *hi|lo, *cfg, psr */
  93   }
  94 reg_type;
  95
  96 /* CRX argument types :
  97    The argument types correspond to instructions operands
  98
  99    Argument types :
 100    r - register
 101    c - constant
 102    d - displacement
 103    ic - immediate
 104    icr - index register
 105    rbase - register base
 106    s - star ('*')
 107    copr - coprocessor register
 108    copsr - coprocessor special register.  */
 109
 110 typedef enum
 111   {
 112     arg_r, arg_c, arg_cr, arg_dc, arg_dcr, arg_sc,
 113     arg_ic, arg_icr, arg_rbase, arg_copr, arg_copsr,
 114     /* Not an argument.  */
 115     nullargs
 116   }
 117 argtype;
 118
 119 /* CRX operand types :
 120    The operand types correspond to instructions operands
 121
 122    Operand Types :
 123    cst4 - 4-bit encoded constant
 124    iN - N-bit immediate field
 125    d, dispsN - N-bit immediate signed displacement
 126    dispuN - N-bit immediate unsigned displacement
 127    absN - N-bit absolute address
 128    rbase - 4-bit genaral-purpose register specifier
 129    regr - 4-bit genaral-purpose register specifier
 130    regr8 - 8-bit register address space
 131    copregr - coprocessor register
 132    copsregr - coprocessor special register
 133    scl2 - 2-bit scaling factor for memory index
 134    ridx - register index.  */
 135
 136 typedef enum
 137   {
 138     dummy, cst4, disps9,
 139     i3, i4, i5, i8, i12, i16, i32,
 140     d5, d9, d17, d25, d33,
 141     abs16, abs32,
 142     rbase, rbase_cst4,
 143     rbase_dispu8, rbase_dispu12, rbase_dispu16, rbase_dispu28, rbase_dispu32,
 144     rbase_ridx_scl2_dispu6, rbase_ridx_scl2_dispu22,
 145     regr, regr8, copregr,copregr8,copsregr,
 146     /* Not an operand.  */
 147     nulloperand,
 148     /* Maximum supported operand.  */
 149     MAX_OPRD
 150   }
 151 operand_type;
 152
 153 /* CRX instruction types.  */
 154
 155 #define ARITH_INS         1
 156 #define LD_STOR_INS       2
 157 #define BRANCH_INS        3
 158 #define ARITH_BYTE_INS    4
 159 #define CMPBR_INS         5
 160 #define SHIFT_INS         6
 161 #define BRANCH_NEQ_INS    7
 162 #define LD_STOR_INS_INC   8
 163 #define STOR_IMM_INS      9
 164 #define CSTBIT_INS       10
 165 #define SYS_INS          11
 166 #define JMP_INS          12
 167 #define MUL_INS          13
 168 #define DIV_INS          14
 169 #define COP_BRANCH_INS   15
 170 #define COP_REG_INS      16
 171 #define DCR_BRANCH_INS   17
 172 #define MMC_INS          18
 173 #define MMU_INS          19
 174
 175 /* Maximum value supported for instruction types.  */
 176 #define CRX_INS_MAX     (1 << 5)
 177 /* Mask to record an instruction type.  */
 178 #define CRX_INS_MASK    (CRX_INS_MAX - 1)
 179 /* Return instruction type, given instruction's attributes.  */
 180 #define CRX_INS_TYPE(attr) ((attr) & CRX_INS_MASK)
 181
 182 /* Indicates whether this instruction has a register list as parameter.  */
 183 #define REG_LIST        CRX_INS_MAX
 184 /* The operands in binary and assembly are placed in reverse order.
 185    load - (REVERSE_MATCH)/store - (! REVERSE_MATCH).  */
 186 #define REVERSE_MATCH  (REG_LIST << 1)
 187
 188 /* Kind of displacement map used DISPU[BWD]4.  */
 189 #define DISPUB4        (REVERSE_MATCH << 1)
 190 #define DISPUW4        (DISPUB4 << 1)
 191 #define DISPUD4        (DISPUW4 << 1)
 192 #define CST4MAP        (DISPUB4 | DISPUW4 | DISPUD4)
 193
 194 /* Printing formats, where the instruction prefix isn't consecutive.  */
 195 #define FMT_1          (DISPUD4 << 1) /* 0xF0F00000 */
 196 #define FMT_2          (FMT_1 << 1)   /* 0xFFF0FF00 */
 197 #define FMT_3          (FMT_2 << 1)   /* 0xFFF00F00 */
 198 #define FMT_4          (FMT_3 << 1)   /* 0xFFF0F000 */
 199 #define FMT_5          (FMT_4 << 1)   /* 0xFFF0FFF0 */
 200 #define FMT_CRX        (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5)
 201
 202 #define RELAXABLE      (FMT_5 << 1)
 203
 204 /* Maximum operands per instruction.  */
 205 #define MAX_OPERANDS      5
 206 /* Maximum words per instruction.  */
 207 #define MAX_WORDS         3
 208 /* Maximum register name length. */
 209 #define MAX_REGNAME_LEN   10
 210 /* Maximum instruction length. */
 211 #define MAX_INST_LEN      256
 212
 213 /* Single operand description.  */
 214
 215 typedef struct
 216   {
 217     /* Operand type.  */
 218     operand_type op_type;
 219     /* Operand location within the opcode.  */
 220     unsigned int shift;
 221   }
 222 operand_desc;
 223
 224 /* Instruction data structure used in instruction table.  */
 225
 226 typedef struct
 227   {
 228     /* Name.  */
 229     const char *mnemonic;
 230     /* Size (in words).  */
 231     unsigned int size;
 232     /* Constant prefix (matched by the disassembler).  */
 233     unsigned long match;
 234     /* Match size (in bits).  */
 235     int match_bits;
 236     /* Attributes.  */
 237     unsigned int flags;
 238     /* Operands (always last, so unreferenced operands are initialized).  */
 239     operand_desc operands[MAX_OPERANDS];
 240   }
 241 inst;
 242
 243 /* Data structure for a single instruction's arguments (Operands).  */
 244
 245 typedef struct
 246   {
 247     /* Register or base register.  */
 248     reg r;
 249     /* Index register.  */
 250     reg i_r;
 251     /* Coprocessor register.  */
 252     copreg cr;
 253     /* Constant/immediate/absolute value.  */
 254     unsigned long int constant;
 255     /* Scaled index mode.  */
 256     unsigned int scale;
 257     /* Argument type.  */
 258     argtype type;
 259     /* Size of the argument (in bits) required to represent.  */
 260     int size;
 261     /* Indicates whether a constant is positive or negative.  */
 262     int signflag;
 263   }
 264 argument;
 265
 266 /* Internal structure to hold the various entities
 267    corresponding to the current assembling instruction.  */
 268
 269 typedef struct
 270   {
 271     /* Number of arguments.  */
 272     int nargs;
 273     /* The argument data structure for storing args (operands).  */
 274     argument arg[MAX_OPERANDS];
 275 /* The following fields are required only by CRX-assembler.  */
 276 #ifdef TC_CRX
 277     /* Expression used for setting the fixups (if any).  */
 278     expressionS exp;
 279     bfd_reloc_code_real_type rtype;
 280 #endif /* TC_CRX */
 281     /* Instruction size (in bytes).  */
 282     int size;
 283   }
 284 ins;
 285
 286 /* Structure to hold information about predefined operands.  */
 287
 288 typedef struct
 289   {
 290     /* Size (in bits).  */
 291     unsigned int bit_size;
 292     /* Argument type.  */
 293     argtype arg_type;
 294   }
 295 operand_entry;
 296
 297 /* Structure to hold trap handler information.  */
 298
 299 typedef struct
 300   {
 301     /* Trap name.  */
 302     char *name;
 303     /* Index in dispatch table.  */
 304     unsigned int entry;
 305   }
 306 trap_entry;
 307
 308 /* Structure to hold information about predefined registers.  */
 309
 310 typedef struct
 311   {
 312     /* Name (string representation).  */
 313     char *name;
 314     /* Value (enum representation).  */
 315     union
 316     {
 317       /* Register.  */
 318       reg reg_val;
 319       /* Coprocessor register.  */
 320       copreg copreg_val;
 321     } value;
 322     /* Register image.  */
 323     int image;
 324     /* Register type.  */
 325     reg_type type;
 326   }
 327 reg_entry;
 328
 329 /* Structure to hold a cst4 operand mapping.  */
 330
 331 typedef struct
 332   {
 333     /* The binary value which is written to the object file.  */
 334     int binary;
 335     /* The value which is mapped.  */
 336     int value;
 337   }
 338 cst4_entry;
 339
 340 /* CRX opcode table.  */
 341 extern const inst crx_instruction[];
 342 extern const int crx_num_opcodes;
 343 #define NUMOPCODES crx_num_opcodes
 344
 345 /* CRX operands table.  */
 346 extern const operand_entry crx_optab[];
 347
 348 /* CRX registers table.  */
 349 extern const reg_entry crx_regtab[];
 350 extern const int crx_num_regs;
 351 #define NUMREGS crx_num_regs
 352
 353 /* CRX coprocessor registers table.  */
 354 extern const reg_entry crx_copregtab[];
 355 extern const int crx_num_copregs;
 356 #define NUMCOPREGS crx_num_copregs
 357
 358 /* CRX trap/interrupt table.  */
 359 extern const trap_entry crx_traps[];
 360 extern const int crx_num_traps;
 361 #define NUMTRAPS crx_num_traps
 362
 363 /* cst4 operand mapping.  */
 364 extern const cst4_entry cst4_map[];
 365 extern const int cst4_maps;
 366
 367 /* Current instruction we're assembling.  */
 368 extern const inst *instruction;
 369
 370 /* A macro for representing the instruction "constant" opcode, that is,
 371    the FIXED part of the instruction. The "constant" opcode is represented
 372    as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT)
 373    over that range.  */
 374 #define BIN(OPC,SHIFT)  (OPC << SHIFT)
 375
 376 /* Is the current instruction type is TYPE ?  */
 377 #define IS_INSN_TYPE(TYPE)            \
 378   (CRX_INS_TYPE(instruction->flags) == TYPE)
 379
 380 /* Is the current instruction mnemonic is MNEMONIC ?  */
 381 #define IS_INSN_MNEMONIC(MNEMONIC)    \
 382   (strcmp(instruction->mnemonic,MNEMONIC) == 0)
 383
 384 /* Does the current instruction has register list ?  */
 385 #define INST_HAS_REG_LIST             \
 386   (instruction->flags & REG_LIST)
 387
 388 /* Long long type handling.  */
 389 /* Replace all appearances of 'long long int' with LONGLONG.  */
 390 typedef long long int LONGLONG;
 391 typedef unsigned long long ULONGLONG;
 392 /* A mask for the upper 31 bits of a 64 bits type.  */
 393 #define UPPER31_MASK    0xFFFFFFFE00000000LL
 394
 395 #endif /* _CRX_H_ */