include/opcode/h8300.h

   1 /* Opcode table for the H8-300
   2    Copyright (C) 1991,1992 Free Software Foundation.
   3    Written by Steve Chamberlain, sac@cygnus.com.
   4
   5    This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 /* Instructions are stored as a sequence of nibbles.
  22    If the nibble has value 15 or less then the representation is complete.
  23    Otherwise, we record what it contains with several flags.  */
  24
  25 typedef int op_type;
  26
  27 #define Hex0    0
  28 #define Hex1    1
  29 #define Hex2    2
  30 #define Hex3    3
  31 #define Hex4    4
  32 #define Hex5    5
  33 #define Hex6    6
  34 #define Hex7    7
  35 #define Hex8    8
  36 #define Hex9    9
  37 #define HexA    10
  38 #define HexB    11
  39 #define HexC    12
  40 #define HexD    13
  41 #define HexE    14
  42 #define HexF    15
  43
  44 #define L_8             0x01
  45 #define L_16            0x02
  46 #define L_32            0x04
  47 #define L_P             0x08
  48 #define L_24            0x10
  49 #define MEMRELAX        0x20                    /* move insn which may relax */
  50 #define SRC             0x40
  51 #define DST             0x80
  52
  53 #define REG             0x100
  54 #define EXR             0x200
  55 #define MACREG          0x800
  56 #define SRC_IN_DST      0x400
  57 #define IMM             0x1000
  58 #define DISP            0x2000
  59 #define IND             0x4000
  60 #define INC             0x8000
  61 #define DEC             0x10000
  62 #define L_3             0x20000
  63 #define KBIT            0x40000
  64 #define DBIT            0x80000
  65 #define DISPREG         0x100000
  66 #define IGNORE          0x200000
  67 #define E               0x400000                /* FIXME: end of nibble sequence? */
  68 #define L_2             0x800000
  69 #define B30             0x1000000               /* bit 3 must be low */
  70 #define B31             0x2000000               /* bit 3 must be high */
  71 #define CCR             0x4000000
  72 #define ABS             0x8000000
  73 #define ABSJMP          0x10000000
  74 #define ABS8MEM         0x20000000
  75 #define PCREL           0x40000000
  76 #define MEMIND          0x80000000
  77
  78 #define IMM3            IMM|L_3
  79 #define IMM2            IMM|L_2
  80
  81 #define SIZE            (L_2|L_3|L_8|L_16|L_32|L_P|L_24)
  82 #define MODE            (REG|IMM|DISP|IND|INC|DEC|CCR|ABS|MEMIND|EXR)
  83
  84 #define RD8             (DST|L_8|REG)
  85 #define RD16            (DST|L_16|REG)
  86 #define RD32            (DST|L_32|REG)
  87 #define RS8             (SRC|L_8|REG)
  88 #define RS16            (SRC|L_16|REG)
  89 #define RS32            (SRC|L_32|REG)
  90
  91 #define RSP             (SRC|L_P|REG)
  92 #define RDP             (DST|L_P|REG)
  93
  94 #define IMM8            (IMM|SRC|L_8)
  95 #define IMM16           (IMM|SRC|L_16)
  96 #define IMM32           (IMM|SRC|L_32)
  97
  98 #define ABS8SRC         (SRC|ABS|L_8|ABS8MEM)
  99 #define ABS8DST         (DST|ABS|L_8|ABS8MEM)
 100
 101 #define DISP8           (PCREL|L_8)
 102 #define DISP16          (PCREL|L_16)
 103
 104 #define DISP8SRC        (DISP|L_8|SRC)
 105 #define DISP16SRC       (DISP|L_16|SRC)
 106
 107 #define DISP8DST        (DISP|L_8|DST)
 108 #define DISP16DST       (DISP|L_16|DST)
 109
 110 #define ABS16SRC        (SRC|ABS|L_16)
 111 #define ABS16DST        (DST|ABS|L_16)
 112 #define ABS24SRC        (SRC|ABS|L_24)
 113 #define ABS24DST        (DST|ABS|L_24)
 114 #define ABS32SRC        (SRC|ABS|L_32)
 115 #define ABS32DST        (DST|ABS|L_32)
 116
 117 #define RDDEC           (DST|DEC)
 118 #define RSINC           (SRC|INC)
 119 #define RDINC           (DST|INC)
 120
 121 #define RDIND           (DST|IND)
 122 #define RSIND           (SRC|IND)
 123
 124 #if 1
 125 #define OR8 RS8         /* ??? OR as in One Register? */
 126 #define OR16 RS16
 127 #define OR32 RS32
 128 #else
 129 #define OR8 RD8
 130 #define OR16 RD16
 131 #define OR32 RD32
 132 #endif
 133
 134 struct code
 135 {
 136   op_type nib[30];
 137 };
 138
 139 struct arg
 140 {
 141   op_type nib[3];
 142 };
 143
 144 struct h8_opcode
 145 {
 146   int how;
 147   int inbase;
 148   int time;
 149   char *name;
 150   struct arg args;
 151   struct code data;
 152   int length;
 153   int noperands;
 154   int idx;
 155   int size;
 156 };
 157
 158 #ifdef DEFINE_TABLE
 159
 160 #define BITOP(code, imm, name, op00, op01,op10,op11, op20,op21,op30)\
 161 { code, 1, 2, name,     {imm,RD8,E},    {op00, op01, imm, RD8, E, 0, 0, 0, 0}, 0, 0, 0, 0},\
 162 { code, 1, 6, name,     {imm,RDIND,E},  {op10, op11, B30|RDIND, 0, op00,op01, imm, 0, E}, 0, 0, 0, 0},\
 163 { code, 1, 6, name,     {imm,ABS8DST,E},{op20, op21, ABS8DST, IGNORE, op00,op01, imm, 0,E}, 0, 0, 0, 0}\
 164 ,{ code, 1, 6, name,    {imm,ABS16DST,E},{0x6,0xa,0x1,op30,ABS16DST,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}, 0, 0, 0, 0},\
 165 { code, 1, 6, name,     {imm,ABS32DST,E},{0x6,0xa,0x3,op30,ABS32DST,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}, 0, 0, 0, 0}
 166
 167
 168 #define EBITOP(code, imm, name, op00, op01,op10,op11, op20,op21,op30)\
 169    BITOP(code,imm, name, op00+1, op01, op10,op11, op20,op21,op30),\
 170    BITOP(code,RS8,  name, op00, op01, op10,op11, op20,op21,op30)
 171
 172 #define WTWOP(code,name, op1, op2) \
 173 { code, 1, 2, name, {RS16, RD16, E}, { op1, op2, RS16, RD16, E, 0, 0, 0, 0}, 0, 0, 0, 0}
 174
 175 #define BRANCH(code, name, op) \
 176 { code, 1, 4,name,{DISP8,E,0}, { 0x4, op, DISP8, IGNORE, E, 0, 0, 0, 0}, 0, 0, 0, 0}, \
 177 { code, 0, 6,name,{DISP16,E,0}, { 0x5, 0x8, op, 0x0, DISP16, IGNORE, IGNORE, IGNORE, E,0}, 0, 0, 0, 0}
 178
 179 #define SOP(code, x,name) \
 180 {code, 1, x,  name
 181
 182 #define NEW_SOP(code, in,x,name) \
 183 {code, in, x,  name
 184 #define EOP  ,0,0,0 }
 185
 186 #define TWOOP(code, name, op1, op2,op3) \
 187 { code,1, 2,name, {IMM8, RD8, E},       { op1, RD8, IMM8, IGNORE, E, 0, 0, 0, 0}, 0, 0, 0, 0},\
 188 { code, 1, 2,name, {RS8, RD8, E},       { op2, op3, RS8, RD8, E, 0, 0, 0, 0}, 0, 0, 0, 0}
 189
 190 #define UNOP(code,name, op1, op2) \
 191 { code, 1, 2, name, {OR8, E, 0}, { op1, op2, 0, OR8, E, 0, 0, 0, 0}, 0, 0, 0, 0}
 192
 193 #define UNOP3(code, name, op1, op2, op3) \
 194 { O(code,SB), 1, 2, name, {OR8,  E, 0}, {op1, op2, op3+0, OR8,  E, 0, 0, 0, 0}, 0, 0, 0, 0}, \
 195 { O(code,SW), 0, 2, name, {OR16, E, 0}, {op1, op2, op3+1, OR16, E, 0, 0, 0, 0}, 0, 0, 0, 0}, \
 196 { O(code,SL), 0, 2, name, {OR32, E, 0}, {op1, op2, op3+3, OR32|B30, E, 0, 0, 0, 0}, 0, 0, 0, 0} \
 197 ,{ O(code,SB), 1, 2, name, {IMM, OR8 | SRC_IN_DST,  E}, {op1, op2, op3+4, OR8 | SRC_IN_DST,  E, 0, 0, 0, 0}, 0, 0, 0, 0}, \
 198 { O(code,SW), 0, 2, name, {IMM, OR16 | SRC_IN_DST, E}, {op1, op2, op3+5, OR16 | SRC_IN_DST, E, 0, 0, 0, 0}, 0, 0, 0, 0}, \
 199 { O(code,SL), 0, 2, name, {IMM, OR32 | SRC_IN_DST, E}, {op1, op2, op3+7, OR32 | SRC_IN_DST|B30 , E, 0, 0, 0, 0}, 0, 0, 0, 0}
 200
 201
 202 #define IMM32LIST IMM32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
 203 #define IMM24LIST IMM24,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
 204 #define IMM16LIST IMM16,IGNORE,IGNORE,IGNORE
 205 #define A16LIST L_16,IGNORE,IGNORE,IGNORE
 206 #define DISP24LIST DISP|L_24,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
 207 #define DISP32LIST DISP|L_32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
 208 #define ABS24LIST ABS|L_24,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
 209 #define ABS32LIST ABS|L_32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
 210 #define A24LIST L_24,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
 211 #define A32LIST L_32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
 212 #define PREFIX32 0x0,0x1,0x0,0x0
 213 #define PREFIXLDC 0x0,0x1,0x4,0x0
 214
 215
 216 #define O(op, size) (op*4+size)
 217
 218 #define O_RECOMPILE 0
 219 #define O_ADD  1
 220 #define O_ADDX 2
 221 #define O_AND  3
 222 #define O_BAND 4
 223 #define O_BRA  5
 224 #define O_BRN  6
 225 #define O_BHI  7
 226 #define O_BLS  8
 227 #define O_BCC  9
 228 #define O_BCS  10
 229 #define O_BNE  11
 230 #define O_BVC  12
 231 #define O_BVS  13
 232 #define O_BPL  14
 233 #define O_BMI  15
 234 #define O_BGE  16
 235 #define O_BLT  17
 236 #define O_BGT  18
 237 #define O_BLE  19
 238 #define O_ANDC 20
 239 #define O_BEQ 21
 240 #define O_BCLR 22
 241 #define O_BIAND 23
 242 #define O_BILD 24
 243 #define O_BIOR 25
 244 #define O_BIXOR 26
 245 #define O_BIST 27
 246 #define O_BLD 28
 247 #define O_BNOT 29
 248 #define O_BSET 30
 249 #define O_BSR 31
 250 #define O_BXOR 32
 251 #define O_CMP 33
 252 #define O_DAA 34
 253 #define O_DAS 35
 254 #define O_DEC 36
 255 #define O_DIVU 37
 256 #define O_DIVS 38
 257 #define O_INC 39
 258 #define O_LDC 40
 259 #define O_MOV_TO_MEM 41
 260 #define O_OR 42
 261 #define O_ROTL 43
 262 #define O_ROTR 44
 263 #define O_ROTXL 45
 264 #define O_ROTXR 46
 265 #define O_BPT 47
 266 #define O_SHAL 48
 267 #define O_SHAR 49
 268 #define O_SHLL 50
 269 #define O_SHLR 51
 270 #define O_SUB  52
 271 #define O_SUBS 53
 272 #define O_TRAPA 54
 273 #define O_XOR 55
 274 #define O_XORC 56
 275 #define O_BOR 57
 276 #define O_BST 58
 277 #define O_BTST 59
 278 #define O_EEPMOV 60
 279 #define O_EXTS 61
 280 #define O_EXTU 62
 281 #define O_JMP 63
 282 #define O_JSR 64
 283 #define O_MULU 65
 284 #define O_MULS 66
 285 #define O_NOP 67
 286 #define O_NOT 68
 287 #define O_ORC 69
 288 #define O_RTE 70
 289 #define O_STC 71
 290 #define O_SUBX 72
 291 #define O_NEG 73
 292 #define O_RTS 74
 293 #define O_SLEEP 75
 294 #define O_ILL 76
 295 #define O_ADDS 77
 296 #define O_SYSCALL 78
 297 #define O_MOV_TO_REG 79
 298 #define O_TAS 80
 299 #define O_CLRMAC 82
 300 #define O_LDMAC 83
 301 #define O_MAC 84
 302 #define O_LDM 85
 303 #define O_STM 86
 304 #define O_LAST 87
 305 #define SB 0
 306 #define SW 1
 307 #define SL 2
 308
 309
 310 /* FIXME: Lots of insns have "E, 0, 0, 0, 0" in the nibble code sequences.
 311    Methinks the zeroes aren't necessary.  Once confirmed, nuke 'em.  */
 312
 313 struct h8_opcode h8_opcodes[] =
 314 {
 315   TWOOP(O(O_ADD,SB),"add.b", 0x8, 0x0,0x8),
 316
 317   NEW_SOP(O(O_ADD,SW),1,2,"add.w"),{RS16,RD16,E },{0x0,0x9,RS16,RD16,E} EOP,
 318   NEW_SOP(O(O_ADD,SW),0,4,"add.w"),{IMM16,RD16,E },{0x7,0x9,0x1,RD16,IMM16,IGNORE,IGNORE,IGNORE,E} EOP,
 319   NEW_SOP(O(O_ADD,SL),0,2,"add.l"),{RS32,RD32,E }, {0x0,0xA,B31|RS32,B30|RD32,E} EOP,
 320   NEW_SOP(O(O_ADD,SL),0,6,"add.l"),{IMM32,RD32,E },{0x7,0xA,0x1,B30|RD32,IMM32LIST,E} EOP,
 321   NEW_SOP(O(O_ADDS,SL),1,2,"adds"), {KBIT,RDP,E},   {0x0,0xB,KBIT,RDP,E,0,0,0,0} EOP,
 322
 323   TWOOP(O(O_ADDX,SB),"addx",0x9,0x0,0xE),
 324   TWOOP(O(O_AND,SB), "and.b",0xE,0x1,0x6),
 325
 326   NEW_SOP(O(O_AND,SW),0,2,"and.w"),{RS16,RD16,E },{0x6,0x6,RS16,RD16,E} EOP,
 327   NEW_SOP(O(O_AND,SW),0,4,"and.w"),{IMM16,RD16,E },{0x7,0x9,0x6,RD16,IMM16,IGNORE,IGNORE,IGNORE,E} EOP,
 328
 329   NEW_SOP(O(O_AND,SL),0,6,"and.l"),{IMM32,RD32,E },{0x7,0xA,0x6,B30|RD32,IMM32LIST,E} EOP,
 330   NEW_SOP(O(O_AND,SL),0,2,"and.l") ,{RS32,RD32,E },{0x0,0x1,0xF,0x0,0x6,0x6,B30|RS32,B30|RD32,E} EOP,
 331
 332   NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {IMM8,CCR,E},{ 0x0,0x6,IMM8,IGNORE,E,0,0,0,0} EOP,
 333   NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {IMM8,EXR,E},{ 0x0,0x1,0x4,0x1,0x0,0x6,IMM8,IGNORE,E,0,0,0,0} EOP,
 334
 335   BITOP(O(O_BAND,SB), IMM3|B30,"band",0x7,0x6,0x7,0xC,0x7,0xE,0x0),
 336   BRANCH(O(O_BRA,SB),"bra",0x0),
 337   BRANCH(O(O_BRA,SB),"bt",0x0),
 338   BRANCH(O(O_BRN,SB),"brn",0x1),
 339   BRANCH(O(O_BRN,SB),"bf",0x1),
 340   BRANCH(O(O_BHI,SB),"bhi",0x2),
 341   BRANCH(O(O_BLS,SB),"bls",0x3),
 342   BRANCH(O(O_BCC,SB),"bcc",0x4),
 343   BRANCH(O(O_BCC,SB),"bhs",0x4),
 344   BRANCH(O(O_BCS,SB),"bcs",0x5),
 345   BRANCH(O(O_BCS,SB),"blo",0x5),
 346   BRANCH(O(O_BNE,SB),"bne",0x6),
 347   BRANCH(O(O_BEQ,SB),"beq",0x7),
 348   BRANCH(O(O_BVC,SB),"bvc",0x8),
 349   BRANCH(O(O_BVS,SB),"bvs",0x9),
 350   BRANCH(O(O_BPL,SB),"bpl",0xA),
 351   BRANCH(O(O_BMI,SB),"bmi",0xB),
 352   BRANCH(O(O_BGE,SB),"bge",0xC),
 353   BRANCH(O(O_BLT,SB),"blt",0xD),
 354   BRANCH(O(O_BGT,SB),"bgt",0xE),
 355   BRANCH(O(O_BLE,SB),"ble",0xF),
 356
 357   EBITOP(O(O_BCLR,SB),IMM3|B30,"bclr", 0x6,0x2,0x7,0xD,0x7,0xF,0x8),
 358   BITOP(O(O_BIAND,SB),IMM3|B31,"biand",0x7,0x6,0x7,0xC,0x7,0xE,0x0),
 359   BITOP(O(O_BILD,SB), IMM3|B31,"bild", 0x7,0x7,0x7,0xC,0x7,0xE,0x0),
 360   BITOP(O(O_BIOR,SB), IMM3|B31,"bior", 0x7,0x4,0x7,0xC,0x7,0xE,0x0),
 361   BITOP(O(O_BIST,SB), IMM3|B31,"bist", 0x6,0x7,0x7,0xD,0x7,0xF,0x8),
 362   BITOP(O(O_BIXOR,SB),IMM3|B31,"bixor",0x7,0x5,0x7,0xC,0x7,0xE,0x0),
 363   BITOP(O(O_BLD,SB),  IMM3|B30,"bld",  0x7,0x7,0x7,0xC,0x7,0xE,0x0),
 364   EBITOP(O(O_BNOT,SB),IMM3|B30,"bnot", 0x6,0x1,0x7,0xD,0x7,0xF,0x8),
 365   BITOP(O(O_BOR,SB),  IMM3|B30,"bor",  0x7,0x4,0x7,0xC,0x7,0xE,0x0),
 366   EBITOP(O(O_BSET,SB),IMM3|B30,"bset", 0x6,0x0,0x7,0xD,0x7,0xF,0x8),
 367
 368   SOP(O(O_BSR,SB),6,"bsr"),{DISP8,E,0},{ 0x5,0x5,DISP8,IGNORE,E,0,0,0,0} EOP,
 369   SOP(O(O_BSR,SB),6,"bsr"),{DISP16,E,0},{ 0x5,0xC,0x0,0x0,DISP16,IGNORE,IGNORE,IGNORE,E,0,0,0,0} EOP,
 370   BITOP(O(O_BST,SB), IMM3|B30,"bst",0x6,0x7,0x7,0xD,0x7,0xF,0x8),
 371   EBITOP(O(O_BTST,SB), IMM3|B30,"btst",0x6,0x3,0x7,0xC,0x7,0xE,0x0),
 372   BITOP(O(O_BXOR,SB), IMM3|B30,"bxor",0x7,0x5,0x7,0xC,0x7,0xE,0x0),
 373
 374   TWOOP(O(O_CMP,SB), "cmp.b",0xA,0x1,0xC),
 375   WTWOP(O(O_CMP,SW), "cmp.w",0x1,0xD),
 376
 377   NEW_SOP(O(O_CMP,SW),1,2,"cmp.w"),{RS16,RD16,E },{0x1,0xD,RS16,RD16,E} EOP,
 378   NEW_SOP(O(O_CMP,SW),0,4,"cmp.w"),{IMM16,RD16,E },{0x7,0x9,0x2,RD16,IMM16,IGNORE,IGNORE,IGNORE,E} EOP,
 379
 380   NEW_SOP(O(O_CMP,SL),0,6,"cmp.l"),{IMM32,RD32,E },{0x7,0xA,0x2,B30|RD32,IMM32LIST,E} EOP,
 381   NEW_SOP(O(O_CMP,SL),0,2,"cmp.l") ,{RS32,RD32,E },{0x1,0xF,B31|RS32,B30|RD32,E} EOP,
 382
 383   UNOP(O(O_DAA,SB), "daa",0x0,0xF),
 384   UNOP(O(O_DAS,SB), "das",0x1,0xF),
 385   UNOP(O(O_DEC,SB), "dec.b",0x1,0xA),
 386
 387   NEW_SOP(O(O_DEC, SW),0,2,"dec.w") ,{DBIT,RD16,E },{0x1,0xB,0x5|DBIT,RD16,E} EOP,
 388   NEW_SOP(O(O_DEC, SL),0,2,"dec.l") ,{DBIT,RD32,E },{0x1,0xB,0x7|DBIT,RD32|B30,E} EOP,
 389
 390   NEW_SOP(O(O_DIVU,SB),1,6,"divxu.b"), {RS8,RD16,E}, {0x5,0x1,RS8,RD16,E,0,0,0,0}EOP,
 391   NEW_SOP(O(O_DIVU,SW),0,20,"divxu.w"),{RS16,RD32,E},{0x5,0x3,RS16,B30|RD32,E}EOP,
 392
 393   NEW_SOP(O(O_DIVS,SB),0,20,"divxs.b") ,{RS8,RD16,E },{0x0,0x1,0xD,0x0,0x5,0x1,RS8,RD16,E} EOP,
 394   NEW_SOP(O(O_DIVS,SW),0,02,"divxs.w") ,{RS16,RD32,E },{0x0,0x1,0xD,0x0,0x5,0x3,RS16,B30|RD32,E} EOP,
 395
 396   NEW_SOP(O(O_EEPMOV,SB),1,50,"eepmov"),{ E,0,0},{0x7,0xB,0x5,0xC,0x5,0x9,0x8,0xF,E}EOP,
 397   NEW_SOP(O(O_EEPMOV,SW),0,50,"eepmov.w"),{E,0,0},{0x7,0xB,0xD,0x4,0x5,0x9,0x8,0xF,E} EOP,
 398
 399   NEW_SOP(O(O_EXTS,SW),0,2,"exts.w"),{OR16,E,0},{0x1,0x7,0xD,OR16,E   }EOP,
 400   NEW_SOP(O(O_EXTS,SL),0,2,"exts.l"),{OR32,E,0},{0x1,0x7,0xF,OR32|B30,E   }EOP,
 401
 402   NEW_SOP(O(O_EXTU,SW),0,2,"extu.w"),{OR16,E,0},{0x1,0x7,0x5,OR16,E   }EOP,
 403   NEW_SOP(O(O_EXTU,SL),0,2,"extu.l"),{OR32,E,0},{0x1,0x7,0x7,OR32|B30,E   }EOP,
 404
 405   UNOP(O(O_INC,SB), "inc",0x0,0xA),
 406
 407   NEW_SOP(O(O_INC,SW),0,2,"inc.w") ,{DBIT,RD16,E },{0x0,0xB,0x5|DBIT,RD16,E} EOP,
 408   NEW_SOP(O(O_INC,SL),0,2,"inc.l") ,{DBIT,RD32,E },{0x0,0xB,0x7|DBIT,RD32|B30,E} EOP,
 409
 410   SOP(O(O_JMP,SB),4,"jmp"),{RSIND,E,0},{0x5,0x9,B30|RSIND,0x0,E,0,0,0,0}EOP,
 411   SOP(O(O_JMP,SB),6,"jmp"),{SRC|ABSJMP,E,0},{0x5,0xA,SRC|ABSJMP,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,E}EOP,
 412   SOP(O(O_JMP,SB),8,"jmp"),{SRC|MEMIND,E,0},{0x5,0xB,SRC|MEMIND,IGNORE,E,0,0,0,0}EOP,
 413
 414   SOP(O(O_JSR,SB),6,"jsr"),{SRC|RSIND,E,0}, {0x5,0xD,B30|RSIND,0x0,E,0,0,0,0}EOP,
 415   SOP(O(O_JSR,SB),8,"jsr"),{SRC|ABSJMP,E,0},{0x5,0xE,SRC|ABSJMP,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,E}EOP,
 416   SOP(O(O_JSR,SB),8,"jsr"),{SRC|MEMIND,E,0},{0x5,0xF,SRC|MEMIND,IGNORE,E,0,0,0,0}EOP,
 417
 418   NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{IMM8,CCR,E},         { 0x0,0x7,IMM8,IGNORE,E,0,0,0,0}EOP,
 419   NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{OR8,CCR,E},          { 0x0,0x3,0x0,OR8,E,0,0,0,0}EOP,
 420   NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{ABS16SRC,CCR,E},     {PREFIXLDC,0x6,0xB,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}EOP,
 421   NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{ABS32SRC,CCR,E},     {PREFIXLDC,0x6,0xB,0x2,0x0,SRC|ABS32LIST,E}EOP,
 422   NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{DISP|SRC|L_16,CCR,E},{PREFIXLDC,0x6,0xF,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}EOP,
 423   NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{DISP|SRC|L_32,CCR,E},{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}EOP,
 424   NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{RSINC,CCR,E},        {PREFIXLDC,0x6,0xD,B30|RSINC,0x0,E}EOP,
 425   NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{RSIND,CCR,E},        {PREFIXLDC,0x6,0x9,B30|RDIND,0x0,E} EOP,
 426
 427   NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{IMM8,EXR,E},         { 0x0,0x1,0x4,0x1,0x0,0x7,IMM8,IGNORE,E,0,0,0,0}EOP,
 428   NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{OR8,EXR,E},          { 0x0,0x3,0x1,OR8,E,0,0,0,0}EOP,
 429   NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{ABS16SRC,EXR,E},     { 0x0,0x1,0x4,0x1,0x6,0xb,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}EOP,
 430   NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{ABS32SRC,EXR,E},     { 0x0,0x1,0x4,0x1,0x6,0xb,0x2,0x0,SRC|ABS32LIST,E}EOP,
 431   NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{DISP|SRC|L_16,EXR,E},{ 0x0,0x1,0x4,0x1,0x6,0xf,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}EOP,
 432   NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{DISP|SRC|L_32,EXR,E},{ 0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}EOP,
 433   NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{RSINC,EXR,E},        { 0x0,0x1,0x4,0x1,0x6,0xd,B30|RSINC,0x0,E}EOP,
 434   NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{RSIND,EXR,E},        { 0x0,0x1,0x4,0x1,0x6,0x9,B30|RDIND,0x0,E} EOP,
 435
 436   SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{ABS|SRC|L_16|MEMRELAX,RD8,E},  { 0x6,0xA,0x0,RD8,SRC|ABS|MEMRELAX|A16LIST,E}EOP,
 437   SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{ABS|SRC|L_32|MEMRELAX,RD8,E }, { 0x6,0xA,0x2,RD8,SRC|ABS|MEMRELAX|A32LIST,E }EOP,
 438   SOP(O(O_MOV_TO_MEM,SB),4,"mov.b"),{RS8,ABS|L_16|MEMRELAX|DST,E},     { 0x6,0xA,0x8,RS8,DST|ABS|MEMRELAX|A16LIST,E}EOP,
 439   SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{RS8,ABS|DST|L_32|MEMRELAX,E },    { 0x6,0xA,0xA,RS8,DST|ABS|MEMRELAX|A32LIST,E }EOP,
 440
 441   SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{DISP|L_32|SRC,RD8,E},  { 0x7,0x8,B30|DISPREG,0x0,0x6,0xA,0x2,RD8,SRC|DISP32LIST,E}EOP,
 442   SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{RS8,DISP|L_32|DST,E},  { 0x7,0x8,B30|DISPREG,0x0,0x6,0xA,0xA,RS8,DST|DISP32LIST,E}EOP,
 443
 444
 445
 446   SOP(O(O_MOV_TO_REG,SB),2,"mov.b"),{RS8,RD8,E},            { 0x0,0xC,RS8,RD8,E,0,0,0,0}EOP,
 447   SOP(O(O_MOV_TO_REG,SB),2,"mov.b"),{IMM8,RD8,E},           { 0xF,RD8,IMM8,IGNORE,E,0,0,0,0}EOP,
 448   SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{RSIND,RD8,E},          { 0x6,0x8,B30|RSIND,RD8,E,0,0,0,0}EOP,
 449   SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{DISP16SRC,RD8,E},      { 0x6,0xE,B30|DISPREG,RD8,DISP16SRC,IGNORE,IGNORE,IGNORE,E}EOP,
 450   SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{RSINC,RD8,E},          { 0x6,0xC,B30|RSINC,RD8,E,0,0,0,0}EOP,
 451
 452   SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{ABS8SRC,RD8,E},        { 0x2,RD8,ABS8SRC,IGNORE,E,0,0,0,0}EOP,
 453   SOP(O(O_MOV_TO_MEM,SB),4,"mov.b"),{RS8,RDIND,E},          { 0x6,0x8,RDIND|B31,RS8,E,0,0,0,0}EOP,
 454   SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{RS8,DISP16DST,E},      { 0x6,0xE,DISPREG|B31,RS8,DISP16DST,IGNORE,IGNORE,IGNORE,E}EOP,
 455   SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{RS8,RDDEC|B31,E},      { 0x6,0xC,RDDEC|B31,RS8,E,0,0,0,0}EOP,
 456
 457   SOP(O(O_MOV_TO_MEM,SB),4,"mov.b"),{RS8,ABS8DST,E},        { 0x3,RS8,ABS8DST,IGNORE,E,0,0,0,0}EOP,
 458
 459   SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{RS16,RDIND,E},        { 0x6,0x9,RDIND|B31,RS16,E,0,0,0,0}EOP,
 460   SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{DISP|L_32|SRC,RD16,E},{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xB,0x2,RD16,SRC|DISP32LIST,E}EOP,
 461   SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{RS16,DISP|L_32|DST,E},{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xB,0xA,RS16,DST|DISP32LIST,E}EOP,
 462   SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{ABS|L_32|MEMRELAX|SRC,RD16,E },{ 0x6,0xB,0x2,RD16,SRC|MEMRELAX|ABS32LIST,E }EOP,
 463   SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{RS16,ABS|L_32|MEMRELAX|DST,E },{ 0x6,0xB,0xA,RS16,DST|MEMRELAX|ABS32LIST,E }EOP,
 464   SOP(O(O_MOV_TO_REG,SW),2,"mov.w"),{RS16,RD16,E},         { 0x0,0xD,RS16, RD16,E,0,0,0,0}EOP,
 465   SOP(O(O_MOV_TO_REG,SW),4,"mov.w"),{IMM16,RD16,E},        { 0x7,0x9,0x0,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}EOP,
 466   SOP(O(O_MOV_TO_REG,SW),4,"mov.w"),{RSIND,RD16,E},        { 0x6,0x9,B30|RSIND,RD16,E,0,0,0,0}EOP,
 467   SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{DISP16SRC,RD16,E},    { 0x6,0xF,B30|DISPREG,RD16,DISP16SRC,IGNORE,IGNORE,IGNORE,E}EOP,
 468   SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{RSINC,RD16,E},        { 0x6,0xD,B30|RSINC,RD16,E,0,0,0,0}EOP,
 469   SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{ABS16SRC,RD16,E},     { 0x6,0xB,0x0,RD16,ABS16SRC,IGNORE,IGNORE,IGNORE,E}EOP,
 470
 471   SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{RS16,DISP16DST,E},    { 0x6,0xF,DISPREG|B31,RS16,DISP16DST,IGNORE,IGNORE,IGNORE,E}EOP,
 472   SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{RS16,RDDEC,E},        { 0x6,0xD,RDDEC|B31,RS16,E,0,0,0,0}EOP,
 473   SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{RS16,ABS16DST,E},     { 0x6,0xB,0x8,RS16,ABS16DST,IGNORE,IGNORE,IGNORE,E}EOP,
 474
 475   SOP(O(O_MOV_TO_REG,SL),4,"mov.l"),{IMM32,RD32,E},        { 0x7,0xA,0x0,B30|RD32,IMM32LIST,E}EOP,
 476   SOP(O(O_MOV_TO_REG,SL),2,"mov.l"),{RS32,RD32,E},         { 0x0,0xF,B31|RS32,B30|RD32,E,0,0,0,0}EOP,
 477
 478   SOP(O(O_MOV_TO_REG,SL),4,"mov.l"),{RSIND,RD32,E},        { PREFIX32,0x6,0x9,RSIND|B30,B30|RD32,E,0,0,0,0 }EOP,
 479   SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{DISP16SRC,RD32,E},    { PREFIX32,0x6,0xF,DISPREG|B30,B30|RD32,DISP16SRC,IGNORE,IGNORE,IGNORE,E }EOP,
 480   SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{DISP|L_32|SRC,RD32,E},{ PREFIX32,0x7,0x8,B30|DISPREG,0x0,0x6,0xB,0x2,B30|RD32,SRC|DISP32LIST,E }EOP,
 481   SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{RSINC,RD32,E},        { PREFIX32,0x6,0xD,B30|RSINC,B30|RD32,E,0,0,0,0 }EOP,
 482   SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{ABS16SRC,RD32,E},     { PREFIX32,0x6,0xB,0x0,B30|RD32,ABS16SRC,IGNORE,IGNORE,IGNORE,E }EOP,
 483   SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{ABS32SRC|MEMRELAX,RD32,E },    { PREFIX32,0x6,0xB,0x2,B30|RD32,SRC|MEMRELAX|ABS32LIST,E }EOP,
 484   SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{RS32,RDIND,E},        { PREFIX32,0x6,0x9,RDIND|B31,B30|RS32,E,0,0,0,0 }EOP,
 485   SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{RS32,DISP16DST,E},    { PREFIX32,0x6,0xF,DISPREG|B31,B30|RS32,DISP16DST,IGNORE,IGNORE,IGNORE,E }EOP,
 486   SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{RS32,DISP|L_32|DST,E},{ PREFIX32,0x7,0x8,B31|DISPREG,0x0,0x6,0xB,0xA,B30|RS32,DST|DISP32LIST,E }EOP,
 487   SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{RS32,RDDEC,E},        { PREFIX32,0x6,0xD,RDDEC|B31,B30|RS32,E,0,0,0,0 }EOP,
 488   SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{RS32,ABS16DST,E},     { PREFIX32,0x6,0xB,0x8,B30|RS32,ABS16DST,IGNORE,IGNORE,IGNORE,E }EOP,
 489   SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{RS32,ABS32DST|MEMRELAX,E },    { PREFIX32,0x6,0xB,0xA,B30|RS32,DST|MEMRELAX|ABS32LIST,E }EOP,
 490
 491   SOP(O(O_MOV_TO_REG,SB),10,"movfpe"),{ABS16SRC,RD8,E},{ 0x6,0xA,0x4,RD8,ABS16SRC,IGNORE,IGNORE,IGNORE,E}EOP,
 492   SOP(O(O_MOV_TO_MEM,SB),10,"movtpe"),{RS8,ABS16DST,E},{ 0x6,0xA,0xC,RS8,ABS16DST,IGNORE,IGNORE,IGNORE,E}EOP,
 493
 494   NEW_SOP(O(O_MULU,SB),1,14,"mulxu.b"),{RS8,RD16,E}, { 0x5,0x0,RS8,RD16,E,0,0,0,0}EOP,
 495   NEW_SOP(O(O_MULU,SW),0,14,"mulxu.w"),{RS16,RD32,E},{ 0x5,0x2,RS16,B30|RD32,E,0,0,0,0}EOP,
 496
 497   NEW_SOP(O(O_MULS,SB),0,20,"mulxs.b"),{RS8,RD16,E}, { 0x0,0x1,0xc,0x0,0x5,0x0,RS8,RD16,E}EOP,
 498   NEW_SOP(O(O_MULS,SW),0,20,"mulxs.w"),{RS16,RD32,E},{ 0x0,0x1,0xc,0x0,0x5,0x2,RS16,B30|RD32,E}EOP,
 499
 500   /* ??? This can use UNOP3.  */
 501   NEW_SOP(O(O_NEG,SB),1,2,"neg.b"),{ OR8,E, 0},{ 0x1,0x7,0x8,OR8,E,0,0,0,0}EOP,
 502   NEW_SOP(O(O_NEG,SW),0,2,"neg.w"),{ OR16,E,0},{ 0x1,0x7,0x9,OR16,E}EOP,
 503   NEW_SOP(O(O_NEG,SL),0,2,"neg.l"),{ OR32,E,0},{ 0x1,0x7,0xB,B30|OR32,E}EOP,
 504
 505   NEW_SOP(O(O_NOP,SB),1,2,"nop"),{E,0,0},{ 0x0,0x0,0x0,0x0,E,0,0,0,0}EOP,
 506
 507   /* ??? This can use UNOP3.  */
 508   NEW_SOP(O(O_NOT,SB),1,2,"not.b"),{ OR8,E, 0},{ 0x1,0x7,0x0,OR8,E,0,0,0,0}EOP,
 509   NEW_SOP(O(O_NOT,SW),0,2,"not.w"),{ OR16,E,0},{ 0x1,0x7,0x1,OR16,E}EOP,
 510   NEW_SOP(O(O_NOT,SL),0,2,"not.l"),{ OR32,E,0},{ 0x1,0x7,0x3,B30|OR32,E}EOP,
 511
 512   TWOOP(O(O_OR, SB),"or.b",0xC,0x1,0x4),
 513   NEW_SOP(O(O_OR,SW),0,4,"or.w"),{IMM16,RD16,E },{0x7,0x9,0x4,RD16,IMM16,IGNORE,IGNORE,IGNORE,E} EOP,
 514   NEW_SOP(O(O_OR,SW),0,2,"or.w"),{RS16,RD16,E },{0x6,0x4,RS16,RD16,E} EOP,
 515
 516   NEW_SOP(O(O_OR,SL),0,6,"or.l"),{IMM32,RD32,E },{0x7,0xA,0x4,B30|RD32,IMM32LIST,E} EOP,
 517   NEW_SOP(O(O_OR,SL),0,2,"or.l"),{RS32,RD32,E },{0x0,0x1,0xF,0x0,0x6,0x4,B30|RS32,B30|RD32,E} EOP,
 518
 519   NEW_SOP(O(O_ORC,SB),1,2,"orc"),{IMM8,CCR,E},{ 0x0,0x4,IMM8,IGNORE,E,0,0,0,0}EOP,
 520   NEW_SOP(O(O_ORC,SB),1,2,"orc"),{IMM8,EXR,E},{ 0x0,0x1,0x4,0x1,0x0,0x4,IMM8,IGNORE,E,0,0,0,0}EOP,
 521
 522   NEW_SOP(O(O_MOV_TO_REG,SW),1,6,"pop.w"),{OR16,E,0},{ 0x6,0xD,0x7,OR16,E,0,0,0,0}EOP,
 523   NEW_SOP(O(O_MOV_TO_REG,SL),0,6,"pop.l"),{OR32,E,0},{ PREFIX32,0x6,0xD,0x7,OR32|B30,E,0,0,0,0}EOP,
 524   NEW_SOP(O(O_MOV_TO_MEM,SW),1,6,"push.w"),{OR16,E,0},{ 0x6,0xD,0xF,OR16,E,0,0,0,0}EOP,
 525   NEW_SOP(O(O_MOV_TO_MEM,SL),0,6,"push.l"),{OR32,E,0},{ PREFIX32,0x6,0xD,0xF,OR32|B30,E,0,0,0,0}EOP,
 526
 527   UNOP3(O_ROTL,  "rotl", 0x1,0x2,0x8),
 528   UNOP3(O_ROTR,  "rotr", 0x1,0x3,0x8),
 529   UNOP3(O_ROTXL, "rotxl",0x1,0x2,0x0),
 530   UNOP3(O_ROTXR, "rotxr",0x1,0x3,0x0),
 531
 532   SOP(O(O_BPT,SB),  10,"bpt"),{E,0,0},{ 0x7,0xA,0xF,0xF,E,0,0,0,0}EOP,
 533   SOP(O(O_RTE,SB),  10,"rte"),{E,0,0},{ 0x5,0x6,0x7,0x0,E,0,0,0,0}EOP,
 534   SOP(O(O_RTS,SB),   8,"rts"),{E,0,0},{ 0x5,0x4,0x7,0x0,E,0,0,0,0}EOP,
 535
 536   UNOP3(O_SHAL,  "shal",0x1,0x0,0x8),
 537   UNOP3(O_SHAR,  "shar",0x1,0x1,0x8),
 538   UNOP3(O_SHLL,  "shll",0x1,0x0,0x0),
 539   UNOP3(O_SHLR,  "shlr",0x1,0x1,0x0),
 540
 541   SOP(O(O_SLEEP,SB),2,"sleep"),{E,0,0},{ 0x0,0x1,0x8,0x0,E,0,0,0,0} EOP,
 542
 543   NEW_SOP(O(O_STC,SB), 1,2,"stc"),{CCR,RD8,E},{ 0x0,0x2,0x0,RD8,E,0,0,0,0} EOP,
 544
 545   NEW_SOP(O(O_STC,SB),0,2,"stc"),{CCR,RSIND,E},        {PREFIXLDC,0x6,0x9,B31|RDIND,0x0,E} EOP,
 546   NEW_SOP(O(O_STC,SB),0,2,"stc"),{CCR,DISP|DST|L_16,E},{PREFIXLDC,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}EOP,
 547   NEW_SOP(O(O_STC,SB),0,2,"stc"),{CCR,DISP|DST|L_32,E},{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}EOP,
 548   NEW_SOP(O(O_STC,SB),0,2,"stc"),{CCR,RDDEC,E},        {PREFIXLDC,0x6,0xD,B31|RDDEC,0x0,E}EOP,
 549
 550   NEW_SOP(O(O_STC,SB),0,2,"stc"),{CCR,ABS16SRC,E},     {PREFIXLDC,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}EOP,
 551   NEW_SOP(O(O_STC,SB),0,2,"stc"),{CCR,ABS32SRC,E},     {PREFIXLDC,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}EOP,
 552
 553   NEW_SOP(O(O_STC,SB), 1,2,"stc"),{EXR,RD8,E},{ 0x0,0x2,0x1,RD8,E,0,0,0,0} EOP,
 554
 555   NEW_SOP(O(O_STC,SB),0,2,"stc"),{EXR,RSIND,E},        {0x0,0x1,0x4,0x1,0x6,0x9,B31|RDIND,0x0,E} EOP,
 556   NEW_SOP(O(O_STC,SB),0,2,"stc"),{EXR,DISP|DST|L_16,E},{0x0,0x1,0x4,0x1,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}EOP,
 557   NEW_SOP(O(O_STC,SB),0,2,"stc"),{EXR,DISP|DST|L_32,E},{0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}EOP,
 558   NEW_SOP(O(O_STC,SB),0,2,"stc"),{EXR,RDDEC,E},        {0x0,0x1,0x4,0x1,0x6,0xD,B31|RDDEC,0x0,E}EOP,
 559
 560   NEW_SOP(O(O_STC,SB),0,2,"stc"),{EXR,ABS16SRC,E},     {0x0,0x1,0x4,0x1,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}EOP,
 561   NEW_SOP(O(O_STC,SB),0,2,"stc"),{EXR,ABS32SRC,E},     {0x0,0x1,0x4,0x1,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}EOP,
 562
 563   SOP(O(O_SUB,SB),2,"sub.b"),{RS8,RD8,E},{ 0x1,0x8,RS8,RD8,E,0,0,0,0}EOP,
 564
 565   NEW_SOP(O(O_SUB,SW),1,2,"sub.w"),{RS16,RD16,E },  {0x1,0x9,RS16,RD16,E} EOP,
 566   NEW_SOP(O(O_SUB,SW),0,4,"sub.w"),{IMM16,RD16,E }, {0x7,0x9,0x3,RD16,IMM16,IGNORE,IGNORE,IGNORE,E} EOP,
 567   NEW_SOP(O(O_SUB,SL),0,2,"sub.l") ,{RS32,RD32,E }, {0x1,0xA,B31|RS32,B30|RD32,E} EOP,
 568   NEW_SOP(O(O_SUB,SL),0,6,"sub.l"), {IMM32,RD32,E },{0x7,0xA,0x3,B30|RD32,IMM32LIST,E} EOP,
 569
 570   SOP(O(O_SUBS,SL),2,"subs"),{KBIT,RDP,E},{ 0x1,0xB,KBIT,RDP,E,0,0,0,0}EOP,
 571   TWOOP(O(O_SUBX,SB),"subx",0xB,0x1,0xE),
 572
 573   NEW_SOP(O(O_TRAPA,SB),0,2,"trapa"),{ IMM2,E},  {0x5,0x7,IMM2,IGNORE,E  }EOP,
 574   NEW_SOP(O(O_TAS,SB),0,2,"tas"),{RSIND,E},  {0x0,0x1,0xe,0x0,0x7,0xb,B30|RSIND,0xc,E  }EOP,
 575
 576   TWOOP(O(O_XOR, SB),"xor",0xD,0x1,0x5),
 577
 578   NEW_SOP(O(O_XOR,SW),0,4,"xor.w"),{IMM16,RD16,E },{0x7,0x9,0x5,RD16,IMM16,IGNORE,IGNORE,IGNORE,E} EOP,
 579   NEW_SOP(O(O_XOR,SW),0,2,"xor.w"),{RS16,RD16,E },{0x6,0x5,RS16,RD16,E} EOP,
 580
 581   NEW_SOP(O(O_XOR,SL),0,6,"xor.l"),{IMM32,RD32,E },{0x7,0xA,0x5,B30|RD32,IMM32LIST,E} EOP,
 582   NEW_SOP(O(O_XOR,SL),0,2,"xor.l") ,{RS32,RD32,E },{0x0,0x1,0xF,0x0,0x6,0x5,B30|RS32,B30|RD32,E} EOP,
 583
 584   SOP(O(O_XORC,SB),2,"xorc"),{IMM8,CCR,E},{ 0x0,0x5,IMM8,IGNORE,E,0,0,0,0}EOP,
 585   SOP(O(O_XORC,SB),2,"xorc"),{IMM8,EXR,E},{ 0x0,0x1,0x4,0x1,0x0,0x5,IMM8,IGNORE,E,0,0,0,0}EOP,
 586
 587   NEW_SOP(O(O_CLRMAC,SL),1,2,"clrmac"),{E, 0, 0},{0x0,0x1,0xa,0x0,E} EOP,
 588   NEW_SOP(O(O_MAC,SL),1,2,"mac"),{RSINC,RDINC,E},{0x0,0x1,0x6,0x0,0x6,0xd,B30|RSINC,B30|RDINC,E} EOP,
 589   NEW_SOP(O(O_LDMAC,SL),1,2,"ldmac"),{RS32,MACREG,E},{0x0,0x3,MACREG,RS32,E} EOP,
 590   NEW_SOP(O(O_LDM,SL),0,6,"ldm.l"),{RSINC, RS32, E},{ 0x0,0x1,IGNORE,0x0,0x6,0xD,0x7,IGNORE,E}EOP,
 591   NEW_SOP(O(O_STM,SL),0,6,"stm.l"),{RS32, RDDEC, E},{0x0,0x1,IGNORE,0x0,0x6,0xD,0xF,IGNORE,E}EOP,
 592   0
 593 };
 594 #else
 595 extern struct h8_opcode h8_opcodes[] ;
 596 #endif
 597
 598
 599
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