include/opcode/h8300.h

   1 /* Opcode table for the H8/300
   2    Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2002, 2003
   3    Free Software Foundation, Inc.
   4    Written by Steve Chamberlain <sac@cygnus.com>.
   5
   6    This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 2 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
  21    02111-1307, USA.  */
  22
  23 /* Instructions are stored as a sequence of nibbles.
  24    If the nibble has value 15 or less than the representation is complete.
  25    Otherwise, we record what it contains with several flags.  */
  26
  27 typedef int op_type;
  28
  29 #define Hex0    0
  30 #define Hex1    1
  31 #define Hex2    2
  32 #define Hex3    3
  33 #define Hex4    4
  34 #define Hex5    5
  35 #define Hex6    6
  36 #define Hex7    7
  37 #define Hex8    8
  38 #define Hex9    9
  39 #define HexA    10
  40 #define HexB    11
  41 #define HexC    12
  42 #define HexD    13
  43 #define HexE    14
  44 #define HexF    15
  45
  46 #define L_8             0x01
  47 #define L_16            0x02
  48 #define L_32            0x04
  49 #define L_P             0x08
  50 #define L_24            0x10
  51 #define MEMRELAX        0x20                    /* Move insn which may relax.  */
  52 #define SRC             0x40
  53 #define DST             0x80
  54
  55 #define REG             0x100
  56 #define EXR             0x200
  57 #define MACREG          0x800
  58 #define SRC_IN_DST      0x400
  59 #define IMM             0x1000
  60 #define DISP            0x2000
  61 #define IND             0x4000
  62 #define INC             0x8000
  63 #define DEC             0x10000
  64 #define L_3             0x20000
  65 #define KBIT            0x40000
  66 #define DBIT            0x80000
  67 #define DISPREG         0x100000
  68 #define IGNORE          0x200000
  69 #define E               0x400000                /* FIXME: end of nibble sequence?  */
  70 #define L_2             0x800000
  71 #define B30             0x1000000               /* Bit 3 must be low.  */
  72 #define B31             0x2000000               /* Bit 3 must be high.  */
  73 #define CCR             0x4000000
  74 #define ABS             0x8000000
  75 #define ABSJMP          0x10000000
  76 #define ABS8MEM         0x20000000
  77 #define PCREL           0x40000000
  78 #define MEMIND          0x80000000
  79
  80 #define IMM3            IMM | L_3
  81 #define IMM2            IMM | L_2
  82
  83 #define SIZE            (L_2 | L_3 | L_8 | L_16 | L_32 | L_P | L_24)
  84 #define MODE            (REG | IMM | DISP | IND | INC | DEC | CCR | ABS | MEMIND | EXR)
  85
  86 #define RD8             (DST | L_8  | REG)
  87 #define RD16            (DST | L_16 | REG)
  88 #define RD32            (DST | L_32 | REG)
  89 #define RS8             (SRC | L_8  | REG)
  90 #define RS16            (SRC | L_16 | REG)
  91 #define RS32            (SRC | L_32 | REG)
  92
  93 #define RSP             (SRC | L_P | REG)
  94 #define RDP             (DST | L_P | REG)
  95
  96 #define IMM8            (IMM | SRC | L_8)
  97 #define IMM16           (IMM | SRC | L_16)
  98 #define IMM32           (IMM | SRC | L_32)
  99
 100 #define ABS8SRC         (SRC | ABS | L_8 | ABS8MEM)
 101 #define ABS8DST         (DST | ABS | L_8 | ABS8MEM)
 102
 103 #define DISP8           (PCREL | L_8)
 104 #define DISP16          (PCREL | L_16)
 105
 106 #define DISP8SRC        (DISP | L_8  | SRC)
 107 #define DISP16SRC       (DISP | L_16 | SRC)
 108
 109 #define DISP8DST        (DISP | L_8  | DST)
 110 #define DISP16DST       (DISP | L_16 | DST)
 111
 112 #define ABS16SRC        (SRC | ABS | L_16)
 113 #define ABS16DST        (DST | ABS | L_16)
 114 #define ABS24SRC        (SRC | ABS | L_24)
 115 #define ABS24DST        (DST | ABS | L_24)
 116 #define ABS32SRC        (SRC | ABS | L_32)
 117 #define ABS32DST        (DST | ABS | L_32)
 118
 119 #define RDDEC           (DST | DEC)
 120 #define RSINC           (SRC | INC)
 121 #define RDINC           (DST | INC)
 122
 123 #define RDIND           (DST | IND)
 124 #define RSIND           (SRC | IND)
 125
 126 #define MS32            (SRC | L_32 | MACREG)
 127 #define MD32            (DST | L_32 | MACREG)
 128
 129 #if 1
 130 #define OR8 RS8         /* ??? OR as in One Register?  */
 131 #define OR16 RS16
 132 #define OR32 RS32
 133 #else
 134 #define OR8 RD8
 135 #define OR16 RD16
 136 #define OR32 RD32
 137 #endif
 138
 139 struct code
 140 {
 141   op_type nib[30];
 142 };
 143
 144 struct arg
 145 {
 146   op_type nib[3];
 147 };
 148
 149 struct h8_opcode
 150 {
 151   int how;
 152   int inbase;
 153   int time;
 154   char *name;
 155   struct arg args;
 156   struct code data;
 157 };
 158
 159 #ifdef DEFINE_TABLE
 160
 161 #define BITOP(code, imm, name, op00, op01,op10,op11, op20,op21,op30)\
 162 { code, 1, 2, name,     {{imm,RD8,E}},  {{op00, op01, imm, RD8, E, 0, 0, 0, 0}}},\
 163 { code, 1, 6, name,     {{imm,RDIND,E}},{{op10, op11, B30|RDIND, 0, op00,op01, imm, 0, E}}},\
 164 { code, 1, 6, name,     {{imm,ABS8DST,E}},{{op20, op21, ABS8DST, IGNORE, op00,op01, imm, 0,E}}}\
 165 ,{ code, 0, 6, name,    {{imm,ABS16DST,E}},{{0x6,0xa,0x1,op30,ABS16DST,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}}},\
 166 { code, 0, 6, name,     {{imm,ABS32DST,E}},{{0x6,0xa,0x3,op30,ABS32DST,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE, op00,op01, imm, 0,E}}}
 167
 168
 169 #define EBITOP(code, imm, name, op00, op01,op10,op11, op20,op21,op30)\
 170    BITOP(code,imm, name, op00+1, op01, op10,op11, op20,op21,op30),\
 171    BITOP(code,RS8,  name, op00, op01, op10,op11, op20,op21,op30)
 172
 173 #define WTWOP(code,name, op1, op2) \
 174 { code, 1, 2, name, {{RS16, RD16, E}}, {{ op1, op2, RS16, RD16, E, 0, 0, 0, 0}}}
 175
 176 #define BRANCH(code, name, op) \
 177 { code, 1, 4,name,{{DISP8,E,0}}, {{ 0x4, op, DISP8, IGNORE, E, 0, 0, 0, 0}}}, \
 178 { code, 0, 6,name,{{DISP16,E,0}}, {{ 0x5, 0x8, op, 0x0, DISP16, IGNORE, IGNORE, IGNORE, E,0}}}
 179
 180 #define SOP(code, x,name) \
 181 {code, 1, x,  name
 182
 183 #define NEW_SOP(code, in,x,name) \
 184 {code, in, x,  name
 185 #define EOP  }
 186
 187 #define TWOOP(code, name, op1, op2,op3) \
 188 { code,1, 2,name, {{IMM8, RD8, E}},     {{ op1, RD8, IMM8, IGNORE, E, 0, 0, 0, 0}}},\
 189 { code, 1, 2,name, {{RS8, RD8, E}},     {{ op2, op3, RS8, RD8, E, 0, 0, 0, 0}}}
 190
 191 #define UNOP(code,name, op1, op2) \
 192 { code, 1, 2, name, {{OR8, E, 0}}, {{ op1, op2, 0, OR8, E, 0, 0, 0, 0}}}
 193
 194 #define UNOP3(code, name, op1, op2, op3) \
 195 { O(code,SB), 1, 2, name, {{OR8,  E, 0}}, {{op1, op2, op3+0, OR8,  E, 0, 0, 0, 0}}}, \
 196 { O(code,SW), 0, 2, name, {{OR16, E, 0}}, {{op1, op2, op3+1, OR16, E, 0, 0, 0, 0}}}, \
 197 { O(code,SL), 0, 2, name, {{OR32, E, 0}}, {{op1, op2, op3+3, OR32|B30, E, 0, 0, 0, 0}}} \
 198 ,{ O(code,SB), 1, 2, name, {{IMM, OR8 | SRC_IN_DST,  E}}, {{op1, op2, op3+4, OR8 | SRC_IN_DST,  E, 0, 0, 0, 0}}}, \
 199 { O(code,SW), 0, 2, name, {{IMM, OR16 | SRC_IN_DST, E}}, {{op1, op2, op3+5, OR16 | SRC_IN_DST, E, 0, 0, 0, 0}}}, \
 200 { O(code,SL), 0, 2, name, {{IMM, OR32 | SRC_IN_DST, E}}, {{op1, op2, op3+7, OR32 | SRC_IN_DST|B30 , E, 0, 0, 0, 0}}}
 201
 202
 203 #define IMM32LIST IMM32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
 204 #define IMM24LIST IMM24,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
 205 #define IMM16LIST IMM16,IGNORE,IGNORE,IGNORE
 206 #define A16LIST L_16,IGNORE,IGNORE,IGNORE
 207 #define DISP24LIST DISP|L_24,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
 208 #define DISP32LIST DISP|L_32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
 209 #define ABS24LIST ABS|L_24,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
 210 #define ABS32LIST ABS|L_32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
 211 #define A24LIST L_24,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
 212 #define A32LIST L_32,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE
 213 #define PREFIX32 0x0,0x1,0x0,0x0
 214 #define PREFIXLDC 0x0,0x1,0x4,0x0
 215
 216
 217 #define O(op, size) (op * 4 + size)
 218
 219 #define O_RECOMPILE 0
 220 #define O_ADD  1
 221 #define O_ADDX 2
 222 #define O_AND  3
 223 #define O_BAND 4
 224 #define O_BRA  5
 225 #define O_BRN  6
 226 #define O_BHI  7
 227 #define O_BLS  8
 228 #define O_BCC  9
 229 #define O_BCS  10
 230 #define O_BNE  11
 231 #define O_BVC  12
 232 #define O_BVS  13
 233 #define O_BPL  14
 234 #define O_BMI  15
 235 #define O_BGE  16
 236 #define O_BLT  17
 237 #define O_BGT  18
 238 #define O_BLE  19
 239 #define O_ANDC 20
 240 #define O_BEQ 21
 241 #define O_BCLR 22
 242 #define O_BIAND 23
 243 #define O_BILD 24
 244 #define O_BIOR 25
 245 #define O_BIXOR 26
 246 #define O_BIST 27
 247 #define O_BLD 28
 248 #define O_BNOT 29
 249 #define O_BSET 30
 250 #define O_BSR 31
 251 #define O_BXOR 32
 252 #define O_CMP 33
 253 #define O_DAA 34
 254 #define O_DAS 35
 255 #define O_DEC 36
 256 #define O_DIVU 37
 257 #define O_DIVS 38
 258 #define O_INC 39
 259 #define O_LDC 40
 260 #define O_MOV_TO_MEM 41
 261 #define O_OR 42
 262 #define O_ROTL 43
 263 #define O_ROTR 44
 264 #define O_ROTXL 45
 265 #define O_ROTXR 46
 266 #define O_BPT 47
 267 #define O_SHAL 48
 268 #define O_SHAR 49
 269 #define O_SHLL 50
 270 #define O_SHLR 51
 271 #define O_SUB  52
 272 #define O_SUBS 53
 273 #define O_TRAPA 54
 274 #define O_XOR 55
 275 #define O_XORC 56
 276 #define O_BOR 57
 277 #define O_BST 58
 278 #define O_BTST 59
 279 #define O_EEPMOV 60
 280 #define O_EXTS 61
 281 #define O_EXTU 62
 282 #define O_JMP 63
 283 #define O_JSR 64
 284 #define O_MULU 65
 285 #define O_MULS 66
 286 #define O_NOP 67
 287 #define O_NOT 68
 288 #define O_ORC 69
 289 #define O_RTE 70
 290 #define O_STC 71
 291 #define O_SUBX 72
 292 #define O_NEG 73
 293 #define O_RTS 74
 294 #define O_SLEEP 75
 295 #define O_ILL 76
 296 #define O_ADDS 77
 297 #define O_SYSCALL 78
 298 #define O_MOV_TO_REG 79
 299 #define O_TAS 80
 300 #define O_CLRMAC 82
 301 #define O_LDMAC 83
 302 #define O_MAC 84
 303 #define O_LDM 85
 304 #define O_STM 86
 305 #define O_STMAC 87
 306 #define O_LAST 88
 307 /* Change made for System Call processing.  */
 308 #define O_SYS_CREAT 100
 309 #define O_SYS_OPEN 101
 310 #define O_SYS_READ 102
 311 #define O_SYS_WRITE 103
 312 #define O_SYS_LSEEK 104
 313 #define O_SYS_CLOSE 105
 314 #define O_SYS_STAT 106
 315 #define O_SYS_FSTAT 107
 316 /* End of System Call specific Changes.  */
 317 #define SB 0
 318 #define SW 1
 319 #define SL 2
 320 #define SN 3
 321
 322 /* FIXME: Lots of insns have "E, 0, 0, 0, 0" in the nibble code sequences.
 323    Methinks the zeroes aren't necessary.  Once confirmed, nuke 'em.  */
 324
 325 const struct h8_opcode h8_opcodes[] =
 326 {
 327   TWOOP(O(O_ADD,SB),"add.b", 0x8, 0x0,0x8),
 328
 329   NEW_SOP(O(O_ADD,SW),1,2,"add.w"),{{RS16,RD16,E}},{{0x0,0x9,RS16,RD16,E}} EOP,
 330   NEW_SOP(O(O_ADD,SW),0,4,"add.w"),{{IMM16,RD16,E}},{{0x7,0x9,0x1,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP,
 331   NEW_SOP(O(O_ADD,SL),0,2,"add.l"),{{RS32,RD32,E }}, {{0x0,0xA,B31|RS32,B30|RD32,E}} EOP,
 332   NEW_SOP(O(O_ADD,SL),0,6,"add.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x1,B30|RD32,IMM32LIST,E}} EOP,
 333   NEW_SOP(O(O_ADDS,SL),1,2,"adds"), {{KBIT,RDP,E}},   {{0x0,0xB,KBIT,RDP,E,0,0,0,0}} EOP,
 334
 335   TWOOP(O(O_ADDX,SB),"addx",0x9,0x0,0xE),
 336   TWOOP(O(O_AND,SB), "and.b",0xE,0x1,0x6),
 337
 338   NEW_SOP(O(O_AND,SW),0,2,"and.w"),{{RS16,RD16,E }},{{0x6,0x6,RS16,RD16,E}} EOP,
 339   NEW_SOP(O(O_AND,SW),0,4,"and.w"),{{IMM16,RD16,E }},{{0x7,0x9,0x6,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP,
 340
 341   NEW_SOP(O(O_AND,SL),0,6,"and.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x6,B30|RD32,IMM32LIST,E}} EOP,
 342   NEW_SOP(O(O_AND,SL),0,2,"and.l") ,{{RS32,RD32,E }},{{0x0,0x1,0xF,0x0,0x6,0x6,B30|RS32,B30|RD32,E}} EOP,
 343
 344   NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {{IMM8,CCR|DST,E}},{{ 0x0,0x6,IMM8,IGNORE,E,0,0,0,0}} EOP,
 345   NEW_SOP(O(O_ANDC,SB),1,2,"andc"), {{IMM8,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x6,IMM8,IGNORE,E,0,0,0,0}} EOP,
 346
 347   BITOP(O(O_BAND,SB), IMM3|B30,"band",0x7,0x6,0x7,0xC,0x7,0xE,0x0),
 348   BRANCH(O(O_BRA,SB),"bra",0x0),
 349   BRANCH(O(O_BRA,SB),"bt",0x0),
 350   BRANCH(O(O_BRN,SB),"brn",0x1),
 351   BRANCH(O(O_BRN,SB),"bf",0x1),
 352   BRANCH(O(O_BHI,SB),"bhi",0x2),
 353   BRANCH(O(O_BLS,SB),"bls",0x3),
 354   BRANCH(O(O_BCC,SB),"bcc",0x4),
 355   BRANCH(O(O_BCC,SB),"bhs",0x4),
 356   BRANCH(O(O_BCS,SB),"bcs",0x5),
 357   BRANCH(O(O_BCS,SB),"blo",0x5),
 358   BRANCH(O(O_BNE,SB),"bne",0x6),
 359   BRANCH(O(O_BEQ,SB),"beq",0x7),
 360   BRANCH(O(O_BVC,SB),"bvc",0x8),
 361   BRANCH(O(O_BVS,SB),"bvs",0x9),
 362   BRANCH(O(O_BPL,SB),"bpl",0xA),
 363   BRANCH(O(O_BMI,SB),"bmi",0xB),
 364   BRANCH(O(O_BGE,SB),"bge",0xC),
 365   BRANCH(O(O_BLT,SB),"blt",0xD),
 366   BRANCH(O(O_BGT,SB),"bgt",0xE),
 367   BRANCH(O(O_BLE,SB),"ble",0xF),
 368
 369   EBITOP(O(O_BCLR,SB),IMM3|B30,"bclr", 0x6,0x2,0x7,0xD,0x7,0xF,0x8),
 370   BITOP(O(O_BIAND,SB),IMM3|B31,"biand",0x7,0x6,0x7,0xC,0x7,0xE,0x0),
 371   BITOP(O(O_BILD,SB), IMM3|B31,"bild", 0x7,0x7,0x7,0xC,0x7,0xE,0x0),
 372   BITOP(O(O_BIOR,SB), IMM3|B31,"bior", 0x7,0x4,0x7,0xC,0x7,0xE,0x0),
 373   BITOP(O(O_BIST,SB), IMM3|B31,"bist", 0x6,0x7,0x7,0xD,0x7,0xF,0x8),
 374   BITOP(O(O_BIXOR,SB),IMM3|B31,"bixor",0x7,0x5,0x7,0xC,0x7,0xE,0x0),
 375   BITOP(O(O_BLD,SB),  IMM3|B30,"bld",  0x7,0x7,0x7,0xC,0x7,0xE,0x0),
 376   EBITOP(O(O_BNOT,SB),IMM3|B30,"bnot", 0x6,0x1,0x7,0xD,0x7,0xF,0x8),
 377   BITOP(O(O_BOR,SB),  IMM3|B30,"bor",  0x7,0x4,0x7,0xC,0x7,0xE,0x0),
 378   EBITOP(O(O_BSET,SB),IMM3|B30,"bset", 0x6,0x0,0x7,0xD,0x7,0xF,0x8),
 379
 380   SOP(O(O_BSR,SB),6,"bsr"),{{DISP8,E,0}},{{ 0x5,0x5,DISP8,IGNORE,E,0,0,0,0}} EOP,
 381   SOP(O(O_BSR,SB),6,"bsr"),{{DISP16,E,0}},{{ 0x5,0xC,0x0,0x0,DISP16,IGNORE,IGNORE,IGNORE,E,0,0,0,0}} EOP,
 382   BITOP(O(O_BST,SB), IMM3|B30,"bst",0x6,0x7,0x7,0xD,0x7,0xF,0x8),
 383   EBITOP(O(O_BTST,SB), IMM3|B30,"btst",0x6,0x3,0x7,0xC,0x7,0xE,0x0),
 384   BITOP(O(O_BXOR,SB), IMM3|B30,"bxor",0x7,0x5,0x7,0xC,0x7,0xE,0x0),
 385
 386   TWOOP(O(O_CMP,SB), "cmp.b",0xA,0x1,0xC),
 387   WTWOP(O(O_CMP,SW), "cmp.w",0x1,0xD),
 388
 389   NEW_SOP(O(O_CMP,SW),1,2,"cmp.w"),{{RS16,RD16,E }},{{0x1,0xD,RS16,RD16,E}} EOP,
 390   NEW_SOP(O(O_CMP,SW),0,4,"cmp.w"),{{IMM16,RD16,E }},{{0x7,0x9,0x2,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP,
 391
 392   NEW_SOP(O(O_CMP,SL),0,6,"cmp.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x2,B30|RD32,IMM32LIST,E}} EOP,
 393   NEW_SOP(O(O_CMP,SL),0,2,"cmp.l") ,{{RS32,RD32,E }},{{0x1,0xF,B31|RS32,B30|RD32,E}} EOP,
 394
 395   UNOP(O(O_DAA,SB), "daa",0x0,0xF),
 396   UNOP(O(O_DAS,SB), "das",0x1,0xF),
 397   UNOP(O(O_DEC,SB), "dec.b",0x1,0xA),
 398
 399   NEW_SOP(O(O_DEC, SW),0,2,"dec.w") ,{{DBIT,RD16,E }},{{0x1,0xB,0x5|DBIT,RD16,E}} EOP,
 400   NEW_SOP(O(O_DEC, SL),0,2,"dec.l") ,{{DBIT,RD32,E }},{{0x1,0xB,0x7|DBIT,RD32|B30,E}} EOP,
 401
 402   NEW_SOP(O(O_DIVU,SB),1,13,"divxu.b"), {{RS8,RD16,E}}, {{0x5,0x1,RS8,RD16,E,0,0,0,0}}EOP,
 403   NEW_SOP(O(O_DIVU,SW),0,21,"divxu.w"),{{RS16,RD32,E}},{{0x5,0x3,RS16,B30|RD32,E}}EOP,
 404
 405   NEW_SOP(O(O_DIVS,SB),0,13,"divxs.b") ,{{RS8,RD16,E }},{{0x0,0x1,0xD,0x0,0x5,0x1,RS8,RD16,E}} EOP,
 406   NEW_SOP(O(O_DIVS,SW),0,21,"divxs.w") ,{{RS16,RD32,E }},{{0x0,0x1,0xD,0x0,0x5,0x3,RS16,B30|RD32,E}} EOP,
 407
 408   NEW_SOP(O(O_EEPMOV,SB),1,4,"eepmov.b"),{{E,0,0}},{{0x7,0xB,0x5,0xC,0x5,0x9,0x8,0xF,E}}EOP,
 409   NEW_SOP(O(O_EEPMOV,SW),0,4,"eepmov.w"),{{E,0,0}},{{0x7,0xB,0xD,0x4,0x5,0x9,0x8,0xF,E}} EOP,
 410
 411   NEW_SOP(O(O_EXTS,SW),0,2,"exts.w"),{{OR16,E,0}},{{0x1,0x7,0xD,OR16,E   }}EOP,
 412   NEW_SOP(O(O_EXTS,SL),0,2,"exts.l"),{{OR32,E,0}},{{0x1,0x7,0xF,OR32|B30,E   }}EOP,
 413
 414   NEW_SOP(O(O_EXTU,SW),0,2,"extu.w"),{{OR16,E,0}},{{0x1,0x7,0x5,OR16,E   }}EOP,
 415   NEW_SOP(O(O_EXTU,SL),0,2,"extu.l"),{{OR32,E,0}},{{0x1,0x7,0x7,OR32|B30,E   }}EOP,
 416
 417   UNOP(O(O_INC,SB), "inc",0x0,0xA),
 418
 419   NEW_SOP(O(O_INC,SW),0,2,"inc.w") ,{{DBIT,RD16,E }},{{0x0,0xB,0x5|DBIT,RD16,E}} EOP,
 420   NEW_SOP(O(O_INC,SL),0,2,"inc.l") ,{{DBIT,RD32,E }},{{0x0,0xB,0x7|DBIT,RD32|B30,E}} EOP,
 421
 422   SOP(O(O_JMP,SB),4,"jmp"),{{RSIND,E,0}},{{0x5,0x9,B30|RSIND,0x0,E,0,0,0,0}}EOP,
 423   SOP(O(O_JMP,SB),6,"jmp"),{{SRC|ABSJMP,E,0}},{{0x5,0xA,SRC|ABSJMP,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,E}}EOP,
 424   SOP(O(O_JMP,SB),8,"jmp"),{{SRC|MEMIND,E,0}},{{0x5,0xB,SRC|MEMIND,IGNORE,E,0,0,0,0}}EOP,
 425
 426   SOP(O(O_JSR,SB),6,"jsr"),{{SRC|RSIND,E,0}}, {{0x5,0xD,B30|RSIND,0x0,E,0,0,0,0}}EOP,
 427   SOP(O(O_JSR,SB),8,"jsr"),{{SRC|ABSJMP,E,0}},{{0x5,0xE,SRC|ABSJMP,IGNORE,IGNORE,IGNORE,IGNORE,IGNORE,E}}EOP,
 428   SOP(O(O_JSR,SB),8,"jsr"),{{SRC|MEMIND,E,0}},{{0x5,0xF,SRC|MEMIND,IGNORE,E,0,0,0,0}}EOP,
 429
 430   NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{IMM8,CCR|DST,E}},         {{ 0x0,0x7,IMM8,IGNORE,E,0,0,0,0}}EOP,
 431   NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{OR8,CCR|DST,E}},          {{ 0x0,0x3,0x0,OR8,E,0,0,0,0}}EOP,
 432   NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS16SRC,CCR|DST,E}},     {{PREFIXLDC,0x6,0xB,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
 433   NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS32SRC,CCR|DST,E}},     {{PREFIXLDC,0x6,0xB,0x2,0x0,SRC|ABS32LIST,E}}EOP,
 434   NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_16,CCR|DST,E}},{{PREFIXLDC,0x6,0xF,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
 435   NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_32,CCR|DST,E}},{{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}}EOP,
 436   NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSINC,CCR|DST,E}},        {{PREFIXLDC,0x6,0xD,B30|RSINC,0x0,E}}EOP,
 437   NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,CCR|DST,E}},        {{PREFIXLDC,0x6,0x9,B30|RDIND,0x0,E}} EOP,
 438
 439   NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{IMM8,EXR|DST,E}},         {{ 0x0,0x1,0x4,0x1,0x0,0x7,IMM8,IGNORE,E,0,0,0,0}}EOP,
 440   NEW_SOP(O(O_LDC,SB),1,2,"ldc"),{{OR8,EXR|DST,E}},          {{ 0x0,0x3,0x1,OR8,E,0,0,0,0}}EOP,
 441   NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS16SRC,EXR|DST,E}},     {{ 0x0,0x1,0x4,0x1,0x6,0xb,0x0,0x0,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
 442   NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{ABS32SRC,EXR|DST,E}},     {{ 0x0,0x1,0x4,0x1,0x6,0xb,0x2,0x0,SRC|ABS32LIST,E}}EOP,
 443   NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_16,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x6,0xf,B30|DISPREG,0,DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
 444   NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{DISP|SRC|L_32,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0x2,0x0,SRC|DISP32LIST,E}}EOP,
 445   NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSINC,EXR|DST,E}},        {{ 0x0,0x1,0x4,0x1,0x6,0xd,B30|RSINC,0x0,E}}EOP,
 446   NEW_SOP(O(O_LDC,SB),0,2,"ldc"),{{RSIND,EXR|DST,E}},        {{ 0x0,0x1,0x4,0x1,0x6,0x9,B30|RDIND,0x0,E}} EOP,
 447
 448   SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{{ABS|SRC|L_16|MEMRELAX,RD8,E}},  {{ 0x6,0xA,0x0,RD8,SRC|ABS|MEMRELAX|A16LIST,E}}EOP,
 449   SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{{ABS|SRC|L_32|MEMRELAX,RD8,E }}, {{ 0x6,0xA,0x2,RD8,SRC|ABS|MEMRELAX|A32LIST,E }}EOP,
 450   SOP(O(O_MOV_TO_MEM,SB),4,"mov.b"),{{RS8,ABS|L_16|MEMRELAX|DST,E}},     {{ 0x6,0xA,0x8,RS8,DST|ABS|MEMRELAX|A16LIST,E}}EOP,
 451   SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{{RS8,ABS|DST|L_32|MEMRELAX,E }},    {{ 0x6,0xA,0xA,RS8,DST|ABS|MEMRELAX|A32LIST,E }}EOP,
 452
 453   SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{{DISP|L_32|SRC,RD8,E}},  {{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xA,0x2,RD8,SRC|DISP32LIST,E}}EOP,
 454   SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{{RS8,DISP|L_32|DST,E}},  {{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xA,0xA,RS8,DST|DISP32LIST,E}}EOP,
 455
 456
 457
 458   SOP(O(O_MOV_TO_REG,SB),2,"mov.b"),{{RS8,RD8,E}},          {{ 0x0,0xC,RS8,RD8,E,0,0,0,0}}EOP,
 459   SOP(O(O_MOV_TO_REG,SB),2,"mov.b"),{{IMM8,RD8,E}},           {{ 0xF,RD8,IMM8,IGNORE,E,0,0,0,0}}EOP,
 460   SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{{RSIND,RD8,E}},          {{ 0x6,0x8,B30|RSIND,RD8,E,0,0,0,0}}EOP,
 461   SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{{DISP16SRC,RD8,E}},      {{ 0x6,0xE,B30|DISPREG,RD8,DISP16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
 462   SOP(O(O_MOV_TO_REG,SB),6,"mov.b"),{{RSINC,RD8,E}},          {{ 0x6,0xC,B30|RSINC,RD8,E,0,0,0,0}}EOP,
 463
 464   SOP(O(O_MOV_TO_REG,SB),4,"mov.b"),{{ABS8SRC,RD8,E}},        {{ 0x2,RD8,ABS8SRC,IGNORE,E,0,0,0,0}}EOP,
 465   SOP(O(O_MOV_TO_MEM,SB),4,"mov.b"),{{RS8,RDIND,E}},          {{ 0x6,0x8,RDIND|B31,RS8,E,0,0,0,0}}EOP,
 466   SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{{RS8,DISP16DST,E}},      {{ 0x6,0xE,DISPREG|B31,RS8,DISP16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
 467   SOP(O(O_MOV_TO_MEM,SB),6,"mov.b"),{{RS8,RDDEC|B31,E}},      {{ 0x6,0xC,RDDEC|B31,RS8,E,0,0,0,0}}EOP,
 468
 469   SOP(O(O_MOV_TO_MEM,SB),4,"mov.b"),{{RS8,ABS8DST,E}},        {{ 0x3,RS8,ABS8DST,IGNORE,E,0,0,0,0}}EOP,
 470
 471   SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,RDIND,E}},        {{ 0x6,0x9,RDIND|B31,RS16,E,0,0,0,0}}EOP,
 472   SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{DISP|L_32|SRC,RD16,E}},{{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xB,0x2,RD16,SRC|DISP32LIST,E}}EOP,
 473   SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,DISP|L_32|DST,E}},{{ 0x7,0x8,B30|DISPREG,0x0,0x6,0xB,0xA,RS16,DST|DISP32LIST,E}}EOP,
 474   SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{ABS|L_32|MEMRELAX|SRC,RD16,E }},{{ 0x6,0xB,0x2,RD16,SRC|MEMRELAX|ABS32LIST,E }}EOP,
 475   SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,ABS|L_32|MEMRELAX|DST,E }},{{ 0x6,0xB,0xA,RS16,DST|MEMRELAX|ABS32LIST,E }}EOP,
 476   SOP(O(O_MOV_TO_REG,SW),2,"mov.w"),{{RS16,RD16,E}},         {{ 0x0,0xD,RS16, RD16,E,0,0,0,0}}EOP,
 477   SOP(O(O_MOV_TO_REG,SW),4,"mov.w"),{{IMM16,RD16,E}},        {{ 0x7,0x9,0x0,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}}EOP,
 478   SOP(O(O_MOV_TO_REG,SW),4,"mov.w"),{{RSIND,RD16,E}},        {{ 0x6,0x9,B30|RSIND,RD16,E,0,0,0,0}}EOP,
 479   SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{DISP16SRC,RD16,E}},    {{ 0x6,0xF,B30|DISPREG,RD16,DISP16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
 480   SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{RSINC,RD16,E}},        {{ 0x6,0xD,B30|RSINC,RD16,E,0,0,0,0}}EOP,
 481   SOP(O(O_MOV_TO_REG,SW),6,"mov.w"),{{ABS16SRC,RD16,E}},     {{ 0x6,0xB,0x0,RD16,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
 482
 483   SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,DISP16DST,E}},    {{ 0x6,0xF,DISPREG|B31,RS16,DISP16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
 484   SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,RDDEC,E}},        {{ 0x6,0xD,RDDEC|B31,RS16,E,0,0,0,0}}EOP,
 485   SOP(O(O_MOV_TO_MEM,SW),6,"mov.w"),{{RS16,ABS16DST,E}},     {{ 0x6,0xB,0x8,RS16,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
 486
 487   SOP(O(O_MOV_TO_REG,SL),4,"mov.l"),{{IMM32,RD32,E}},        {{ 0x7,0xA,0x0,B30|RD32,IMM32LIST,E}}EOP,
 488   SOP(O(O_MOV_TO_REG,SL),2,"mov.l"),{{RS32,RD32,E}},         {{ 0x0,0xF,B31|RS32,B30|RD32,E,0,0,0,0}}EOP,
 489
 490   SOP(O(O_MOV_TO_REG,SL),4,"mov.l"),{{RSIND,RD32,E}},        {{ PREFIX32,0x6,0x9,RSIND|B30,B30|RD32,E,0,0,0,0 }}EOP,
 491   SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{DISP16SRC,RD32,E}},    {{ PREFIX32,0x6,0xF,DISPREG|B30,B30|RD32,DISP16SRC,IGNORE,IGNORE,IGNORE,E }}EOP,
 492   SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{DISP|L_32|SRC,RD32,E}},{{ PREFIX32,0x7,0x8,B30|DISPREG,0x0,0x6,0xB,0x2,B30|RD32,SRC|DISP32LIST,E }}EOP,
 493   SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{RSINC,RD32,E}},        {{ PREFIX32,0x6,0xD,B30|RSINC,B30|RD32,E,0,0,0,0 }}EOP,
 494   SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{ABS16SRC,RD32,E}},     {{ PREFIX32,0x6,0xB,0x0,B30|RD32,ABS16SRC,IGNORE,IGNORE,IGNORE,E }}EOP,
 495   SOP(O(O_MOV_TO_REG,SL),6,"mov.l"),{{ABS32SRC|MEMRELAX,RD32,E }},    {{ PREFIX32,0x6,0xB,0x2,B30|RD32,SRC|MEMRELAX|ABS32LIST,E }}EOP,
 496   SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,RDIND,E}},        {{ PREFIX32,0x6,0x9,RDIND|B31,B30|RS32,E,0,0,0,0 }}EOP,
 497   SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,DISP16DST,E}},    {{ PREFIX32,0x6,0xF,DISPREG|B31,B30|RS32,DISP16DST,IGNORE,IGNORE,IGNORE,E }}EOP,
 498   SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,DISP|L_32|DST,E}},{{ PREFIX32,0x7,0x8,B31|DISPREG,0x0,0x6,0xB,0xA,B30|RS32,DST|DISP32LIST,E }}EOP,
 499   SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,RDDEC,E}},        {{ PREFIX32,0x6,0xD,RDDEC|B31,B30|RS32,E,0,0,0,0 }}EOP,
 500   SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,ABS16DST,E}},     {{ PREFIX32,0x6,0xB,0x8,B30|RS32,ABS16DST,IGNORE,IGNORE,IGNORE,E }}EOP,
 501   SOP(O(O_MOV_TO_MEM,SL),6,"mov.l"),{{RS32,ABS32DST|MEMRELAX,E }},    {{ PREFIX32,0x6,0xB,0xA,B30|RS32,DST|MEMRELAX|ABS32LIST,E }}EOP,
 502
 503   SOP(O(O_MOV_TO_REG,SB),10,"movfpe"),{{ABS16SRC,RD8,E}},{{ 0x6,0xA,0x4,RD8,ABS16SRC,IGNORE,IGNORE,IGNORE,E}}EOP,
 504   SOP(O(O_MOV_TO_MEM,SB),10,"movtpe"),{{RS8,ABS16DST,E}},{{ 0x6,0xA,0xC,RS8,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
 505
 506   NEW_SOP(O(O_MULU,SB),1,14,"mulxu.b"),{{RS8,RD16,E}}, {{ 0x5,0x0,RS8,RD16,E,0,0,0,0}}EOP,
 507   NEW_SOP(O(O_MULU,SW),0,14,"mulxu.w"),{{RS16,RD32,E}},{{ 0x5,0x2,RS16,B30|RD32,E,0,0,0,0}}EOP,
 508
 509   NEW_SOP(O(O_MULS,SB),0,20,"mulxs.b"),{{RS8,RD16,E}}, {{ 0x0,0x1,0xc,0x0,0x5,0x0,RS8,RD16,E}}EOP,
 510   NEW_SOP(O(O_MULS,SW),0,20,"mulxs.w"),{{RS16,RD32,E}},{{ 0x0,0x1,0xc,0x0,0x5,0x2,RS16,B30|RD32,E}}EOP,
 511
 512   /* ??? This can use UNOP3.  */
 513   NEW_SOP(O(O_NEG,SB),1,2,"neg.b"),{{ OR8,E, 0}},{{ 0x1,0x7,0x8,OR8,E,0,0,0,0}}EOP,
 514   NEW_SOP(O(O_NEG,SW),0,2,"neg.w"),{{ OR16,E,0}},{{ 0x1,0x7,0x9,OR16,E}}EOP,
 515   NEW_SOP(O(O_NEG,SL),0,2,"neg.l"),{{ OR32,E,0}},{{ 0x1,0x7,0xB,B30|OR32,E}}EOP,
 516
 517   NEW_SOP(O(O_NOP,SN),1,2,"nop"),{{E,0,0}},{{ 0x0,0x0,0x0,0x0,E,0,0,0,0}}EOP,
 518
 519   /* ??? This can use UNOP3.  */
 520   NEW_SOP(O(O_NOT,SB),1,2,"not.b"),{{ OR8,E, 0}},{{ 0x1,0x7,0x0,OR8,E,0,0,0,0}}EOP,
 521   NEW_SOP(O(O_NOT,SW),0,2,"not.w"),{{ OR16,E,0}},{{ 0x1,0x7,0x1,OR16,E}}EOP,
 522   NEW_SOP(O(O_NOT,SL),0,2,"not.l"),{{ OR32,E,0}},{{ 0x1,0x7,0x3,B30|OR32,E}}EOP,
 523
 524   TWOOP(O(O_OR, SB),"or.b",0xC,0x1,0x4),
 525   NEW_SOP(O(O_OR,SW),0,4,"or.w"),{{IMM16,RD16,E }},{{0x7,0x9,0x4,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP,
 526   NEW_SOP(O(O_OR,SW),0,2,"or.w"),{{RS16,RD16,E }},{{0x6,0x4,RS16,RD16,E}} EOP,
 527
 528   NEW_SOP(O(O_OR,SL),0,6,"or.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x4,B30|RD32,IMM32LIST,E}} EOP,
 529   NEW_SOP(O(O_OR,SL),0,2,"or.l"),{{RS32,RD32,E }},{{0x0,0x1,0xF,0x0,0x6,0x4,B30|RS32,B30|RD32,E}} EOP,
 530
 531   NEW_SOP(O(O_ORC,SB),1,2,"orc"),{{IMM8,CCR|DST,E}},{{ 0x0,0x4,IMM8,IGNORE,E,0,0,0,0}}EOP,
 532   NEW_SOP(O(O_ORC,SB),1,2,"orc"),{{IMM8,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x4,IMM8,IGNORE,E,0,0,0,0}}EOP,
 533
 534   NEW_SOP(O(O_MOV_TO_REG,SW),1,6,"pop.w"),{{OR16,E,0}},{{ 0x6,0xD,0x7,OR16,E,0,0,0,0}}EOP,
 535   NEW_SOP(O(O_MOV_TO_REG,SL),0,6,"pop.l"),{{OR32,E,0}},{{ PREFIX32,0x6,0xD,0x7,OR32|B30,E,0,0,0,0}}EOP,
 536   NEW_SOP(O(O_MOV_TO_MEM,SW),1,6,"push.w"),{{OR16,E,0}},{{ 0x6,0xD,0xF,OR16,E,0,0,0,0}}EOP,
 537   NEW_SOP(O(O_MOV_TO_MEM,SL),0,6,"push.l"),{{OR32,E,0}},{{ PREFIX32,0x6,0xD,0xF,OR32|B30,E,0,0,0,0}}EOP,
 538
 539   UNOP3(O_ROTL,  "rotl", 0x1,0x2,0x8),
 540   UNOP3(O_ROTR,  "rotr", 0x1,0x3,0x8),
 541   UNOP3(O_ROTXL, "rotxl",0x1,0x2,0x0),
 542   UNOP3(O_ROTXR, "rotxr",0x1,0x3,0x0),
 543
 544   SOP(O(O_BPT,SN),  10,"bpt"),{{E,0,0}},{{ 0x7,0xA,0xF,0xF,E,0,0,0,0}}EOP,
 545   SOP(O(O_RTE,SN),  10,"rte"),{{E,0,0}},{{ 0x5,0x6,0x7,0x0,E,0,0,0,0}}EOP,
 546   SOP(O(O_RTS,SN),   8,"rts"),{{E,0,0}},{{ 0x5,0x4,0x7,0x0,E,0,0,0,0}}EOP,
 547
 548   UNOP3(O_SHAL,  "shal",0x1,0x0,0x8),
 549   UNOP3(O_SHAR,  "shar",0x1,0x1,0x8),
 550   UNOP3(O_SHLL,  "shll",0x1,0x0,0x0),
 551   UNOP3(O_SHLR,  "shlr",0x1,0x1,0x0),
 552
 553   SOP(O(O_SLEEP,SN),2,"sleep"),{{E,0,0}},{{ 0x0,0x1,0x8,0x0,E,0,0,0,0}} EOP,
 554
 555   NEW_SOP(O(O_STC,SB), 1,2,"stc"),{{CCR|SRC,RD8,E}},{{ 0x0,0x2,0x0,RD8,E,0,0,0,0}} EOP,
 556
 557   NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,RSIND,E}},        {{PREFIXLDC,0x6,0x9,B31|RDIND,0x0,E}} EOP,
 558   NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,DISP|DST|L_16,E}},{{PREFIXLDC,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
 559   NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,DISP|DST|L_32,E}},{{PREFIXLDC,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}}EOP,
 560   NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,RDDEC,E}},        {{PREFIXLDC,0x6,0xD,B31|RDDEC,0x0,E}}EOP,
 561
 562   NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,ABS16DST,E}},     {{PREFIXLDC,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
 563   NEW_SOP(O(O_STC,SB),0,2,"stc"),{{CCR|SRC,ABS32DST,E}},     {{PREFIXLDC,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}}EOP,
 564
 565   NEW_SOP(O(O_STC,SB), 1,2,"stc"),{{EXR|SRC,RD8,E}},{{ 0x0,0x2,0x1,RD8,E,0,0,0,0}} EOP,
 566
 567   NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,RSIND,E}},        {{0x0,0x1,0x4,0x1,0x6,0x9,B31|RDIND,0x0,E}} EOP,
 568   NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,DISP|DST|L_16,E}},{{0x0,0x1,0x4,0x1,0x6,0xF,B31|DISPREG,0,DST|DISP|L_16,IGNORE,IGNORE,IGNORE,E}}EOP,
 569   NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,DISP|DST|L_32,E}},{{0x0,0x1,0x4,0x1,0x7,0x8,B30|DISPREG,0,0x6,0xB,0xA,0x0,DST|DISP32LIST,E}}EOP,
 570   NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,RDDEC,E}},        {{0x0,0x1,0x4,0x1,0x6,0xD,B31|RDDEC,0x0,E}}EOP,
 571
 572   NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,ABS16DST,E}},     {{0x0,0x1,0x4,0x1,0x6,0xB,0x8,0x0,ABS16DST,IGNORE,IGNORE,IGNORE,E}}EOP,
 573   NEW_SOP(O(O_STC,SB),0,2,"stc"),{{EXR|SRC,ABS32DST,E}},     {{0x0,0x1,0x4,0x1,0x6,0xB,0xA,0x0,DST|ABS32LIST,E}}EOP,
 574
 575   SOP(O(O_SUB,SB),2,"sub.b"),{{RS8,RD8,E}},{{ 0x1,0x8,RS8,RD8,E,0,0,0,0}}EOP,
 576
 577   NEW_SOP(O(O_SUB,SW),1,2,"sub.w"),{{RS16,RD16,E }},  {{0x1,0x9,RS16,RD16,E}} EOP,
 578   NEW_SOP(O(O_SUB,SW),0,4,"sub.w"),{{IMM16,RD16,E }}, {{0x7,0x9,0x3,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP,
 579   NEW_SOP(O(O_SUB,SL),0,2,"sub.l") ,{{RS32,RD32,E }}, {{0x1,0xA,B31|RS32,B30|RD32,E}} EOP,
 580   NEW_SOP(O(O_SUB,SL),0,6,"sub.l"), {{IMM32,RD32,E }},{{0x7,0xA,0x3,B30|RD32,IMM32LIST,E}} EOP,
 581
 582   SOP(O(O_SUBS,SL),2,"subs"),{{KBIT,RDP,E}},{{ 0x1,0xB,KBIT,RDP,E,0,0,0,0}}EOP,
 583   TWOOP(O(O_SUBX,SB),"subx",0xB,0x1,0xE),
 584
 585   NEW_SOP(O(O_TRAPA,SB),0,2,"trapa"),{{ IMM2,E}},  {{0x5,0x7,IMM2,IGNORE,E  }}EOP,
 586   NEW_SOP(O(O_TAS,SB),0,2,"tas"),{{RSIND,E}},  {{0x0,0x1,0xe,0x0,0x7,0xb,B30|RSIND,0xc,E  }}EOP,
 587
 588   TWOOP(O(O_XOR, SB),"xor",0xD,0x1,0x5),
 589
 590   NEW_SOP(O(O_XOR,SW),0,4,"xor.w"),{{IMM16,RD16,E }},{{0x7,0x9,0x5,RD16,IMM16,IGNORE,IGNORE,IGNORE,E}} EOP,
 591   NEW_SOP(O(O_XOR,SW),0,2,"xor.w"),{{RS16,RD16,E }},{{0x6,0x5,RS16,RD16,E}} EOP,
 592
 593   NEW_SOP(O(O_XOR,SL),0,6,"xor.l"),{{IMM32,RD32,E }},{{0x7,0xA,0x5,B30|RD32,IMM32LIST,E}} EOP,
 594   NEW_SOP(O(O_XOR,SL),0,2,"xor.l") ,{{RS32,RD32,E }},{{0x0,0x1,0xF,0x0,0x6,0x5,B30|RS32,B30|RD32,E}} EOP,
 595
 596   SOP(O(O_XORC,SB),2,"xorc"),{{IMM8,CCR|DST,E}},{{ 0x0,0x5,IMM8,IGNORE,E,0,0,0,0}}EOP,
 597   SOP(O(O_XORC,SB),2,"xorc"),{{IMM8,EXR|DST,E}},{{ 0x0,0x1,0x4,0x1,0x0,0x5,IMM8,IGNORE,E,0,0,0,0}}EOP,
 598
 599   NEW_SOP(O(O_CLRMAC,SN),1,2,"clrmac"),{{E, 0, 0}},{{0x0,0x1,0xa,0x0,E}} EOP,
 600   NEW_SOP(O(O_MAC,SL),1,2,"mac"),{{RSINC,RDINC,E}},{{0x0,0x1,0x6,0x0,0x6,0xd,B30|RSINC,B30|RDINC,E}} EOP,
 601   NEW_SOP(O(O_LDMAC,SL),1,2,"ldmac"),{{RS32,MD32,E}},{{0x0,0x3,MD32,RS32,E}} EOP,
 602   NEW_SOP(O(O_STMAC,SL),1,2,"stmac"),{{MS32,RD32,E}},{{0x0,0x2,MS32,RD32,E}} EOP,
 603   NEW_SOP(O(O_LDM,SL),0,6,"ldm.l"),{{RSINC, RS32, E}},{{ 0x0,0x1,IGNORE,0x0,0x6,0xD,0x7,IGNORE,E}}EOP,
 604   NEW_SOP(O(O_STM,SL),0,6,"stm.l"),{{RS32, RDDEC, E}},{{0x0,0x1,IGNORE,0x0,0x6,0xD,0xF,IGNORE,E}}EOP,
 605   {0, 0, 0, NULL, {{0,0,0}}, {{0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}}}
 606 };
 607 #else
 608 extern const struct h8_opcode h8_opcodes[];
 609 #endif