include/opcode/hppa.h

   1 /* Table of opcodes for the PA-RISC.
   2    Copyright (C) 1990, 1991, 1993, 1995, 1999 Free Software Foundation, Inc.
   3
   4    Contributed by the Center for Software Science at the
   5    University of Utah (pa-gdb-bugs@cs.utah.edu).
   6
   7 This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
   8
   9 GAS/GDB is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 1, or (at your option)
  12 any later version.
  13
  14 GAS/GDB is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License
  20 along with GAS or GDB; see the file COPYING.  If not, write to
  21 the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  22
  23 #if !defined(__STDC__) && !defined(const)
  24 #define const
  25 #endif
  26
  27 /*
  28  * Structure of an opcode table entry.
  29  */
  30
  31 /* There are two kinds of delay slot nullification: normal which is
  32  * controled by the nullification bit, and conditional, which depends
  33  * on the direction of the branch and its success or failure.
  34  *
  35  * NONE is unfortunately #defined in the hiux system include files.
  36  * #undef it away.
  37  */
  38 #undef NONE
  39 struct pa_opcode
  40 {
  41     const char *name;
  42     unsigned long int match;    /* Bits that must be set...  */
  43     unsigned long int mask;     /* ... in these bits. */
  44     char *args;
  45     enum pa_arch arch;
  46     char flags;
  47 };
  48
  49 /* Enable/disable strict syntax checking.  Not currently used, but will
  50    be necessary for PA2.0 support in the future.  */
  51 #define FLAG_STRICT 0x1
  52
  53 /*
  54    All hppa opcodes are 32 bits.
  55
  56    The match component is a mask saying which bits must match a
  57    particular opcode in order for an instruction to be an instance
  58    of that opcode.
  59
  60    The args component is a string containing one character for each operand of
  61    the instruction.  Characters used as a prefix allow any second character to
  62    be used without conflicting with the main operand characters.
  63
  64    Bit positions in this description follow HP usage of lsb = 31,
  65    "at" is lsb of field.
  66
  67    In the args field, the following characters must match exactly:
  68
  69         '+,() '
  70
  71    In the args field, the following characters are unused:
  72
  73         '  "   &     -  /   34 6789:;< > @'
  74         '  C                     Y [\]  '
  75         '    e                   y   } '
  76
  77    Here are all the characters:
  78
  79         ' !"#$%&'()*+-,./0123456789:;<=>?@'
  80         'ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_'
  81         'abcdefghijklmnopqrstuvwxyz{|}~'
  82
  83 Kinds of operands:
  84    x    integer register field at 15.
  85    b    integer register field at 10.
  86    t    integer register field at 31.
  87    a    integer register field at 10 and 15 (for PERMH)
  88    5    5 bit immediate at 15.
  89    s    2 bit space specifier at 17.
  90    S    3 bit space specifier at 18.
  91    V    5 bit immediate value at 31
  92    i    11 bit immediate value at 31
  93    j    14 bit immediate value at 31
  94    k    21 bit immediate value at 31
  95    n    nullification for branch instructions
  96    N    nullification for spop and copr instructions
  97    w    12 bit branch displacement
  98    W    17 bit branch displacement (PC relative)
  99    X    22 bit branch displacement (PC relative)
 100    z    17 bit branch displacement (just a number, not an address)
 101
 102 Also these:
 103
 104    .    2 bit shift amount at 25
 105    *    4 bit shift amount at 25
 106    p    5 bit shift count at 26 (to support the SHD instruction) encoded as
 107         31-p
 108    ~    6 bit shift count at 20,22:26 encoded as 63-~.
 109    P    5 bit bit position at 26
 110    q    6 bit bit position at 20,22:26
 111    T    5 bit field length at 31 (encoded as 32-T)
 112    %    6 bit field length at 23,27:31 (variable extract/deposit)
 113    |    6 bit field length at 19,27:31 (fixed extract/deposit)
 114    A    13 bit immediate at 18 (to support the BREAK instruction)
 115    ^    like b, but describes a control register
 116    !    sar (cr11) register
 117    D    26 bit immediate at 31 (to support the DIAG instruction)
 118    $    9 bit immediate at 28 (to support POPBTS)
 119
 120    v    3 bit Special Function Unit identifier at 25
 121    O    20 bit Special Function Unit operation split between 15 bits at 20
 122         and 5 bits at 31
 123    o    15 bit Special Function Unit operation at 20
 124    2    22 bit Special Function Unit operation split between 17 bits at 20
 125         and 5 bits at 31
 126    1    15 bit Special Function Unit operation split between 10 bits at 20
 127         and 5 bits at 31
 128    0    10 bit Special Function Unit operation split between 5 bits at 20
 129         and 5 bits at 31
 130    u    3 bit coprocessor unit identifier at 25
 131    F    Source Floating Point Operand Format Completer encoded 2 bits at 20
 132    I    Source Floating Point Operand Format Completer encoded 1 bits at 20
 133         (for 0xe format FP instructions)
 134    G    Destination Floating Point Operand Format Completer encoded 2 bits at 18
 135    H    Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub'
 136         (very similar to 'F')
 137
 138    r    5 bit immediate value at 31 (for the break instruction)
 139         (very similar to V above, except the value is unsigned instead of
 140         low_sign_ext)
 141    R    5 bit immediate value at 15 (for the ssm, rsm, probei instructions)
 142         (same as r above, except the value is in a different location)
 143    U    10 bit immediate value at 15 (for SSM, RSM on pa2.0)
 144    Q    5 bit immediate value at 10 (a bit position specified in
 145         the bb instruction. It's the same as r above, except the
 146         value is in a different location)
 147    Z    %r1 -- implicit target of addil instruction.
 148    g    ,gate completer for new syntax branch
 149    l    ,l completer for new syntax branch
 150    M    ,push completer for new syntax branch
 151    L    ,%r2 completer for new syntax branch
 152    B    ,pop completer for new syntax branch
 153    {    Source format completer for fcnv
 154    _    Destination format completer for fcnv
 155    h    cbit for fcmp
 156    =    gfx tests for ftest
 157    d    14bit offset for single precision FP long load/store.
 158    #    14bit offset for double precision FP load long/store.
 159    J    Yet another 14bit offset with an unusual encoding.
 160    K    Yet another 14bit offset with an unusual encoding.
 161
 162 Completer operands all have 'c' as the prefix:
 163
 164    cx   indexed load completer.
 165    cm   short load and store completer.
 166    cq   short load and store completer (like cm, but inserted into a
 167         different location in the target instruction).
 168    cs   store bytes short completer.
 169    cc   Another load/store completer with a different encoding than the
 170         others
 171
 172    cw   read/write completer for PROBE
 173    cW   wide completer for MFCTL
 174    cL   local processor completer for cache control
 175    cZ   System Control Completer (to support LPA, LHA, etc.)
 176
 177    ci   correction completer for DCOR
 178    ca   add completer
 179    cy   32 bit add carry completer
 180    cY   64 bit add carry completer
 181    cv   signed overflow trap completer
 182    ct   trap on condition completer for ADDI, SUB
 183    cT   trap on condition completer for UADDCM
 184    cb   32 bit borrow completer for SUB
 185    cB   64 bit borrow completer for SUB
 186
 187    ch   left/right half completer
 188    cH   signed/unsigned saturation completer
 189    cS   signed/unsigned completer at 21
 190    c*   permutation completer
 191
 192 Condition operands all have '?' as the prefix:
 193
 194    ?f   Floating point compare conditions (encoded as 5 bits at 31)
 195
 196    ?a   add conditions
 197    ?A   64 bit add conditions
 198    ?@   add branch conditions followed by nullify
 199    ?d   non-negated add branch conditions
 200    ?D   negated add branch conditions
 201    ?w   wide mode non-negated add branch conditions
 202    ?W   wide mode negated add branch conditions
 203
 204    ?s   compare/subtract conditions
 205    ?S   64 bit compare/subtract conditions
 206    ?t   non-negated compare conditions
 207    ?T   negated compare conditions
 208    ?r   64 bit non-negated compare conditions
 209    ?R   64 bit negated compare conditions
 210    ?Q   64 bit compare conditions for CMPIB instruction
 211    ?n   compare conditions followed by nullify
 212
 213    ?l   logical conditions
 214    ?L   64 bit logical conditions
 215
 216    ?b   branch on bit conditions
 217    ?B   64 bit branch on bit conditions
 218
 219    ?x   shift/extract/deposit conditions
 220    ?X   64 bit shift/extract/deposit conditions
 221    ?y   shift/extract/deposit conditions followed by nullify for conditional
 222         branches
 223
 224    ?u   unit conditions
 225    ?U   64 bit unit conditions
 226
 227 Floating point registers all have 'f' as a prefix:
 228
 229    ft   target register at 31
 230    fT   target register with L/R halves at 31
 231    fa   operand 1 register at 10
 232    fA   operand 1 register with L/R halves at 10
 233    fX   Same as fA, except prints a space before register during disasm
 234    fb   operand 2 register at 15
 235    fB   operand 2 register with L/R halves at 15
 236    fC   operand 3 register with L/R halves at 16:18,21:23
 237    fe   Like fT, but encoding is different.
 238
 239 Float registers for fmpyadd and fmpysub:
 240
 241    fi   mult operand 1 register at 10
 242    fj   mult operand 2 register at 15
 243    fk   mult target register at 20
 244    fl   add/sub operand register at 25
 245    fm   add/sub target register at 31
 246
 247 */
 248
 249
 250 /* List of characters not to put a space after.  Note that
 251    "," is included, as the "spopN" operations use literal
 252    commas in their completer sections. */
 253 static const char *const completer_chars = ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e$m}";
 254
 255 /* The order of the opcodes in this table is significant:
 256
 257    * The assembler requires that all instances of the same mnemonic must be
 258    consecutive.  If they aren't, the assembler will bomb at runtime.
 259
 260    * The disassembler should not care about the order of the opcodes.  */
 261
 262 static const struct pa_opcode pa_opcodes[] =
 263 {
 264
 265
 266 { "b",          0xe8002000, 0xfc00e000, "gnW,b", pa10, FLAG_STRICT},
 267 { "b",          0xe8008000, 0xfc00e000, "lMnXL", pa20, FLAG_STRICT},
 268 { "b",          0xe800a000, 0xfc00e000, "lnXL", pa20, FLAG_STRICT},
 269 { "b",          0xe8000000, 0xfc00e000, "lnW,b", pa10, FLAG_STRICT},
 270 { "b",          0xe8000000, 0xffe0e000, "nW", pa10, 0}, /* bl foo,r0 */
 271 { "ldi",        0x34000000, 0xffe0c000, "j,x", pa10, 0},/* ldo val(r0),r */
 272 { "comib",      0x84000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/
 273 /* This entry is for the disassembler only.  It will never be used by
 274    assembler.  */
 275 { "comib",      0x8c000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/
 276 { "comb",       0x80000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */
 277 /* This entry is for the disassembler only.  It will never be used by
 278    assembler.  */
 279 { "comb",       0x88000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */
 280 { "addb",       0xa0000000, 0xfc000000, "?@nx,b,w", pa10, 0}, /* addb{tf} */
 281 /* This entry is for the disassembler only.  It will never be used by
 282    assembler.  */
 283 { "addb",       0xa8000000, 0xfc000000, "?@nx,b,w", pa10, 0},
 284 { "addib",      0xa4000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/
 285 /* This entry is for the disassembler only.  It will never be used by
 286    assembler.  */
 287 { "addib",      0xac000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/
 288 { "nop",        0x08000240, 0xffffffff, "", pa10, 0},      /* or 0,0,0 */
 289 { "copy",       0x08000240, 0xffe0ffe0, "x,t", pa10, 0},   /* or r,0,t */
 290 { "mtsar",      0x01601840, 0xffe0ffff, "x", pa10, 0}, /* mtctl r,cr11 */
 291
 292 /* Loads and Stores for integer registers.  */
 293 { "ldd",        0x0c0000c0, 0xfc001fc0, "cxx(s,b),t", pa20, FLAG_STRICT},
 294 { "ldd",        0x0c0000c0, 0xfc001fc0, "cxx(b),t", pa20, FLAG_STRICT},
 295 { "ldd",        0x0c0010c0, 0xfc001fc0, "cm5(s,b),t", pa20, FLAG_STRICT},
 296 { "ldd",        0x0c0010c0, 0xfc001fc0, "cm5(b),t", pa20, FLAG_STRICT},
 297 { "ldd",        0x50000000, 0xfc000002, "cq#(s,b),x", pa20, FLAG_STRICT},
 298 { "ldd",        0x50000000, 0xfc000002, "cq#(b),x", pa20, FLAG_STRICT},
 299 { "ldw",        0x0c000080, 0xfc001fc0, "cxx(s,b),t", pa10, FLAG_STRICT},
 300 { "ldw",        0x0c000080, 0xfc001fc0, "cxx(b),t", pa10, FLAG_STRICT},
 301 { "ldw",        0x0c001080, 0xfc001fc0, "cm5(s,b),t", pa10, FLAG_STRICT},
 302 { "ldw",        0x0c001080, 0xfc001fc0, "cm5(b),t", pa10, FLAG_STRICT},
 303 { "ldw",        0x4c000000, 0xfc000000, "ccJ(s,b),x", pa10, FLAG_STRICT},
 304 { "ldw",        0x4c000000, 0xfc000000, "ccJ(b),x", pa10, FLAG_STRICT},
 305 { "ldw",        0x5c000004, 0xfc000006, "ccK(s,b),x", pa20, FLAG_STRICT},
 306 { "ldw",        0x5c000004, 0xfc000006, "ccK(b),x", pa20, FLAG_STRICT},
 307 { "ldw",        0x48000000, 0xfc000000, "j(s,b),x", pa10, 0},
 308 { "ldw",        0x48000000, 0xfc000000, "j(s,b),x", pa10, 0},
 309 { "ldw",        0x48000000, 0xfc000000, "j(b),x", pa10, 0},
 310 { "ldh",        0x0c000040, 0xfc001fc0, "cxx(s,b),t", pa10, FLAG_STRICT},
 311 { "ldh",        0x0c000040, 0xfc001fc0, "cxx(b),t", pa10, FLAG_STRICT},
 312 { "ldh",        0x0c001040, 0xfc001fc0, "cm5(s,b),t", pa10, FLAG_STRICT},
 313 { "ldh",        0x0c001040, 0xfc001fc0, "cm5(b),t", pa10, FLAG_STRICT},
 314 { "ldh",        0x44000000, 0xfc000000, "j(s,b),x", pa10, 0},
 315 { "ldh",        0x44000000, 0xfc000000, "j(b),x", pa10, 0},
 316 { "ldb",        0x0c000000, 0xfc001fc0, "cxx(s,b),t", pa10, FLAG_STRICT},
 317 { "ldb",        0x0c000000, 0xfc001fc0, "cxx(b),t", pa10, FLAG_STRICT},
 318 { "ldb",        0x0c001000, 0xfc001fc0, "cm5(s,b),t", pa10, FLAG_STRICT},
 319 { "ldb",        0x0c001000, 0xfc001fc0, "cm5(b),t", pa10, FLAG_STRICT},
 320 { "ldb",        0x40000000, 0xfc000000, "j(s,b),x", pa10, 0},
 321 { "ldb",        0x40000000, 0xfc000000, "j(b),x", pa10, 0},
 322 { "std",        0x0c0012c0, 0xfc001fc0, "cmx,V(s,b)", pa20, FLAG_STRICT},
 323 { "std",        0x0c0012c0, 0xfc001fc0, "cmx,V(b)", pa20, FLAG_STRICT},
 324 { "std",        0x70000000, 0xfc000002, "cqx,#(s,b)", pa20, FLAG_STRICT},
 325 { "std",        0x70000000, 0xfc000002, "cqx,#(b)", pa20, FLAG_STRICT},
 326 { "stw",        0x0c001280, 0xfc001fc0, "cmx,V(s,b)", pa10, FLAG_STRICT},
 327 { "stw",        0x0c001280, 0xfc001fc0, "cmx,V(b)", pa10, FLAG_STRICT},
 328 { "stw",        0x6c000000, 0xfc000000, "ccx,J(s,b)", pa10, FLAG_STRICT},
 329 { "stw",        0x6c000000, 0xfc000000, "ccx,J(b)", pa10, FLAG_STRICT},
 330 { "stw",        0x7c000004, 0xfc000006, "ccx,K(s,b)", pa20, FLAG_STRICT},
 331 { "stw",        0x7c000004, 0xfc000006, "ccx,K(b)", pa20, FLAG_STRICT},
 332 { "stw",        0x68000000, 0xfc000000, "x,j(s,b)", pa10, 0},
 333 { "stw",        0x68000000, 0xfc000000, "x,j(b)", pa10, 0},
 334 { "sth",        0x0c001240, 0xfc001fc0, "cmx,V(s,b)", pa10, FLAG_STRICT},
 335 { "sth",        0x0c001240, 0xfc001fc0, "cmx,V(b)", pa10, FLAG_STRICT},
 336 { "sth",        0x64000000, 0xfc000000, "x,j(s,b)", pa10, 0},
 337 { "sth",        0x64000000, 0xfc000000, "x,j(b)", pa10, 0},
 338 { "stb",        0x0c001200, 0xfc001fc0, "cmx,V(s,b)", pa10, FLAG_STRICT},
 339 { "stb",        0x0c001200, 0xfc001fc0, "cmx,V(b)", pa10, FLAG_STRICT},
 340 { "stb",        0x60000000, 0xfc000000, "x,j(s,b)", pa10, 0},
 341 { "stb",        0x60000000, 0xfc000000, "x,j(b)", pa10, 0},
 342 { "ldwm",       0x4c000000, 0xfc000000, "j(s,b),x", pa10, 0},
 343 { "ldwm",       0x4c000000, 0xfc000000, "j(b),x", pa10, 0},
 344 { "stwm",       0x6c000000, 0xfc000000, "x,j(s,b)", pa10, 0},
 345 { "stwm",       0x6c000000, 0xfc000000, "x,j(b)", pa10, 0},
 346 { "ldwx",       0x0c000080, 0xfc001fc0, "cxx(s,b),t", pa10, 0},
 347 { "ldwx",       0x0c000080, 0xfc001fc0, "cxx(b),t", pa10, 0},
 348 { "ldhx",       0x0c000040, 0xfc001fc0, "cxx(s,b),t", pa10, 0},
 349 { "ldhx",       0x0c000040, 0xfc001fc0, "cxx(b),t", pa10, 0},
 350 { "ldbx",       0x0c000000, 0xfc001fc0, "cxx(s,b),t", pa10, 0},
 351 { "ldbx",       0x0c000000, 0xfc001fc0, "cxx(b),t", pa10, 0},
 352 { "ldwa",       0x0c000180, 0xfc00dfc0, "cxx(b),t", pa10, FLAG_STRICT},
 353 { "ldwa",       0x0c001180, 0xfc00dfc0, "cm5(b),t", pa10, FLAG_STRICT},
 354 { "ldcw",       0x0c0001c0, 0xfc001fc0, "cxx(s,b),t", pa10, FLAG_STRICT},
 355 { "ldcw",       0x0c0001c0, 0xfc001fc0, "cxx(b),t", pa10, FLAG_STRICT},
 356 { "ldcw",       0x0c0011c0, 0xfc001fc0, "cm5(s,b),t", pa10, FLAG_STRICT},
 357 { "ldcw",       0x0c0011c0, 0xfc001fc0, "cm5(b),t", pa10, FLAG_STRICT},
 358 { "stwa",       0x0c001380, 0xfc00dfc0, "cmx,V(b)", pa10, FLAG_STRICT},
 359 { "stby",       0x0c001300, 0xfc001fc0, "csx,V(s,b)", pa10, FLAG_STRICT},
 360 { "stby",       0x0c001300, 0xfc001fc0, "csx,V(b)", pa10, FLAG_STRICT},
 361 { "ldda",       0x0c000100, 0xfc00dfc0, "cxx(b),t", pa20, FLAG_STRICT},
 362 { "ldda",       0x0c001100, 0xfc00dfc0, "cm5(b),t", pa20, FLAG_STRICT},
 363 { "ldcd",       0x0c000140, 0xfc001fc0, "cxx(s,b),t", pa20, FLAG_STRICT},
 364 { "ldcd",       0x0c000140, 0xfc001fc0, "cxx(b),t", pa20, FLAG_STRICT},
 365 { "ldcd",       0x0c001140, 0xfc001fc0, "cm5(s,b),t", pa20, FLAG_STRICT},
 366 { "ldcd",       0x0c001140, 0xfc001fc0, "cm5(b),t", pa20, FLAG_STRICT},
 367 { "stda",       0x0c0013c0, 0xfc001fc0, "cmx,V(s,b)", pa20, FLAG_STRICT},
 368 { "stda",       0x0c0013c0, 0xfc001fc0, "cmx,V(b)", pa20, FLAG_STRICT},
 369 { "ldwax",      0x0c000180, 0xfc00dfc0, "cxx(b),t", pa10, 0},
 370 { "ldcwx",      0x0c0001c0, 0xfc001fc0, "cxx(s,b),t", pa10, 0},
 371 { "ldcwx",      0x0c0001c0, 0xfc001fc0, "cxx(b),t", pa10, 0},
 372 { "ldws",       0x0c001080, 0xfc001fc0, "cm5(s,b),t", pa10, 0},
 373 { "ldws",       0x0c001080, 0xfc001fc0, "cm5(b),t", pa10, 0},
 374 { "ldhs",       0x0c001040, 0xfc001fc0, "cm5(s,b),t", pa10, 0},
 375 { "ldhs",       0x0c001040, 0xfc001fc0, "cm5(b),t", pa10, 0},
 376 { "ldbs",       0x0c001000, 0xfc001fc0, "cm5(s,b),t", pa10, 0},
 377 { "ldbs",       0x0c001000, 0xfc001fc0, "cm5(b),t", pa10, 0},
 378 { "ldwas",      0x0c001180, 0xfc00dfc0, "cm5(b),t", pa10, 0},
 379 { "ldcws",      0x0c0011c0, 0xfc001fc0, "cm5(s,b),t", pa10, 0},
 380 { "ldcws",      0x0c0011c0, 0xfc001fc0, "cm5(b),t", pa10, 0},
 381 { "stws",       0x0c001280, 0xfc001fc0, "cmx,V(s,b)", pa10, 0},
 382 { "stws",       0x0c001280, 0xfc001fc0, "cmx,V(b)", pa10, 0},
 383 { "sths",       0x0c001240, 0xfc001fc0, "cmx,V(s,b)", pa10, 0},
 384 { "sths",       0x0c001240, 0xfc001fc0, "cmx,V(b)", pa10, 0},
 385 { "stbs",       0x0c001200, 0xfc001fc0, "cmx,V(s,b)", pa10, 0},
 386 { "stbs",       0x0c001200, 0xfc001fc0, "cmx,V(b)", pa10, 0},
 387 { "stwas",      0x0c001380, 0xfc00dfc0, "cmx,V(b)", pa10, 0},
 388 { "stdby",      0x0c001340, 0xfc001fc0, "csx,V(s,b)", pa20, FLAG_STRICT},
 389 { "stdby",      0x0c001340, 0xfc001fc0, "csx,V(b)", pa20, FLAG_STRICT},
 390 { "stbys",      0x0c001300, 0xfc001fc0, "csx,V(s,b)", pa10, 0},
 391 { "stbys",      0x0c001300, 0xfc001fc0, "csx,V(b)", pa10, 0},
 392
 393 /* Immediate instructions.  */
 394 { "ldo",        0x34000000, 0xfc00c000, "j(b),x", pa10, 0},
 395 { "ldil",       0x20000000, 0xfc000000, "k,b", pa10, 0},
 396 { "addil",      0x28000000, 0xfc000000, "k,b,Z", pa10, 0},
 397 { "addil",      0x28000000, 0xfc000000, "k,b", pa10, 0},
 398
 399 /* Branching instructions. */
 400 { "bl",         0xe8000000, 0xfc00e000, "nW,b", pa10, 0},
 401 { "gate",       0xe8002000, 0xfc00e000, "nW,b", pa10, 0},
 402 { "blr",        0xe8004000, 0xfc00e001, "nx,b", pa10, 0},
 403 { "bv",         0xe800c000, 0xfc00fffd, "nx(b)", pa10, 0},
 404 { "bv",         0xe800c000, 0xfc00fffd, "n(b)", pa10, 0},
 405 { "bve",        0xe800f001, 0xfc00ffff, "lMn(b)L", pa20, FLAG_STRICT},
 406 { "bve",        0xe800f000, 0xfc00ffff, "ln(b)L", pa20, FLAG_STRICT},
 407 { "bve",        0xe800d001, 0xfc00ffff, "Bn(b)", pa20, FLAG_STRICT},
 408 { "bve",        0xe800d000, 0xfc00ffff, "n(b)", pa20, FLAG_STRICT},
 409 { "be",         0xe4000000, 0xfc000000, "lnz(S,b)", pa10, FLAG_STRICT},
 410 { "be",         0xe0000000, 0xfc000000, "nz(S,b)", pa10, FLAG_STRICT},
 411 { "be",         0xe0000000, 0xfc000000, "nz(S,b)", pa10, 0},
 412 { "ble",        0xe4000000, 0xfc000000, "nz(S,b)", pa10, 0},
 413 { "movb",       0xc8000000, 0xfc000000, "?ynx,b,w", pa10, 0},
 414 { "movib",      0xcc000000, 0xfc000000, "?yn5,b,w", pa10, 0},
 415 { "combt",      0x80000000, 0xfc000000, "?tnx,b,w", pa10, 0},
 416 { "combf",      0x88000000, 0xfc000000, "?tnx,b,w", pa10, 0},
 417 { "comibt",     0x84000000, 0xfc000000, "?tn5,b,w", pa10, 0},
 418 { "comibf",     0x8c000000, 0xfc000000, "?tn5,b,w", pa10, 0},
 419 { "addbt",      0xa0000000, 0xfc000000, "?dnx,b,w", pa10, 0},
 420 { "addbf",      0xa8000000, 0xfc000000, "?dnx,b,w", pa10, 0},
 421 { "addibt",     0xa4000000, 0xfc000000, "?dn5,b,w", pa10, 0},
 422 { "addibf",     0xac000000, 0xfc000000, "?dn5,b,w", pa10, 0},
 423 { "bb",         0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT},
 424 { "bb",         0xc4006000, 0xfc006000, "?Bnx,Q,w", pa20, FLAG_STRICT},
 425 { "bb",         0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT},
 426 { "bb",         0xc4004000, 0xfc004000, "?bnx,Q,w", pa10, 0},
 427 { "bvb",        0xc0004000, 0xffe04000, "?bnx,w", pa10, 0},
 428 { "clrbts",     0xe8004005, 0xffffffff, "", pa20, FLAG_STRICT},
 429 { "popbts",     0xe8004005, 0xfffff007, "$", pa20, FLAG_STRICT},
 430 { "pushnom",    0xe8004001, 0xffffffff, "", pa20, FLAG_STRICT},
 431 { "pushbts",    0xe8004001, 0xffe0ffff, "x", pa20, FLAG_STRICT},
 432
 433 /* Computation Instructions */
 434
 435 { "cmpclr",     0x080008a0, 0xfc000fe0, "?Sx,b,t", pa20, FLAG_STRICT},
 436 { "cmpclr",     0x08000880, 0xfc000fe0, "?sx,b,t", pa10, FLAG_STRICT},
 437 { "comclr",     0x08000880, 0xfc000fe0, "?sx,b,t", pa10, 0},
 438 { "or",         0x08000260, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
 439 { "or",         0x08000240, 0xfc000fe0, "?lx,b,t", pa10, 0},
 440 { "xor",        0x080002a0, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
 441 { "xor",        0x08000280, 0xfc000fe0, "?lx,b,t", pa10, 0},
 442 { "and",        0x08000220, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
 443 { "and",        0x08000200, 0xfc000fe0, "?lx,b,t", pa10, 0},
 444 { "andcm",      0x08000020, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
 445 { "andcm",      0x08000000, 0xfc000fe0, "?lx,b,t", pa10, 0},
 446 { "uxor",       0x080003a0, 0xfc000fe0, "?Ux,b,t", pa20, FLAG_STRICT},
 447 { "uxor",       0x08000380, 0xfc000fe0, "?ux,b,t", pa10, 0},
 448 { "uaddcm",     0x080009a0, 0xfc000fa0, "cT?Ux,b,t", pa20, FLAG_STRICT},
 449 { "uaddcm",     0x08000980, 0xfc000fa0, "cT?ux,b,t", pa10, FLAG_STRICT},
 450 { "uaddcm",     0x08000980, 0xfc000fe0, "?ux,b,t", pa10, 0},
 451 { "uaddcmt",    0x080009c0, 0xfc000fe0, "?ux,b,t", pa10, 0},
 452 { "dcor",       0x08000ba0, 0xfc1f0fa0, "ci?Ub,t", pa20, FLAG_STRICT},
 453 { "dcor",       0x08000b80, 0xfc1f0fa0, "ci?ub,t", pa10, FLAG_STRICT},
 454 { "dcor",       0x08000b80, 0xfc1f0fe0, "?ub,t",   pa10, 0},
 455 { "idcor",      0x08000bc0, 0xfc1f0fe0, "?ub,t",   pa10, 0},
 456 { "addi",       0xb0000000, 0xfc000000, "ct?ai,b,x", pa10, FLAG_STRICT},
 457 { "addi",       0xb4000000, 0xfc000000, "cv?ai,b,x", pa10, FLAG_STRICT},
 458 { "addi",       0xb4000000, 0xfc000800, "?ai,b,x", pa10, 0},
 459 { "addio",      0xb4000800, 0xfc000800, "?ai,b,x", pa10, 0},
 460 { "addit",      0xb0000000, 0xfc000800, "?ai,b,x", pa10, 0},
 461 { "addito",     0xb0000800, 0xfc000800, "?ai,b,x", pa10, 0},
 462 { "add",        0x08000720, 0xfc0007e0, "cY?Ax,b,t", pa20, FLAG_STRICT},
 463 { "add",        0x08000700, 0xfc0007e0, "cy?ax,b,t", pa10, FLAG_STRICT},
 464 { "add",        0x08000220, 0xfc0003e0, "ca?Ax,b,t", pa20, FLAG_STRICT},
 465 { "add",        0x08000200, 0xfc0003e0, "ca?ax,b,t", pa10, FLAG_STRICT},
 466 { "add",        0x08000600, 0xfc000fe0, "?ax,b,t", pa10, 0},
 467 { "addl",       0x08000a00, 0xfc000fe0, "?ax,b,t", pa10, 0},
 468 { "addo",       0x08000e00, 0xfc000fe0, "?ax,b,t", pa10, 0},
 469 { "addc",       0x08000700, 0xfc000fe0, "?ax,b,t", pa10, 0},
 470 { "addco",      0x08000f00, 0xfc000fe0, "?ax,b,t", pa10, 0},
 471 { "sub",        0x080004e0, 0xfc0007e0, "ct?Sx,b,t", pa20, FLAG_STRICT},
 472 { "sub",        0x080004c0, 0xfc0007e0, "ct?sx,b,t", pa10, FLAG_STRICT},
 473 { "sub",        0x08000520, 0xfc0007e0, "cB?Sx,b,t", pa20, FLAG_STRICT},
 474 { "sub",        0x08000500, 0xfc0007e0, "cb?sx,b,t", pa10, FLAG_STRICT},
 475 { "sub",        0x08000420, 0xfc0007e0, "cv?Sx,b,t", pa20, FLAG_STRICT},
 476 { "sub",        0x08000400, 0xfc0007e0, "cv?sx,b,t", pa10, FLAG_STRICT},
 477 { "sub",        0x08000400, 0xfc000fe0, "?sx,b,t", pa10, 0},
 478 { "subo",       0x08000c00, 0xfc000fe0, "?sx,b,t", pa10, 0},
 479 { "subb",       0x08000500, 0xfc000fe0, "?sx,b,t", pa10, 0},
 480 { "subbo",      0x08000d00, 0xfc000fe0, "?sx,b,t", pa10, 0},
 481 { "subt",       0x080004c0, 0xfc000fe0, "?sx,b,t", pa10, 0},
 482 { "subto",      0x08000cc0, 0xfc000fe0, "?sx,b,t", pa10, 0},
 483 { "ds",         0x08000440, 0xfc000fe0, "?sx,b,t", pa10, 0},
 484 { "subi",       0x94000000, 0xfc000000, "cv?si,b,x", pa10, FLAG_STRICT},
 485 { "subi",       0x94000000, 0xfc000800, "?si,b,x", pa10, 0},
 486 { "subio",      0x94000800, 0xfc000800, "?si,b,x", pa10, 0},
 487 { "cmpiclr",    0x90000800, 0xfc000800, "?Si,b,x", pa20, FLAG_STRICT},
 488 { "cmpiclr",    0x90000000, 0xfc000800, "?si,b,x", pa10, FLAG_STRICT},
 489 { "comiclr",    0x90000000, 0xfc000800, "?si,b,x", pa10, 0},
 490 { "shladd",     0x08000220, 0xfc000320, "ca?Ax,.,b,t", pa20, FLAG_STRICT},
 491 { "shladd",     0x08000200, 0xfc000320, "ca?ax,.,b,t", pa10, FLAG_STRICT},
 492 { "sh1add",     0x08000640, 0xfc000fe0, "?ax,b,t", pa10, 0},
 493 { "sh1addl",    0x08000a40, 0xfc000fe0, "?ax,b,t", pa10, 0},
 494 { "sh1addo",    0x08000e40, 0xfc000fe0, "?ax,b,t", pa10, 0},
 495 { "sh2add",     0x08000680, 0xfc000fe0, "?ax,b,t", pa10, 0},
 496 { "sh2addl",    0x08000a80, 0xfc000fe0, "?ax,b,t", pa10, 0},
 497 { "sh2addo",    0x08000e80, 0xfc000fe0, "?ax,b,t", pa10, 0},
 498 { "sh3add",     0x080006c0, 0xfc000fe0, "?ax,b,t", pa10, 0},
 499 { "sh3addl",    0x08000ac0, 0xfc000fe0, "?ax,b,t", pa10, 0},
 500 { "sh3addo",    0x08000ec0, 0xfc000fe0, "?ax,b,t", pa10, 0},
 501
 502 /* Subword Operation Instructions */
 503
 504 { "hadd",       0x08000300, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT},
 505 { "havg",       0x080002c0, 0xfc00ffe0, "x,b,t", pa20, FLAG_STRICT},
 506 { "hshl",       0xf8008800, 0xffe0fc20, "x,*,t", pa20, FLAG_STRICT},
 507 { "hshladd",    0x08000700, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT},
 508 { "hshr",       0xf800c800, 0xfc1ff820, "cSb,*,t", pa20, FLAG_STRICT},
 509 { "hshradd",    0x08000500, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT},
 510 { "hsub",       0x08000100, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT},
 511 { "mixh",       0xf8008400, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT},
 512 { "mixw",       0xf8008000, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT},
 513 { "permh",      0xf8000000, 0xfc009020, "c*a,t", pa20, FLAG_STRICT},
 514
 515
 516 /* Extract and Deposit Instructions */
 517
 518 { "shrpd",      0xd0000200, 0xfc001fe0, "?Xx,b,!,t", pa20, FLAG_STRICT},
 519 { "shrpd",      0xd0000400, 0xfc001400, "?Xx,b,~,t", pa20, FLAG_STRICT},
 520 { "shrpw",      0xd0000000, 0xfc001fe0, "?xx,b,!,t", pa10, FLAG_STRICT},
 521 { "shrpw",      0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, FLAG_STRICT},
 522 { "vshd",       0xd0000000, 0xfc001fe0, "?xx,b,t", pa10, 0},
 523 { "shd",        0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, 0},
 524 { "extrd",      0xd0001200, 0xfc001ae0, "cS?Xb,!,%,x", pa20, FLAG_STRICT},
 525 { "extrd",      0xd8000000, 0xfc000000, "cS?Xb,q,|,x", pa20, FLAG_STRICT},
 526 { "extrw",      0xd0001000, 0xfc001be0, "cS?xb,!,T,x", pa10, FLAG_STRICT},
 527 { "extrw",      0xd0001800, 0xfc001800, "cS?xb,P,T,x", pa10, FLAG_STRICT},
 528 { "vextru",     0xd0001000, 0xfc001fe0, "?xb,T,x", pa10, 0},
 529 { "vextrs",     0xd0001400, 0xfc001fe0, "?xb,T,x", pa10, 0},
 530 { "extru",      0xd0001800, 0xfc001c00, "?xb,P,T,x", pa10, 0},
 531 { "extrs",      0xd0001c00, 0xfc001c00, "?xb,P,T,x", pa10, 0},
 532 { "depd",       0xd4000200, 0xfc001ae0, "cz?Xx,!,%,b", pa20, FLAG_STRICT},
 533 { "depd",       0xf0000000, 0xfc000000, "cz?Xx,~,|,b", pa20, FLAG_STRICT},
 534 { "depdi",      0xd4001200, 0xfc001ae0, "cz?X5,!,%,b", pa20, FLAG_STRICT},
 535 { "depdi",      0xf4000000, 0xfc000000, "cz?X5,~,|,b", pa20, FLAG_STRICT},
 536 { "depw",       0xd4000000, 0xfc001be0, "cz?xx,!,T,b", pa10, FLAG_STRICT},
 537 { "depw",       0xd4000800, 0xfc001800, "cz?xx,p,T,b", pa10, FLAG_STRICT},
 538 { "depwi",      0xd4001000, 0xfc001be0, "cz?x5,!,T,b", pa10, FLAG_STRICT},
 539 { "depwi",      0xd4001800, 0xfc001800, "cz?x5,p,T,b", pa10, FLAG_STRICT},
 540 { "zvdep",      0xd4000000, 0xfc001fe0, "?xx,T,b", pa10, 0},
 541 { "vdep",       0xd4000400, 0xfc001fe0, "?xx,T,b", pa10, 0},
 542 { "zdep",       0xd4000800, 0xfc001c00, "?xx,p,T,b", pa10, 0},
 543 { "dep",        0xd4000c00, 0xfc001c00, "?xx,p,T,b", pa10, 0},
 544 { "zvdepi",     0xd4001000, 0xfc001fe0, "?x5,T,b", pa10, 0},
 545 { "vdepi",      0xd4001400, 0xfc001fe0, "?x5,T,b", pa10, 0},
 546 { "zdepi",      0xd4001800, 0xfc001c00, "?x5,p,T,b", pa10, 0},
 547 { "depi",       0xd4001c00, 0xfc001c00, "?x5,p,T,b", pa10, 0},
 548
 549 /* System Control Instructions */
 550
 551 { "break",      0x00000000, 0xfc001fe0, "r,A", pa10, 0},
 552 { "rfi",        0x00000c00, 0xffffff1f, "cr", pa10, FLAG_STRICT},
 553 { "rfi",        0x00000c00, 0xffffffff, "", pa10, 0},
 554 { "rfir",       0x00000ca0, 0xffffffff, "", pa11, 0},
 555 { "ssm",        0x00000d60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT},
 556 { "ssm",        0x00000d60, 0xffe0ffe0, "R,t", pa10, 0},
 557 { "rsm",        0x00000e60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT},
 558 { "rsm",        0x00000e60, 0xffe0ffe0, "R,t", pa10, 0},
 559 { "mtsm",       0x00001860, 0xffe0ffff, "x", pa10, 0},
 560 { "ldsid",      0x000010a0, 0xfc1f3fe0, "(s,b),t", pa10, 0},
 561 { "ldsid",      0x000010a0, 0xfc1f3fe0, "(b),t", pa10, 0},
 562 { "mtsp",       0x00001820, 0xffe01fff, "x,S", pa10, 0},
 563 { "mtctl",      0x00001840, 0xfc00ffff, "x,^", pa10, 0},
 564 { "mtsarcm",    0x016018C0, 0xffe0ffff, "x", pa20, FLAG_STRICT},
 565 { "mfia",       0x000014A0, 0xffffffe0, "t", pa20, FLAG_STRICT},
 566 { "mfsp",       0x000004a0, 0xffff1fe0, "S,t", pa10, 0},
 567 { "mfctl",      0x016048a0, 0xffffffe0, "cW!,t", pa20, FLAG_STRICT},
 568 { "mfctl",      0x000008a0, 0xfc1fffe0, "^,t", pa10, 0},
 569 { "sync",       0x00000400, 0xffffffff, "", pa10, 0},
 570 { "syncdma",    0x00100400, 0xffffffff, "", pa10, 0},
 571 { "probe",      0x04001180, 0xfc003fa0, "cw(s,b),x,t", pa10, FLAG_STRICT},
 572 { "probe",      0x04001180, 0xfc003fa0, "cw(b),x,t", pa10, FLAG_STRICT},
 573 { "probei",     0x04003180, 0xfc003fa0, "cw(s,b),R,t", pa10, FLAG_STRICT},
 574 { "probei",     0x04003180, 0xfc003fa0, "cw(b),R,t", pa10, FLAG_STRICT},
 575 { "prober",     0x04001180, 0xfc003fe0, "(s,b),x,t", pa10, 0},
 576 { "prober",     0x04001180, 0xfc003fe0, "(b),x,t", pa10, 0},
 577 { "proberi",    0x04003180, 0xfc003fe0, "(s,b),R,t", pa10, 0},
 578 { "proberi",    0x04003180, 0xfc003fe0, "(b),R,t", pa10, 0},
 579 { "probew",     0x040011c0, 0xfc003fe0, "(s,b),x,t", pa10, 0},
 580 { "probew",     0x040011c0, 0xfc003fe0, "(b),x,t", pa10, 0},
 581 { "probewi",    0x040031c0, 0xfc003fe0, "(s,b),R,t", pa10, 0},
 582 { "probewi",    0x040031c0, 0xfc003fe0, "(b),R,t", pa10, 0},
 583 { "lpa",        0x04001340, 0xfc003fc0, "cZx(s,b),t", pa10, 0},
 584 { "lpa",        0x04001340, 0xfc003fc0, "cZx(b),t", pa10, 0},
 585 { "lha",        0x04001300, 0xfc003fc0, "cZx(s,b),t", pa10, 0},
 586 { "lha",        0x04001300, 0xfc003fc0, "cZx(b),t", pa10, 0},
 587 { "lci",        0x04001300, 0xfc003fe0, "x(s,b),t", pa10, 0},
 588 { "lci",        0x04001300, 0xfc003fe0, "x(b),t", pa10, 0},
 589 { "pdtlb",      0x04001600, 0xfc003fdf, "cLcZx(s,b)", pa20, FLAG_STRICT},
 590 { "pdtlb",      0x04001600, 0xfc003fdf, "cLcZx(b)", pa20, FLAG_STRICT},
 591 { "pdtlb",      0x04001200, 0xfc003fdf, "cZx(s,b)", pa10, 0},
 592 { "pdtlb",      0x04001200, 0xfc003fdf, "cZx(b)", pa10, 0},
 593 { "pitlb",      0x04000600, 0xfc001fdf, "cLcZx(S,b)", pa20, FLAG_STRICT},
 594 { "pitlb",      0x04000600, 0xfc001fdf, "cLcZx(b)", pa20, FLAG_STRICT},
 595 { "pitlb",      0x04000200, 0xfc001fdf, "cZx(S,b)", pa10, 0},
 596 { "pitlb",      0x04000200, 0xfc001fdf, "cZx(b)", pa10, 0},
 597 { "pdtlbe",     0x04001240, 0xfc003fdf, "cZx(s,b)", pa10, 0},
 598 { "pdtlbe",     0x04001240, 0xfc003fdf, "cZx(b)", pa10, 0},
 599 { "pitlbe",     0x04000240, 0xfc001fdf, "cZx(S,b)", pa10, 0},
 600 { "pitlbe",     0x04000240, 0xfc001fdf, "cZx(b)", pa10, 0},
 601 { "idtlba",     0x04001040, 0xfc003fff, "x,(s,b)", pa10, 0},
 602 { "idtlba",     0x04001040, 0xfc003fff, "x,(b)", pa10, 0},
 603 { "iitlba",     0x04000040, 0xfc001fff, "x,(S,b)", pa10, 0},
 604 { "iitlba",     0x04000040, 0xfc001fff, "x,(b)", pa10, 0},
 605 { "idtlbp",     0x04001000, 0xfc003fff, "x,(s,b)", pa10, 0},
 606 { "idtlbp",     0x04001000, 0xfc003fff, "x,(b)", pa10, 0},
 607 { "iitlbp",     0x04000000, 0xfc001fff, "x,(S,b)", pa10, 0},
 608 { "iitlbp",     0x04000000, 0xfc001fff, "x,(b)", pa10, 0},
 609 { "pdc",        0x04001380, 0xfc003fdf, "cZx(s,b)", pa10, 0},
 610 { "pdc",        0x04001380, 0xfc003fdf, "cZx(b)", pa10, 0},
 611 { "fdc",        0x04001280, 0xfc003fdf, "cZx(s,b)", pa10, 0},
 612 { "fdc",        0x04001280, 0xfc003fdf, "cZx(b)", pa10, 0},
 613 { "fic",        0x04000280, 0xfc001fdf, "cZx(S,b)", pa10, 0},
 614 { "fic",        0x04000280, 0xfc001fdf, "cZx(b)", pa10, 0},
 615 { "fdce",       0x040012c0, 0xfc003fdf, "cZx(s,b)", pa10, 0},
 616 { "fdce",       0x040012c0, 0xfc003fdf, "cZx(b)", pa10, 0},
 617 { "fice",       0x040002c0, 0xfc001fdf, "cZx(S,b)", pa10, 0},
 618 { "fice",       0x040002c0, 0xfc001fdf, "cZx(b)", pa10, 0},
 619 { "diag",       0x14000000, 0xfc000000, "D", pa10, 0},
 620 { "idtlbt",     0x04001800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT},
 621 { "iitlbt",     0x04000800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT},
 622
 623 /* These may be specific to certain versions of the PA.  Joel claimed
 624    they were 72000 (7200?) specific.  However, I'm almost certain the
 625    mtcpu/mfcpu were undocumented, but available in the older 700 machines.  */
 626 { "mtcpu",      0x14001600, 0xfc00ffff, "x,^", pa10, 0},
 627 { "mfcpu",      0x14001A00, 0xfc00ffff, "^,x", pa10, 0},
 628 { "tocen",      0x14403600, 0xffffffff, "", pa10, 0},
 629 { "tocdis",     0x14401620, 0xffffffff, "", pa10, 0},
 630 { "shdwgr",     0x14402600, 0xffffffff, "", pa10, 0},
 631 { "grshdw",     0x14400620, 0xffffffff, "", pa10, 0},
 632
 633 /* gfw and gfr are not in the HP PA 1.1 manual, but they are in either
 634    the Timex FPU or the Mustang ERS (not sure which) manual.  */
 635 { "gfw",        0x04001680, 0xfc003fdf, "cZx(s,b)", pa11, 0},
 636 { "gfw",        0x04001680, 0xfc003fdf, "cZx(b)", pa11, 0},
 637 { "gfr",        0x04001a80, 0xfc003fdf, "cZx(s,b)", pa11, 0},
 638 { "gfr",        0x04001a80, 0xfc003fdf, "cZx(b)", pa11, 0},
 639
 640 /* Floating Point Coprocessor Instructions */
 641
 642 { "fldw",       0x24000000, 0xfc001f80, "cxx(s,b),fT", pa10, FLAG_STRICT},
 643 { "fldw",       0x24000000, 0xfc001f80, "cxx(b),fT", pa10, FLAG_STRICT},
 644 { "fldw",       0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10, FLAG_STRICT},
 645 { "fldw",       0x24001000, 0xfc001f80, "cm5(b),fT", pa10, FLAG_STRICT},
 646 { "fldw",       0x5c000000, 0xfc000004, "d(s,b),fe", pa20, FLAG_STRICT},
 647 { "fldw",       0x5c000000, 0xfc000004, "d(b),fe", pa20, FLAG_STRICT},
 648 { "fldw",       0x58000000, 0xfc000004, "cJd(s,b),fe", pa20, FLAG_STRICT},
 649 { "fldw",       0x58000000, 0xfc000004, "cJd(b),fe", pa20, FLAG_STRICT},
 650 { "fldd",       0x2c000000, 0xfc001fc0, "cxx(s,b),ft", pa10, FLAG_STRICT},
 651 { "fldd",       0x2c000000, 0xfc001fc0, "cxx(b),ft", pa10, FLAG_STRICT},
 652 { "fldd",       0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10, FLAG_STRICT},
 653 { "fldd",       0x2c001000, 0xfc001fc0, "cm5(b),ft", pa10, FLAG_STRICT},
 654 { "fldd",       0x50000002, 0xfc000002, "cq#(s,b),x", pa20, FLAG_STRICT},
 655 { "fldd",       0x50000002, 0xfc000002, "cq#(b),x", pa20, FLAG_STRICT},
 656 { "fstw",       0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10, FLAG_STRICT},
 657 { "fstw",       0x24000200, 0xfc001f80, "cxfT,x(b)", pa10, FLAG_STRICT},
 658 { "fstw",       0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10, FLAG_STRICT},
 659 { "fstw",       0x24001200, 0xfc001f80, "cmfT,5(b)", pa10, FLAG_STRICT},
 660 { "fstw",       0x7c000000, 0xfc000004, "fe,d(s,b)", pa20, FLAG_STRICT},
 661 { "fstw",       0x7c000000, 0xfc000004, "fe,d(b)", pa20, FLAG_STRICT},
 662 { "fstw",       0x78000000, 0xfc000004, "cJfe,d(s,b)", pa20, FLAG_STRICT},
 663 { "fstw",       0x78000000, 0xfc000004, "cJfe,d(b)", pa20, FLAG_STRICT},
 664 { "fstd",       0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, FLAG_STRICT},
 665 { "fstd",       0x2c000200, 0xfc001fc0, "cxft,x(b)", pa10, FLAG_STRICT},
 666 { "fstd",       0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, FLAG_STRICT},
 667 { "fstd",       0x2c001200, 0xfc001fc0, "cmft,5(b)", pa10, FLAG_STRICT},
 668 { "fstd",       0x70000002, 0xfc000002, "cqx,#(s,b)", pa20, FLAG_STRICT},
 669 { "fstd",       0x70000002, 0xfc000002, "cqx,#(b)", pa20, FLAG_STRICT},
 670 { "fldwx",      0x24000000, 0xfc001f80, "cxx(s,b),fT", pa10, 0},
 671 { "fldwx",      0x24000000, 0xfc001f80, "cxx(b),fT", pa10, 0},
 672 { "flddx",      0x2c000000, 0xfc001fc0, "cxx(s,b),ft", pa10, 0},
 673 { "flddx",      0x2c000000, 0xfc001fc0, "cxx(b),ft", pa10, 0},
 674 { "fstwx",      0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10, 0},
 675 { "fstwx",      0x24000200, 0xfc001f80, "cxfT,x(b)", pa10, 0},
 676 { "fstdx",      0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0},
 677 { "fstdx",      0x2c000200, 0xfc001fc0, "cxft,x(b)", pa10, 0},
 678 { "fstqx",      0x3c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0},
 679 { "fstqx",      0x3c000200, 0xfc001fc0, "cxft,x(b)", pa10, 0},
 680 { "fldws",      0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10, 0},
 681 { "fldws",      0x24001000, 0xfc001f80, "cm5(b),fT", pa10, 0},
 682 { "fldds",      0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10, 0},
 683 { "fldds",      0x2c001000, 0xfc001fc0, "cm5(b),ft", pa10, 0},
 684 { "fstws",      0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10, 0},
 685 { "fstws",      0x24001200, 0xfc001f80, "cmfT,5(b)", pa10, 0},
 686 { "fstds",      0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0},
 687 { "fstds",      0x2c001200, 0xfc001fc0, "cmft,5(b)", pa10, 0},
 688 { "fstqs",      0x3c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0},
 689 { "fstqs",      0x3c001200, 0xfc001fc0, "cmft,5(b)", pa10, 0},
 690 { "fadd",       0x30000600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
 691 { "fadd",       0x38000600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
 692 { "fsub",       0x30002600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
 693 { "fsub",       0x38002600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
 694 { "fmpy",       0x30004600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
 695 { "fmpy",       0x38004600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
 696 { "fdiv",       0x30006600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
 697 { "fdiv",       0x38006600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
 698 { "fsqrt",      0x30008000, 0xfc1fe7e0, "Ffa,fT", pa10, 0},
 699 { "fsqrt",      0x38008000, 0xfc1fe720, "FfA,fT", pa10, 0},
 700 { "fabs",       0x30006000, 0xfc1fe7e0, "Ffa,fT", pa10, 0},
 701 { "fabs",       0x38006000, 0xfc1fe720, "FfA,fT", pa10, 0},
 702 { "frem",       0x30008600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
 703 { "frem",       0x38008600, 0xfc00e720, "FfA,fB,fT", pa10, 0},
 704 { "frnd",       0x3000a000, 0xfc1fe7e0, "Ffa,fT", pa10, 0},
 705 { "frnd",       0x3800a000, 0xfc1fe720, "FfA,fT", pa10, 0},
 706 { "fcpy",       0x30004000, 0xfc1fe7e0, "Ffa,fT", pa10, 0},
 707 { "fcpy",       0x38004000, 0xfc1fe720, "FfA,fT", pa10, 0},
 708 { "fcnvff",     0x30000200, 0xfc1f87e0, "FGfa,fT", pa10, 0},
 709 { "fcnvff",     0x38000200, 0xfc1f8720, "FGfA,fT", pa10, 0},
 710 { "fcnvxf",     0x30008200, 0xfc1f87e0, "FGfa,fT", pa10, 0},
 711 { "fcnvxf",     0x38008200, 0xfc1f8720, "FGfA,fT", pa10, 0},
 712 { "fcnvfx",     0x30010200, 0xfc1f87e0, "FGfa,fT", pa10, 0},
 713 { "fcnvfx",     0x38010200, 0xfc1f8720, "FGfA,fT", pa10, 0},
 714 { "fcnvfxt",    0x30018200, 0xfc1f87e0, "FGfa,fT", pa10, 0},
 715 { "fcnvfxt",    0x38018200, 0xfc1f8720, "FGfA,fT", pa10, 0},
 716 { "fmpyfadd",   0xb8000000, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT},
 717 { "fmpynfadd",  0xb8000020, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT},
 718 { "fneg",       0x3000c000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT},
 719 { "fneg",       0x3800c000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT},
 720 { "fnegabs",    0x3000e000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT},
 721 { "fnegabs",    0x3800e000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT},
 722 { "fcnv",       0x30000200, 0xfc1c0720, "{_fa,fT", pa20, FLAG_STRICT},
 723 { "fcnv",       0x38000200, 0xfc1c0720, "FGfA,fT", pa20, FLAG_STRICT},
 724 { "fcmp",       0x30000400, 0xfc0007e0, "F?ffa,fb,h", pa20, FLAG_STRICT},
 725 { "fcmp",       0x38000400, 0xfc000720, "I?ffA,fB,h", pa20, FLAG_STRICT},
 726 { "fcmp",       0x30000400, 0xfc00e7e0, "F?ffa,fb", pa10, 0},
 727 { "fcmp",       0x38000400, 0xfc00e720, "I?ffA,fB", pa10, 0},
 728 { "xmpyu",      0x38004700, 0xfc00e720, "fX,fB,fT", pa11, 0},
 729 { "fmpyadd",    0x18000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0},
 730 { "fmpysub",    0x98000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0},
 731 { "ftest",      0x30002420, 0xffffffe0, ",=", pa20, FLAG_STRICT},
 732 { "ftest",      0x30000420, 0xffff1fff, "m", pa20, FLAG_STRICT},
 733 { "ftest",      0x30002420, 0xffffffff, "", pa10, 0},
 734 { "fid",        0x30000000, 0xffffffff, "", pa11, 0},
 735
 736 /* Performance Monitor Instructions */
 737
 738 { "pmdis",      0x30000280, 0xffffffdf, "N", pa20, FLAG_STRICT},
 739 { "pmenb",      0x30000680, 0xffffffff, "", pa20, FLAG_STRICT},
 740
 741 /* Assist Instructions */
 742
 743 { "spop0",      0x10000000, 0xfc000600, "v,ON", pa10, 0},
 744 { "spop1",      0x10000200, 0xfc000600, "v,oNt", pa10, 0},
 745 { "spop2",      0x10000400, 0xfc000600, "v,1Nb", pa10, 0},
 746 { "spop3",      0x10000600, 0xfc000600, "v,0Nx,b", pa10, 0},
 747 { "copr",       0x30000000, 0xfc000000, "u,2N", pa10, 0},
 748 { "cldwx",      0x24000000, 0xfc001e00, "ucxx(s,b),t", pa10, 0},
 749 { "cldwx",      0x24000000, 0xfc001e00, "ucxx(b),t", pa10, 0},
 750 { "clddx",      0x2c000000, 0xfc001e00, "ucxx(s,b),t", pa10, 0},
 751 { "clddx",      0x2c000000, 0xfc001e00, "ucxx(b),t", pa10, 0},
 752 { "cstwx",      0x24000200, 0xfc001e00, "ucxt,x(s,b)", pa10, 0},
 753 { "cstwx",      0x24000200, 0xfc001e00, "ucxt,x(b)", pa10, 0},
 754 { "cstdx",      0x2c000200, 0xfc001e00, "ucxt,x(s,b)", pa10, 0},
 755 { "cstdx",      0x2c000200, 0xfc001e00, "ucxt,x(b)", pa10, 0},
 756 { "cldws",      0x24001000, 0xfc001e00, "ucm5(s,b),t", pa10, 0},
 757 { "cldws",      0x24001000, 0xfc001e00, "ucm5(b),t", pa10, 0},
 758 { "cldds",      0x2c001000, 0xfc001e00, "ucm5(s,b),t", pa10, 0},
 759 { "cldds",      0x2c001000, 0xfc001e00, "ucm5(b),t", pa10, 0},
 760 { "cstws",      0x24001200, 0xfc001e00, "ucmt,5(s,b)", pa10, 0},
 761 { "cstws",      0x24001200, 0xfc001e00, "ucmt,5(b)", pa10, 0},
 762 { "cstds",      0x2c001200, 0xfc001e00, "ucmt,5(s,b)", pa10, 0},
 763 { "cstds",      0x2c001200, 0xfc001e00, "ucmt,5(b)", pa10, 0},
 764 { "cldw",       0x24000000, 0xfc001e00, "ucxx(s,b),t", pa10, FLAG_STRICT},
 765 { "cldw",       0x24000000, 0xfc001e00, "ucxx(b),t", pa10, FLAG_STRICT},
 766 { "cldw",       0x24001000, 0xfc001e00, "ucm5(s,b),t", pa10, FLAG_STRICT},
 767 { "cldw",       0x24001000, 0xfc001e00, "ucm5(b),t", pa10, FLAG_STRICT},
 768 { "cldd",       0x2c000000, 0xfc001e00, "ucxx(s,b),t", pa10, FLAG_STRICT},
 769 { "cldd",       0x2c000000, 0xfc001e00, "ucxx(b),t", pa10, FLAG_STRICT},
 770 { "cldd",       0x2c001000, 0xfc001e00, "ucm5(s,b),t", pa10, FLAG_STRICT},
 771 { "cldd",       0x2c001000, 0xfc001e00, "ucm5(b),t", pa20, FLAG_STRICT},
 772 { "cstw",       0x24000200, 0xfc001e00, "ucxt,x(s,b)", pa10, FLAG_STRICT},
 773 { "cstw",       0x24000200, 0xfc001e00, "ucxt,x(b)", pa10, FLAG_STRICT},
 774 { "cstw",       0x24001200, 0xfc001e00, "ucmt,5(s,b)", pa10, FLAG_STRICT},
 775 { "cstw",       0x24001200, 0xfc001e00, "ucmt,5(b)", pa10, FLAG_STRICT},
 776 { "cstd",       0x2c000200, 0xfc001e00, "ucxt,x(s,b)", pa10, FLAG_STRICT},
 777 { "cstd",       0x2c000200, 0xfc001e00, "ucxt,x(b)", pa10, FLAG_STRICT},
 778 { "cstd",       0x2c001200, 0xfc001e00, "ucmt,5(s,b)", pa10, FLAG_STRICT},
 779 { "cstd",       0x2c001200, 0xfc001e00, "ucmt,5(b)", pa10, FLAG_STRICT},
 780 };
 781
 782 #define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0]))
 783
 784 /* SKV 12/18/92. Added some denotations for various operands. */
 785
 786 #define PA_IMM11_AT_31 'i'
 787 #define PA_IMM14_AT_31 'j'
 788 #define PA_IMM21_AT_31 'k'
 789 #define PA_DISP12 'w'
 790 #define PA_DISP17 'W'
 791
 792 #define N_HPPA_OPERAND_FORMATS 5