include/opcode/nds32.h

   1 /* nds32.h -- Header file for nds32 opcode table
   2    Copyright (C) 2012-2013 Free Software Foundation, Inc.
   3    Contributed by Andes Technology Corporation.
   4
   5    This program is free software; you can redistribute it and/or modify
   6    it under the terms of the GNU General Public License as published by
   7    the Free Software Foundation; either version 3, or (at your option)
   8    any later version.
   9
  10    This program is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13    GNU General Public License for more details.
  14
  15    You should have received a copy of the GNU General Public License
  16    along with this program; if not, write to the Free Software
  17    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
  18    02110-1301, USA.  */
  19
  20 #ifndef OPCODE_NDS32_H
  21 #define OPCODE_NDS32_H
  22
  23 /* Registers.  */
  24 #define REG_R5          5
  25 #define REG_R8          8
  26 #define REG_R10         10
  27 #define REG_R12         12
  28 #define REG_R15         15
  29 #define REG_R16         16
  30 #define REG_R20         20
  31 #define REG_TA          15
  32 #define REG_FP          28
  33 #define REG_GP          29
  34 #define REG_LP          30
  35 #define REG_SP          31
  36 \f
  37 /* Macros for extracting fields or making an instruction.  */
  38 static const int nds32_r45map[] =
  39 {
  40   0, 1, 2,  3,  4,  5,  6,  7,
  41   8, 9, 10, 11, 16, 17, 18, 19
  42 };
  43
  44 static const int nds32_r54map[] =
  45 {
  46    0,  1,  2,  3,  4,  5,  6,  7,
  47    8,  9, 10, 11, -1, -1, -1, -1,
  48   12, 13, 14, 15, -1, -1, -1, -1,
  49   -1, -1, -1, -1, -1, -1, -1, -1
  50 };
  51
  52 #define __BIT(n)                (1 << (n))
  53 #define __MASK(n)               (__BIT (n) - 1)
  54 #define __MF(v, off, bs)        (((v) & __MASK (bs)) << (off))
  55 #define __GF(v, off, bs)        (((v) >> off) & __MASK (bs))
  56 #define __SEXT(v, bs)           ((((v) & ((1 << (bs)) - 1)) ^ (1 << ((bs) - 1))) - (1 << ((bs) - 1)))
  57
  58 /* Make nds32 instructions.  */
  59
  60 #define N32_TYPE4(op6, rt5, ra5, rb5, rd5, sub5)  \
  61         (__MF (N32_OP6_##op6, 25, 6) | __MF (rt5, 20, 5) \
  62          | __MF (ra5, 15, 5) | __MF (rb5, 10, 5) \
  63          | __MF (rd5, 5, 5) | __MF (sub5, 0, 5))
  64 #define N32_TYPE3(op6, rt5, ra5, rb5, sub10) \
  65         (N32_TYPE4 (op6, rt5, ra5, rb5, 0, 0) \
  66          | __MF (sub10, 0, 10))
  67 #define N32_TYPE2(op6, rt5, ra5, imm15) \
  68         (N32_TYPE3 (op6, rt5, ra5, 0, 0) | __MF (imm15, 0, 15))
  69 #define N32_TYPE1(op6, rt5, imm20) \
  70         (N32_TYPE2 (op6, rt5, 0, 0) | __MF (imm20, 0, 20))
  71 #define N32_TYPE0(op6, imm25) \
  72         (N32_TYPE1 (op6, 0, 0) | __MF (imm25, 0, 25))
  73 #define N32_ALU1(sub, rt, ra, rb) \
  74         N32_TYPE4 (ALU1, rt, ra, rb, 0, N32_ALU1_##sub)
  75 #define N32_ALU1_SH(sub, rt, ra, rb, rd) \
  76         N32_TYPE4 (ALU1, rt, ra, rb, rd, N32_ALU1_##sub)
  77 #define N32_ALU2(sub, rt, ra, rb) \
  78         N32_TYPE3 (ALU2, rt, ra, rb, N32_ALU2_##sub)
  79 #define N32_BR1(sub, rt, ra, imm14s) \
  80         N32_TYPE2 (BR1, rt, ra, (N32_BR1_##sub << 14) | (imm14s & __MASK (14)))
  81 #define N32_BR2(sub, rt, imm16s) \
  82         N32_TYPE1 (BR2, rt, (N32_BR2_##sub << 16) | (imm16s & __MASK (16)))
  83 #define N32_BR3(sub, rt, imm11s, imm8s) \
  84         N32_TYPE1 (BR3, rt, (N32_BR3_##sub << 19) \
  85                             | ((imm11s & __MASK (11)) << 8) \
  86                             | (imm8s & __MASK (8)))
  87 #define N32_JI(sub, imm24s) \
  88         N32_TYPE0 (JI, (N32_JI_##sub << 24) | (imm24s & __MASK (24)))
  89 #define N32_JREG(sub, rt, rb, dtit, hint) \
  90         N32_TYPE4(JREG, rt, 0, rb, (dtit << 3) | (hint & 7), N32_JREG_##sub)
  91 #define N32_MEM(sub, rt, ra, rb, sv) \
  92         N32_TYPE3 (MEM, rt, ra, rb, (sv << 8) | N32_MEM_##sub)
  93
  94 #define N16_TYPE55(op5, rt5, ra5) \
  95         (0x8000 | __MF (N16_T55_##op5, 10, 5) | __MF (rt5, 5, 5) \
  96          | __MF (ra5, 0, 5))
  97 #define N16_TYPE45(op6, rt4, ra5) \
  98         (0x8000 | __MF (N16_T45_##op6, 9, 6) | __MF (rt4, 5, 4) \
  99          | __MF (ra5, 0, 5))
 100 #define N16_TYPE333(op6, rt3, ra3, rb3) \
 101         (0x8000 | __MF (N16_T333_##op6, 9, 6) | __MF (rt3, 6, 3) \
 102          | __MF (ra3, 3, 3) | __MF (rb3, 0, 3))
 103 #define N16_TYPE36(op6, rt3, imm6) \
 104         (0x8000 | __MF (N16_T36_##op6, 9, 6) | __MF (rt3, 6, 3) \
 105          | __MF (imm6, 0, 6))
 106 #define N16_TYPE38(op4, rt3, imm8) \
 107         (0x8000 | __MF (N16_T38_##op4, 11, 4) | __MF (rt3, 8, 3) \
 108          | __MF (imm8, 0, 8))
 109 #define N16_TYPE37(op4, rt3, ls, imm7) \
 110         (0x8000 | __MF (N16_T37_##op4, 11, 4) | __MF (rt3, 8, 3) \
 111          | __MF (imm7, 0, 7) | __MF (ls, 7, 1))
 112 #define N16_TYPE5(op10, imm5) \
 113         (0x8000 | __MF (N16_T5_##op10, 5, 10) | __MF (imm5, 0, 5))
 114 #define N16_TYPE8(op7, imm8) \
 115         (0x8000 | __MF (N16_T8_##op7, 8, 7) | __MF (imm8, 0, 8))
 116 #define N16_TYPE9(op6, imm9) \
 117         (0x8000 | __MF (N16_T9_##op6, 9, 6) | __MF (imm9, 0, 9))
 118 #define N16_TYPE10(op5, imm10) \
 119         (0x8000 | __MF (N16_T10_##op5, 10, 5) | __MF (imm10, 0, 10))
 120 #define N16_TYPE25(op8, re, imm5) \
 121         (0x8000 | __MF (N16_T25_##op8, 7, 8) | __MF (re, 5, 2) \
 122          | __MF (imm5, 0, 5))
 123
 124 #define N16_MISC33(sub, rt, ra) \
 125         N16_TYPE333 (MISC33, rt, ra, N16_MISC33_##sub)
 126 #define N16_BFMI333(sub, rt, ra) \
 127         N16_TYPE333 (BFMI333, rt, ra, N16_BFMI333_##sub)
 128
 129 /* Get instruction fields.
 130
 131    Macros used for handling 32-bit and 16-bit instructions are
 132    prefixed with N32_ and N16_ respectively.  */
 133
 134 #define N32_OP6(insn)           (((insn) >> 25) & 0x3f)
 135 #define N32_RT5(insn)           (((insn) >> 20) & 0x1f)
 136 #define N32_RT53(insn)          (N32_RT5 (insn) & 0x7)
 137 #define N32_RT54(insn)          nds32_r54map[N32_RT5 (insn)]
 138 #define N32_RA5(insn)           (((insn) >> 15) & 0x1f)
 139 #define N32_RA53(insn)          (N32_RA5 (insn) & 0x7)
 140 #define N32_RA54(insn)          nds32_r54map[N32_RA5 (insn)]
 141 #define N32_RB5(insn)           (((insn) >> 10) & 0x1f)
 142 #define N32_UB5(insn)           (((insn) >> 10) & 0x1f)
 143 #define N32_RB53(insn)          (N32_RB5 (insn) & 0x7)
 144 #define N32_RB54(insn)          nds32_r54map[N32_RB5 (insn)]
 145 #define N32_RD5(insn)           (((insn) >> 5) & 0x1f)
 146 #define N32_SH5(insn)           (((insn) >> 5) & 0x1f)
 147 #define N32_SUB5(insn)          (((insn) >> 0) & 0x1f)
 148 #define N32_SWID(insn)          (((insn) >> 5) & 0x3ff)
 149 #define N32_IMMU(insn, bs)      ((insn) & __MASK (bs))
 150 #define N32_IMMS(insn, bs)      ((signed) __SEXT (((insn) & __MASK (bs)), bs))
 151 #define N32_IMM5U(insn)         N32_IMMU (insn, 5)
 152 #define N32_IMM12S(insn)        N32_IMMS (insn, 12)
 153 #define N32_IMM14S(insn)        N32_IMMS (insn, 14)
 154 #define N32_IMM15U(insn)        N32_IMMU (insn, 15)
 155 #define N32_IMM15S(insn)        N32_IMMS (insn, 15)
 156 #define N32_IMM16S(insn)        N32_IMMS (insn, 16)
 157 #define N32_IMM17S(insn)        N32_IMMS (insn, 17)
 158 #define N32_IMM20S(insn)        N32_IMMS (insn, 20)
 159 #define N32_IMM20U(insn)        N32_IMMU (insn, 20)
 160 #define N32_IMM24S(insn)        N32_IMMS (insn, 24)
 161
 162 #define N16_RT5(insn)           (((insn) >> 5) & 0x1f)
 163 #define N16_RT4(insn)           nds32_r45map[(((insn) >> 5) & 0xf)]
 164 #define N16_RT3(insn)           (((insn) >> 6) & 0x7)
 165 #define N16_RT38(insn)          (((insn) >> 8) & 0x7)
 166 #define N16_RT8(insn)           (((insn) >> 8) & 0x7)
 167 #define N16_RA5(insn)           ((insn) & 0x1f)
 168 #define N16_RA3(insn)           (((insn) >> 3) & 0x7)
 169 #define N16_RB3(insn)           ((insn) & 0x7)
 170 #define N16_IMM3U(insn)         N32_IMMU (insn, 3)
 171 #define N16_IMM5U(insn)         N32_IMMU (insn, 5)
 172 #define N16_IMM5S(insn)         N32_IMMS (insn, 5)
 173 #define N16_IMM6U(insn)         N32_IMMU (insn, 6)
 174 #define N16_IMM7U(insn)         N32_IMMU (insn, 7)
 175 #define N16_IMM8S(insn)         N32_IMMS (insn, 8)
 176 #define N16_IMM9U(insn)         N32_IMMU (insn, 9)
 177 #define N16_IMM10S(insn)        N32_IMMS (insn, 10)
 178
 179 #define IS_WITHIN_U(v, n)       (((v) >> n) == 0)
 180 #define IS_WITHIN_S(v, n)       IS_WITHIN_U ((v) + (1 << ((n) - 1)), n)
 181
 182 /* Get fields for specific instruction.  */
 183 #define N32_JREG_T(insn)        (((insn) >> 8) & 0x3)
 184 #define N32_JREG_HINT(insn)     (((insn) >> 5) & 0x7)
 185 #define N32_BR2_SUB(insn)       (((insn) >> 16) & 0xf)
 186 #define N32_COP_SUB(insn)       ((insn) & 0xf)
 187 #define N32_COP_CP(insn)        (((insn) >> 4) & 0x3)
 188
 189 /* Check fields.  */
 190 #define N32_IS_RT3(insn)        (N32_RT5 (insn) < 8)
 191 #define N32_IS_RA3(insn)        (N32_RA5 (insn) < 8)
 192 #define N32_IS_RB3(insn)        (N32_RB5 (insn) < 8)
 193 #define N32_IS_RT4(insn)        (nds32_r54map[N32_RT5 (insn)] != -1)
 194 #define N32_IS_RA4(insn)        (nds32_r54map[N32_RA5 (insn)] != -1)
 195 #define N32_IS_RB4(insn)        (nds32_r54map[N32_RB5 (insn)] != -1)
 196
 197
 198 /* These are opcodes for Nxx_TYPE macros.
 199    They are prefixed by corresponding TYPE to avoid misusing.  */
 200
 201 enum n32_opcodes
 202 {
 203   /* Main opcodes (OP6).  */
 204
 205   N32_OP6_LBI = 0x0,
 206   N32_OP6_LHI,
 207   N32_OP6_LWI,
 208   N32_OP6_LDI,
 209   N32_OP6_LBI_BI,
 210   N32_OP6_LHI_BI,
 211   N32_OP6_LWI_BI,
 212   N32_OP6_LDI_BI,
 213
 214   N32_OP6_SBI = 0x8,
 215   N32_OP6_SHI,
 216   N32_OP6_SWI,
 217   N32_OP6_SDI,
 218   N32_OP6_SBI_BI,
 219   N32_OP6_SHI_BI,
 220   N32_OP6_SWI_BI,
 221   N32_OP6_SDI_BI,
 222
 223   N32_OP6_LBSI = 0x10,
 224   N32_OP6_LHSI,
 225   N32_OP6_LWSI,
 226   N32_OP6_DPREFI,
 227   N32_OP6_LBSI_BI,
 228   N32_OP6_LHSI_BI,
 229   N32_OP6_LWSI_BI,
 230   N32_OP6_LBGP,
 231
 232   N32_OP6_LWC = 0x18,
 233   N32_OP6_SWC,
 234   N32_OP6_LDC,
 235   N32_OP6_SDC,
 236   N32_OP6_MEM,
 237   N32_OP6_LSMW,
 238   N32_OP6_HWGP,
 239   N32_OP6_SBGP,
 240
 241   N32_OP6_ALU1 = 0x20,
 242   N32_OP6_ALU2,
 243   N32_OP6_MOVI,
 244   N32_OP6_SETHI,
 245   N32_OP6_JI,
 246   N32_OP6_JREG,
 247   N32_OP6_BR1,
 248   N32_OP6_BR2,
 249
 250   N32_OP6_ADDI = 0x28,
 251   N32_OP6_SUBRI,
 252   N32_OP6_ANDI,
 253   N32_OP6_XORI,
 254   N32_OP6_ORI,
 255   N32_OP6_BR3,
 256   N32_OP6_SLTI,
 257   N32_OP6_SLTSI,
 258
 259   N32_OP6_AEXT = 0x30,
 260   N32_OP6_CEXT,
 261   N32_OP6_MISC,
 262   N32_OP6_BITCI,
 263   N32_OP6_0x34,
 264   N32_OP6_COP,
 265   N32_OP6_0x36,
 266   N32_OP6_0x37,
 267
 268   N32_OP6_SIMD = 0x38,
 269
 270   /* Sub-opcodes of specific opcode.  */
 271
 272   /* bit-24 */
 273   N32_BR1_BEQ = 0,
 274   N32_BR1_BNE = 1,
 275
 276   /* bit[16:19] */
 277   N32_BR2_IFCALL = 0,
 278   N32_BR2_BEQZ = 2,
 279   N32_BR2_BNEZ = 3,
 280   N32_BR2_BGEZ = 4,
 281   N32_BR2_BLTZ = 5,
 282   N32_BR2_BGTZ = 6,
 283   N32_BR2_BLEZ = 7,
 284   N32_BR2_BGEZAL = 0xc,
 285   N32_BR2_BLTZAL = 0xd,
 286
 287   /* bit-19 */
 288   N32_BR3_BEQC = 0,
 289   N32_BR3_BNEC = 1,
 290
 291   /* bit-24 */
 292   N32_JI_J = 0,
 293   N32_JI_JAL = 1,
 294
 295   /* bit[0:4] */
 296   N32_JREG_JR = 0,
 297   N32_JREG_JRAL = 1,
 298   N32_JREG_JRNEZ = 2,
 299   N32_JREG_JRALNEZ = 3,
 300
 301   /* bit[0:4] */
 302   N32_ALU1_ADD_SLLI = 0x0,
 303   N32_ALU1_SUB_SLLI,
 304   N32_ALU1_AND_SLLI,
 305   N32_ALU1_XOR_SLLI,
 306   N32_ALU1_OR_SLLI,
 307   N32_ALU1_ADD = 0x0,
 308   N32_ALU1_SUB,
 309   N32_ALU1_AND,
 310   N32_ALU1_XOR,
 311   N32_ALU1_OR,
 312   N32_ALU1_NOR,
 313   N32_ALU1_SLT,
 314   N32_ALU1_SLTS,
 315   N32_ALU1_SLLI = 0x8,
 316   N32_ALU1_SRLI,
 317   N32_ALU1_SRAI,
 318   N32_ALU1_ROTRI,
 319   N32_ALU1_SLL,
 320   N32_ALU1_SRL,
 321   N32_ALU1_SRA,
 322   N32_ALU1_ROTR,
 323   N32_ALU1_SEB = 0x10,
 324   N32_ALU1_SEH,
 325   N32_ALU1_BITC,
 326   N32_ALU1_ZEH,
 327   N32_ALU1_WSBH,
 328   N32_ALU1_OR_SRLI,
 329   N32_ALU1_DIVSR,
 330   N32_ALU1_DIVR,
 331   N32_ALU1_SVA = 0x18,
 332   N32_ALU1_SVS,
 333   N32_ALU1_CMOVZ,
 334   N32_ALU1_CMOVN,
 335   N32_ALU1_ADD_SRLI,
 336   N32_ALU1_SUB_SRLI,
 337   N32_ALU1_AND_SRLI,
 338   N32_ALU1_XOR_SRLI,
 339
 340   /* bit[0:5], where bit[6:9] == 0 */
 341   N32_ALU2_MAX = 0,
 342   N32_ALU2_MIN,
 343   N32_ALU2_AVE,
 344   N32_ALU2_ABS,
 345   N32_ALU2_CLIPS,
 346   N32_ALU2_CLIP,
 347   N32_ALU2_CLO,
 348   N32_ALU2_CLZ,
 349   N32_ALU2_BSET = 0x8,
 350   N32_ALU2_BCLR,
 351   N32_ALU2_BTGL,
 352   N32_ALU2_BTST,
 353   N32_ALU2_BSE,
 354   N32_ALU2_BSP,
 355   N32_ALU2_FFB,
 356   N32_ALU2_FFMISM,
 357   N32_ALU2_ADD_SC = 0x10,
 358   N32_ALU2_SUB_SC,
 359   N32_ALU2_ADD_WC,
 360   N32_ALU2_SUB_WC,
 361   N32_ALU2_0x14,
 362   N32_ALU2_0x15,
 363   N32_ALU2_0x16,
 364   N32_ALU2_FFZMISM,
 365   N32_ALU2_QADD = 0x18,
 366   N32_ALU2_QSUB,
 367   N32_ALU2_MFUSR = 0x20,
 368   N32_ALU2_MTUSR,
 369   N32_ALU2_0x22,
 370   N32_ALU2_0x23,
 371   N32_ALU2_MUL,
 372   N32_ALU2_0x25,
 373   N32_ALU2_0x26,
 374   N32_ALU2_MULTS64 = 0x28,
 375   N32_ALU2_MULT64,
 376   N32_ALU2_MADDS64,
 377   N32_ALU2_MADD64,
 378   N32_ALU2_MSUBS64,
 379   N32_ALU2_MSUB64,
 380   N32_ALU2_DIVS,
 381   N32_ALU2_DIV,
 382   N32_ALU2_0x30 = 0x30,
 383   N32_ALU2_MULT32,
 384   N32_ALU2_0x32,
 385   N32_ALU2_MADD32,
 386   N32_ALU2_0x34,
 387   N32_ALU2_MSUB32,
 388
 389   /* bit[0:5], where bit[6:9] != 0  */
 390   N32_ALU2_FFBI = 0xe,
 391   N32_ALU2_FLMISM = 0xf,
 392   N32_ALU2_MULSR64 = 0x28,
 393   N32_ALU2_MULR64 = 0x29,
 394   N32_ALU2_MADDR32 = 0x33,
 395   N32_ALU2_MSUBR32 = 0x35,
 396
 397   /* bit[0:5] */
 398   N32_MEM_LB = 0,
 399   N32_MEM_LH,
 400   N32_MEM_LW,
 401   N32_MEM_LD,
 402   N32_MEM_LB_BI,
 403   N32_MEM_LH_BI,
 404   N32_MEM_LW_BI,
 405   N32_MEM_LD_BI,
 406   N32_MEM_SB,
 407   N32_MEM_SH,
 408   N32_MEM_SW,
 409   N32_MEM_SD,
 410   N32_MEM_SB_BI,
 411   N32_MEM_SH_BI,
 412   N32_MEM_SW_BI,
 413   N32_MEM_SD_BI,
 414   N32_MEM_LBS,
 415   N32_MEM_LHS,
 416   N32_MEM_LWS, /* Not used.  */
 417   N32_MEM_DPREF,
 418   N32_MEM_LBS_BI,
 419   N32_MEM_LHS_BI,
 420   N32_MEM_LWS_BI, /* Not used.  */
 421   N32_MEM_0x17, /* Not used.  */
 422   N32_MEM_LLW,
 423   N32_MEM_SCW,
 424   N32_MEM_LBUP = 0x20,
 425   N32_MEM_LWUP = 0x22,
 426   N32_MEM_SBUP = 0x28,
 427   N32_MEM_SWUP = 0x2a,
 428
 429   /* bit[0:1] */
 430   N32_LSMW_LSMW = 0,
 431   N32_LSMW_LSMWA,
 432   N32_LSMW_LSMWZB,
 433
 434   /* bit[2:4] */
 435   N32_LSMW_BI = 0,
 436   N32_LSMW_BIM,
 437   N32_LSMW_BD,
 438   N32_LSMW_BDM,
 439   N32_LSMW_AI,
 440   N32_LSMW_AIM,
 441   N32_LSMW_AD,
 442   N32_LSMW_ADM,
 443
 444   /* bit[0:4] */
 445   N32_MISC_STANDBY = 0,
 446   N32_MISC_CCTL,
 447   N32_MISC_MFSR,
 448   N32_MISC_MTSR,
 449   N32_MISC_IRET,
 450   N32_MISC_TRAP,
 451   N32_MISC_TEQZ,
 452   N32_MISC_TNEZ,
 453   N32_MISC_DSB = 0x8,
 454   N32_MISC_ISB,
 455   N32_MISC_BREAK,
 456   N32_MISC_SYSCALL,
 457   N32_MISC_MSYNC,
 458   N32_MISC_ISYNC,
 459   N32_MISC_TLBOP,
 460   N32_MISC_0xf,
 461
 462   /* bit[0;4] */
 463   N32_SIMD_PBSAD = 0,
 464   N32_SIMD_PBSADA = 1,
 465
 466   /* bit[0:3] */
 467   N32_COP_CPE1 = 0,
 468   N32_COP_MFCP,
 469   N32_COP_CPLW,
 470   N32_COP_CPLD,
 471   N32_COP_CPE2,
 472   N32_COP_CPE3 = 8,
 473   N32_COP_MTCP,
 474   N32_COP_CPSW,
 475   N32_COP_CPSD,
 476   N32_COP_CPE4,
 477
 478   /* cop/0 b[3:0] */
 479   N32_FPU_FS1 = 0,
 480   N32_FPU_MFCP,
 481   N32_FPU_FLS,
 482   N32_FPU_FLD,
 483   N32_FPU_FS2,
 484   N32_FPU_FD1 = 8,
 485   N32_FPU_MTCP,
 486   N32_FPU_FSS,
 487   N32_FPU_FSD,
 488   N32_FPU_FD2,
 489
 490   /* FS1 b[9:6] */
 491   N32_FPU_FS1_FADDS = 0,
 492   N32_FPU_FS1_FSUBS,
 493   N32_FPU_FS1_FCPYNSS,
 494   N32_FPU_FS1_FCPYSS,
 495   N32_FPU_FS1_FMADDS,
 496   N32_FPU_FS1_FMSUBS,
 497   N32_FPU_FS1_FCMOVNS,
 498   N32_FPU_FS1_FCMOVZS,
 499   N32_FPU_FS1_FNMADDS,
 500   N32_FPU_FS1_FNMSUBS,
 501   N32_FPU_FS1_10,
 502   N32_FPU_FS1_11,
 503   N32_FPU_FS1_FMULS = 12,
 504   N32_FPU_FS1_FDIVS,
 505   N32_FPU_FS1_14,
 506   N32_FPU_FS1_F2OP = 15,
 507
 508   /* FS1/F2OP b[14:10] */
 509   N32_FPU_FS1_F2OP_FS2D = 0x00,
 510   N32_FPU_FS1_F2OP_FSQRTS  = 0x01,
 511   N32_FPU_FS1_F2OP_FABSS  = 0x05,
 512   N32_FPU_FS1_F2OP_FUI2S  = 0x08,
 513   N32_FPU_FS1_F2OP_FSI2S  = 0x0c,
 514   N32_FPU_FS1_F2OP_FS2UI  = 0x10,
 515   N32_FPU_FS1_F2OP_FS2UI_Z = 0x14,
 516   N32_FPU_FS1_F2OP_FS2SI  = 0x18,
 517   N32_FPU_FS1_F2OP_FS2SI_Z = 0x1c,
 518
 519   /* FS2 b[9:6] */
 520   N32_FPU_FS2_FCMPEQS = 0x0,
 521   N32_FPU_FS2_FCMPLTS = 0x2,
 522   N32_FPU_FS2_FCMPLES = 0x4,
 523   N32_FPU_FS2_FCMPUNS = 0x6,
 524   N32_FPU_FS2_FCMPEQS_E = 0x1,
 525   N32_FPU_FS2_FCMPLTS_E = 0x3,
 526   N32_FPU_FS2_FCMPLES_E = 0x5,
 527   N32_FPU_FS2_FCMPUNS_E = 0x7,
 528
 529   /* FD1 b[9:6] */
 530   N32_FPU_FD1_FADDD = 0,
 531   N32_FPU_FD1_FSUBD,
 532   N32_FPU_FD1_FCPYNSD,
 533   N32_FPU_FD1_FCPYSD,
 534   N32_FPU_FD1_FMADDD,
 535   N32_FPU_FD1_FMSUBD,
 536   N32_FPU_FD1_FCMOVND,
 537   N32_FPU_FD1_FCMOVZD,
 538   N32_FPU_FD1_FNMADDD,
 539   N32_FPU_FD1_FNMSUBD,
 540   N32_FPU_FD1_10,
 541   N32_FPU_FD1_11,
 542   N32_FPU_FD1_FMULD = 12,
 543   N32_FPU_FD1_FDIVD,
 544   N32_FPU_FD1_14,
 545   N32_FPU_FD1_F2OP = 15,
 546
 547   /* FD1/F2OP b[14:10] */
 548   N32_FPU_FD1_F2OP_FD2S = 0x00,
 549   N32_FPU_FD1_F2OP_FSQRTD = 0x01,
 550   N32_FPU_FD1_F2OP_FABSD = 0x05,
 551   N32_FPU_FD1_F2OP_FUI2D = 0x08,
 552   N32_FPU_FD1_F2OP_FSI2D = 0x0c,
 553   N32_FPU_FD1_F2OP_FD2UI = 0x10,
 554   N32_FPU_FD1_F2OP_FD2UI_Z = 0x14,
 555   N32_FPU_FD1_F2OP_FD2SI = 0x18,
 556   N32_FPU_FD1_F2OP_FD2SI_Z = 0x1c,
 557
 558   /* FD2 b[9:6] */
 559   N32_FPU_FD2_FCMPEQD = 0x0,
 560   N32_FPU_FD2_FCMPLTD = 0x2,
 561   N32_FPU_FD2_FCMPLED = 0x4,
 562   N32_FPU_FD2_FCMPUND = 0x6,
 563   N32_FPU_FD2_FCMPEQD_E = 0x1,
 564   N32_FPU_FD2_FCMPLTD_E = 0x3,
 565   N32_FPU_FD2_FCMPLED_E = 0x5,
 566   N32_FPU_FD2_FCMPUND_E = 0x7,
 567
 568   /* MFCP b[9:6] */
 569   N32_FPU_MFCP_FMFSR = 0x0,
 570   N32_FPU_MFCP_FMFDR = 0x1,
 571   N32_FPU_MFCP_XR = 0xc,
 572
 573   /* MFCP/XR b[14:10] */
 574   N32_FPU_MFCP_XR_FMFCFG = 0x0,
 575   N32_FPU_MFCP_XR_FMFCSR = 0x1,
 576
 577   /* MTCP b[9:6] */
 578   N32_FPU_MTCP_FMTSR = 0x0,
 579   N32_FPU_MTCP_FMTDR = 0x1,
 580   N32_FPU_MTCP_XR = 0xc,
 581
 582   /* MTCP/XR b[14:10] */
 583   N32_FPU_MTCP_XR_FMTCSR = 0x1
 584 };
 585
 586 enum n16_opcodes
 587 {
 588   N16_T55_MOV55 = 0x0,
 589   N16_T55_MOVI55 = 0x1,
 590
 591   N16_T45_0 = 0,
 592   N16_T45_ADD45 = 0x4,
 593   N16_T45_SUB45 = 0x5,
 594   N16_T45_ADDI45 = 0x6,
 595   N16_T45_SUBI45 = 0x7,
 596   N16_T45_SRAI45 = 0x8,
 597   N16_T45_SRLI45 = 0x9,
 598   N16_T45_LWI45_FE = 0x19,
 599   N16_T45_LWI450 = 0x1a,
 600   N16_T45_SWI450 = 0x1b,
 601   N16_T45_SLTS45 = 0x30,
 602   N16_T45_SLT45 = 0x31,
 603   N16_T45_SLTSI45 = 0x32,
 604   N16_T45_SLTI45 = 0x33,
 605   N16_T45_MOVPI45 = 0x3d,
 606
 607   N15_T44_MOVD44 = 0x7d,
 608
 609   N16_T333_0 = 0,
 610   N16_T333_SLLI333 = 0xa,
 611   N16_T333_BFMI333 = 0xb,
 612   N16_T333_ADD333 = 0xc,
 613   N16_T333_SUB333 = 0xd,
 614   N16_T333_ADDI333 = 0xe,
 615   N16_T333_SUBI333 = 0xf,
 616   N16_T333_LWI333 = 0x10,
 617   N16_T333_LWI333_BI = 0x11,
 618   N16_T333_LHI333 = 0x12,
 619   N16_T333_LBI333 = 0x13,
 620   N16_T333_SWI333 = 0x14,
 621   N16_T333_SWI333_BI = 0x15,
 622   N16_T333_SHI333 = 0x16,
 623   N16_T333_SBI333 = 0x17,
 624   N16_T333_MISC33 = 0x3f,
 625
 626   N16_T36_ADDRI36_SP = 0x18,
 627
 628   N16_T37_XWI37 = 0x7,
 629   N16_T37_XWI37SP = 0xe,
 630
 631   N16_T38_BEQZ38 = 0x8,
 632   N16_T38_BNEZ38 = 0x9,
 633   N16_T38_BEQS38 = 0xa,
 634   N16_T38_BNES38 = 0xb,
 635
 636   N16_T5_JR5 = 0x2e8,
 637   N16_T5_JRAL5 = 0x2e9,
 638   N16_T5_EX9IT = 0x2ea,
 639   /* 0x2eb reserved.  */
 640   N16_T5_RET5 = 0x2ec,
 641   N16_T5_ADD5PC = 0x2ed,
 642   /* 0x2e[ef] reserved.  */
 643   N16_T5_BREAK16 = 0x350,
 644
 645   N16_T8_J8 = 0x55,
 646   N16_T8_BEQZS8 = 0x68,
 647   N16_T8_BNEZS8 = 0x69,
 648
 649   /* N16_T9_BREAK16 = 0x35
 650      Since v3, SWID of BREAK16 above 32 are used for encoding EX9.IT.  */
 651   N16_T9_EX9IT = 0x35,
 652   N16_T9_IFCALL9 = 0x3c,
 653
 654   N16_T10_ADDI10S = 0x1b,
 655
 656   N16_T25_PUSH25 = 0xf8,
 657   N16_T25_POP25 = 0xf9,
 658
 659   /* Sub-opcodes.  */
 660   N16_MISC33_0 = 0,
 661   N16_MISC33_1 = 1,
 662   N16_MISC33_NEG33 = 2,
 663   N16_MISC33_NOT33 = 3,
 664   N16_MISC33_MUL33 = 4,
 665   N16_MISC33_XOR33 = 5,
 666   N16_MISC33_AND33 = 6,
 667   N16_MISC33_OR33 = 7,
 668
 669   N16_BFMI333_ZEB33 = 0,
 670   N16_BFMI333_ZEH33 = 1,
 671   N16_BFMI333_SEB33 = 2,
 672   N16_BFMI333_SEH33 = 3,
 673   N16_BFMI333_XLSB33 = 4,
 674   N16_BFMI333_X11B33 = 5,
 675   N16_BFMI333_BMSKI33 = 6,
 676   N16_BFMI333_FEXTI33 = 7
 677 };
 678 \f
 679 /* These macros a deprecated.  DO NOT use them anymore.
 680    And please help rewrite code used them.  */
 681
 682 /* 32-bit instructions without operands.  */
 683 #define INSN_SETHI  0x46000000
 684 #define INSN_ORI    0x58000000
 685 #define INSN_JR     0x4a000000
 686 #define INSN_RET    0x4a000020
 687 #define INSN_JAL    0x49000000
 688 #define INSN_J      0x48000000
 689 #define INSN_JRAL   0x4a000001
 690 #define INSN_BGEZAL 0x4e0c0000
 691 #define INSN_BLTZAL 0x4e0d0000
 692 #define INSN_BEQ    0x4c000000
 693 #define INSN_BNE    0x4c004000
 694 #define INSN_BEQZ   0x4e020000
 695 #define INSN_BNEZ   0x4e030000
 696 #define INSN_BGEZ   0x4e040000
 697 #define INSN_BLTZ   0x4e050000
 698 #define INSN_BGTZ   0x4e060000
 699 #define INSN_BLEZ   0x4e070000
 700 #define INSN_MOVI   0x44000000
 701 #define INSN_ADDI   0x50000000
 702 #define INSN_ANDI   0x54000000
 703 #define INSN_LDI    0x06000000
 704 #define INSN_SDI    0x16000000
 705 #define INSN_LWI    0x04000000
 706 #define INSN_LWSI   0x24000000
 707 #define INSN_LWIP   0x0c000000
 708 #define INSN_LHI    0x02000000
 709 #define INSN_LHSI   0x22000000
 710 #define INSN_LBI    0x00000000
 711 #define INSN_LBSI   0x20000000
 712 #define INSN_SWI    0x14000000
 713 #define INSN_SWIP   0x1c000000
 714 #define INSN_SHI    0x12000000
 715 #define INSN_SBI    0x10000000
 716 #define INSN_SLTI   0x5c000000
 717 #define INSN_SLTSI  0x5e000000
 718 #define INSN_ADD    0x40000000
 719 #define INSN_SUB    0x40000001
 720 #define INSN_SLT    0x40000006
 721 #define INSN_SLTS   0x40000007
 722 #define INSN_SLLI   0x40000008
 723 #define INSN_SRLI   0x40000009
 724 #define INSN_SRAI   0x4000000a
 725 #define INSN_SEB    0x40000010
 726 #define INSN_SEH    0x40000011
 727 #define INSN_ZEB    INSN_ANDI + 0xFF
 728 #define INSN_ZEH    0x40000013
 729 #define INSN_BREAK  0x6400000a
 730 #define INSN_NOP    0x40000009
 731 #define INSN_FLSI   0x30000000
 732 #define INSN_FSSI   0x32000000
 733 #define INSN_FLDI   0x34000000
 734 #define INSN_FSDI   0x36000000
 735 #define INSN_BEQC   0x5a000000
 736 #define INSN_BNEC   0x5a080000
 737 #define INSN_DSB    0x64000008
 738 #define INSN_IFCALL 0x4e000000
 739 #define INSN_IFRET  0x4a000060
 740 #define INSN_BR1    0x4c000000
 741 #define INSN_BR2    0x4e000000
 742
 743 /* 16-bit instructions without operand.  */
 744 #define INSN_MOV55      0x8000
 745 #define INSN_MOVI55     0x8400
 746 #define INSN_ADD45      0x8800
 747 #define INSN_SUB45      0x8a00
 748 #define INSN_ADDI45     0x8c00
 749 #define INSN_SUBI45     0x8e00
 750 #define INSN_SRAI45     0x9000
 751 #define INSN_SRLI45     0x9200
 752 #define INSN_SLLI333    0x9400
 753 #define INSN_BFMI333    0x9600
 754 #define INSN_ADD333     0x9800
 755 #define INSN_SUB333     0x9a00
 756 #define INSN_ADDI333    0x9c00
 757 #define INSN_SUBI333    0x9e00
 758 #define INSN_LWI333     0xa000
 759 #define INSN_LWI333P    0xa200
 760 #define INSN_LHI333     0xa400
 761 #define INSN_LBI333     0xa600
 762 #define INSN_SWI333     0xa800
 763 #define INSN_SWI333P    0xaa00
 764 #define INSN_SHI333     0xac00
 765 #define INSN_SBI333     0xae00
 766 #define INSN_RSV01      0xb000
 767 #define INSN_RSV02      0xb200
 768 #define INSN_LWI450     0xb400
 769 #define INSN_SWI450     0xb600
 770 #define INSN_LWI37      0xb800
 771 #define INSN_SWI37      0xb880
 772 #define INSN_BEQZ38     0xc000
 773 #define INSN_BNEZ38     0xc800
 774 #define INSN_BEQS38     0xd000
 775 #define INSN_J8         0xd500
 776 #define INSN_BNES38     0xd800
 777 #define INSN_JR5        0xdd00
 778 #define INSN_RET5       0xdd80
 779 #define INSN_JRAL5      0xdd20
 780 #define INSN_EX9_IT_2   0xdd40
 781 #define INSN_SLTS45     0xe000
 782 #define INSN_SLT45      0xe200
 783 #define INSN_SLTSI45    0xe400
 784 #define INSN_SLTI45     0xe600
 785 #define INSN_BEQZS8     0xe800
 786 #define INSN_BNEZS8     0xe900
 787 #define INSN_BREAK16    0xea00
 788 #define INSN_EX9_IT_1   0xea00
 789 #define INSN_NOP16      0x9200
 790 /* 16-bit version 2.  */
 791 #define INSN_ADDI10_SP  0xec00
 792 #define INSN_LWI37SP    0xf000
 793 #define INSN_SWI37SP    0xf080
 794 /* 16-bit version 3.  */
 795 #define INSN_IFRET16    0x83ff
 796 #define INSN_ADDRI36_SP 0xb000
 797 #define INSN_LWI45_FE   0xb200
 798 #define INSN_IFCALL9    0xf800
 799 #define INSN_MISC33     0xfe00
 800
 801 /* Instruction with specific operands.  */
 802 #define INSN_ADDI_GP_TO_FP      0x51cd8000      /* BASELINE_V1.  */
 803 #define INSN_ADDIGP_TO_FP       0x3fc80000      /* BASELINE_V2.  */
 804 #define INSN_MOVI_TO_FP         0x45c00000
 805 #define INSN_MFUSR_PC           0x420F8020
 806 #define INSN_MFUSR_PC_MASK      0xFE0FFFFF
 807
 808 /* Instructions use $ta register as operand.  */
 809 #define INSN_SETHI_TA   (INSN_SETHI | (REG_TA << 20))
 810 #define INSN_ORI_TA     (INSN_ORI | (REG_TA << 20) | (REG_TA << 15))
 811 #define INSN_ADD_TA     (INSN_ADD | (REG_TA << 20))
 812 #define INSN_ADD45_TA   (INSN_ADD45 | (REG_TA << 5))
 813 #define INSN_JR5_TA     (INSN_JR5 | (REG_TA << 0))
 814 #define INSN_RET5_TA    (INSN_RET5 | (REG_TA << 0))
 815 #define INSN_JR_TA      (INSN_JR | (REG_TA << 10))
 816 #define INSN_RET_TA     (INSN_RET | (REG_TA << 10))
 817 #define INSN_JRAL_TA    (INSN_JRAL | (REG_LP << 20) | (REG_TA << 10))
 818 #define INSN_JRAL5_TA   (INSN_JRAL5 | (REG_TA << 0))
 819 #define INSN_BEQZ_TA    (INSN_BEQZ | (REG_TA << 20))
 820 #define INSN_BNEZ_TA    (INSN_BNEZ | (REG_TA << 20))
 821 #define INSN_MOVI_TA    (INSN_MOVI | (REG_TA << 20))
 822 #define INSN_BEQ_TA     (INSN_BEQ | (REG_TA << 15))
 823 #define INSN_BNE_TA     (INSN_BNE | (REG_TA << 15))
 824
 825 /* Instructions use $r5 register as operand.  */
 826 #define INSN_BNE_R5     (INSN_BNE | (REG_R5 << 15))
 827 #define INSN_BEQ_R5     (INSN_BEQ | (REG_R5 << 15))
 828
 829 #endif