include/uapi/drm/drm.h

   1 /**
   2  * \file drm.h
   3  * Header for the Direct Rendering Manager
   4  *
   5  * \author Rickard E. (Rik) Faith <faith@valinux.com>
   6  *
   7  * \par Acknowledgments:
   8  * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
   9  */
  10
  11 /*
  12  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  13  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  14  * All rights reserved.
  15  *
  16  * Permission is hereby granted, free of charge, to any person obtaining a
  17  * copy of this software and associated documentation files (the "Software"),
  18  * to deal in the Software without restriction, including without limitation
  19  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  20  * and/or sell copies of the Software, and to permit persons to whom the
  21  * Software is furnished to do so, subject to the following conditions:
  22  *
  23  * The above copyright notice and this permission notice (including the next
  24  * paragraph) shall be included in all copies or substantial portions of the
  25  * Software.
  26  *
  27  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  28  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  29  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  30  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  31  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  32  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  33  * OTHER DEALINGS IN THE SOFTWARE.
  34  */
  35
  36 #ifndef _DRM_H_
  37 #define _DRM_H_
  38
  39 #if defined(__KERNEL__) || defined(__linux__)
  40
  41 #include <linux/types.h>
  42 #include <asm/ioctl.h>
  43 typedef unsigned int drm_handle_t;
  44
  45 #else /* One of the BSDs */
  46
  47 #include <sys/ioccom.h>
  48 #include <sys/types.h>
  49 typedef int8_t   __s8;
  50 typedef uint8_t  __u8;
  51 typedef int16_t  __s16;
  52 typedef uint16_t __u16;
  53 typedef int32_t  __s32;
  54 typedef uint32_t __u32;
  55 typedef int64_t  __s64;
  56 typedef uint64_t __u64;
  57 typedef size_t   __kernel_size_t;
  58 typedef unsigned long drm_handle_t;
  59
  60 #endif
  61
  62 #define DRM_NAME        "drm"     /**< Name in kernel, /dev, and /proc */
  63 #define DRM_MIN_ORDER   5         /**< At least 2^5 bytes = 32 bytes */
  64 #define DRM_MAX_ORDER   22        /**< Up to 2^22 bytes = 4MB */
  65 #define DRM_RAM_PERCENT 10        /**< How much system ram can we lock? */
  66
  67 #define _DRM_LOCK_HELD  0x80000000U /**< Hardware lock is held */
  68 #define _DRM_LOCK_CONT  0x40000000U /**< Hardware lock is contended */
  69 #define _DRM_LOCK_IS_HELD(lock)    ((lock) & _DRM_LOCK_HELD)
  70 #define _DRM_LOCK_IS_CONT(lock)    ((lock) & _DRM_LOCK_CONT)
  71 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
  72
  73 typedef unsigned int drm_context_t;
  74 typedef unsigned int drm_drawable_t;
  75 typedef unsigned int drm_magic_t;
  76
  77 /**
  78  * Cliprect.
  79  *
  80  * \warning: If you change this structure, make sure you change
  81  * XF86DRIClipRectRec in the server as well
  82  *
  83  * \note KW: Actually it's illegal to change either for
  84  * backwards-compatibility reasons.
  85  */
  86 struct drm_clip_rect {
  87         unsigned short x1;
  88         unsigned short y1;
  89         unsigned short x2;
  90         unsigned short y2;
  91 };
  92
  93 /**
  94  * Drawable information.
  95  */
  96 struct drm_drawable_info {
  97         unsigned int num_rects;
  98         struct drm_clip_rect *rects;
  99 };
 100
 101 /**
 102  * Texture region,
 103  */
 104 struct drm_tex_region {
 105         unsigned char next;
 106         unsigned char prev;
 107         unsigned char in_use;
 108         unsigned char padding;
 109         unsigned int age;
 110 };
 111
 112 /**
 113  * Hardware lock.
 114  *
 115  * The lock structure is a simple cache-line aligned integer.  To avoid
 116  * processor bus contention on a multiprocessor system, there should not be any
 117  * other data stored in the same cache line.
 118  */
 119 struct drm_hw_lock {
 120         __volatile__ unsigned int lock;         /**< lock variable */
 121         char padding[60];                       /**< Pad to cache line */
 122 };
 123
 124 /**
 125  * DRM_IOCTL_VERSION ioctl argument type.
 126  *
 127  * \sa drmGetVersion().
 128  */
 129 struct drm_version {
 130         int version_major;        /**< Major version */
 131         int version_minor;        /**< Minor version */
 132         int version_patchlevel;   /**< Patch level */
 133         __kernel_size_t name_len;         /**< Length of name buffer */
 134         char __user *name;        /**< Name of driver */
 135         __kernel_size_t date_len;         /**< Length of date buffer */
 136         char __user *date;        /**< User-space buffer to hold date */
 137         __kernel_size_t desc_len;         /**< Length of desc buffer */
 138         char __user *desc;        /**< User-space buffer to hold desc */
 139 };
 140
 141 /**
 142  * DRM_IOCTL_GET_UNIQUE ioctl argument type.
 143  *
 144  * \sa drmGetBusid() and drmSetBusId().
 145  */
 146 struct drm_unique {
 147         __kernel_size_t unique_len;       /**< Length of unique */
 148         char __user *unique;      /**< Unique name for driver instantiation */
 149 };
 150
 151 struct drm_list {
 152         int count;                /**< Length of user-space structures */
 153         struct drm_version __user *version;
 154 };
 155
 156 struct drm_block {
 157         int unused;
 158 };
 159
 160 /**
 161  * DRM_IOCTL_CONTROL ioctl argument type.
 162  *
 163  * \sa drmCtlInstHandler() and drmCtlUninstHandler().
 164  */
 165 struct drm_control {
 166         enum {
 167                 DRM_ADD_COMMAND,
 168                 DRM_RM_COMMAND,
 169                 DRM_INST_HANDLER,
 170                 DRM_UNINST_HANDLER
 171         } func;
 172         int irq;
 173 };
 174
 175 /**
 176  * Type of memory to map.
 177  */
 178 enum drm_map_type {
 179         _DRM_FRAME_BUFFER = 0,    /**< WC (no caching), no core dump */
 180         _DRM_REGISTERS = 1,       /**< no caching, no core dump */
 181         _DRM_SHM = 2,             /**< shared, cached */
 182         _DRM_AGP = 3,             /**< AGP/GART */
 183         _DRM_SCATTER_GATHER = 4,  /**< Scatter/gather memory for PCI DMA */
 184         _DRM_CONSISTENT = 5,      /**< Consistent memory for PCI DMA */
 185 };
 186
 187 /**
 188  * Memory mapping flags.
 189  */
 190 enum drm_map_flags {
 191         _DRM_RESTRICTED = 0x01,      /**< Cannot be mapped to user-virtual */
 192         _DRM_READ_ONLY = 0x02,
 193         _DRM_LOCKED = 0x04,          /**< shared, cached, locked */
 194         _DRM_KERNEL = 0x08,          /**< kernel requires access */
 195         _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
 196         _DRM_CONTAINS_LOCK = 0x20,   /**< SHM page that contains lock */
 197         _DRM_REMOVABLE = 0x40,       /**< Removable mapping */
 198         _DRM_DRIVER = 0x80           /**< Managed by driver */
 199 };
 200
 201 struct drm_ctx_priv_map {
 202         unsigned int ctx_id;     /**< Context requesting private mapping */
 203         void *handle;            /**< Handle of map */
 204 };
 205
 206 /**
 207  * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
 208  * argument type.
 209  *
 210  * \sa drmAddMap().
 211  */
 212 struct drm_map {
 213         unsigned long offset;    /**< Requested physical address (0 for SAREA)*/
 214         unsigned long size;      /**< Requested physical size (bytes) */
 215         enum drm_map_type type;  /**< Type of memory to map */
 216         enum drm_map_flags flags;        /**< Flags */
 217         void *handle;            /**< User-space: "Handle" to pass to mmap() */
 218                                  /**< Kernel-space: kernel-virtual address */
 219         int mtrr;                /**< MTRR slot used */
 220         /*   Private data */
 221 };
 222
 223 /**
 224  * DRM_IOCTL_GET_CLIENT ioctl argument type.
 225  */
 226 struct drm_client {
 227         int idx;                /**< Which client desired? */
 228         int auth;               /**< Is client authenticated? */
 229         unsigned long pid;      /**< Process ID */
 230         unsigned long uid;      /**< User ID */
 231         unsigned long magic;    /**< Magic */
 232         unsigned long iocs;     /**< Ioctl count */
 233 };
 234
 235 enum drm_stat_type {
 236         _DRM_STAT_LOCK,
 237         _DRM_STAT_OPENS,
 238         _DRM_STAT_CLOSES,
 239         _DRM_STAT_IOCTLS,
 240         _DRM_STAT_LOCKS,
 241         _DRM_STAT_UNLOCKS,
 242         _DRM_STAT_VALUE,        /**< Generic value */
 243         _DRM_STAT_BYTE,         /**< Generic byte counter (1024bytes/K) */
 244         _DRM_STAT_COUNT,        /**< Generic non-byte counter (1000/k) */
 245
 246         _DRM_STAT_IRQ,          /**< IRQ */
 247         _DRM_STAT_PRIMARY,      /**< Primary DMA bytes */
 248         _DRM_STAT_SECONDARY,    /**< Secondary DMA bytes */
 249         _DRM_STAT_DMA,          /**< DMA */
 250         _DRM_STAT_SPECIAL,      /**< Special DMA (e.g., priority or polled) */
 251         _DRM_STAT_MISSED        /**< Missed DMA opportunity */
 252             /* Add to the *END* of the list */
 253 };
 254
 255 /**
 256  * DRM_IOCTL_GET_STATS ioctl argument type.
 257  */
 258 struct drm_stats {
 259         unsigned long count;
 260         struct {
 261                 unsigned long value;
 262                 enum drm_stat_type type;
 263         } data[15];
 264 };
 265
 266 /**
 267  * Hardware locking flags.
 268  */
 269 enum drm_lock_flags {
 270         _DRM_LOCK_READY = 0x01,      /**< Wait until hardware is ready for DMA */
 271         _DRM_LOCK_QUIESCENT = 0x02,  /**< Wait until hardware quiescent */
 272         _DRM_LOCK_FLUSH = 0x04,      /**< Flush this context's DMA queue first */
 273         _DRM_LOCK_FLUSH_ALL = 0x08,  /**< Flush all DMA queues first */
 274         /* These *HALT* flags aren't supported yet
 275            -- they will be used to support the
 276            full-screen DGA-like mode. */
 277         _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
 278         _DRM_HALT_CUR_QUEUES = 0x20  /**< Halt all current queues */
 279 };
 280
 281 /**
 282  * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
 283  *
 284  * \sa drmGetLock() and drmUnlock().
 285  */
 286 struct drm_lock {
 287         int context;
 288         enum drm_lock_flags flags;
 289 };
 290
 291 /**
 292  * DMA flags
 293  *
 294  * \warning
 295  * These values \e must match xf86drm.h.
 296  *
 297  * \sa drm_dma.
 298  */
 299 enum drm_dma_flags {
 300         /* Flags for DMA buffer dispatch */
 301         _DRM_DMA_BLOCK = 0x01,        /**<
 302                                        * Block until buffer dispatched.
 303                                        *
 304                                        * \note The buffer may not yet have
 305                                        * been processed by the hardware --
 306                                        * getting a hardware lock with the
 307                                        * hardware quiescent will ensure
 308                                        * that the buffer has been
 309                                        * processed.
 310                                        */
 311         _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
 312         _DRM_DMA_PRIORITY = 0x04,     /**< High priority dispatch */
 313
 314         /* Flags for DMA buffer request */
 315         _DRM_DMA_WAIT = 0x10,         /**< Wait for free buffers */
 316         _DRM_DMA_SMALLER_OK = 0x20,   /**< Smaller-than-requested buffers OK */
 317         _DRM_DMA_LARGER_OK = 0x40     /**< Larger-than-requested buffers OK */
 318 };
 319
 320 /**
 321  * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
 322  *
 323  * \sa drmAddBufs().
 324  */
 325 struct drm_buf_desc {
 326         int count;               /**< Number of buffers of this size */
 327         int size;                /**< Size in bytes */
 328         int low_mark;            /**< Low water mark */
 329         int high_mark;           /**< High water mark */
 330         enum {
 331                 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
 332                 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
 333                 _DRM_SG_BUFFER = 0x04,  /**< Scatter/gather memory buffer */
 334                 _DRM_FB_BUFFER = 0x08,  /**< Buffer is in frame buffer */
 335                 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
 336         } flags;
 337         unsigned long agp_start; /**<
 338                                   * Start address of where the AGP buffers are
 339                                   * in the AGP aperture
 340                                   */
 341 };
 342
 343 /**
 344  * DRM_IOCTL_INFO_BUFS ioctl argument type.
 345  */
 346 struct drm_buf_info {
 347         int count;              /**< Entries in list */
 348         struct drm_buf_desc __user *list;
 349 };
 350
 351 /**
 352  * DRM_IOCTL_FREE_BUFS ioctl argument type.
 353  */
 354 struct drm_buf_free {
 355         int count;
 356         int __user *list;
 357 };
 358
 359 /**
 360  * Buffer information
 361  *
 362  * \sa drm_buf_map.
 363  */
 364 struct drm_buf_pub {
 365         int idx;                       /**< Index into the master buffer list */
 366         int total;                     /**< Buffer size */
 367         int used;                      /**< Amount of buffer in use (for DMA) */
 368         void __user *address;          /**< Address of buffer */
 369 };
 370
 371 /**
 372  * DRM_IOCTL_MAP_BUFS ioctl argument type.
 373  */
 374 struct drm_buf_map {
 375         int count;              /**< Length of the buffer list */
 376         void __user *virtual;           /**< Mmap'd area in user-virtual */
 377         struct drm_buf_pub __user *list;        /**< Buffer information */
 378 };
 379
 380 /**
 381  * DRM_IOCTL_DMA ioctl argument type.
 382  *
 383  * Indices here refer to the offset into the buffer list in drm_buf_get.
 384  *
 385  * \sa drmDMA().
 386  */
 387 struct drm_dma {
 388         int context;                      /**< Context handle */
 389         int send_count;                   /**< Number of buffers to send */
 390         int __user *send_indices;         /**< List of handles to buffers */
 391         int __user *send_sizes;           /**< Lengths of data to send */
 392         enum drm_dma_flags flags;         /**< Flags */
 393         int request_count;                /**< Number of buffers requested */
 394         int request_size;                 /**< Desired size for buffers */
 395         int __user *request_indices;      /**< Buffer information */
 396         int __user *request_sizes;
 397         int granted_count;                /**< Number of buffers granted */
 398 };
 399
 400 enum drm_ctx_flags {
 401         _DRM_CONTEXT_PRESERVED = 0x01,
 402         _DRM_CONTEXT_2DONLY = 0x02
 403 };
 404
 405 /**
 406  * DRM_IOCTL_ADD_CTX ioctl argument type.
 407  *
 408  * \sa drmCreateContext() and drmDestroyContext().
 409  */
 410 struct drm_ctx {
 411         drm_context_t handle;
 412         enum drm_ctx_flags flags;
 413 };
 414
 415 /**
 416  * DRM_IOCTL_RES_CTX ioctl argument type.
 417  */
 418 struct drm_ctx_res {
 419         int count;
 420         struct drm_ctx __user *contexts;
 421 };
 422
 423 /**
 424  * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
 425  */
 426 struct drm_draw {
 427         drm_drawable_t handle;
 428 };
 429
 430 /**
 431  * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
 432  */
 433 typedef enum {
 434         DRM_DRAWABLE_CLIPRECTS,
 435 } drm_drawable_info_type_t;
 436
 437 struct drm_update_draw {
 438         drm_drawable_t handle;
 439         unsigned int type;
 440         unsigned int num;
 441         unsigned long long data;
 442 };
 443
 444 /**
 445  * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
 446  */
 447 struct drm_auth {
 448         drm_magic_t magic;
 449 };
 450
 451 /**
 452  * DRM_IOCTL_IRQ_BUSID ioctl argument type.
 453  *
 454  * \sa drmGetInterruptFromBusID().
 455  */
 456 struct drm_irq_busid {
 457         int irq;        /**< IRQ number */
 458         int busnum;     /**< bus number */
 459         int devnum;     /**< device number */
 460         int funcnum;    /**< function number */
 461 };
 462
 463 enum drm_vblank_seq_type {
 464         _DRM_VBLANK_ABSOLUTE = 0x0,     /**< Wait for specific vblank sequence number */
 465         _DRM_VBLANK_RELATIVE = 0x1,     /**< Wait for given number of vblanks */
 466         /* bits 1-6 are reserved for high crtcs */
 467         _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e,
 468         _DRM_VBLANK_EVENT = 0x4000000,   /**< Send event instead of blocking */
 469         _DRM_VBLANK_FLIP = 0x8000000,   /**< Scheduled buffer swap should flip */
 470         _DRM_VBLANK_NEXTONMISS = 0x10000000,    /**< If missed, wait for next vblank */
 471         _DRM_VBLANK_SECONDARY = 0x20000000,     /**< Secondary display controller */
 472         _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */
 473 };
 474 #define _DRM_VBLANK_HIGH_CRTC_SHIFT 1
 475
 476 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
 477 #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \
 478                                 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)
 479
 480 struct drm_wait_vblank_request {
 481         enum drm_vblank_seq_type type;
 482         unsigned int sequence;
 483         unsigned long signal;
 484 };
 485
 486 struct drm_wait_vblank_reply {
 487         enum drm_vblank_seq_type type;
 488         unsigned int sequence;
 489         long tval_sec;
 490         long tval_usec;
 491 };
 492
 493 /**
 494  * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
 495  *
 496  * \sa drmWaitVBlank().
 497  */
 498 union drm_wait_vblank {
 499         struct drm_wait_vblank_request request;
 500         struct drm_wait_vblank_reply reply;
 501 };
 502
 503 #define _DRM_PRE_MODESET 1
 504 #define _DRM_POST_MODESET 2
 505
 506 /**
 507  * DRM_IOCTL_MODESET_CTL ioctl argument type
 508  *
 509  * \sa drmModesetCtl().
 510  */
 511 struct drm_modeset_ctl {
 512         __u32 crtc;
 513         __u32 cmd;
 514 };
 515
 516 /**
 517  * DRM_IOCTL_AGP_ENABLE ioctl argument type.
 518  *
 519  * \sa drmAgpEnable().
 520  */
 521 struct drm_agp_mode {
 522         unsigned long mode;     /**< AGP mode */
 523 };
 524
 525 /**
 526  * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
 527  *
 528  * \sa drmAgpAlloc() and drmAgpFree().
 529  */
 530 struct drm_agp_buffer {
 531         unsigned long size;     /**< In bytes -- will round to page boundary */
 532         unsigned long handle;   /**< Used for binding / unbinding */
 533         unsigned long type;     /**< Type of memory to allocate */
 534         unsigned long physical; /**< Physical used by i810 */
 535 };
 536
 537 /**
 538  * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
 539  *
 540  * \sa drmAgpBind() and drmAgpUnbind().
 541  */
 542 struct drm_agp_binding {
 543         unsigned long handle;   /**< From drm_agp_buffer */
 544         unsigned long offset;   /**< In bytes -- will round to page boundary */
 545 };
 546
 547 /**
 548  * DRM_IOCTL_AGP_INFO ioctl argument type.
 549  *
 550  * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
 551  * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
 552  * drmAgpVendorId() and drmAgpDeviceId().
 553  */
 554 struct drm_agp_info {
 555         int agp_version_major;
 556         int agp_version_minor;
 557         unsigned long mode;
 558         unsigned long aperture_base;    /* physical address */
 559         unsigned long aperture_size;    /* bytes */
 560         unsigned long memory_allowed;   /* bytes */
 561         unsigned long memory_used;
 562
 563         /* PCI information */
 564         unsigned short id_vendor;
 565         unsigned short id_device;
 566 };
 567
 568 /**
 569  * DRM_IOCTL_SG_ALLOC ioctl argument type.
 570  */
 571 struct drm_scatter_gather {
 572         unsigned long size;     /**< In bytes -- will round to page boundary */
 573         unsigned long handle;   /**< Used for mapping / unmapping */
 574 };
 575
 576 /**
 577  * DRM_IOCTL_SET_VERSION ioctl argument type.
 578  */
 579 struct drm_set_version {
 580         int drm_di_major;
 581         int drm_di_minor;
 582         int drm_dd_major;
 583         int drm_dd_minor;
 584 };
 585
 586 /** DRM_IOCTL_GEM_CLOSE ioctl argument type */
 587 struct drm_gem_close {
 588         /** Handle of the object to be closed. */
 589         __u32 handle;
 590         __u32 pad;
 591 };
 592
 593 /** DRM_IOCTL_GEM_FLINK ioctl argument type */
 594 struct drm_gem_flink {
 595         /** Handle for the object being named */
 596         __u32 handle;
 597
 598         /** Returned global name */
 599         __u32 name;
 600 };
 601
 602 /** DRM_IOCTL_GEM_OPEN ioctl argument type */
 603 struct drm_gem_open {
 604         /** Name of object being opened */
 605         __u32 name;
 606
 607         /** Returned handle for the object */
 608         __u32 handle;
 609
 610         /** Returned size of the object */
 611         __u64 size;
 612 };
 613
 614 #define DRM_CAP_DUMB_BUFFER             0x1
 615 #define DRM_CAP_VBLANK_HIGH_CRTC        0x2
 616 #define DRM_CAP_DUMB_PREFERRED_DEPTH    0x3
 617 #define DRM_CAP_DUMB_PREFER_SHADOW      0x4
 618 #define DRM_CAP_PRIME                   0x5
 619 #define  DRM_PRIME_CAP_IMPORT           0x1
 620 #define  DRM_PRIME_CAP_EXPORT           0x2
 621 #define DRM_CAP_TIMESTAMP_MONOTONIC     0x6
 622 #define DRM_CAP_ASYNC_PAGE_FLIP         0x7
 623 /*
 624  * The CURSOR_WIDTH and CURSOR_HEIGHT capabilities return a valid widthxheight
 625  * combination for the hardware cursor. The intention is that a hardware
 626  * agnostic userspace can query a cursor plane size to use.
 627  *
 628  * Note that the cross-driver contract is to merely return a valid size;
 629  * drivers are free to attach another meaning on top, eg. i915 returns the
 630  * maximum plane size.
 631  */
 632 #define DRM_CAP_CURSOR_WIDTH            0x8
 633 #define DRM_CAP_CURSOR_HEIGHT           0x9
 634 #define DRM_CAP_ADDFB2_MODIFIERS        0x10
 635
 636 /** DRM_IOCTL_GET_CAP ioctl argument type */
 637 struct drm_get_cap {
 638         __u64 capability;
 639         __u64 value;
 640 };
 641
 642 /**
 643  * DRM_CLIENT_CAP_STEREO_3D
 644  *
 645  * if set to 1, the DRM core will expose the stereo 3D capabilities of the
 646  * monitor by advertising the supported 3D layouts in the flags of struct
 647  * drm_mode_modeinfo.
 648  */
 649 #define DRM_CLIENT_CAP_STEREO_3D        1
 650
 651 /**
 652  * DRM_CLIENT_CAP_UNIVERSAL_PLANES
 653  *
 654  * If set to 1, the DRM core will expose all planes (overlay, primary, and
 655  * cursor) to userspace.
 656  */
 657 #define DRM_CLIENT_CAP_UNIVERSAL_PLANES  2
 658
 659 /**
 660  * DRM_CLIENT_CAP_ATOMIC
 661  *
 662  * If set to 1, the DRM core will expose atomic properties to userspace
 663  */
 664 #define DRM_CLIENT_CAP_ATOMIC   3
 665
 666 /** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
 667 struct drm_set_client_cap {
 668         __u64 capability;
 669         __u64 value;
 670 };
 671
 672 #define DRM_CLOEXEC O_CLOEXEC
 673 struct drm_prime_handle {
 674         __u32 handle;
 675
 676         /** Flags.. only applicable for handle->fd */
 677         __u32 flags;
 678
 679         /** Returned dmabuf file descriptor */
 680         __s32 fd;
 681 };
 682
 683 #include <drm/drm_mode.h>
 684
 685 #define DRM_IOCTL_BASE                  'd'
 686 #define DRM_IO(nr)                      _IO(DRM_IOCTL_BASE,nr)
 687 #define DRM_IOR(nr,type)                _IOR(DRM_IOCTL_BASE,nr,type)
 688 #define DRM_IOW(nr,type)                _IOW(DRM_IOCTL_BASE,nr,type)
 689 #define DRM_IOWR(nr,type)               _IOWR(DRM_IOCTL_BASE,nr,type)
 690
 691 #define DRM_IOCTL_VERSION               DRM_IOWR(0x00, struct drm_version)
 692 #define DRM_IOCTL_GET_UNIQUE            DRM_IOWR(0x01, struct drm_unique)
 693 #define DRM_IOCTL_GET_MAGIC             DRM_IOR( 0x02, struct drm_auth)
 694 #define DRM_IOCTL_IRQ_BUSID             DRM_IOWR(0x03, struct drm_irq_busid)
 695 #define DRM_IOCTL_GET_MAP               DRM_IOWR(0x04, struct drm_map)
 696 #define DRM_IOCTL_GET_CLIENT            DRM_IOWR(0x05, struct drm_client)
 697 #define DRM_IOCTL_GET_STATS             DRM_IOR( 0x06, struct drm_stats)
 698 #define DRM_IOCTL_SET_VERSION           DRM_IOWR(0x07, struct drm_set_version)
 699 #define DRM_IOCTL_MODESET_CTL           DRM_IOW(0x08, struct drm_modeset_ctl)
 700 #define DRM_IOCTL_GEM_CLOSE             DRM_IOW (0x09, struct drm_gem_close)
 701 #define DRM_IOCTL_GEM_FLINK             DRM_IOWR(0x0a, struct drm_gem_flink)
 702 #define DRM_IOCTL_GEM_OPEN              DRM_IOWR(0x0b, struct drm_gem_open)
 703 #define DRM_IOCTL_GET_CAP               DRM_IOWR(0x0c, struct drm_get_cap)
 704 #define DRM_IOCTL_SET_CLIENT_CAP        DRM_IOW( 0x0d, struct drm_set_client_cap)
 705
 706 #define DRM_IOCTL_SET_UNIQUE            DRM_IOW( 0x10, struct drm_unique)
 707 #define DRM_IOCTL_AUTH_MAGIC            DRM_IOW( 0x11, struct drm_auth)
 708 #define DRM_IOCTL_BLOCK                 DRM_IOWR(0x12, struct drm_block)
 709 #define DRM_IOCTL_UNBLOCK               DRM_IOWR(0x13, struct drm_block)
 710 #define DRM_IOCTL_CONTROL               DRM_IOW( 0x14, struct drm_control)
 711 #define DRM_IOCTL_ADD_MAP               DRM_IOWR(0x15, struct drm_map)
 712 #define DRM_IOCTL_ADD_BUFS              DRM_IOWR(0x16, struct drm_buf_desc)
 713 #define DRM_IOCTL_MARK_BUFS             DRM_IOW( 0x17, struct drm_buf_desc)
 714 #define DRM_IOCTL_INFO_BUFS             DRM_IOWR(0x18, struct drm_buf_info)
 715 #define DRM_IOCTL_MAP_BUFS              DRM_IOWR(0x19, struct drm_buf_map)
 716 #define DRM_IOCTL_FREE_BUFS             DRM_IOW( 0x1a, struct drm_buf_free)
 717
 718 #define DRM_IOCTL_RM_MAP                DRM_IOW( 0x1b, struct drm_map)
 719
 720 #define DRM_IOCTL_SET_SAREA_CTX         DRM_IOW( 0x1c, struct drm_ctx_priv_map)
 721 #define DRM_IOCTL_GET_SAREA_CTX         DRM_IOWR(0x1d, struct drm_ctx_priv_map)
 722
 723 #define DRM_IOCTL_SET_MASTER            DRM_IO(0x1e)
 724 #define DRM_IOCTL_DROP_MASTER           DRM_IO(0x1f)
 725
 726 #define DRM_IOCTL_ADD_CTX               DRM_IOWR(0x20, struct drm_ctx)
 727 #define DRM_IOCTL_RM_CTX                DRM_IOWR(0x21, struct drm_ctx)
 728 #define DRM_IOCTL_MOD_CTX               DRM_IOW( 0x22, struct drm_ctx)
 729 #define DRM_IOCTL_GET_CTX               DRM_IOWR(0x23, struct drm_ctx)
 730 #define DRM_IOCTL_SWITCH_CTX            DRM_IOW( 0x24, struct drm_ctx)
 731 #define DRM_IOCTL_NEW_CTX               DRM_IOW( 0x25, struct drm_ctx)
 732 #define DRM_IOCTL_RES_CTX               DRM_IOWR(0x26, struct drm_ctx_res)
 733 #define DRM_IOCTL_ADD_DRAW              DRM_IOWR(0x27, struct drm_draw)
 734 #define DRM_IOCTL_RM_DRAW               DRM_IOWR(0x28, struct drm_draw)
 735 #define DRM_IOCTL_DMA                   DRM_IOWR(0x29, struct drm_dma)
 736 #define DRM_IOCTL_LOCK                  DRM_IOW( 0x2a, struct drm_lock)
 737 #define DRM_IOCTL_UNLOCK                DRM_IOW( 0x2b, struct drm_lock)
 738 #define DRM_IOCTL_FINISH                DRM_IOW( 0x2c, struct drm_lock)
 739
 740 #define DRM_IOCTL_PRIME_HANDLE_TO_FD    DRM_IOWR(0x2d, struct drm_prime_handle)
 741 #define DRM_IOCTL_PRIME_FD_TO_HANDLE    DRM_IOWR(0x2e, struct drm_prime_handle)
 742
 743 #define DRM_IOCTL_AGP_ACQUIRE           DRM_IO(  0x30)
 744 #define DRM_IOCTL_AGP_RELEASE           DRM_IO(  0x31)
 745 #define DRM_IOCTL_AGP_ENABLE            DRM_IOW( 0x32, struct drm_agp_mode)
 746 #define DRM_IOCTL_AGP_INFO              DRM_IOR( 0x33, struct drm_agp_info)
 747 #define DRM_IOCTL_AGP_ALLOC             DRM_IOWR(0x34, struct drm_agp_buffer)
 748 #define DRM_IOCTL_AGP_FREE              DRM_IOW( 0x35, struct drm_agp_buffer)
 749 #define DRM_IOCTL_AGP_BIND              DRM_IOW( 0x36, struct drm_agp_binding)
 750 #define DRM_IOCTL_AGP_UNBIND            DRM_IOW( 0x37, struct drm_agp_binding)
 751
 752 #define DRM_IOCTL_SG_ALLOC              DRM_IOWR(0x38, struct drm_scatter_gather)
 753 #define DRM_IOCTL_SG_FREE               DRM_IOW( 0x39, struct drm_scatter_gather)
 754
 755 #define DRM_IOCTL_WAIT_VBLANK           DRM_IOWR(0x3a, union drm_wait_vblank)
 756
 757 #define DRM_IOCTL_UPDATE_DRAW           DRM_IOW(0x3f, struct drm_update_draw)
 758
 759 #define DRM_IOCTL_MODE_GETRESOURCES     DRM_IOWR(0xA0, struct drm_mode_card_res)
 760 #define DRM_IOCTL_MODE_GETCRTC          DRM_IOWR(0xA1, struct drm_mode_crtc)
 761 #define DRM_IOCTL_MODE_SETCRTC          DRM_IOWR(0xA2, struct drm_mode_crtc)
 762 #define DRM_IOCTL_MODE_CURSOR           DRM_IOWR(0xA3, struct drm_mode_cursor)
 763 #define DRM_IOCTL_MODE_GETGAMMA         DRM_IOWR(0xA4, struct drm_mode_crtc_lut)
 764 #define DRM_IOCTL_MODE_SETGAMMA         DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
 765 #define DRM_IOCTL_MODE_GETENCODER       DRM_IOWR(0xA6, struct drm_mode_get_encoder)
 766 #define DRM_IOCTL_MODE_GETCONNECTOR     DRM_IOWR(0xA7, struct drm_mode_get_connector)
 767 #define DRM_IOCTL_MODE_ATTACHMODE       DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */
 768 #define DRM_IOCTL_MODE_DETACHMODE       DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */
 769
 770 #define DRM_IOCTL_MODE_GETPROPERTY      DRM_IOWR(0xAA, struct drm_mode_get_property)
 771 #define DRM_IOCTL_MODE_SETPROPERTY      DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
 772 #define DRM_IOCTL_MODE_GETPROPBLOB      DRM_IOWR(0xAC, struct drm_mode_get_blob)
 773 #define DRM_IOCTL_MODE_GETFB            DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
 774 #define DRM_IOCTL_MODE_ADDFB            DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
 775 #define DRM_IOCTL_MODE_RMFB             DRM_IOWR(0xAF, unsigned int)
 776 #define DRM_IOCTL_MODE_PAGE_FLIP        DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
 777 #define DRM_IOCTL_MODE_DIRTYFB          DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)
 778
 779 #define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)
 780 #define DRM_IOCTL_MODE_MAP_DUMB    DRM_IOWR(0xB3, struct drm_mode_map_dumb)
 781 #define DRM_IOCTL_MODE_DESTROY_DUMB    DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)
 782 #define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res)
 783 #define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane)
 784 #define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane)
 785 #define DRM_IOCTL_MODE_ADDFB2           DRM_IOWR(0xB8, struct drm_mode_fb_cmd2)
 786 #define DRM_IOCTL_MODE_OBJ_GETPROPERTIES        DRM_IOWR(0xB9, struct drm_mode_obj_get_properties)
 787 #define DRM_IOCTL_MODE_OBJ_SETPROPERTY  DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
 788 #define DRM_IOCTL_MODE_CURSOR2          DRM_IOWR(0xBB, struct drm_mode_cursor2)
 789 #define DRM_IOCTL_MODE_ATOMIC           DRM_IOWR(0xBC, struct drm_mode_atomic)
 790 #define DRM_IOCTL_MODE_CREATEPROPBLOB   DRM_IOWR(0xBD, struct drm_mode_create_blob)
 791 #define DRM_IOCTL_MODE_DESTROYPROPBLOB  DRM_IOWR(0xBE, struct drm_mode_destroy_blob)
 792
 793 /**
 794  * Device specific ioctls should only be in their respective headers
 795  * The device specific ioctl range is from 0x40 to 0x9f.
 796  * Generic IOCTLS restart at 0xA0.
 797  *
 798  * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
 799  * drmCommandReadWrite().
 800  */
 801 #define DRM_COMMAND_BASE                0x40
 802 #define DRM_COMMAND_END                 0xA0
 803
 804 /**
 805  * Header for events written back to userspace on the drm fd.  The
 806  * type defines the type of event, the length specifies the total
 807  * length of the event (including the header), and user_data is
 808  * typically a 64 bit value passed with the ioctl that triggered the
 809  * event.  A read on the drm fd will always only return complete
 810  * events, that is, if for example the read buffer is 100 bytes, and
 811  * there are two 64 byte events pending, only one will be returned.
 812  *
 813  * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and
 814  * up are chipset specific.
 815  */
 816 struct drm_event {
 817         __u32 type;
 818         __u32 length;
 819 };
 820
 821 #define DRM_EVENT_VBLANK 0x01
 822 #define DRM_EVENT_FLIP_COMPLETE 0x02
 823
 824 struct drm_event_vblank {
 825         struct drm_event base;
 826         __u64 user_data;
 827         __u32 tv_sec;
 828         __u32 tv_usec;
 829         __u32 sequence;
 830         __u32 reserved;
 831 };
 832
 833 /* typedef area */
 834 #ifndef __KERNEL__
 835 typedef struct drm_clip_rect drm_clip_rect_t;
 836 typedef struct drm_drawable_info drm_drawable_info_t;
 837 typedef struct drm_tex_region drm_tex_region_t;
 838 typedef struct drm_hw_lock drm_hw_lock_t;
 839 typedef struct drm_version drm_version_t;
 840 typedef struct drm_unique drm_unique_t;
 841 typedef struct drm_list drm_list_t;
 842 typedef struct drm_block drm_block_t;
 843 typedef struct drm_control drm_control_t;
 844 typedef enum drm_map_type drm_map_type_t;
 845 typedef enum drm_map_flags drm_map_flags_t;
 846 typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
 847 typedef struct drm_map drm_map_t;
 848 typedef struct drm_client drm_client_t;
 849 typedef enum drm_stat_type drm_stat_type_t;
 850 typedef struct drm_stats drm_stats_t;
 851 typedef enum drm_lock_flags drm_lock_flags_t;
 852 typedef struct drm_lock drm_lock_t;
 853 typedef enum drm_dma_flags drm_dma_flags_t;
 854 typedef struct drm_buf_desc drm_buf_desc_t;
 855 typedef struct drm_buf_info drm_buf_info_t;
 856 typedef struct drm_buf_free drm_buf_free_t;
 857 typedef struct drm_buf_pub drm_buf_pub_t;
 858 typedef struct drm_buf_map drm_buf_map_t;
 859 typedef struct drm_dma drm_dma_t;
 860 typedef union drm_wait_vblank drm_wait_vblank_t;
 861 typedef struct drm_agp_mode drm_agp_mode_t;
 862 typedef enum drm_ctx_flags drm_ctx_flags_t;
 863 typedef struct drm_ctx drm_ctx_t;
 864 typedef struct drm_ctx_res drm_ctx_res_t;
 865 typedef struct drm_draw drm_draw_t;
 866 typedef struct drm_update_draw drm_update_draw_t;
 867 typedef struct drm_auth drm_auth_t;
 868 typedef struct drm_irq_busid drm_irq_busid_t;
 869 typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
 870
 871 typedef struct drm_agp_buffer drm_agp_buffer_t;
 872 typedef struct drm_agp_binding drm_agp_binding_t;
 873 typedef struct drm_agp_info drm_agp_info_t;
 874 typedef struct drm_scatter_gather drm_scatter_gather_t;
 875 typedef struct drm_set_version drm_set_version_t;
 876 #endif
 877
 878 #endif