1 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
3 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
4 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
5 (aarch64_sys_reg_supported_p): Update checks for the above.
7 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
9 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
10 cases MVE_SQRSHRL and MVE_UQRSHLL.
11 (print_insn_mve): Add case for specifier 'k' to check
12 specific bit of the instruction.
14 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
17 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
18 encountering an unknown machine type.
19 (print_insn_arc): Handle arc_insn_length returning 0. In error
20 cases return -1 rather than calling abort.
22 2019-08-07 Jan Beulich <jbeulich@suse.com>
24 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
25 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
27 * i386-tbl.h: Re-generate.
29 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
31 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
34 2019-07-30 Mel Chen <mel.chen@sifive.com>
36 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
37 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
39 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
42 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
44 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
45 and MPY class instructions.
46 (parse_option): Add nps400 option.
47 (print_arc_disassembler_options): Add nps400 info.
49 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
51 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
54 * arc-opc.c (RAD_CHK): Add.
55 * arc-tbl.h: Regenerate.
57 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
59 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
60 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
62 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
64 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
65 instructions as UNPREDICTABLE.
67 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
69 * bpf-desc.c: Regenerated.
71 2019-07-17 Jan Beulich <jbeulich@suse.com>
73 * i386-gen.c (static_assert): Define.
75 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
76 (Opcode_Modifier_Num): ... this.
79 2019-07-16 Jan Beulich <jbeulich@suse.com>
81 * i386-gen.c (operand_types): Move RegMem ...
82 (opcode_modifiers): ... here.
83 * i386-opc.h (RegMem): Move to opcode modifer enum.
84 (union i386_operand_type): Move regmem field ...
85 (struct i386_opcode_modifier): ... here.
86 * i386-opc.tbl (RegMem): Define.
87 (mov, movq): Move RegMem on segment, control, debug, and test
89 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
90 to non-SSE2AVX flavor.
91 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
92 Move RegMem on register only flavors. Drop IgnoreSize from
93 legacy encoding flavors.
94 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
96 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
97 register only flavors.
98 (vmovd): Move RegMem and drop IgnoreSize on register only
99 flavor. Change opcode and operand order to store form.
100 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
102 2019-07-16 Jan Beulich <jbeulich@suse.com>
104 * i386-gen.c (operand_type_init, operand_types): Replace SReg
106 * i386-opc.h (SReg2, SReg3): Replace by ...
108 (union i386_operand_type): Replace sreg fields.
109 * i386-opc.tbl (mov, ): Use SReg.
110 (push, pop): Likewies. Drop i386 and x86-64 specific segment
112 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
113 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
115 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
117 * bpf-desc.c: Regenerate.
118 * bpf-opc.c: Likewise.
119 * bpf-opc.h: Likewise.
121 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
123 * bpf-desc.c: Regenerate.
124 * bpf-opc.c: Likewise.
126 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
128 * arm-dis.c (print_insn_coprocessor): Rename index to
131 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
133 * riscv-opc.c (riscv_insn_types): Add r4 type.
135 * riscv-opc.c (riscv_insn_types): Add b and j type.
137 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
138 format for sb type and correct s type.
140 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
142 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
143 SVE FMOV alias of FCPY.
145 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
147 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
148 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
150 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
152 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
153 registers in an instruction prefixed by MOVPRFX.
155 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
157 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
158 sve_size_13 icode to account for variant behaviour of
160 * aarch64-dis-2.c: Regenerate.
161 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
162 sve_size_13 icode to account for variant behaviour of
164 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
165 (OP_SVE_VVV_Q_D): Add new qualifier.
166 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
167 (struct aarch64_opcode): Split pmull{t,b} into those requiring
170 2019-07-01 Jan Beulich <jbeulich@suse.com>
172 * opcodes/i386-gen.c (operand_type_init): Remove
173 OPERAND_TYPE_VEC_IMM4 entry.
174 (operand_types): Remove Vec_Imm4.
175 * opcodes/i386-opc.h (Vec_Imm4): Delete.
176 (union i386_operand_type): Remove vec_imm4.
177 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
178 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
180 2019-07-01 Jan Beulich <jbeulich@suse.com>
182 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
183 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
184 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
185 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
186 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
187 monitorx, mwaitx): Drop ImmExt from operand-less forms.
188 * i386-tbl.h: Re-generate.
190 2019-07-01 Jan Beulich <jbeulich@suse.com>
192 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
194 * i386-tbl.h: Re-generate.
196 2019-07-01 Jan Beulich <jbeulich@suse.com>
198 * i386-opc.tbl (C): New.
199 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
200 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
201 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
202 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
203 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
204 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
205 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
206 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
207 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
208 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
209 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
210 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
211 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
212 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
213 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
214 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
215 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
216 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
217 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
218 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
219 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
220 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
221 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
222 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
223 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
224 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
226 * i386-tbl.h: Re-generate.
228 2019-07-01 Jan Beulich <jbeulich@suse.com>
230 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
232 * i386-tbl.h: Re-generate.
234 2019-07-01 Jan Beulich <jbeulich@suse.com>
236 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
237 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
238 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
239 * i386-tbl.h: Re-generate.
241 2019-07-01 Jan Beulich <jbeulich@suse.com>
243 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
244 Disp8MemShift from register only templates.
245 * i386-tbl.h: Re-generate.
247 2019-07-01 Jan Beulich <jbeulich@suse.com>
249 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
250 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
251 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
252 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
253 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
254 EVEX_W_0F11_P_3_M_1): Delete.
255 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
256 EVEX_W_0F11_P_3): New.
257 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
258 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
259 MOD_EVEX_0F11_PREFIX_3 table entries.
260 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
261 PREFIX_EVEX_0F11 table entries.
262 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
263 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
264 EVEX_W_0F11_P_3_M_{0,1} table entries.
266 2019-07-01 Jan Beulich <jbeulich@suse.com>
268 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
271 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
274 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
275 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
276 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
277 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
278 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
279 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
280 EVEX_LEN_0F38C7_R_6_P_2_W_1.
281 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
282 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
283 PREFIX_EVEX_0F38C6_REG_6 entries.
284 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
285 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
286 EVEX_W_0F38C7_R_6_P_2 entries.
287 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
288 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
289 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
290 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
291 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
292 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
293 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
295 2019-06-27 Jan Beulich <jbeulich@suse.com>
297 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
298 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
299 VEX_LEN_0F2D_P_3): Delete.
300 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
301 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
302 (prefix_table): ... here.
304 2019-06-27 Jan Beulich <jbeulich@suse.com>
306 * i386-dis.c (Iq): Delete.
308 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
310 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
311 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
312 (OP_E_memory): Also honor needindex when deciding whether an
313 address size prefix needs printing.
314 (OP_I): Remove handling of q_mode. Add handling of d_mode.
316 2019-06-26 Jim Wilson <jimw@sifive.com>
319 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
320 Set info->display_endian to info->endian_code.
322 2019-06-25 Jan Beulich <jbeulich@suse.com>
324 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
325 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
326 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
327 OPERAND_TYPE_ACC64 entries.
328 * i386-init.h: Re-generate.
330 2019-06-25 Jan Beulich <jbeulich@suse.com>
332 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
334 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
336 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
338 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
339 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
341 2019-06-25 Jan Beulich <jbeulich@suse.com>
343 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
346 2019-06-25 Jan Beulich <jbeulich@suse.com>
348 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
349 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
351 * i386-opc.tbl (movnti): Add IgnoreSize.
352 * i386-tbl.h: Re-generate.
354 2019-06-25 Jan Beulich <jbeulich@suse.com>
356 * i386-opc.tbl (and): Mark Imm8S form for optimization.
357 * i386-tbl.h: Re-generate.
359 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
361 * i386-dis-evex.h: Break into ...
362 * i386-dis-evex-len.h: New file.
363 * i386-dis-evex-mod.h: Likewise.
364 * i386-dis-evex-prefix.h: Likewise.
365 * i386-dis-evex-reg.h: Likewise.
366 * i386-dis-evex-w.h: Likewise.
367 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
368 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
371 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
374 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
375 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
377 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
378 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
379 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
380 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
381 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
382 EVEX_LEN_0F385B_P_2_W_1.
383 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
384 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
385 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
386 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
387 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
388 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
389 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
390 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
391 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
392 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
394 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
397 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
398 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
399 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
400 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
401 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
402 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
403 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
404 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
405 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
406 EVEX_LEN_0F3A43_P_2_W_1.
407 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
408 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
409 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
410 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
411 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
412 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
413 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
414 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
415 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
416 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
417 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
418 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
420 2019-06-14 Nick Clifton <nickc@redhat.com>
422 * po/fr.po; Updated French translation.
424 2019-06-13 Stafford Horne <shorne@gmail.com>
426 * or1k-asm.c: Regenerated.
427 * or1k-desc.c: Regenerated.
428 * or1k-desc.h: Regenerated.
429 * or1k-dis.c: Regenerated.
430 * or1k-ibld.c: Regenerated.
431 * or1k-opc.c: Regenerated.
432 * or1k-opc.h: Regenerated.
433 * or1k-opinst.c: Regenerated.
435 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
437 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
439 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
442 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
443 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
444 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
445 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
446 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
447 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
448 EVEX_LEN_0F3A1B_P_2_W_1.
449 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
450 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
451 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
452 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
453 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
454 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
455 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
456 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
458 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
461 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
462 EVEX.vvvv when disassembling VEX and EVEX instructions.
463 (OP_VEX): Set vex.register_specifier to 0 after readding
464 vex.register_specifier.
465 (OP_Vex_2src_1): Likewise.
466 (OP_Vex_2src_2): Likewise.
467 (OP_LWP_E): Likewise.
468 (OP_EX_Vex): Don't check vex.register_specifier.
469 (OP_XMM_Vex): Likewise.
471 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
472 Lili Cui <lili.cui@intel.com>
474 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
475 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
477 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
478 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
479 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
480 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
481 (i386_cpu_flags): Add cpuavx512_vp2intersect.
482 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
483 * i386-init.h: Regenerated.
484 * i386-tbl.h: Likewise.
486 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
487 Lili Cui <lili.cui@intel.com>
489 * doc/c-i386.texi: Document enqcmd.
490 * testsuite/gas/i386/enqcmd-intel.d: New file.
491 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
492 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
493 * testsuite/gas/i386/enqcmd.d: Likewise.
494 * testsuite/gas/i386/enqcmd.s: Likewise.
495 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
496 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
497 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
498 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
499 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
500 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
501 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
504 2019-06-04 Alan Hayward <alan.hayward@arm.com>
506 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
508 2019-06-03 Alan Modra <amodra@gmail.com>
510 * ppc-dis.c (prefix_opcd_indices): Correct size.
512 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
515 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
517 * i386-tbl.h: Regenerated.
519 2019-05-24 Alan Modra <amodra@gmail.com>
521 * po/POTFILES.in: Regenerate.
523 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
524 Alan Modra <amodra@gmail.com>
526 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
527 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
528 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
529 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
530 XTOP>): Define and add entries.
531 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
532 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
533 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
534 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
536 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
537 Alan Modra <amodra@gmail.com>
539 * ppc-dis.c (ppc_opts): Add "future" entry.
540 (PREFIX_OPCD_SEGS): Define.
541 (prefix_opcd_indices): New array.
542 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
543 (lookup_prefix): New function.
544 (print_insn_powerpc): Handle 64-bit prefix instructions.
545 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
546 (PMRR, POWERXX): Define.
547 (prefix_opcodes): New instruction table.
548 (prefix_num_opcodes): New constant.
550 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
552 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
553 * configure: Regenerated.
554 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
556 (HFILES): Add bpf-desc.h and bpf-opc.h.
557 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
558 bpf-ibld.c and bpf-opc.c.
560 * Makefile.in: Regenerated.
561 * disassemble.c (ARCH_bpf): Define.
562 (disassembler): Add case for bfd_arch_bpf.
563 (disassemble_init_for_target): Likewise.
564 (enum epbf_isa_attr): Define.
565 * disassemble.h: extern print_insn_bpf.
566 * bpf-asm.c: Generated.
567 * bpf-opc.h: Likewise.
568 * bpf-opc.c: Likewise.
569 * bpf-ibld.c: Likewise.
570 * bpf-dis.c: Likewise.
571 * bpf-desc.h: Likewise.
572 * bpf-desc.c: Likewise.
574 2019-05-21 Sudakshina Das <sudi.das@arm.com>
576 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
577 and VMSR with the new operands.
579 2019-05-21 Sudakshina Das <sudi.das@arm.com>
581 * arm-dis.c (enum mve_instructions): New enum
582 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
584 (mve_opcodes): New instructions as above.
585 (is_mve_encoding_conflict): Add cases for csinc, csinv,
587 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
589 2019-05-21 Sudakshina Das <sudi.das@arm.com>
591 * arm-dis.c (emun mve_instructions): Updated for new instructions.
592 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
593 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
594 uqshl, urshrl and urshr.
595 (is_mve_okay_in_it): Add new instructions to TRUE list.
596 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
597 (print_insn_mve): Updated to accept new %j,
598 %<bitfield>m and %<bitfield>n patterns.
600 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
602 * mips-opc.c (mips_builtin_opcodes): Change source register
605 2019-05-20 Nick Clifton <nickc@redhat.com>
607 * po/fr.po: Updated French translation.
609 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
610 Michael Collison <michael.collison@arm.com>
612 * arm-dis.c (thumb32_opcodes): Add new instructions.
613 (enum mve_instructions): Likewise.
614 (enum mve_undefined): Add new reasons.
615 (is_mve_encoding_conflict): Handle new instructions.
616 (is_mve_undefined): Likewise.
617 (is_mve_unpredictable): Likewise.
618 (print_mve_undefined): Likewise.
619 (print_mve_size): Likewise.
621 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
622 Michael Collison <michael.collison@arm.com>
624 * arm-dis.c (thumb32_opcodes): Add new instructions.
625 (enum mve_instructions): Likewise.
626 (is_mve_encoding_conflict): Handle new instructions.
627 (is_mve_undefined): Likewise.
628 (is_mve_unpredictable): Likewise.
629 (print_mve_size): Likewise.
631 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
632 Michael Collison <michael.collison@arm.com>
634 * arm-dis.c (thumb32_opcodes): Add new instructions.
635 (enum mve_instructions): Likewise.
636 (is_mve_encoding_conflict): Likewise.
637 (is_mve_unpredictable): Likewise.
638 (print_mve_size): Likewise.
640 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
641 Michael Collison <michael.collison@arm.com>
643 * arm-dis.c (thumb32_opcodes): Add new instructions.
644 (enum mve_instructions): Likewise.
645 (is_mve_encoding_conflict): Handle new instructions.
646 (is_mve_undefined): Likewise.
647 (is_mve_unpredictable): Likewise.
648 (print_mve_size): Likewise.
650 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
651 Michael Collison <michael.collison@arm.com>
653 * arm-dis.c (thumb32_opcodes): Add new instructions.
654 (enum mve_instructions): Likewise.
655 (is_mve_encoding_conflict): Handle new instructions.
656 (is_mve_undefined): Likewise.
657 (is_mve_unpredictable): Likewise.
658 (print_mve_size): Likewise.
659 (print_insn_mve): Likewise.
661 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
662 Michael Collison <michael.collison@arm.com>
664 * arm-dis.c (thumb32_opcodes): Add new instructions.
665 (print_insn_thumb32): Handle new instructions.
667 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
668 Michael Collison <michael.collison@arm.com>
670 * arm-dis.c (enum mve_instructions): Add new instructions.
671 (enum mve_undefined): Add new reasons.
672 (is_mve_encoding_conflict): Handle new instructions.
673 (is_mve_undefined): Likewise.
674 (is_mve_unpredictable): Likewise.
675 (print_mve_undefined): Likewise.
676 (print_mve_size): Likewise.
677 (print_mve_shift_n): Likewise.
678 (print_insn_mve): Likewise.
680 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
681 Michael Collison <michael.collison@arm.com>
683 * arm-dis.c (enum mve_instructions): Add new instructions.
684 (is_mve_encoding_conflict): Handle new instructions.
685 (is_mve_unpredictable): Likewise.
686 (print_mve_rotate): Likewise.
687 (print_mve_size): Likewise.
688 (print_insn_mve): Likewise.
690 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
691 Michael Collison <michael.collison@arm.com>
693 * arm-dis.c (enum mve_instructions): Add new instructions.
694 (is_mve_encoding_conflict): Handle new instructions.
695 (is_mve_unpredictable): Likewise.
696 (print_mve_size): Likewise.
697 (print_insn_mve): Likewise.
699 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
700 Michael Collison <michael.collison@arm.com>
702 * arm-dis.c (enum mve_instructions): Add new instructions.
703 (enum mve_undefined): Add new reasons.
704 (is_mve_encoding_conflict): Handle new instructions.
705 (is_mve_undefined): Likewise.
706 (is_mve_unpredictable): Likewise.
707 (print_mve_undefined): Likewise.
708 (print_mve_size): Likewise.
709 (print_insn_mve): Likewise.
711 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
712 Michael Collison <michael.collison@arm.com>
714 * arm-dis.c (enum mve_instructions): Add new instructions.
715 (is_mve_encoding_conflict): Handle new instructions.
716 (is_mve_undefined): Likewise.
717 (is_mve_unpredictable): Likewise.
718 (print_mve_size): Likewise.
719 (print_insn_mve): Likewise.
721 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
722 Michael Collison <michael.collison@arm.com>
724 * arm-dis.c (enum mve_instructions): Add new instructions.
725 (enum mve_unpredictable): Add new reasons.
726 (enum mve_undefined): Likewise.
727 (is_mve_okay_in_it): Handle new isntructions.
728 (is_mve_encoding_conflict): Likewise.
729 (is_mve_undefined): Likewise.
730 (is_mve_unpredictable): Likewise.
731 (print_mve_vmov_index): Likewise.
732 (print_simd_imm8): Likewise.
733 (print_mve_undefined): Likewise.
734 (print_mve_unpredictable): Likewise.
735 (print_mve_size): Likewise.
736 (print_insn_mve): Likewise.
738 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
739 Michael Collison <michael.collison@arm.com>
741 * arm-dis.c (enum mve_instructions): Add new instructions.
742 (enum mve_unpredictable): Add new reasons.
743 (enum mve_undefined): Likewise.
744 (is_mve_encoding_conflict): Handle new instructions.
745 (is_mve_undefined): Likewise.
746 (is_mve_unpredictable): Likewise.
747 (print_mve_undefined): Likewise.
748 (print_mve_unpredictable): Likewise.
749 (print_mve_rounding_mode): Likewise.
750 (print_mve_vcvt_size): Likewise.
751 (print_mve_size): Likewise.
752 (print_insn_mve): Likewise.
754 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
755 Michael Collison <michael.collison@arm.com>
757 * arm-dis.c (enum mve_instructions): Add new instructions.
758 (enum mve_unpredictable): Add new reasons.
759 (enum mve_undefined): Likewise.
760 (is_mve_undefined): Handle new instructions.
761 (is_mve_unpredictable): Likewise.
762 (print_mve_undefined): Likewise.
763 (print_mve_unpredictable): Likewise.
764 (print_mve_size): Likewise.
765 (print_insn_mve): Likewise.
767 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
768 Michael Collison <michael.collison@arm.com>
770 * arm-dis.c (enum mve_instructions): Add new instructions.
771 (enum mve_undefined): Add new reasons.
772 (insns): Add new instructions.
773 (is_mve_encoding_conflict):
774 (print_mve_vld_str_addr): New print function.
775 (is_mve_undefined): Handle new instructions.
776 (is_mve_unpredictable): Likewise.
777 (print_mve_undefined): Likewise.
778 (print_mve_size): Likewise.
779 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
780 (print_insn_mve): Handle new operands.
782 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
783 Michael Collison <michael.collison@arm.com>
785 * arm-dis.c (enum mve_instructions): Add new instructions.
786 (enum mve_unpredictable): Add new reasons.
787 (is_mve_encoding_conflict): Handle new instructions.
788 (is_mve_unpredictable): Likewise.
789 (mve_opcodes): Add new instructions.
790 (print_mve_unpredictable): Handle new reasons.
791 (print_mve_register_blocks): New print function.
792 (print_mve_size): Handle new instructions.
793 (print_insn_mve): Likewise.
795 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
796 Michael Collison <michael.collison@arm.com>
798 * arm-dis.c (enum mve_instructions): Add new instructions.
799 (enum mve_unpredictable): Add new reasons.
800 (enum mve_undefined): Likewise.
801 (is_mve_encoding_conflict): Handle new instructions.
802 (is_mve_undefined): Likewise.
803 (is_mve_unpredictable): Likewise.
804 (coprocessor_opcodes): Move NEON VDUP from here...
805 (neon_opcodes): ... to here.
806 (mve_opcodes): Add new instructions.
807 (print_mve_undefined): Handle new reasons.
808 (print_mve_unpredictable): Likewise.
809 (print_mve_size): Handle new instructions.
810 (print_insn_neon): Handle vdup.
811 (print_insn_mve): Handle new operands.
813 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
814 Michael Collison <michael.collison@arm.com>
816 * arm-dis.c (enum mve_instructions): Add new instructions.
817 (enum mve_unpredictable): Add new values.
818 (mve_opcodes): Add new instructions.
819 (vec_condnames): New array with vector conditions.
820 (mve_predicatenames): New array with predicate suffixes.
821 (mve_vec_sizename): New array with vector sizes.
822 (enum vpt_pred_state): New enum with vector predication states.
823 (struct vpt_block): New struct type for vpt blocks.
824 (vpt_block_state): Global struct to keep track of state.
825 (mve_extract_pred_mask): New helper function.
826 (num_instructions_vpt_block): Likewise.
827 (mark_outside_vpt_block): Likewise.
828 (mark_inside_vpt_block): Likewise.
829 (invert_next_predicate_state): Likewise.
830 (update_next_predicate_state): Likewise.
831 (update_vpt_block_state): Likewise.
832 (is_vpt_instruction): Likewise.
833 (is_mve_encoding_conflict): Add entries for new instructions.
834 (is_mve_unpredictable): Likewise.
835 (print_mve_unpredictable): Handle new cases.
836 (print_instruction_predicate): Likewise.
837 (print_mve_size): New function.
838 (print_vec_condition): New function.
839 (print_insn_mve): Handle vpt blocks and new print operands.
841 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
843 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
844 8, 14 and 15 for Armv8.1-M Mainline.
846 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
847 Michael Collison <michael.collison@arm.com>
849 * arm-dis.c (enum mve_instructions): New enum.
850 (enum mve_unpredictable): Likewise.
851 (enum mve_undefined): Likewise.
852 (struct mopcode32): New struct.
853 (is_mve_okay_in_it): New function.
854 (is_mve_architecture): Likewise.
855 (arm_decode_field): Likewise.
856 (arm_decode_field_multiple): Likewise.
857 (is_mve_encoding_conflict): Likewise.
858 (is_mve_undefined): Likewise.
859 (is_mve_unpredictable): Likewise.
860 (print_mve_undefined): Likewise.
861 (print_mve_unpredictable): Likewise.
862 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
863 (print_insn_mve): New function.
864 (print_insn_thumb32): Handle MVE architecture.
865 (select_arm_features): Force thumb for Armv8.1-m Mainline.
867 2019-05-10 Nick Clifton <nickc@redhat.com>
870 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
871 end of the table prematurely.
873 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
875 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
878 2019-05-11 Alan Modra <amodra@gmail.com>
880 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
881 when -Mraw is in effect.
883 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
885 * aarch64-dis-2.c: Regenerate.
886 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
887 (OP_SVE_BBB): New variant set.
888 (OP_SVE_DDDD): New variant set.
889 (OP_SVE_HHH): New variant set.
890 (OP_SVE_HHHU): New variant set.
891 (OP_SVE_SSS): New variant set.
892 (OP_SVE_SSSU): New variant set.
893 (OP_SVE_SHH): New variant set.
894 (OP_SVE_SBBU): New variant set.
895 (OP_SVE_DSS): New variant set.
896 (OP_SVE_DHHU): New variant set.
897 (OP_SVE_VMV_HSD_BHS): New variant set.
898 (OP_SVE_VVU_HSD_BHS): New variant set.
899 (OP_SVE_VVVU_SD_BH): New variant set.
900 (OP_SVE_VVVU_BHSD): New variant set.
901 (OP_SVE_VVV_QHD_DBS): New variant set.
902 (OP_SVE_VVV_HSD_BHS): New variant set.
903 (OP_SVE_VVV_HSD_BHS2): New variant set.
904 (OP_SVE_VVV_BHS_HSD): New variant set.
905 (OP_SVE_VV_BHS_HSD): New variant set.
906 (OP_SVE_VVV_SD): New variant set.
907 (OP_SVE_VVU_BHS_HSD): New variant set.
908 (OP_SVE_VZVV_SD): New variant set.
909 (OP_SVE_VZVV_BH): New variant set.
910 (OP_SVE_VZV_SD): New variant set.
911 (aarch64_opcode_table): Add sve2 instructions.
913 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
915 * aarch64-asm-2.c: Regenerated.
916 * aarch64-dis-2.c: Regenerated.
917 * aarch64-opc-2.c: Regenerated.
918 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
919 for SVE_SHLIMM_UNPRED_22.
920 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
921 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
924 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
926 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
927 sve_size_tsz_bhs iclass encode.
928 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
929 sve_size_tsz_bhs iclass decode.
931 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
933 * aarch64-asm-2.c: Regenerated.
934 * aarch64-dis-2.c: Regenerated.
935 * aarch64-opc-2.c: Regenerated.
936 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
937 for SVE_Zm4_11_INDEX.
938 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
939 (fields): Handle SVE_i2h field.
940 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
941 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
943 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
945 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
946 sve_shift_tsz_bhsd iclass encode.
947 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
948 sve_shift_tsz_bhsd iclass decode.
950 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
952 * aarch64-asm-2.c: Regenerated.
953 * aarch64-dis-2.c: Regenerated.
954 * aarch64-opc-2.c: Regenerated.
955 * aarch64-asm.c (aarch64_ins_sve_shrimm):
956 (aarch64_encode_variant_using_iclass): Handle
957 sve_shift_tsz_hsd iclass encode.
958 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
959 sve_shift_tsz_hsd iclass decode.
960 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
961 for SVE_SHRIMM_UNPRED_22.
962 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
963 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
966 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
968 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
969 sve_size_013 iclass encode.
970 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
971 sve_size_013 iclass decode.
973 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
975 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
976 sve_size_bh iclass encode.
977 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
978 sve_size_bh iclass decode.
980 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
982 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
983 sve_size_sd2 iclass encode.
984 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
985 sve_size_sd2 iclass decode.
986 * aarch64-opc.c (fields): Handle SVE_sz2 field.
987 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
989 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
991 * aarch64-asm-2.c: Regenerated.
992 * aarch64-dis-2.c: Regenerated.
993 * aarch64-opc-2.c: Regenerated.
994 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
996 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
997 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
999 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1001 * aarch64-asm-2.c: Regenerated.
1002 * aarch64-dis-2.c: Regenerated.
1003 * aarch64-opc-2.c: Regenerated.
1004 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1005 for SVE_Zm3_11_INDEX.
1006 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1007 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1008 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1010 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1012 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1014 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1015 sve_size_hsd2 iclass encode.
1016 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1017 sve_size_hsd2 iclass decode.
1018 * aarch64-opc.c (fields): Handle SVE_size field.
1019 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1021 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1023 * aarch64-asm-2.c: Regenerated.
1024 * aarch64-dis-2.c: Regenerated.
1025 * aarch64-opc-2.c: Regenerated.
1026 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1028 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1029 (fields): Handle SVE_rot3 field.
1030 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1031 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1033 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1035 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1038 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1041 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1042 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1043 aarch64_feature_sve2bitperm): New feature sets.
1044 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1045 for feature set addresses.
1046 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1047 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1049 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1050 Faraz Shahbazker <fshahbazker@wavecomp.com>
1052 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1053 argument and set ASE_EVA_R6 appropriately.
1054 (set_default_mips_dis_options): Pass ISA to above.
1055 (parse_mips_dis_option): Likewise.
1056 * mips-opc.c (EVAR6): New macro.
1057 (mips_builtin_opcodes): Add llwpe, scwpe.
1059 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1061 * aarch64-asm-2.c: Regenerated.
1062 * aarch64-dis-2.c: Regenerated.
1063 * aarch64-opc-2.c: Regenerated.
1064 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1065 AARCH64_OPND_TME_UIMM16.
1066 (aarch64_print_operand): Likewise.
1067 * aarch64-tbl.h (QL_IMM_NIL): New.
1070 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1072 2019-04-29 John Darrington <john@darrington.wattle.id.au>
1074 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1076 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1077 Faraz Shahbazker <fshahbazker@wavecomp.com>
1079 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1081 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1083 * s12z-opc.h: Add extern "C" bracketing to help
1084 users who wish to use this interface in c++ code.
1086 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1088 * s12z-opc.c (bm_decode): Handle bit map operations with the
1091 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1093 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1094 specifier. Add entries for VLDR and VSTR of system registers.
1095 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1096 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1097 of %J and %K format specifier.
1099 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1101 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1102 Add new entries for VSCCLRM instruction.
1103 (print_insn_coprocessor): Handle new %C format control code.
1105 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1107 * arm-dis.c (enum isa): New enum.
1108 (struct sopcode32): New structure.
1109 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1110 set isa field of all current entries to ANY.
1111 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1112 Only match an entry if its isa field allows the current mode.
1114 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1116 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1118 (print_insn_thumb32): Add logic to print %n CLRM register list.
1120 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1122 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1125 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1127 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1128 (print_insn_thumb32): Edit the switch case for %Z.
1130 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1132 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1134 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1136 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1138 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1140 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1142 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1144 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1145 Arm register with r13 and r15 unpredictable.
1146 (thumb32_opcodes): New instructions for bfx and bflx.
1148 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1150 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1152 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1154 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1156 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1158 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1160 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1162 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1164 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1166 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1167 "optr". ("operator" is a reserved word in c++).
1169 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1171 * aarch64-opc.c (aarch64_print_operand): Add case for
1173 (verify_constraints): Likewise.
1174 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1175 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1176 to accept Rt|SP as first operand.
1177 (AARCH64_OPERANDS): Add new Rt_SP.
1178 * aarch64-asm-2.c: Regenerated.
1179 * aarch64-dis-2.c: Regenerated.
1180 * aarch64-opc-2.c: Regenerated.
1182 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1184 * aarch64-asm-2.c: Regenerated.
1185 * aarch64-dis-2.c: Likewise.
1186 * aarch64-opc-2.c: Likewise.
1187 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1189 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1191 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1193 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1195 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1196 * i386-init.h: Regenerated.
1198 2019-04-07 Alan Modra <amodra@gmail.com>
1200 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1201 op_separator to control printing of spaces, comma and parens
1202 rather than need_comma, need_paren and spaces vars.
1204 2019-04-07 Alan Modra <amodra@gmail.com>
1207 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1208 (print_insn_neon, print_insn_arm): Likewise.
1210 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1212 * i386-dis-evex.h (evex_table): Updated to support BF16
1214 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1215 and EVEX_W_0F3872_P_3.
1216 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1217 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1218 * i386-opc.h (enum): Add CpuAVX512_BF16.
1219 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1220 * i386-opc.tbl: Add AVX512 BF16 instructions.
1221 * i386-init.h: Regenerated.
1222 * i386-tbl.h: Likewise.
1224 2019-04-05 Alan Modra <amodra@gmail.com>
1226 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1227 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1228 to favour printing of "-" branch hint when using the "y" bit.
1229 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1231 2019-04-05 Alan Modra <amodra@gmail.com>
1233 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1234 opcode until first operand is output.
1236 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1239 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1240 (valid_bo_post_v2): Add support for 'at' branch hints.
1241 (insert_bo): Only error on branch on ctr.
1242 (get_bo_hint_mask): New function.
1243 (insert_boe): Add new 'branch_taken' formal argument. Add support
1244 for inserting 'at' branch hints.
1245 (extract_boe): Add new 'branch_taken' formal argument. Add support
1246 for extracting 'at' branch hints.
1247 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1248 (BOE): Delete operand.
1249 (BOM, BOP): New operands.
1251 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1252 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1253 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1254 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1255 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1256 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1257 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1258 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1259 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1260 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1261 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1262 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1263 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1264 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1265 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1266 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1267 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1268 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1269 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1270 bttarl+>: New extended mnemonics.
1272 2019-03-28 Alan Modra <amodra@gmail.com>
1275 * ppc-opc.c (BTF): Define.
1276 (powerpc_opcodes): Use for mtfsb*.
1277 * ppc-dis.c (print_insn_powerpc): Print fields with both
1278 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1280 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1282 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1283 (mapping_symbol_for_insn): Implement new algorithm.
1284 (print_insn): Remove duplicate code.
1286 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1288 * aarch64-dis.c (print_insn_aarch64):
1291 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1293 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1296 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1298 * aarch64-dis.c (last_stop_offset): New.
1299 (print_insn_aarch64): Use stop_offset.
1301 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1304 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1306 * i386-init.h: Regenerated.
1308 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1311 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1312 vmovdqu16, vmovdqu32 and vmovdqu64.
1313 * i386-tbl.h: Regenerated.
1315 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1317 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1318 from vstrszb, vstrszh, and vstrszf.
1320 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1322 * s390-opc.txt: Add instruction descriptions.
1324 2019-02-08 Jim Wilson <jimw@sifive.com>
1326 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1329 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1331 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1333 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1336 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1337 * aarch64-opc.c (verify_elem_sd): New.
1338 (fields): Add FLD_sz entr.
1339 * aarch64-tbl.h (_SIMD_INSN): New.
1340 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1341 fmulx scalar and vector by element isns.
1343 2019-02-07 Nick Clifton <nickc@redhat.com>
1345 * po/sv.po: Updated Swedish translation.
1347 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1349 * s390-mkopc.c (main): Accept arch13 as cpu string.
1350 * s390-opc.c: Add new instruction formats and instruction opcode
1352 * s390-opc.txt: Add new arch13 instructions.
1354 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1356 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1357 (aarch64_opcode): Change encoding for stg, stzg
1359 * aarch64-asm-2.c: Regenerated.
1360 * aarch64-dis-2.c: Regenerated.
1361 * aarch64-opc-2.c: Regenerated.
1363 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1365 * aarch64-asm-2.c: Regenerated.
1366 * aarch64-dis-2.c: Likewise.
1367 * aarch64-opc-2.c: Likewise.
1368 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1370 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1371 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1373 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1374 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1375 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1376 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1377 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1378 case for ldstgv_indexed.
1379 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1380 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1381 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1382 * aarch64-asm-2.c: Regenerated.
1383 * aarch64-dis-2.c: Regenerated.
1384 * aarch64-opc-2.c: Regenerated.
1386 2019-01-23 Nick Clifton <nickc@redhat.com>
1388 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1390 2019-01-21 Nick Clifton <nickc@redhat.com>
1392 * po/de.po: Updated German translation.
1393 * po/uk.po: Updated Ukranian translation.
1395 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1396 * mips-dis.c (mips_arch_choices): Fix typo in
1397 gs464, gs464e and gs264e descriptors.
1399 2019-01-19 Nick Clifton <nickc@redhat.com>
1401 * configure: Regenerate.
1402 * po/opcodes.pot: Regenerate.
1404 2018-06-24 Nick Clifton <nickc@redhat.com>
1406 2.32 branch created.
1408 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1410 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1412 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1415 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1417 * configure: Regenerate.
1419 2019-01-07 Alan Modra <amodra@gmail.com>
1421 * configure: Regenerate.
1422 * po/POTFILES.in: Regenerate.
1424 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1426 * s12z-opc.c: New file.
1427 * s12z-opc.h: New file.
1428 * s12z-dis.c: Removed all code not directly related to display
1429 of instructions. Used the interface provided by the new files
1431 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1432 * Makefile.in: Regenerate.
1433 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1434 * configure: Regenerate.
1436 2019-01-01 Alan Modra <amodra@gmail.com>
1438 Update year range in copyright notice of all files.
1440 For older changes see ChangeLog-2018
1442 Copyright (C) 2019 Free Software Foundation, Inc.
1444 Copying and distribution of this file, with or without modification,
1445 are permitted in any medium without royalty provided the copyright
1446 notice and this notice are preserved.
1452 version-control: never