opcodes/ChangeLog

   1 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
   2
   3         * arc-dis.c (find_format, find_format, get_auxreg)
   4         (print_insn_arc): Changed.
   5         * arc-ext.h (INSERT_XOP): Likewise.
   6
   7 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
   8
   9         * tic54x-dis.c (sprint_mmr): Adjust.
  10         * tic54x-opc.c: Likewise.
  11
  12 2016-05-19  Alan Modra  <amodra@gmail.com>
  13
  14         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
  15
  16 2016-05-19  Alan Modra  <amodra@gmail.com>
  17
  18         * ppc-opc.c: Formatting.
  19         (NSISIGNOPT): Define.
  20         (powerpc_opcodes <subis>): Use NSISIGNOPT.
  21
  22 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
  23
  24         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
  25         replacing references to `micromips_ase' throughout.
  26         (_print_insn_mips): Don't use file-level microMIPS annotation to
  27         determine the disassembly mode with the symbol table.
  28
  29 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
  30
  31         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
  32
  33 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
  34
  35         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
  36         mips64r6.
  37         * mips-opc.c (D34): New macro.
  38         (mips_builtin_opcodes): Define bposge32c for DSPr3.
  39
  40 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
  41
  42         * i386-dis.c (prefix_table): Add RDPID instruction.
  43         * i386-gen.c (cpu_flag_init): Add RDPID flag.
  44         (cpu_flags): Add RDPID bitfield.
  45         * i386-opc.h (enum): Add RDPID element.
  46         (i386_cpu_flags): Add RDPID field.
  47         * i386-opc.tbl: Add RDPID instruction.
  48         * i386-init.h: Regenerate.
  49         * i386-tbl.h: Regenerate.
  50
  51 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  52
  53         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
  54         branch type of a symbol.
  55         (print_insn): Likewise.
  56
  57 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
  58
  59         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
  60         Mainline Security Extensions instructions.
  61         (thumb_opcodes): Add entries for narrow ARMv8-M Security
  62         Extensions instructions.
  63         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
  64         instructions.
  65         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
  66         special registers.
  67
  68 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
  69
  70         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
  71
  72 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
  73
  74         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
  75         (arcExtMap_genOpcode): Likewise.
  76         * arc-opc.c (arg_32bit_rc): Define new variable.
  77         (arg_32bit_u6): Likewise.
  78         (arg_32bit_limm): Likewise.
  79
  80 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  81
  82         * aarch64-gen.c (VERIFIER): Define.
  83         * aarch64-opc.c (VERIFIER): Define.
  84         (verify_ldpsw): Use static linkage.
  85         * aarch64-opc.h (verify_ldpsw): Remove.
  86         * aarch64-tbl.h: Use VERIFIER for verifiers.
  87
  88 2016-04-28  Nick Clifton  <nickc@redhat.com>
  89
  90         PR target/19722
  91         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
  92         * aarch64-opc.c (verify_ldpsw): New function.
  93         * aarch64-opc.h (verify_ldpsw): New prototype.
  94         * aarch64-tbl.h: Add initialiser for verifier field.
  95         (LDPSW): Set verifier to verify_ldpsw.
  96
  97 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
  98
  99         PR binutils/19983
 100         PR binutils/19984
 101         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
 102         smaller than address size.
 103
 104 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 105
 106         * alpha-dis.c: Regenerate.
 107         * crx-dis.c: Likewise.
 108         * disassemble.c: Likewise.
 109         * epiphany-opc.c: Likewise.
 110         * fr30-opc.c: Likewise.
 111         * frv-opc.c: Likewise.
 112         * ip2k-opc.c: Likewise.
 113         * iq2000-opc.c: Likewise.
 114         * lm32-opc.c: Likewise.
 115         * lm32-opinst.c: Likewise.
 116         * m32c-opc.c: Likewise.
 117         * m32r-opc.c: Likewise.
 118         * m32r-opinst.c: Likewise.
 119         * mep-opc.c: Likewise.
 120         * mt-opc.c: Likewise.
 121         * or1k-opc.c: Likewise.
 122         * or1k-opinst.c: Likewise.
 123         * tic80-opc.c: Likewise.
 124         * xc16x-opc.c: Likewise.
 125         * xstormy16-opc.c: Likewise.
 126
 127 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 128
 129         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
 130         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
 131         calcsd, and calcxd instructions.
 132         * arc-opc.c (insert_nps_bitop_size): Delete.
 133         (extract_nps_bitop_size): Delete.
 134         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
 135         (extract_nps_qcmp_m3): Define.
 136         (extract_nps_qcmp_m2): Define.
 137         (extract_nps_qcmp_m1): Define.
 138         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
 139         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
 140         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
 141         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
 142         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
 143         NPS_QCMP_M3.
 144
 145 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
 146
 147         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
 148
 149 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
 150
 151         * Makefile.in: Regenerated with automake 1.11.6.
 152         * aclocal.m4: Likewise.
 153
 154 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 155
 156         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
 157         instructions.
 158         * arc-opc.c (insert_nps_cmem_uimm16): New function.
 159         (extract_nps_cmem_uimm16): New function.
 160         (arc_operands): Add NPS_XLDST_UIMM16 operand.
 161
 162 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
 163
 164         * arc-dis.c (arc_insn_length): New function.
 165         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
 166         (find_format): Change insnLen parameter to unsigned.
 167
 168 2016-04-13  Nick Clifton  <nickc@redhat.com>
 169
 170         PR target/19937
 171         * v850-opc.c (v850_opcodes): Correct masks for long versions of
 172         the LD.B and LD.BU instructions.
 173
 174 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 175
 176         * arc-dis.c (find_format): Check for extension flags.
 177         (print_flags): New function.
 178         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
 179         .extAuxRegister.
 180         * arc-ext.c (arcExtMap_coreRegName): Use
 181         LAST_EXTENSION_CORE_REGISTER.
 182         (arcExtMap_coreReadWrite): Likewise.
 183         (dump_ARC_extmap): Update printing.
 184         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
 185         (arc_aux_regs): Add cpu field.
 186         * arc-regs.h: Add cpu field, lower case name aux registers.
 187
 188 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 189
 190         * arc-tbl.h: Add rtsc, sleep with no arguments.
 191
 192 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 193
 194         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
 195         Initialize.
 196         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
 197         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
 198         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
 199         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
 200         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
 201         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
 202         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
 203         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
 204         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
 205         (arc_opcode arc_opcodes): Null terminate the array.
 206         (arc_num_opcodes): Remove.
 207         * arc-ext.h (INSERT_XOP): Define.
 208         (extInstruction_t): Likewise.
 209         (arcExtMap_instName): Delete.
 210         (arcExtMap_insn): New function.
 211         (arcExtMap_genOpcode): Likewise.
 212         * arc-ext.c (ExtInstruction): Remove.
 213         (create_map): Zero initialize instruction fields.
 214         (arcExtMap_instName): Remove.
 215         (arcExtMap_insn): New function.
 216         (dump_ARC_extmap): More info while debuging.
 217         (arcExtMap_genOpcode): New function.
 218         * arc-dis.c (find_format): New function.
 219         (print_insn_arc): Use find_format.
 220         (arc_get_disassembler): Enable dump_ARC_extmap only when
 221         debugging.
 222
 223 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
 224
 225         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
 226         instruction bits out.
 227
 228 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 229
 230         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
 231         * arc-opc.c (arc_flag_operands): Add new flags.
 232         (arc_flag_classes): Add new classes.
 233
 234 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
 235
 236         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
 237
 238 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
 239
 240         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
 241         encode1, rflt, crc16, and crc32 instructions.
 242         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
 243         (arc_flag_classes): Add C_NPS_R.
 244         (insert_nps_bitop_size_2b): New function.
 245         (extract_nps_bitop_size_2b): Likewise.
 246         (insert_nps_bitop_uimm8): Likewise.
 247         (extract_nps_bitop_uimm8): Likewise.
 248         (arc_operands): Add new operand entries.
 249
 250 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
 251
 252         * arc-regs.h: Add a new subclass field.  Add double assist
 253         accumulator register values.
 254         * arc-tbl.h: Use DPA subclass to mark the double assist
 255         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
 256         * arc-opc.c (RSP): Define instead of SP.
 257         (arc_aux_regs): Add the subclass field.
 258
 259 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
 260
 261         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
 262
 263 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
 264
 265         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
 266         NPS_R_SRC1.
 267
 268 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
 269
 270         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
 271         issues.  No functional changes.
 272
 273 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
 274
 275         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
 276         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
 277         (RTT): Remove duplicate.
 278         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
 279         (PCT_CONFIG*): Remove.
 280         (D1L, D1H, D2H, D2L): Define.
 281
 282 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 283
 284         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
 285
 286 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
 287
 288         * arc-tbl.h (invld07): Remove.
 289         * arc-ext-tbl.h: New file.
 290         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
 291         * arc-opc.c (arc_opcodes): Add ext-tbl include.
 292
 293 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
 294
 295         Fix -Wstack-usage warnings.
 296         * aarch64-dis.c (print_operands): Substitute size.
 297         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
 298
 299 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
 300
 301         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
 302         to get a proper diagnostic when an invalid ASR register is used.
 303
 304 2016-03-22  Nick Clifton  <nickc@redhat.com>
 305
 306         * configure: Regenerate.
 307
 308 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 309
 310         * arc-nps400-tbl.h: New file.
 311         * arc-opc.c: Add top level comment.
 312         (insert_nps_3bit_dst): New function.
 313         (extract_nps_3bit_dst): New function.
 314         (insert_nps_3bit_src2): New function.
 315         (extract_nps_3bit_src2): New function.
 316         (insert_nps_bitop_size): New function.
 317         (extract_nps_bitop_size): New function.
 318         (arc_flag_operands): Add nps400 entries.
 319         (arc_flag_classes): Add nps400 entries.
 320         (arc_operands): Add nps400 entries.
 321         (arc_opcodes): Add nps400 include.
 322
 323 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 324
 325         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
 326         the new class enum values.
 327
 328 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 329
 330         * arc-dis.c (print_insn_arc): Handle nps400.
 331
 332 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
 333
 334         * arc-opc.c (BASE): Delete.
 335
 336 2016-03-18  Nick Clifton  <nickc@redhat.com>
 337
 338         PR target/19721
 339         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
 340         of MOV insn that aliases an ORR insn.
 341
 342 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
 343
 344         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
 345
 346 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
 347
 348         * mcore-opc.h: Add const qualifiers.
 349         * microblaze-opc.h (struct op_code_struct): Likewise.
 350         * sh-opc.h: Likewise.
 351         * tic4x-dis.c (tic4x_print_indirect): Likewise.
 352         (tic4x_print_op): Likewise.
 353
 354 2016-03-02  Alan Modra  <amodra@gmail.com>
 355
 356         * or1k-desc.h: Regenerate.
 357         * fr30-ibld.c: Regenerate.
 358         * rl78-decode.c: Regenerate.
 359
 360 2016-03-01  Nick Clifton  <nickc@redhat.com>
 361
 362         PR target/19747
 363         * rl78-dis.c (print_insn_rl78_common): Fix typo.
 364
 365 2016-02-24  Renlin Li  <renlin.li@arm.com>
 366
 367         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
 368         (print_insn_coprocessor): Support fp16 instructions.
 369
 370 2016-02-24  Renlin Li  <renlin.li@arm.com>
 371
 372         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
 373         vminnm, vrint(mpna).
 374
 375 2016-02-24  Renlin Li  <renlin.li@arm.com>
 376
 377         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
 378         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
 379
 380 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
 381
 382         * i386-dis.c (print_insn): Parenthesize expression to prevent
 383         truncated addresses.
 384         (OP_J): Likewise.
 385
 386 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
 387             Janek van Oirschot  <jvanoirs@synopsys.com>
 388
 389         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
 390         variable.
 391
 392 2016-02-04  Nick Clifton  <nickc@redhat.com>
 393
 394         PR target/19561
 395         * msp430-dis.c (print_insn_msp430): Add a special case for
 396         decoding an RRC instruction with the ZC bit set in the extension
 397         word.
 398
 399 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 400
 401         * cgen-ibld.in (insert_normal): Rework calculation of shift.
 402         * epiphany-ibld.c: Regenerate.
 403         * fr30-ibld.c: Regenerate.
 404         * frv-ibld.c: Regenerate.
 405         * ip2k-ibld.c: Regenerate.
 406         * iq2000-ibld.c: Regenerate.
 407         * lm32-ibld.c: Regenerate.
 408         * m32c-ibld.c: Regenerate.
 409         * m32r-ibld.c: Regenerate.
 410         * mep-ibld.c: Regenerate.
 411         * mt-ibld.c: Regenerate.
 412         * or1k-ibld.c: Regenerate.
 413         * xc16x-ibld.c: Regenerate.
 414         * xstormy16-ibld.c: Regenerate.
 415
 416 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
 417
 418         * epiphany-dis.c: Regenerated from latest cpu files.
 419
 420 2016-02-01  Michael McConville  <mmcco@mykolab.com>
 421
 422         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
 423         test bit.
 424
 425 2016-01-25  Renlin Li  <renlin.li@arm.com>
 426
 427         * arm-dis.c (mapping_symbol_for_insn): New function.
 428         (find_ifthen_state): Call mapping_symbol_for_insn().
 429
 430 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
 431
 432         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
 433         of MSR UAO immediate operand.
 434
 435 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
 436
 437         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
 438         instruction support.
 439
 440 2016-01-17  Alan Modra  <amodra@gmail.com>
 441
 442         * configure: Regenerate.
 443
 444 2016-01-14  Nick Clifton  <nickc@redhat.com>
 445
 446         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
 447         instructions that can support stack pointer operations.
 448         * rl78-decode.c: Regenerate.
 449         * rl78-dis.c: Fix display of stack pointer in MOVW based
 450         instructions.
 451
 452 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
 453
 454         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
 455         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
 456         erxtatus_el1 and erxaddr_el1.
 457
 458 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
 459
 460         * arm-dis.c (arm_opcodes): Add "esb".
 461         (thumb_opcodes): Likewise.
 462
 463 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
 464
 465         * ppc-opc.c <xscmpnedp>: Delete.
 466         <xvcmpnedp>: Likewise.
 467         <xvcmpnedp.>: Likewise.
 468         <xvcmpnesp>: Likewise.
 469         <xvcmpnesp.>: Likewise.
 470
 471 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
 472
 473         PR gas/13050
 474         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
 475         addition to ISA_A.
 476
 477 2016-01-01  Alan Modra  <amodra@gmail.com>
 478
 479         Update year range in copyright notice of all files.
 480
 481 For older changes see ChangeLog-2015
 482 \f
 483 Copyright (C) 2016 Free Software Foundation, Inc.
 484
 485 Copying and distribution of this file, with or without modification,
 486 are permitted in any medium without royalty provided the copyright
 487 notice and this notice are preserved.
 488
 489 Local Variables:
 490 mode: change-log
 491 left-margin: 8
 492 fill-column: 74
 493 version-control: never
 494 End: