opcodes/ChangeLog

   1 2017-03-30  Pip Cet  <pipcet@gmail.com>
   2
   3         * configure.ac: Add (empty) bfd_wasm32_arch target.
   4         * configure: Regenerate
   5         * po/opcodes.pot: Regenerate.
   6
   7 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
   8
   9         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
  10         OSA2015.
  11         * opcodes/sparc-opc.c (asi_table): New ASIs.
  12
  13 2017-03-29  Alan Modra  <amodra@gmail.com>
  14
  15         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
  16         "raw" option.
  17         (lookup_powerpc): Don't special case -1 dialect.  Handle
  18         PPC_OPCODE_RAW.
  19         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
  20         lookup_powerpc call, pass it on second.
  21
  22 2017-03-27  Alan Modra  <amodra@gmail.com>
  23
  24         PR 21303
  25         * ppc-dis.c (struct ppc_mopt): Comment.
  26         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
  27
  28 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
  29
  30         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
  31         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
  32         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
  33         (insert_nps_misc_imm_offset): New function.
  34         (extract_nps_misc imm_offset): New function.
  35         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
  36         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
  37
  38 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
  39
  40         * s390-mkopc.c (main): Remove vx2 check.
  41         * s390-opc.txt: Remove vx2 instruction flags.
  42
  43 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
  44
  45         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
  46         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
  47         (insert_nps_imm_offset): New function.
  48         (extract_nps_imm_offset): New function.
  49         (insert_nps_imm_entry): New function.
  50         (extract_nps_imm_entry): New function.
  51
  52 2017-03-17  Alan Modra  <amodra@gmail.com>
  53
  54         PR 21248
  55         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
  56         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
  57         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
  58
  59 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
  60
  61         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
  62         <c.andi>: Likewise.
  63         <c.addiw> Likewise.
  64
  65 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
  66
  67         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
  68
  69 2017-03-13  Andrew Waterman  <andrew@sifive.com>
  70
  71         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
  72         <srl> Likewise.
  73         <srai> Likewise.
  74         <sra> Likewise.
  75
  76 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
  77
  78         * i386-gen.c (opcode_modifiers): Replace S with Load.
  79         * i386-opc.h (S): Removed.
  80         (Load): New.
  81         (i386_opcode_modifier): Replace s with load.
  82         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
  83         and {evex}.  Replace S with Load.
  84         * i386-tbl.h: Regenerated.
  85
  86 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
  87
  88         * i386-opc.tbl: Use CpuCET on rdsspq.
  89         * i386-tbl.h: Regenerated.
  90
  91 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
  92
  93         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
  94         <vsx>: Do not use PPC_OPCODE_VSX3;
  95
  96 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
  97
  98         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
  99
 100 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 101
 102         * i386-dis.c (REG_0F1E_MOD_3): New enum.
 103         (MOD_0F1E_PREFIX_1): Likewise.
 104         (MOD_0F38F5_PREFIX_2): Likewise.
 105         (MOD_0F38F6_PREFIX_0): Likewise.
 106         (RM_0F1E_MOD_3_REG_7): Likewise.
 107         (PREFIX_MOD_0_0F01_REG_5): Likewise.
 108         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 109         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
 110         (PREFIX_0F1E): Likewise.
 111         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
 112         (PREFIX_0F38F5): Likewise.
 113         (dis386_twobyte): Use PREFIX_0F1E.
 114         (reg_table): Add REG_0F1E_MOD_3.
 115         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
 116         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
 117         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
 118         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
 119         (three_byte_table): Use PREFIX_0F38F5.
 120         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
 121         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
 122         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
 123         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
 124         PREFIX_MOD_3_0F01_REG_5_RM_2.
 125         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
 126         (cpu_flags): Add CpuCET.
 127         * i386-opc.h (CpuCET): New enum.
 128         (CpuUnused): Commented out.
 129         (i386_cpu_flags): Add cpucet.
 130         * i386-opc.tbl: Add Intel CET instructions.
 131         * i386-init.h: Regenerated.
 132         * i386-tbl.h: Likewise.
 133
 134 2017-03-06  Alan Modra  <amodra@gmail.com>
 135
 136         PR 21124
 137         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
 138         (extract_raq, extract_ras, extract_rbx): New functions.
 139         (powerpc_operands): Use opposite corresponding insert function.
 140         (Q_MASK): Define.
 141         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
 142         register restriction.
 143
 144 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
 145
 146         * disassemble.c Include "safe-ctype.h".
 147         (disassemble_init_for_target): Handle s390 init.
 148         (remove_whitespace_and_extra_commas): New function.
 149         (disassembler_options_cmp): Likewise.
 150         * arm-dis.c: Include "libiberty.h".
 151         (NUM_ELEM): Delete.
 152         (regnames): Use long disassembler style names.
 153         Add force-thumb and no-force-thumb options.
 154         (NUM_ARM_REGNAMES): Rename from this...
 155         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
 156         (get_arm_regname_num_options): Delete.
 157         (set_arm_regname_option): Likewise.
 158         (get_arm_regnames): Likewise.
 159         (parse_disassembler_options): Likewise.
 160         (parse_arm_disassembler_option): Rename from this...
 161         (parse_arm_disassembler_options): ...to this.  Make static.
 162         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 163         (print_insn): Use parse_arm_disassembler_options.
 164         (disassembler_options_arm): New function.
 165         (print_arm_disassembler_options): Handle updated regnames.
 166         * ppc-dis.c: Include "libiberty.h".
 167         (ppc_opts): Add "32" and "64" entries.
 168         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 169         (powerpc_init_dialect): Add break to switch statement.
 170         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 171         (disassembler_options_powerpc): New function.
 172         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 173         Remove printing of "32" and "64".
 174         * s390-dis.c: Include "libiberty.h".
 175         (init_flag): Remove unneeded variable.
 176         (struct s390_options_t): New structure type.
 177         (options): New structure.
 178         (init_disasm): Rename from this...
 179         (disassemble_init_s390): ...to this.  Add initializations for
 180         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 181         (print_insn_s390): Delete call to init_disasm.
 182         (disassembler_options_s390): New function.
 183         (print_s390_disassembler_options): Print using information from
 184         struct 'options'.
 185         * po/opcodes.pot: Regenerate.
 186
 187 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 188
 189         * i386-dis.c (PCMPESTR_Fixup): New.
 190         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 191         (prefix_table): Use PCMPESTR_Fixup.
 192         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 193         PCMPESTR_Fixup.
 194         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 195         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 196         Split 64-bit and non-64-bit variants.
 197         * opcodes/i386-tbl.h: Re-generate.
 198
 199 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 200
 201         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 202         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 203         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 204         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 205         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 206         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 207         (OP_SVE_V_HSD): New macros.
 208         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 209         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 210         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 211         (aarch64_opcode_table): Add new SVE instructions.
 212         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 213         for rotation operands.  Add new SVE operands.
 214         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 215         (ins_sve_quad_index): Likewise.
 216         (ins_imm_rotate): Split into...
 217         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 218         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 219         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 220         functions.
 221         (aarch64_ins_sve_addr_ri_s4): New function.
 222         (aarch64_ins_sve_quad_index): Likewise.
 223         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 224         * aarch64-asm-2.c: Regenerate.
 225         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 226         (ext_sve_quad_index): Likewise.
 227         (ext_imm_rotate): Split into...
 228         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 229         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 230         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 231         functions.
 232         (aarch64_ext_sve_addr_ri_s4): New function.
 233         (aarch64_ext_sve_quad_index): Likewise.
 234         (aarch64_ext_sve_index): Allow quad indices.
 235         (do_misc_decoding): Likewise.
 236         * aarch64-dis-2.c: Regenerate.
 237         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 238         aarch64_field_kinds.
 239         (OPD_F_OD_MASK): Widen by one bit.
 240         (OPD_F_NO_ZR): Bump accordingly.
 241         (get_operand_field_width): New function.
 242         * aarch64-opc.c (fields): Add new SVE fields.
 243         (operand_general_constraint_met_p): Handle new SVE operands.
 244         (aarch64_print_operand): Likewise.
 245         * aarch64-opc-2.c: Regenerate.
 246
 247 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 248
 249         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 250         (aarch64_feature_compnum): ...this.
 251         (SIMD_V8_3): Replace with...
 252         (COMPNUM): ...this.
 253         (CNUM_INSN): New macro.
 254         (aarch64_opcode_table): Use it for the complex number instructions.
 255
 256 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 257
 258         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 259
 260 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 261
 262         Add support for associating SPARC ASIs with an architecture level.
 263         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 264         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 265         decoding of SPARC ASIs.
 266
 267 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 268
 269         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 270         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 271
 272 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 273
 274         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 275         1 (instead of to itself). Correct typo.
 276
 277 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 278
 279         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 280         pseudoinstructions.
 281
 282 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 283
 284         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 285         (aarch64_sys_reg_supported_p): Handle them.
 286
 287 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 288
 289         * arc-opc.c (UIMM6_20R): Define.
 290         (SIMM12_20): Use above.
 291         (SIMM12_20R): Define.
 292         (SIMM3_5_S): Use above.
 293         (UIMM7_A32_11R_S): Define.
 294         (UIMM7_9_S): Use above.
 295         (UIMM3_13R_S): Define.
 296         (SIMM11_A32_7_S): Use above.
 297         (SIMM9_8R): Define.
 298         (UIMM10_A32_8_S): Use above.
 299         (UIMM8_8R_S): Define.
 300         (W6): Use above.
 301         (arc_relax_opcodes): Use all above defines.
 302
 303 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 304
 305         * arc-regs.h: Distinguish some of the registers different on
 306         ARC700 and HS38 cpus.
 307
 308 2017-02-14  Alan Modra  <amodra@gmail.com>
 309
 310         PR 21118
 311         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 312         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 313
 314 2017-02-11  Stafford Horne  <shorne@gmail.com>
 315             Alan Modra  <amodra@gmail.com>
 316
 317         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 318         Use insn_bytes_value and insn_int_value directly instead.  Don't
 319         free allocated memory until function exit.
 320
 321 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 322
 323         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 324
 325 2017-02-03  Nick Clifton  <nickc@redhat.com>
 326
 327         PR 21096
 328         * aarch64-opc.c (print_register_list): Ensure that the register
 329         list index will fir into the tb buffer.
 330         (print_register_offset_address): Likewise.
 331         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 332
 333 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 334
 335         PR 21056
 336         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 337         instructions when the previous fetch packet ends with a 32-bit
 338         instruction.
 339
 340 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 341
 342         * pru-opc.c: Remove vague reference to a future GDB port.
 343
 344 2017-01-20  Nick Clifton  <nickc@redhat.com>
 345
 346         * po/ga.po: Updated Irish translation.
 347
 348 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 349
 350         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 351
 352 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 353
 354         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 355         if FETCH_DATA returns 0.
 356         (m68k_scan_mask): Likewise.
 357         (print_insn_m68k): Update code to handle -1 return value.
 358
 359 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 360
 361         * m68k-dis.c (enum print_insn_arg_error): New.
 362         (NEXTBYTE): Replace -3 with
 363         PRINT_INSN_ARG_MEMORY_ERROR.
 364         (NEXTULONG): Likewise.
 365         (NEXTSINGLE): Likewise.
 366         (NEXTDOUBLE): Likewise.
 367         (NEXTDOUBLE): Likewise.
 368         (NEXTPACKED): Likewise.
 369         (FETCH_ARG): Likewise.
 370         (FETCH_DATA): Update comments.
 371         (print_insn_arg): Update comments. Replace magic numbers with
 372         enum.
 373         (match_insn_m68k): Likewise.
 374
 375 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 376
 377         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 378         * i386-dis-evex.h (evex_table): Updated.
 379         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 380         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 381         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 382         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 383         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 384         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 385         * i386-init.h: Regenerate.
 386         * i386-tbl.h: Ditto.
 387
 388 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 389
 390         * msp430-dis.c (msp430_singleoperand): Return -1 if
 391         msp430dis_opcode_signed returns false.
 392         (msp430_doubleoperand): Likewise.
 393         (msp430_branchinstr): Return -1 if
 394         msp430dis_opcode_unsigned returns false.
 395         (msp430x_calla_instr): Likewise.
 396         (print_insn_msp430): Likewise.
 397
 398 2017-01-05  Nick Clifton  <nickc@redhat.com>
 399
 400         PR 20946
 401         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 402         could not be matched.
 403         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 404         NULL.
 405
 406 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 407
 408         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 409         (aarch64_opcode_table): Use RCPC_INSN.
 410
 411 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 412
 413         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 414         extension.
 415         * riscv-opcodes/all-opcodes: Likewise.
 416
 417 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 418
 419         * riscv-dis.c (print_insn_args): Add fall through comment.
 420
 421 2017-01-03  Nick Clifton  <nickc@redhat.com>
 422
 423         * po/sr.po: New Serbian translation.
 424         * configure.ac (ALL_LINGUAS): Add sr.
 425         * configure: Regenerate.
 426
 427 2017-01-02  Alan Modra  <amodra@gmail.com>
 428
 429         * epiphany-desc.h: Regenerate.
 430         * epiphany-opc.h: Regenerate.
 431         * fr30-desc.h: Regenerate.
 432         * fr30-opc.h: Regenerate.
 433         * frv-desc.h: Regenerate.
 434         * frv-opc.h: Regenerate.
 435         * ip2k-desc.h: Regenerate.
 436         * ip2k-opc.h: Regenerate.
 437         * iq2000-desc.h: Regenerate.
 438         * iq2000-opc.h: Regenerate.
 439         * lm32-desc.h: Regenerate.
 440         * lm32-opc.h: Regenerate.
 441         * m32c-desc.h: Regenerate.
 442         * m32c-opc.h: Regenerate.
 443         * m32r-desc.h: Regenerate.
 444         * m32r-opc.h: Regenerate.
 445         * mep-desc.h: Regenerate.
 446         * mep-opc.h: Regenerate.
 447         * mt-desc.h: Regenerate.
 448         * mt-opc.h: Regenerate.
 449         * or1k-desc.h: Regenerate.
 450         * or1k-opc.h: Regenerate.
 451         * xc16x-desc.h: Regenerate.
 452         * xc16x-opc.h: Regenerate.
 453         * xstormy16-desc.h: Regenerate.
 454         * xstormy16-opc.h: Regenerate.
 455
 456 2017-01-02  Alan Modra  <amodra@gmail.com>
 457
 458         Update year range in copyright notice of all files.
 459
 460 For older changes see ChangeLog-2016
 461 \f
 462 Copyright (C) 2017 Free Software Foundation, Inc.
 463
 464 Copying and distribution of this file, with or without modification,
 465 are permitted in any medium without royalty provided the copyright
 466 notice and this notice are preserved.
 467
 468 Local Variables:
 469 mode: change-log
 470 left-margin: 8
 471 fill-column: 74
 472 version-control: never
 473 End: