opcodes/ChangeLog

   1 2016-12-08  Luis Machado  <lgustavo@codesourcery.com>
   2
   3         * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
   4
   5 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
   6
   7         * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
   8
   9 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  10
  11         * mips16-opc.c (mips16_opcodes): Update comment naming structure
  12         members.
  13
  14 2016-12-07  Maciej W. Rozycki  <macro@imgtec.com>
  15
  16         * mips-dis.c (print_mips_disassembler_options): Reformat output.
  17
  18 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  19
  20         * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
  21         (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
  22
  23 2016-12-05  Szabolcs Nagy  <szabolcs.nagy@arm.com>
  24
  25         * arm-dis.c (coprocessor_opcodes): Add vjcvt.
  26
  27 2016-12-01  Nick Clifton  <nickc@redhat.com>
  28
  29         PR binutils/20893
  30         * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
  31         opcode designator.
  32
  33 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
  34
  35         * arc-opc.c (insert_ra_chk): New function.
  36         (insert_rb_chk): Likewise.
  37         (insert_rad): Update text error message.
  38         (insert_rcd): Likewise.
  39         (insert_rhv2): Likewise.
  40         (insert_r0): Likewise.
  41         (insert_r1): Likewise.
  42         (insert_r2): Likewise.
  43         (insert_r3): Likewise.
  44         (insert_sp): Likewise.
  45         (insert_gp): Likewise.
  46         (insert_pcl): Likewise.
  47         (insert_blink): Likewise.
  48         (insert_ilink1): Likewise.
  49         (insert_ilink2): Likewise.
  50         (insert_ras): Likewise.
  51         (insert_rbs): Likewise.
  52         (insert_rcs): Likewise.
  53         (insert_simm3s): Likewise.
  54         (insert_rrange): Likewise.
  55         (insert_fpel): Likewise.
  56         (insert_blinkel): Likewise.
  57         (insert_pcel): Likewise.
  58         (insert_nps_3bit_dst): Likewise.
  59         (insert_nps_3bit_dst_short): Likewise.
  60         (insert_nps_3bit_src2_short): Likewise.
  61         (insert_nps_bitop_size_2b): Likewise.
  62         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
  63         (RA_CHK): Define.
  64         (RB): Adjust.
  65         (RB_CHK): Define.
  66         (RC): Adjust.
  67         * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
  68         * arc-tbl.h (div, divu): All instructions are DIVREM class.
  69         Change first insn argument to check for LP_COUNT usage.
  70         (rem): Likewise.
  71         (ld, ldd): All instructions are LOAD class.  Change first insn
  72         argument to check for LP_COUNT usage.
  73         (st, std): All instructions are STORE class.
  74         (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
  75         Change first insn argument to check for LP_COUNT usage.
  76         (mov): All instructions are MOVE class.  Change first insn
  77         argument to check for LP_COUNT usage.
  78
  79 2016-11-29  Claudiu Zissulescu  <claziss@synopsys.com>
  80
  81         * arc-dis.c (is_compatible_p): Remove function.
  82         (skip_this_opcode): Don't add any decoding class to decode list.
  83         Remove warning.
  84         (find_format_from_table): Go through all opcodes, and warn if we
  85         use a guessed mnemonic.
  86
  87 2016-11-28  Ramiro Polla  <ramiro@hex-rays.com>
  88             Amit Pawar  <amit.pawar@amd.com>
  89
  90         PR binutils/20637
  91         * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
  92         instructions.
  93
  94 2016-11-22  Ambrogino Modigliani  <ambrogino.modigliani@gmail.com>
  95
  96         * configure: Regenerate.
  97
  98 2016-11-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
  99
 100         * sparc-opc.c (HWS_V8): Definition moved from
 101         gas/config/tc-sparc.c.
 102         (HWS_V9): Likewise.
 103         (HWS_VA): Likewise.
 104         (HWS_VB): Likewise.
 105         (HWS_VC): Likewise.
 106         (HWS_VD): Likewise.
 107         (HWS_VE): Likewise.
 108         (HWS_VV): Likewise.
 109         (HWS_VM): Likewise.
 110         (HWS2_VM): Likewise.
 111         (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
 112         existing entries.
 113
 114 2016-11-22  Claudiu Zissulescu  <claziss@synopsys.com>
 115
 116         * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
 117         instructions.
 118
 119 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 120
 121         * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
 122         (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
 123         (aarch64_opcode_table): Add fcmla and fcadd.
 124         (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
 125         * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
 126         * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
 127         * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
 128         * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
 129         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
 130         * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
 131         (operand_general_constraint_met_p): Rotate and index range check.
 132         (aarch64_print_operand): Handle rotate operand.
 133         * aarch64-asm-2.c: Regenerate.
 134         * aarch64-dis-2.c: Likewise.
 135         * aarch64-opc-2.c: Likewise.
 136
 137 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 138
 139         * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
 140         * aarch64-asm-2.c: Regenerate.
 141         * aarch64-dis-2.c: Regenerate.
 142         * aarch64-opc-2.c: Regenerate.
 143
 144 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 145
 146         * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
 147         (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
 148         * aarch64-asm-2.c: Regenerate.
 149         * aarch64-dis-2.c: Regenerate.
 150         * aarch64-opc-2.c: Regenerate.
 151
 152 2016-11-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 153
 154         * aarch64-tbl.h (QL_X1NIL): New.
 155         (arch64_opcode_table): Add ldraa, ldrab.
 156         (AARCH64_OPERANDS): Add "ADDR_SIMM10".
 157         * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
 158         * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
 159         * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
 160         * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
 161         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
 162         * aarch64-opc.c (fields): Add data for FLD_S_simm10.
 163         (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
 164         (aarch64_print_operand): Likewise.
 165         * aarch64-asm-2.c: Regenerate.
 166         * aarch64-dis-2.c: Regenerate.
 167         * aarch64-opc-2.c: Regenerate.
 168
 169 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 170
 171         * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
 172         brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
 173         * aarch64-asm-2.c: Regenerate.
 174         * aarch64-dis-2.c: Regenerate.
 175         * aarch64-opc-2.c: Regenerate.
 176
 177 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 178
 179         * aarch64-tbl.h (arch64_opcode_table): Add pacga.
 180         (AARCH64_OPERANDS): Add Rm_SP.
 181         * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
 182         * aarch64-asm-2.c: Regenerate.
 183         * aarch64-dis-2.c: Regenerate.
 184         * aarch64-opc-2.c: Regenerate.
 185
 186 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 187
 188         * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
 189         autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
 190         autdzb, xpaci, xpacd.
 191         * aarch64-asm-2.c: Regenerate.
 192         * aarch64-dis-2.c: Regenerate.
 193         * aarch64-opc-2.c: Regenerate.
 194
 195 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 196
 197         * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
 198         apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
 199         apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
 200         (aarch64_sys_reg_supported_p): Add feature test for new registers.
 201
 202 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 203
 204         * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
 205         (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
 206         autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
 207         autibsp.
 208         * aarch64-asm-2.c: Regenerate.
 209         * aarch64-dis-2.c: Regenerate.
 210
 211 2016-11-11  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 212
 213         * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
 214
 215 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 216
 217         PR binutils/20799
 218         * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
 219         * i386-dis.c (EdqwS): Removed.
 220         (dqw_swap_mode): Likewise.
 221         (intel_operand_size): Don't check dqw_swap_mode.
 222         (OP_E_register): Likewise.
 223         (OP_E_memory): Likewise.
 224         (OP_G): Likewise.
 225         (OP_EX): Likewise.
 226         * i386-opc.tbl: Remove "S" from EVEX vpextrw.
 227         * i386-tbl.h: Regerated.
 228
 229 2016-11-09  H.J. Lu  <hongjiu.lu@intel.com>
 230
 231         * i386-opc.tbl: Merge AVX512F vmovq.
 232         * i386-tbl.h: Regerated.
 233
 234 2016-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 235
 236         PR binutils/20701
 237         * i386-dis.c (THREE_BYTE_0F7A): Removed.
 238         (dis386_twobyte): Don't use THREE_BYTE_0F7A.
 239         (three_byte_table): Remove THREE_BYTE_0F7A.
 240
 241 2016-11-07  H.J. Lu  <hongjiu.lu@intel.com>
 242
 243         PR binutils/20775
 244         * i386-dis.c (FGRPd9_2): Replace 0 with 1.
 245         (FGRPd9_4): Replace 1 with 2.
 246         (FGRPd9_5): Replace 2 with 3.
 247         (FGRPd9_6): Replace 3 with 4.
 248         (FGRPd9_7): Replace 4 with 5.
 249         (FGRPda_5): Replace 5 with 6.
 250         (FGRPdb_4): Replace 6 with 7.
 251         (FGRPde_3): Replace 7 with 8.
 252         (FGRPdf_4): Replace 8 with 9.
 253         (fgrps): Add an entry for Bad_Opcode.
 254
 255 2016-11-04  Andrew Burgess  <andrew.burgess@embecosm.com>
 256
 257         * arc-opc.c (arc_flag_operands): Add F_DI14.
 258         (arc_flag_classes): Add C_DI14.
 259         * arc-nps400-tbl.h: Add new exc instructions.
 260
 261 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 262
 263         * arc-dis.c (arc_insn_length): Return length 8 for instructions with
 264         major opcode 0xa.
 265         * arc-nps-400-tbl.h: Add dcmac instruction.
 266         * arc-opc.c (arc_operands): Added operands for dcmac instruction.
 267         (insert_nps_rbdouble_64): Added.
 268         (extract_nps_rbdouble_64): Added.
 269         (insert_nps_proto_size): Added.
 270         (extract_nps_proto_size): Added.
 271
 272 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 273
 274         * arc-dis.c (struct arc_operand_iterator): Remove all fields
 275         relating to long instruction processing, add new limm field.
 276         (OPCODE): Rename to...
 277         (OPCODE_32BIT_INSN): ...this.
 278         (OPCODE_AC): Delete.
 279         (skip_this_opcode): Handle different instruction lengths, update
 280         macro name.
 281         (special_flag_p): Update parameter type.
 282         (find_format_from_table): Update for more instruction lengths.
 283         (find_format_long_instructions): Delete.
 284         (find_format): Update for more instruction lengths.
 285         (arc_insn_length): Likewise.
 286         (extract_operand_value): Update for more instruction lengths.
 287         (operand_iterator_next): Remove code relating to long
 288         instructions.
 289         (arc_opcode_to_insn_type): New function.
 290         (print_insn_arc):Update for more instructions lengths.
 291         * arc-ext.c (extInstruction_t): Change argument type.
 292         * arc-ext.h (extInstruction_t): Change argument type.
 293         * arc-fxi.h: Change type unsigned to unsigned long long
 294         extensively throughout.
 295         * arc-nps400-tbl.h: Add long instructions taken from
 296         arc_long_opcodes table in arc-opc.c.
 297         * arc-opc.c: Update parameter types on insert/extract handlers.
 298         (arc_long_opcodes): Delete.
 299         (arc_num_long_opcodes): Delete.
 300         (arc_opcode_len): Update for more instruction lengths.
 301
 302 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 303
 304         * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
 305
 306 2016-11-03  Graham Markall  <graham.markall@embecosm.com>
 307
 308         * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
 309         with arc_opcode_len.
 310         (find_format_long_instructions): Likewise.
 311         * arc-opc.c (arc_opcode_len): New function.
 312
 313 2016-11-03  Andrew Burgess  <andrew.burgess@embecosm.com>
 314
 315         * arc-nps400-tbl.h: Fix some instruction masks.
 316
 317 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 318
 319         * i386-dis.c (REG_82): Removed.
 320         (X86_64_82_REG_0): Likewise.
 321         (X86_64_82_REG_1): Likewise.
 322         (X86_64_82_REG_2): Likewise.
 323         (X86_64_82_REG_3): Likewise.
 324         (X86_64_82_REG_4): Likewise.
 325         (X86_64_82_REG_5): Likewise.
 326         (X86_64_82_REG_6): Likewise.
 327         (X86_64_82_REG_7): Likewise.
 328         (X86_64_82): New.
 329         (dis386): Use X86_64_82 instead of REG_82.
 330         (reg_table): Remove REG_82.
 331         (x86_64_table): Add X86_64_82.  Remove X86_64_82_REG_0,
 332         X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
 333         X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
 334         X86_64_82_REG_7.
 335
 336 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 337
 338         PR binutils/20754
 339         * i386-dis.c (REG_82): New.
 340         (X86_64_82_REG_0): Likewise.
 341         (X86_64_82_REG_1): Likewise.
 342         (X86_64_82_REG_2): Likewise.
 343         (X86_64_82_REG_3): Likewise.
 344         (X86_64_82_REG_4): Likewise.
 345         (X86_64_82_REG_5): Likewise.
 346         (X86_64_82_REG_6): Likewise.
 347         (X86_64_82_REG_7): Likewise.
 348         (dis386): Use REG_82.
 349         (reg_table): Add REG_82.
 350         (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
 351         X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
 352         X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
 353
 354 2016-11-03  H.J. Lu  <hongjiu.lu@intel.com>
 355
 356         * i386-dis.c (REG_82): Renamed to ...
 357         (REG_83): This.
 358         (dis386): Updated.
 359         (reg_table): Likewise.
 360
 361 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 362
 363         * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
 364         * i386-dis-evex.h (evex_table): Updated.
 365         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
 366         CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 367         (cpu_flags): Add CpuAVX512_4VNNIW.
 368         * i386-opc.h (enum): (AVX512_4VNNIW): New.
 369         (i386_cpu_flags): Add cpuavx512_4vnniw.
 370         * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
 371         * i386-init.h: Regenerate.
 372         * i386-tbl.h: Ditto.
 373
 374 2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 375
 376         * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
 377         PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
 378         * i386-dis-evex.h (evex_table): Updated.
 379         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
 380         CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 381         (cpu_flags): Add CpuAVX512_4FMAPS.
 382         (opcode_modifiers): Add ImplicitQuadGroup modifier.
 383         * i386-opc.h (AVX512_4FMAP): New.
 384         (i386_cpu_flags): Add cpuavx512_4fmaps.
 385         (ImplicitQuadGroup): New.
 386         (i386_opcode_modifier): Add implicitquadgroup.
 387         * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
 388         * i386-init.h: Regenerate.
 389         * i386-tbl.h: Ditto.
 390
 391 2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
 392             Andrew Waterman <andrew@sifive.com>
 393
 394         Add support for RISC-V architecture.
 395         * configure.ac: Add entry for bfd_riscv_arch.
 396         * configure: Regenerate.
 397         * disassemble.c (disassembler): Add support for riscv.
 398         (disassembler_usage): Likewise.
 399         * riscv-dis.c: New file.
 400         * riscv-opc.c: New file.
 401
 402 2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
 403
 404         * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
 405         (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
 406         (rm_table): Update the RM_0FAE_REG_7 entry.
 407         * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
 408         (cpu_flags): Remove CpuPCOMMIT.
 409         * i386-opc.h (CpuPCOMMIT): Removed.
 410         (i386_cpu_flags): Remove cpupcommit.
 411         * i386-opc.tbl: Remove pcommit.
 412         * i386-init.h: Regenerated.
 413         * i386-tbl.h: Likewise.
 414
 415 2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
 416
 417         PR binutis/20705
 418         * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
 419         the highest bit in VEX.vvvv for the 3-byte VEX prefix in
 420         32-bit mode.  Don't check vex.register_specifier in 32-bit
 421         mode.
 422         (OP_VEX): Check for invalid mask registers.
 423
 424 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 425
 426         PR binutis/20699
 427         * i386-dis.c (OP_E_memory): Check addr32flag in stead of
 428         sizeflag.
 429
 430 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 431
 432         PR binutis/20704
 433         * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
 434
 435 2016-10-18  Maciej W. Rozycki  <macro@imgtec.com>
 436
 437         * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
 438         local variable to `index_regno'.
 439
 440 2016-10-17  Cupertino Miranda  <cmiranda@synopsys.com>
 441
 442         * arc-tbl.h: Removed any "inv.+" instructions from the table.
 443
 444 2016-10-14  Claudiu Zissulescu  <claziss@synopsys.com>
 445
 446         * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
 447         usage on ISA basis.
 448
 449 2016-10-11  Jiong Wang  <jiong.wang@arm.com>
 450
 451         PR target/20666
 452         * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
 453
 454 2016-10-07  Jiong Wang  <jiong.wang@arm.com>
 455
 456         PR target/20667
 457         * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
 458         available.
 459
 460 2016-10-07  Alan Modra  <amodra@gmail.com>
 461
 462         * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
 463
 464 2016-10-06  Alan Modra  <amodra@gmail.com>
 465
 466         * aarch64-opc.c: Spell fall through comments consistently.
 467         * i386-dis.c: Likewise.
 468         * aarch64-dis.c: Add missing fall through comments.
 469         * aarch64-opc.c: Likewise.
 470         * arc-dis.c: Likewise.
 471         * arm-dis.c: Likewise.
 472         * i386-dis.c: Likewise.
 473         * m68k-dis.c: Likewise.
 474         * mep-asm.c: Likewise.
 475         * ns32k-dis.c: Likewise.
 476         * sh-dis.c: Likewise.
 477         * tic4x-dis.c: Likewise.
 478         * tic6x-dis.c: Likewise.
 479         * vax-dis.c: Likewise.
 480
 481 2016-10-06  Alan Modra  <amodra@gmail.com>
 482
 483         * arc-ext.c (create_map): Add missing break.
 484         * msp430-decode.opc (encode_as): Likewise.
 485         * msp430-decode.c: Regenerate.
 486
 487 2016-10-06  Alan Modra  <amodra@gmail.com>
 488
 489         * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
 490         * crx-dis.c (print_insn_crx): Likewise.
 491
 492 2016-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 493
 494         PR binutils/20657
 495         * i386-dis.c (putop): Don't assign alt twice.
 496
 497 2016-09-29  Jiong Wang  <jiong.wang@arm.com>
 498
 499         PR target/20553
 500         * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
 501
 502 2016-09-29  Alan Modra  <amodra@gmail.com>
 503
 504         * ppc-opc.c (L): Make compulsory.
 505         (LOPT): New, optional form of L.
 506         (HTM_R): Define as LOPT.
 507         (L0, L1): Delete.
 508         (L32OPT): New, optional for 32-bit L.
 509         (L2OPT): New, 2-bit L for dcbf.
 510         (SVC_LEC): Update.
 511         (L2): Define.
 512         (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
 513         (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
 514         <dcbf>: Use L2OPT.
 515         <tlbiel, tlbie>: Use LOPT.
 516         <wclr, wclrall>: Use L2.
 517
 518 2016-09-26  Vlad Zakharov  <vzakhar@synopsys.com>
 519
 520         * Makefile.in: Regenerate.
 521         * configure: Likewise.
 522
 523 2016-09-26  Claudiu Zissulescu  <claziss@synopsys.com>
 524
 525         * arc-ext-tbl.h (EXTINSN2OPF): Define.
 526         (EXTINSN2OP): Use EXTINSN2OPF.
 527         (bspeekm, bspop, modapp): New extension instructions.
 528         * arc-opc.c (F_DNZ_ND): Define.
 529         (F_DNZ_D): Likewise.
 530         (F_SIZEB1): Changed.
 531         (C_DNZ_D): Define.
 532         (C_HARD): Changed.
 533         * arc-tbl.h (dbnz): New instruction.
 534         (prealloc): Allow it for ARC EM.
 535         (xbfu): Likewise.
 536
 537 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 538
 539         * aarch64-opc.c (print_immediate_offset_address): Print spaces
 540         after commas in addresses.
 541         (aarch64_print_operand): Likewise.
 542
 543 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 544
 545         * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
 546         rather than "should be" or "expected to be" in error messages.
 547
 548 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 549
 550         * aarch64-dis.c (remove_dot_suffix): New function, split out from...
 551         (print_mnemonic_name): ...here.
 552         (print_comment): New function.
 553         (print_aarch64_insn): Call it.
 554         * aarch64-opc.c (aarch64_conds): Add SVE names.
 555         (aarch64_print_operand): Print alternative condition names in
 556         a comment.
 557
 558 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 559
 560         * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
 561         (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
 562         (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
 563         (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
 564         (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
 565         (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
 566         (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
 567         (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
 568         (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
 569         (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
 570         (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
 571         (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
 572         (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
 573         (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
 574         (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
 575         (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
 576         (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
 577         (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
 578         (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
 579         (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
 580         (OP_SVE_XWU, OP_SVE_XXU): New macros.
 581         (aarch64_feature_sve): New variable.
 582         (SVE): New macro.
 583         (_SVE_INSN): Likewise.
 584         (aarch64_opcode_table): Add SVE instructions.
 585         * aarch64-opc.h (extract_fields): Declare.
 586         * aarch64-opc-2.c: Regenerate.
 587         * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
 588         * aarch64-asm-2.c: Regenerate.
 589         * aarch64-dis.c (extract_fields): Make global.
 590         (do_misc_decoding): Handle the new SVE aarch64_ops.
 591         * aarch64-dis-2.c: Regenerate.
 592
 593 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 594
 595         * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
 596         (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
 597         aarch64_field_kinds.
 598         * aarch64-opc.c (fields): Add corresponding entries.
 599         * aarch64-asm.c (aarch64_get_variant): New function.
 600         (aarch64_encode_variant_using_iclass): Likewise.
 601         (aarch64_opcode_encode): Call it.
 602         * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
 603         (aarch64_opcode_decode): Call it.
 604
 605 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 606
 607         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
 608         and FP register operands.
 609         * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
 610         (FLD_SVE_Vn): New aarch64_field_kinds.
 611         * aarch64-opc.c (fields): Add corresponding entries.
 612         (aarch64_print_operand): Handle the new SVE core and FP register
 613         operands.
 614         * aarch64-opc-2.c: Regenerate.
 615         * aarch64-asm-2.c: Likewise.
 616         * aarch64-dis-2.c: Likewise.
 617
 618 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 619
 620         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
 621         immediate operands.
 622         * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
 623         * aarch64-opc.c (fields): Add corresponding entry.
 624         (operand_general_constraint_met_p): Handle the new SVE FP immediate
 625         operands.
 626         (aarch64_print_operand): Likewise.
 627         * aarch64-opc-2.c: Regenerate.
 628         * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
 629         (ins_sve_float_zero_one): New inserters.
 630         * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
 631         (aarch64_ins_sve_float_half_two): Likewise.
 632         (aarch64_ins_sve_float_zero_one): Likewise.
 633         * aarch64-asm-2.c: Regenerate.
 634         * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
 635         (ext_sve_float_zero_one): New extractors.
 636         * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
 637         (aarch64_ext_sve_float_half_two): Likewise.
 638         (aarch64_ext_sve_float_zero_one): Likewise.
 639         * aarch64-dis-2.c: Regenerate.
 640
 641 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 642
 643         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 644         integer immediate operands.
 645         * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
 646         (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
 647         (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
 648         * aarch64-opc.c (fields): Add corresponding entries.
 649         (operand_general_constraint_met_p): Handle the new SVE integer
 650         immediate operands.
 651         (aarch64_print_operand): Likewise.
 652         (aarch64_sve_dupm_mov_immediate_p): New function.
 653         * aarch64-opc-2.c: Regenerate.
 654         * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
 655         (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
 656         * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
 657         (aarch64_ins_limm): ...here.
 658         (aarch64_ins_inv_limm): New function.
 659         (aarch64_ins_sve_aimm): Likewise.
 660         (aarch64_ins_sve_asimm): Likewise.
 661         (aarch64_ins_sve_limm_mov): Likewise.
 662         (aarch64_ins_sve_shlimm): Likewise.
 663         (aarch64_ins_sve_shrimm): Likewise.
 664         * aarch64-asm-2.c: Regenerate.
 665         * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
 666         (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
 667         * aarch64-dis.c (decode_limm): New function, split out from...
 668         (aarch64_ext_limm): ...here.
 669         (aarch64_ext_inv_limm): New function.
 670         (decode_sve_aimm): Likewise.
 671         (aarch64_ext_sve_aimm): Likewise.
 672         (aarch64_ext_sve_asimm): Likewise.
 673         (aarch64_ext_sve_limm_mov): Likewise.
 674         (aarch64_top_bit): Likewise.
 675         (aarch64_ext_sve_shlimm): Likewise.
 676         (aarch64_ext_sve_shrimm): Likewise.
 677         * aarch64-dis-2.c: Regenerate.
 678
 679 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 680
 681         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
 682         operands.
 683         * aarch64-opc.c (aarch64_operand_modifiers): Initialize
 684         the AARCH64_MOD_MUL_VL entry.
 685         (value_aligned_p): Cope with non-power-of-two alignments.
 686         (operand_general_constraint_met_p): Handle the new MUL VL addresses.
 687         (print_immediate_offset_address): Likewise.
 688         (aarch64_print_operand): Likewise.
 689         * aarch64-opc-2.c: Regenerate.
 690         * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
 691         (ins_sve_addr_ri_s9xvl): New inserters.
 692         * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
 693         (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
 694         (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
 695         * aarch64-asm-2.c: Regenerate.
 696         * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
 697         (ext_sve_addr_ri_s9xvl): New extractors.
 698         * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
 699         (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
 700         (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
 701         (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
 702         * aarch64-dis-2.c: Regenerate.
 703
 704 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 705
 706         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
 707         address operands.
 708         * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
 709         (FLD_SVE_xs_22): New aarch64_field_kinds.
 710         (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
 711         (get_operand_specific_data): New function.
 712         * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
 713         FLD_SVE_xs_14 and FLD_SVE_xs_22.
 714         (operand_general_constraint_met_p): Handle the new SVE address
 715         operands.
 716         (sve_reg): New array.
 717         (get_addr_sve_reg_name): New function.
 718         (aarch64_print_operand): Handle the new SVE address operands.
 719         * aarch64-opc-2.c: Regenerate.
 720         * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
 721         (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
 722         (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
 723         * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
 724         (aarch64_ins_sve_addr_rr_lsl): Likewise.
 725         (aarch64_ins_sve_addr_rz_xtw): Likewise.
 726         (aarch64_ins_sve_addr_zi_u5): Likewise.
 727         (aarch64_ins_sve_addr_zz): Likewise.
 728         (aarch64_ins_sve_addr_zz_lsl): Likewise.
 729         (aarch64_ins_sve_addr_zz_sxtw): Likewise.
 730         (aarch64_ins_sve_addr_zz_uxtw): Likewise.
 731         * aarch64-asm-2.c: Regenerate.
 732         * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
 733         (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
 734         (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
 735         * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
 736         (aarch64_ext_sve_addr_ri_u6): Likewise.
 737         (aarch64_ext_sve_addr_rr_lsl): Likewise.
 738         (aarch64_ext_sve_addr_rz_xtw): Likewise.
 739         (aarch64_ext_sve_addr_zi_u5): Likewise.
 740         (aarch64_ext_sve_addr_zz): Likewise.
 741         (aarch64_ext_sve_addr_zz_lsl): Likewise.
 742         (aarch64_ext_sve_addr_zz_sxtw): Likewise.
 743         (aarch64_ext_sve_addr_zz_uxtw): Likewise.
 744         * aarch64-dis-2.c: Regenerate.
 745
 746 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 747
 748         * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
 749         AARCH64_OPND_SVE_PATTERN_SCALED.
 750         * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
 751         * aarch64-opc.c (fields): Add a corresponding entry.
 752         (set_multiplier_out_of_range_error): New function.
 753         (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
 754         (operand_general_constraint_met_p): Handle
 755         AARCH64_OPND_SVE_PATTERN_SCALED.
 756         (print_register_offset_address): Use PRIi64 to print the
 757         shift amount.
 758         (aarch64_print_operand): Likewise.  Handle
 759         AARCH64_OPND_SVE_PATTERN_SCALED.
 760         * aarch64-opc-2.c: Regenerate.
 761         * aarch64-asm.h (ins_sve_scale): New inserter.
 762         * aarch64-asm.c (aarch64_ins_sve_scale): New function.
 763         * aarch64-asm-2.c: Regenerate.
 764         * aarch64-dis.h (ext_sve_scale): New inserter.
 765         * aarch64-dis.c (aarch64_ext_sve_scale): New function.
 766         * aarch64-dis-2.c: Regenerate.
 767
 768 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 769
 770         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
 771         AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
 772         * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
 773         (FLD_SVE_prfop): Likewise.
 774         * aarch64-opc.c: Include libiberty.h.
 775         (aarch64_sve_pattern_array): New variable.
 776         (aarch64_sve_prfop_array): Likewise.
 777         (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
 778         (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
 779         AARCH64_OPND_SVE_PRFOP.
 780         * aarch64-asm-2.c: Regenerate.
 781         * aarch64-dis-2.c: Likewise.
 782         * aarch64-opc-2.c: Likewise.
 783
 784 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 785
 786         * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
 787         AARCH64_OPND_QLF_P_[ZM].
 788         (aarch64_print_operand): Print /z and /m where appropriate.
 789
 790 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 791
 792         * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
 793         * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
 794         (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
 795         (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
 796         (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
 797         * aarch64-opc.c (fields): Add corresponding entries here.
 798         (operand_general_constraint_met_p): Check that SVE register lists
 799         have the correct length.  Check the ranges of SVE index registers.
 800         Check for cases where p8-p15 are used in 3-bit predicate fields.
 801         (aarch64_print_operand): Handle the new SVE operands.
 802         * aarch64-opc-2.c: Regenerate.
 803         * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
 804         * aarch64-asm.c (aarch64_ins_sve_index): New function.
 805         (aarch64_ins_sve_reglist): Likewise.
 806         * aarch64-asm-2.c: Regenerate.
 807         * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
 808         * aarch64-dis.c (aarch64_ext_sve_index): New function.
 809         (aarch64_ext_sve_reglist): Likewise.
 810         * aarch64-dis-2.c: Regenerate.
 811
 812 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 813
 814         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
 815         (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
 816         (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
 817         * aarch64-opc.c (aarch64_match_operands_constraint): Check for
 818         tied operands.
 819
 820 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 821
 822         * aarch64-opc.c (get_offset_int_reg_name): New function.
 823         (print_immediate_offset_address): Likewise.
 824         (print_register_offset_address): Take the base and offset
 825         registers as parameters.
 826         (aarch64_print_operand): Update caller accordingly.  Use
 827         print_immediate_offset_address.
 828
 829 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 830
 831         * aarch64-opc.c (BANK): New macro.
 832         (R32, R64): Take a register number as argument
 833         (int_reg): Use BANK.
 834
 835 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 836
 837         * aarch64-opc.c (print_register_list): Add a prefix parameter.
 838         (aarch64_print_operand): Update accordingly.
 839
 840 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 841
 842         * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
 843         for FPIMM.
 844         * aarch64-asm.h (ins_fpimm): New inserter.
 845         * aarch64-asm.c (aarch64_ins_fpimm): New function.
 846         * aarch64-asm-2.c: Regenerate.
 847         * aarch64-dis.h (ext_fpimm): New extractor.
 848         * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
 849         (aarch64_ext_fpimm): New function.
 850         * aarch64-dis-2.c: Regenerate.
 851
 852 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 853
 854         * aarch64-asm.c: Include libiberty.h.
 855         (insert_fields): New function.
 856         (aarch64_ins_imm): Use it.
 857         * aarch64-dis.c (extract_fields): New function.
 858         (aarch64_ext_imm): Use it.
 859
 860 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 861
 862         * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
 863         with an esize parameter.
 864         (operand_general_constraint_met_p): Update accordingly.
 865         Fix misindented code.
 866         * aarch64-asm.c (aarch64_ins_limm): Update call to
 867         aarch64_logical_immediate_p.
 868
 869 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 870
 871         * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
 872
 873 2016-09-21  Richard Sandiford  <richard.sandiford@arm.com>
 874
 875         * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
 876
 877 2016-09-15  Claudiu Zissulescu  <claziss@synopsys.com>
 878
 879         * arc-dis.c (find_format): Walk the linked list pointed by einsn.
 880
 881 2016-09-14  Peter Bergner <bergner@vnet.ibm.com>
 882
 883         * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
 884         <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
 885         xor3>: Delete mnemonics.
 886         <cp_abort>: Rename mnemonic from ...
 887         <cpabort>: ...to this.
 888         <setb>: Change to a X form instruction.
 889         <sync>: Change to 1 operand form.
 890         <copy>: Delete mnemonic.
 891         <copy_first>: Rename mnemonic from ...
 892         <copy>: ...to this.
 893         <paste, paste.>: Delete mnemonics.
 894         <paste_last>: Rename mnemonic from ...
 895         <paste.>: ...to this.
 896
 897 2016-09-14  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 898
 899         * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
 900
 901 2016-09-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 902
 903         * s390-mkopc.c (main): Support alternate arch strings.
 904
 905 2016-09-12  Patrick Steuer  <steuer@linux.vnet.ibm.com>
 906
 907         * s390-opc.txt: Fix kmctr instruction type.
 908
 909 2016-09-07  H.J. Lu  <hongjiu.lu@intel.com>
 910
 911         * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
 912         * i386-init.h: Regenerated.
 913
 914 2016-08-30  Cupertino Miranda  <cmiranda@synopsys.com>
 915
 916         * opcodes/arc-dis.c (print_insn_arc): Changed.
 917
 918 2016-08-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 919
 920         * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
 921         camellia_fl.
 922
 923 2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 924
 925         * arm-dis.c (psr_name): Use hex as case labels.  Add detection for
 926         MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
 927         FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
 928
 929 2016-08-24  H.J. Lu  <hongjiu.lu@intel.com>
 930
 931         * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
 932         (PREFIX_MOD_3_0FAE_REG_4): Likewise.
 933         (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
 934         PREFIX_MOD_3_0FAE_REG_4.
 935         (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
 936         PREFIX_MOD_3_0FAE_REG_4.
 937         * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
 938         (cpu_flags): Add CpuPTWRITE.
 939         * i386-opc.h (CpuPTWRITE): New.
 940         (i386_cpu_flags): Add cpuptwrite.
 941         * i386-opc.tbl: Add ptwrite instruction.
 942         * i386-init.h: Regenerated.
 943         * i386-tbl.h: Likewise.
 944
 945 2016-08-24  Anton Kolesov  <Anton.Kolesov@synopsys.com>
 946
 947         * arc-dis.h: Wrap around in extern "C".
 948
 949 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 950
 951         * aarch64-tbl.h (V8_2_INSN): New macro.
 952         (aarch64_opcode_table): Use it.
 953
 954 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 955
 956         * aarch64-tbl.h (aarch64_opcode_table): Make more use of
 957         CORE_INSN, __FP_INSN and SIMD_INSN.
 958
 959 2016-08-23  Richard Sandiford  <richard.sandiford@arm.com>
 960
 961         * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
 962         (aarch64_opcode_table): Update uses accordingly.
 963
 964 2016-07-25  Andrew Jenner  <andrew@codesourcery.com>
 965         Kwok Cheung Yeung  <kcy@codesourcery.com>
 966
 967         opcodes/
 968         * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
 969         'e_cmplwi' to 'e_cmpli' instead.
 970         (OPVUPRT, OPVUPRT_MASK): Define.
 971         (powerpc_opcodes): Add E200Z4 insns.
 972         (vle_opcodes): Add context save/restore insns.
 973
 974 2016-07-27  Maciej W. Rozycki  <macro@imgtec.com>
 975
 976         * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
 977         "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
 978         "j".
 979
 980 2016-07-27  Graham Markall  <graham.markall@embecosm.com>
 981
 982         * arc-nps400-tbl.h: Change block comments to GNU format.
 983         * arc-dis.c: Add new globals addrtypenames,
 984         addrtypenames_max, and addtypeunknown.
 985         (get_addrtype): New function.
 986         (print_insn_arc): Print colons and address types when
 987         required.
 988         * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
 989         define insert and extract functions for all address types.
 990         (arc_operands): Add operands for colon and all address
 991         types.
 992         * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
 993         * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
 994         insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
 995         * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
 996         * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
 997         insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
 998
 999 2016-07-21  H.J. Lu  <hongjiu.lu@intel.com>
1000
1001         * configure: Regenerated.
1002
1003 2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
1004
1005         * arc-dis.c (skipclass): New structure.
1006         (decodelist): New variable.
1007         (is_compatible_p): New function.
1008         (new_element): Likewise.
1009         (skip_class_p): Likewise.
1010         (find_format_from_table): Use skip_class_p function.
1011         (find_format): Decode first the extension instructions.
1012         (print_insn_arc): Select either ARCEM or ARCHS based on elf
1013         e_flags.
1014         (parse_option): New function.
1015         (parse_disassembler_options): Likewise.
1016         (print_arc_disassembler_options): Likewise.
1017         (print_insn_arc): Use parse_disassembler_options function.  Proper
1018         select ARCv2 cpu variant.
1019         * disassemble.c (disassembler_usage): Add ARC disassembler
1020         options.
1021
1022 2016-07-13  Maciej W. Rozycki  <macro@imgtec.com>
1023
1024         * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1025         annotation from the "nal" entry and reorder it beyond "bltzal".
1026
1027 2016-07-12  Jose E. Marchesi  <jose.marchesi@oracle.com>
1028
1029         * sparc-opc.c (ldtxa): New macro.
1030         (sparc_opcodes): Use the macro defined above to add entries for
1031         the LDTXA instructions.
1032         (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1033         instruction.
1034
1035 2016-07-07  James Bowman  <james.bowman@ftdichip.com>
1036
1037         * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1038         and "jmpc".
1039
1040 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1041
1042         * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1043         (movzb): Adjust to cover all permitted suffixes.
1044         (movzw): New.
1045         * i386-tbl.h: Re-generate.
1046
1047 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1048
1049         * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1050         (lgdt): Remove Tbyte from non-64-bit variant.
1051         (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1052         xsaves64, xsavec64): Remove Disp16.
1053         (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1054         Remove Disp32S from non-64-bit variants. Remove Disp16 from
1055         64-bit variants.
1056         (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1057         vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1058         vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1059         64-bit variants.
1060         * i386-tbl.h: Re-generate.
1061
1062 2016-07-01  Jan Beulich  <jbeulich@suse.com>
1063
1064         * i386-opc.tbl (xlat): Remove RepPrefixOk.
1065         * i386-tbl.h: Re-generate.
1066
1067 2016-06-30  Yao Qi  <yao.qi@linaro.org>
1068
1069         * arm-dis.c (print_insn): Fix typo in comment.
1070
1071 2016-06-28  Richard Sandiford  <richard.sandiford@arm.com>
1072
1073         * aarch64-opc.c (operand_general_constraint_met_p): Check the
1074         range of ldst_elemlist operands.
1075         (print_register_list): Use PRIi64 to print the index.
1076         (aarch64_print_operand): Likewise.
1077
1078 2016-06-25  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1079
1080         * mcore-opc.h: Remove sentinal.
1081         * mcore-dis.c (print_insn_mcore): Adjust.
1082
1083 2016-06-23  Graham Markall  <graham.markall@embecosm.com>
1084
1085         * arc-opc.c: Correct description of availability of NPS400
1086         features.
1087
1088 2016-06-22  Peter Bergner <bergner@vnet.ibm.com>
1089
1090         * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1091         (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1092         mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1093         xor3>: New mnemonics.
1094         <setb>: Change to a VX form instruction.
1095         (insert_sh6): Add support for rldixor.
1096         (extract_sh6): Likewise.
1097
1098 2016-06-22  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1099
1100         * arc-ext.h: Wrap in extern C.
1101
1102 2016-06-21  Graham Markall  <graham.markall@embecosm.com>
1103
1104         * arc-dis.c (arc_insn_length): Add comment on instruction length.
1105         Use same method for determining instruction length on ARC700 and
1106         NPS-400.
1107         (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1108         * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1109         with the NPS400 subclass.
1110         * arc-opc.c: Likewise.
1111
1112 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1113
1114         * sparc-opc.c (rdasr): New macro.
1115         (wrasr): Likewise.
1116         (rdpr): Likewise.
1117         (wrpr): Likewise.
1118         (rdhpr): Likewise.
1119         (wrhpr): Likewise.
1120         (sparc_opcodes): Use the macros above to fix and expand the
1121         definition of read/write instructions from/to
1122         asr/privileged/hyperprivileged instructions.
1123         * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1124         %hva_mask_nz.  Prefer softint_set and softint_clear over
1125         set_softint and clear_softint.
1126         (print_insn_sparc): Support %ver in Rd.
1127
1128 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1129
1130         * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1131         architecture according to the hardware capabilities they require.
1132
1133 2016-06-17  Jose E. Marchesi  <jose.marchesi@oracle.com>
1134
1135         * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1136         (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1137         bfd_mach_sparc_v9{c,d,e,v,m}.
1138         * sparc-opc.c (MASK_V9C): Define.
1139         (MASK_V9D): Likewise.
1140         (MASK_V9E): Likewise.
1141         (MASK_V9V): Likewise.
1142         (MASK_V9M): Likewise.
1143         (v6): Add MASK_V9{C,D,E,V,M}.
1144         (v6notlet): Likewise.
1145         (v7): Likewise.
1146         (v8): Likewise.
1147         (v9): Likewise.
1148         (v9andleon): Likewise.
1149         (v9a): Likewise.
1150         (v9b): Likewise.
1151         (v9c): Define.
1152         (v9d): Likewise.
1153         (v9e): Likewise.
1154         (v9v): Likewise.
1155         (v9m): Likewise.
1156         (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1157
1158 2016-06-15  Nick Clifton  <nickc@redhat.com>
1159
1160         * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1161         constants to match expected behaviour.
1162         (nds32_parse_opcode): Likewise.  Also for whitespace.
1163
1164 2016-06-15  Andrew Burgess  <andrew.burgess@embecosm.com>
1165
1166         * arc-opc.c (extract_rhv1): Extract value from insn.
1167
1168 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1169
1170         * arc-nps400-tbl.h: Add ldbit instruction.
1171         * arc-opc.c: Add flag classes required for ldbit.
1172
1173 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1174
1175         * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1176         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1177         support the above instructions.
1178
1179 2016-06-14  Graham Markall  <graham.markall@embecosm.com>
1180
1181         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1182         imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1183         csma, cbba, zncv, and hofs.
1184         * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1185         support the above instructions.
1186
1187 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1188
1189         * arc-nps400-tbl.h: Add andab and orab instructions.
1190
1191 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1192
1193         * arc-nps400-tbl.h: Add addl-like instructions.
1194
1195 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1196
1197         * arc-nps400-tbl.h: Add mxb and imxb instructions.
1198
1199 2016-06-06  Graham Markall  <graham.markall@embecosm.com>
1200
1201         * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1202         instructions.
1203
1204 2016-06-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
1205
1206         * s390-dis.c (option_use_insn_len_bits_p): New file scope
1207         variable.
1208         (init_disasm): Handle new command line option "insnlength".
1209         (print_s390_disassembler_options): Mention new option in help
1210         output.
1211         (print_insn_s390): Use the encoded insn length when dumping
1212         unknown instructions.
1213
1214 2016-06-03  Pitchumani Sivanupandi  <pitchumani.s@atmel.com>
1215
1216         * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1217          to the address and set as symbol address for LDS/ STS immediate operands.
1218
1219 2016-06-07  Alan Modra  <amodra@gmail.com>
1220
1221         * ppc-dis.c (ppc_opts): Delete extraneous parentheses.  Default
1222         cpu for "vle" to e500.
1223         * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1224         (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1225         (PPCNONE): Delete, substitute throughout.
1226         (powerpc_opcodes): Remove PPCVLE from "flags".  Add to "deprecated"
1227         except for major opcode 4 and 31.
1228         (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1229
1230 2016-06-07  Matthew Wahab  <matthew.wahab@arm.com>
1231
1232         * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1233         ARM_EXT_RAS in relevant entries.
1234
1235 2016-06-03  Peter Bergner <bergner@vnet.ibm.com>
1236
1237         PR binutils/20196
1238         * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1239         opcodes for E6500.
1240
1241 2016-06-03  H.J. Lu  <hongjiu.lu@intel.com>
1242
1243         PR binutis/18386
1244         * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1245         (indir_v_mode): New.
1246         Add comments for '&'.
1247         (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1248         (putop): Handle '&'.
1249         (intel_operand_size): Handle indir_v_mode.
1250         (OP_E_register): Likewise.
1251         * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64.  Add
1252         64-bit indirect call/jmp for AMD64.
1253         * i386-tbl.h: Regenerated
1254
1255 2016-06-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1256
1257         * arc-dis.c (struct arc_operand_iterator): New structure.
1258         (find_format_from_table): All the old content from find_format,
1259         with some minor adjustments, and parameter renaming.
1260         (find_format_long_instructions): New function.
1261         (find_format): Rewritten.
1262         (arc_insn_length): Add LSB parameter.
1263         (extract_operand_value): New function.
1264         (operand_iterator_next): New function.
1265         (print_insn_arc): Use new functions to find opcode, and iterator
1266         over operands.
1267         * arc-opc.c (insert_nps_3bit_dst_short): New function.
1268         (extract_nps_3bit_dst_short): New function.
1269         (insert_nps_3bit_src2_short): New function.
1270         (extract_nps_3bit_src2_short): New function.
1271         (insert_nps_bitop1_size): New function.
1272         (extract_nps_bitop1_size): New function.
1273         (insert_nps_bitop2_size): New function.
1274         (extract_nps_bitop2_size): New function.
1275         (insert_nps_bitop_mod4_msb): New function.
1276         (extract_nps_bitop_mod4_msb): New function.
1277         (insert_nps_bitop_mod4_lsb): New function.
1278         (extract_nps_bitop_mod4_lsb): New function.
1279         (insert_nps_bitop_dst_pos3_pos4): New function.
1280         (extract_nps_bitop_dst_pos3_pos4): New function.
1281         (insert_nps_bitop_ins_ext): New function.
1282         (extract_nps_bitop_ins_ext): New function.
1283         (arc_operands): Add new operands.
1284         (arc_long_opcodes): New global array.
1285         (arc_num_long_opcodes): New global.
1286         * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1287
1288 2016-06-01  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1289
1290         * nds32-asm.h: Add extern "C".
1291         * sh-opc.h: Likewise.
1292
1293 2016-06-01  Graham Markall  <graham.markall@embecosm.com>
1294
1295         * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1296         0,b,limm to the rflt instruction.
1297
1298 2016-05-31  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1299
1300         * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1301         constant.
1302
1303 2016-05-29  H.J. Lu  <hongjiu.lu@intel.com>
1304
1305         PR gas/20145
1306         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1307         CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1308         CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1309         CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1310         CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1311         * i386-init.h: Regenerated.
1312
1313 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1314
1315         PR gas/20145
1316         * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
1317         CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
1318         CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1319         Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1320         CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
1321         CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1322         CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1323         Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
1324         CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1325         CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1326         CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
1327         for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
1328         CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
1329         CpuRegMask for AVX512.
1330         (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1331         and CpuRegMask.
1332         (set_bitfield_from_cpu_flag_init): New function.
1333         (set_bitfield): Remove const on f.  Call
1334         set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1335         * i386-opc.h (CpuRegMMX): New.
1336         (CpuRegXMM): Likewise.
1337         (CpuRegYMM): Likewise.
1338         (CpuRegZMM): Likewise.
1339         (CpuRegMask): Likewise.
1340         (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1341         and cpuregmask.
1342         * i386-init.h: Regenerated.
1343         * i386-tbl.h: Likewise.
1344
1345 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1346
1347         PR gas/20154
1348         * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1349         (opcode_modifiers): Add AMD64 and Intel64.
1350         (main): Properly verify CpuMax.
1351         * i386-opc.h (CpuAMD64): Removed.
1352         (CpuIntel64): Likewise.
1353         (CpuMax): Set to CpuNo64.
1354         (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1355         (AMD64): New.
1356         (Intel64): Likewise.
1357         (i386_opcode_modifier): Add amd64 and intel64.
1358         (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1359         on call and jmp.
1360         * i386-init.h: Regenerated.
1361         * i386-tbl.h: Likewise.
1362
1363 2016-05-27  H.J. Lu  <hongjiu.lu@intel.com>
1364
1365         PR gas/20154
1366         * i386-gen.c (main): Fail if CpuMax is incorrect.
1367         * i386-opc.h (CpuMax): Set to CpuIntel64.
1368         * i386-tbl.h: Regenerated.
1369
1370 2016-05-27  Nick Clifton  <nickc@redhat.com>
1371
1372         PR target/20150
1373         * msp430-dis.c (msp430dis_read_two_bytes): New function.
1374         (msp430dis_opcode_unsigned): New function.
1375         (msp430dis_opcode_signed): New function.
1376         (msp430_singleoperand): Use the new opcode reading functions.
1377         Only disassenmble bytes if they were successfully read.
1378         (msp430_doubleoperand): Likewise.
1379         (msp430_branchinstr): Likewise.
1380         (msp430x_callx_instr): Likewise.
1381         (print_insn_msp430): Check that it is safe to read bytes before
1382         attempting disassembly.  Use the new opcode reading functions.
1383
1384 2016-05-26  Peter Bergner <bergner@vnet.ibm.com>
1385
1386         * ppc-opc.c (CY): New define.  Document it.
1387         (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1388
1389 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1390
1391         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1392         CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1393         and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
1394         CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1395         CPU_ANY_AVX_FLAGS.
1396         * i386-init.h: Regenerated.
1397
1398 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1399
1400         PR gas/20141
1401         * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1402         CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1403         * i386-init.h: Regenerated.
1404
1405 2016-05-25  H.J. Lu  <hongjiu.lu@intel.com>
1406
1407         * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1408         CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
1409         * i386-init.h: Regenerated.
1410
1411 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1412
1413         * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1414         information.
1415         (print_insn_arc): Set insn_type information.
1416         * arc-opc.c (C_CC): Add F_CLASS_COND.
1417         * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1418         (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1419         (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1420         (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1421         (brne, brne_s, jeq_s, jne_s): Likewise.
1422
1423 2016-05-23  Claudiu Zissulescu  <claziss@synopsys.com>
1424
1425         * arc-tbl.h (neg): New instruction variant.
1426
1427 2016-05-23  Cupertino Miranda  <cmiranda@synopsys.com>
1428
1429         * arc-dis.c (find_format, find_format, get_auxreg)
1430         (print_insn_arc): Changed.
1431         * arc-ext.h (INSERT_XOP): Likewise.
1432
1433 2016-05-23  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1434
1435         * tic54x-dis.c (sprint_mmr): Adjust.
1436         * tic54x-opc.c: Likewise.
1437
1438 2016-05-19  Alan Modra  <amodra@gmail.com>
1439
1440         * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1441
1442 2016-05-19  Alan Modra  <amodra@gmail.com>
1443
1444         * ppc-opc.c: Formatting.
1445         (NSISIGNOPT): Define.
1446         (powerpc_opcodes <subis>): Use NSISIGNOPT.
1447
1448 2016-05-18  Maciej W. Rozycki  <macro@imgtec.com>
1449
1450         * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1451         replacing references to `micromips_ase' throughout.
1452         (_print_insn_mips): Don't use file-level microMIPS annotation to
1453         determine the disassembly mode with the symbol table.
1454
1455 2016-05-13  Peter Bergner <bergner@vnet.ibm.com>
1456
1457         * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1458
1459 2016-05-11  Andrew Bennett  <andrew.bennett@imgtec.com>
1460
1461         * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1462         mips64r6.
1463         * mips-opc.c (D34): New macro.
1464         (mips_builtin_opcodes): Define bposge32c for DSPr3.
1465
1466 2016-05-10  Alexander Fomin  <alexander.fomin@intel.com>
1467
1468         * i386-dis.c (prefix_table): Add RDPID instruction.
1469         * i386-gen.c (cpu_flag_init): Add RDPID flag.
1470         (cpu_flags): Add RDPID bitfield.
1471         * i386-opc.h (enum): Add RDPID element.
1472         (i386_cpu_flags): Add RDPID field.
1473         * i386-opc.tbl: Add RDPID instruction.
1474         * i386-init.h: Regenerate.
1475         * i386-tbl.h: Regenerate.
1476
1477 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1478
1479         * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1480         branch type of a symbol.
1481         (print_insn): Likewise.
1482
1483 2016-05-10  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1484
1485         * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1486         Mainline Security Extensions instructions.
1487         (thumb_opcodes): Add entries for narrow ARMv8-M Security
1488         Extensions instructions.
1489         (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1490         instructions.
1491         (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1492         special registers.
1493
1494 2016-05-09  Jose E. Marchesi  <jose.marchesi@oracle.com>
1495
1496         * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1497
1498 2016-05-03  Claudiu Zissulescu  <claziss@synopsys.com>
1499
1500         * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1501         (arcExtMap_genOpcode): Likewise.
1502         * arc-opc.c (arg_32bit_rc): Define new variable.
1503         (arg_32bit_u6): Likewise.
1504         (arg_32bit_limm): Likewise.
1505
1506 2016-05-03  Szabolcs Nagy  <szabolcs.nagy@arm.com>
1507
1508         * aarch64-gen.c (VERIFIER): Define.
1509         * aarch64-opc.c (VERIFIER): Define.
1510         (verify_ldpsw): Use static linkage.
1511         * aarch64-opc.h (verify_ldpsw): Remove.
1512         * aarch64-tbl.h: Use VERIFIER for verifiers.
1513
1514 2016-04-28  Nick Clifton  <nickc@redhat.com>
1515
1516         PR target/19722
1517         * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1518         * aarch64-opc.c (verify_ldpsw): New function.
1519         * aarch64-opc.h (verify_ldpsw): New prototype.
1520         * aarch64-tbl.h: Add initialiser for verifier field.
1521         (LDPSW): Set verifier to verify_ldpsw.
1522
1523 2016-04-23  H.J. Lu  <hongjiu.lu@intel.com>
1524
1525         PR binutils/19983
1526         PR binutils/19984
1527         * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1528         smaller than address size.
1529
1530 2016-04-20  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1531
1532         * alpha-dis.c: Regenerate.
1533         * crx-dis.c: Likewise.
1534         * disassemble.c: Likewise.
1535         * epiphany-opc.c: Likewise.
1536         * fr30-opc.c: Likewise.
1537         * frv-opc.c: Likewise.
1538         * ip2k-opc.c: Likewise.
1539         * iq2000-opc.c: Likewise.
1540         * lm32-opc.c: Likewise.
1541         * lm32-opinst.c: Likewise.
1542         * m32c-opc.c: Likewise.
1543         * m32r-opc.c: Likewise.
1544         * m32r-opinst.c: Likewise.
1545         * mep-opc.c: Likewise.
1546         * mt-opc.c: Likewise.
1547         * or1k-opc.c: Likewise.
1548         * or1k-opinst.c: Likewise.
1549         * tic80-opc.c: Likewise.
1550         * xc16x-opc.c: Likewise.
1551         * xstormy16-opc.c: Likewise.
1552
1553 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1554
1555         * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1556         fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1557         calcsd, and calcxd instructions.
1558         * arc-opc.c (insert_nps_bitop_size): Delete.
1559         (extract_nps_bitop_size): Delete.
1560         (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1561         (extract_nps_qcmp_m3): Define.
1562         (extract_nps_qcmp_m2): Define.
1563         (extract_nps_qcmp_m1): Define.
1564         (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1565         (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1566         (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1567         NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1568         NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1569         NPS_QCMP_M3.
1570
1571 2016-04-19  Andrew Burgess  <andrew.burgess@embecosm.com>
1572
1573         * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1574
1575 2016-04-15  H.J. Lu  <hongjiu.lu@intel.com>
1576
1577         * Makefile.in: Regenerated with automake 1.11.6.
1578         * aclocal.m4: Likewise.
1579
1580 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1581
1582         * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1583         instructions.
1584         * arc-opc.c (insert_nps_cmem_uimm16): New function.
1585         (extract_nps_cmem_uimm16): New function.
1586         (arc_operands): Add NPS_XLDST_UIMM16 operand.
1587
1588 2016-04-14  Andrew Burgess  <andrew.burgess@embecosm.com>
1589
1590         * arc-dis.c (arc_insn_length): New function.
1591         (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1592         (find_format): Change insnLen parameter to unsigned.
1593
1594 2016-04-13  Nick Clifton  <nickc@redhat.com>
1595
1596         PR target/19937
1597         * v850-opc.c (v850_opcodes): Correct masks for long versions of
1598         the LD.B and LD.BU instructions.
1599
1600 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1601
1602         * arc-dis.c (find_format): Check for extension flags.
1603         (print_flags): New function.
1604         (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1605         .extAuxRegister.
1606         * arc-ext.c (arcExtMap_coreRegName): Use
1607         LAST_EXTENSION_CORE_REGISTER.
1608         (arcExtMap_coreReadWrite): Likewise.
1609         (dump_ARC_extmap): Update printing.
1610         * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1611         (arc_aux_regs): Add cpu field.
1612         * arc-regs.h: Add cpu field, lower case name aux registers.
1613
1614 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1615
1616         * arc-tbl.h: Add rtsc, sleep with no arguments.
1617
1618 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
1619
1620         * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1621         Initialize.
1622         (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1623         (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1624         (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1625         (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1626         (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1627         (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1628         (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1629         (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1630         (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1631         (arc_opcode arc_opcodes): Null terminate the array.
1632         (arc_num_opcodes): Remove.
1633         * arc-ext.h (INSERT_XOP): Define.
1634         (extInstruction_t): Likewise.
1635         (arcExtMap_instName): Delete.
1636         (arcExtMap_insn): New function.
1637         (arcExtMap_genOpcode): Likewise.
1638         * arc-ext.c (ExtInstruction): Remove.
1639         (create_map): Zero initialize instruction fields.
1640         (arcExtMap_instName): Remove.
1641         (arcExtMap_insn): New function.
1642         (dump_ARC_extmap): More info while debuging.
1643         (arcExtMap_genOpcode): New function.
1644         * arc-dis.c (find_format): New function.
1645         (print_insn_arc): Use find_format.
1646         (arc_get_disassembler): Enable dump_ARC_extmap only when
1647         debugging.
1648
1649 2016-04-11  Maciej W. Rozycki  <macro@imgtec.com>
1650
1651         * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1652         instruction bits out.
1653
1654 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1655
1656         * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1657         * arc-opc.c (arc_flag_operands): Add new flags.
1658         (arc_flag_classes): Add new classes.
1659
1660 2016-04-07  Andrew Burgess  <andrew.burgess@embecosm.com>
1661
1662         * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1663
1664 2016-04-05  Andrew Burgess  <andrew.burgess@embecosm.com>
1665
1666         * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1667         encode1, rflt, crc16, and crc32 instructions.
1668         * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1669         (arc_flag_classes): Add C_NPS_R.
1670         (insert_nps_bitop_size_2b): New function.
1671         (extract_nps_bitop_size_2b): Likewise.
1672         (insert_nps_bitop_uimm8): Likewise.
1673         (extract_nps_bitop_uimm8): Likewise.
1674         (arc_operands): Add new operand entries.
1675
1676 2016-04-05  Claudiu Zissulescu  <claziss@synopsys.com>
1677
1678         * arc-regs.h: Add a new subclass field.  Add double assist
1679         accumulator register values.
1680         * arc-tbl.h: Use DPA subclass to mark the double assist
1681         instructions.  Use DPX/SPX subclas to mark the FPX instructions.
1682         * arc-opc.c (RSP): Define instead of SP.
1683         (arc_aux_regs): Add the subclass field.
1684
1685 2016-04-05  Jiong Wang  <jiong.wang@arm.com>
1686
1687         * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1688
1689 2016-03-31  Andrew Burgess  <andrew.burgess@embecosm.com>
1690
1691         * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1692         NPS_R_SRC1.
1693
1694 2016-03-30  Andrew Burgess  <andrew.burgess@embecosm.com>
1695
1696         * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1697         issues.  No functional changes.
1698
1699 2016-03-30  Claudiu Zissulescu  <claziss@synopsys.com>
1700
1701         * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1702         (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1703         (RTT): Remove duplicate.
1704         (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1705         (PCT_CONFIG*): Remove.
1706         (D1L, D1H, D2H, D2L): Define.
1707
1708 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1709
1710         * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1711
1712 2016-03-29  Claudiu Zissulescu  <claziss@synopsys.com>
1713
1714         * arc-tbl.h (invld07): Remove.
1715         * arc-ext-tbl.h: New file.
1716         * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1717         * arc-opc.c (arc_opcodes): Add ext-tbl include.
1718
1719 2016-03-24  Jan Kratochvil  <jan.kratochvil@redhat.com>
1720
1721         Fix -Wstack-usage warnings.
1722         * aarch64-dis.c (print_operands): Substitute size.
1723         * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1724
1725 2016-03-22  Jose E. Marchesi  <jose.marchesi@oracle.com>
1726
1727         * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1728         to get a proper diagnostic when an invalid ASR register is used.
1729
1730 2016-03-22  Nick Clifton  <nickc@redhat.com>
1731
1732         * configure: Regenerate.
1733
1734 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1735
1736         * arc-nps400-tbl.h: New file.
1737         * arc-opc.c: Add top level comment.
1738         (insert_nps_3bit_dst): New function.
1739         (extract_nps_3bit_dst): New function.
1740         (insert_nps_3bit_src2): New function.
1741         (extract_nps_3bit_src2): New function.
1742         (insert_nps_bitop_size): New function.
1743         (extract_nps_bitop_size): New function.
1744         (arc_flag_operands): Add nps400 entries.
1745         (arc_flag_classes): Add nps400 entries.
1746         (arc_operands): Add nps400 entries.
1747         (arc_opcodes): Add nps400 include.
1748
1749 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1750
1751         * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1752         the new class enum values.
1753
1754 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1755
1756         * arc-dis.c (print_insn_arc): Handle nps400.
1757
1758 2016-03-21  Andrew Burgess  <andrew.burgess@embecosm.com>
1759
1760         * arc-opc.c (BASE): Delete.
1761
1762 2016-03-18  Nick Clifton  <nickc@redhat.com>
1763
1764         PR target/19721
1765         * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1766         of MOV insn that aliases an ORR insn.
1767
1768 2016-03-16  Jiong Wang  <jiong.wang@arm.com>
1769
1770         * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1771
1772 2016-03-07  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>
1773
1774         * mcore-opc.h: Add const qualifiers.
1775         * microblaze-opc.h (struct op_code_struct): Likewise.
1776         * sh-opc.h: Likewise.
1777         * tic4x-dis.c (tic4x_print_indirect): Likewise.
1778         (tic4x_print_op): Likewise.
1779
1780 2016-03-02  Alan Modra  <amodra@gmail.com>
1781
1782         * or1k-desc.h: Regenerate.
1783         * fr30-ibld.c: Regenerate.
1784         * rl78-decode.c: Regenerate.
1785
1786 2016-03-01  Nick Clifton  <nickc@redhat.com>
1787
1788         PR target/19747
1789         * rl78-dis.c (print_insn_rl78_common): Fix typo.
1790
1791 2016-02-24  Renlin Li  <renlin.li@arm.com>
1792
1793         * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1794         (print_insn_coprocessor): Support fp16 instructions.
1795
1796 2016-02-24  Renlin Li  <renlin.li@arm.com>
1797
1798         * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1799         vminnm, vrint(mpna).
1800
1801 2016-02-24  Renlin Li  <renlin.li@arm.com>
1802
1803         * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1804         cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1805
1806 2016-02-15  H.J. Lu  <hongjiu.lu@intel.com>
1807
1808         * i386-dis.c (print_insn): Parenthesize expression to prevent
1809         truncated addresses.
1810         (OP_J): Likewise.
1811
1812 2016-02-10  Claudiu Zissulescu  <claziss@synopsys.com>
1813             Janek van Oirschot  <jvanoirs@synopsys.com>
1814
1815         * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1816         variable.
1817
1818 2016-02-04  Nick Clifton  <nickc@redhat.com>
1819
1820         PR target/19561
1821         * msp430-dis.c (print_insn_msp430): Add a special case for
1822         decoding an RRC instruction with the ZC bit set in the extension
1823         word.
1824
1825 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1826
1827         * cgen-ibld.in (insert_normal): Rework calculation of shift.
1828         * epiphany-ibld.c: Regenerate.
1829         * fr30-ibld.c: Regenerate.
1830         * frv-ibld.c: Regenerate.
1831         * ip2k-ibld.c: Regenerate.
1832         * iq2000-ibld.c: Regenerate.
1833         * lm32-ibld.c: Regenerate.
1834         * m32c-ibld.c: Regenerate.
1835         * m32r-ibld.c: Regenerate.
1836         * mep-ibld.c: Regenerate.
1837         * mt-ibld.c: Regenerate.
1838         * or1k-ibld.c: Regenerate.
1839         * xc16x-ibld.c: Regenerate.
1840         * xstormy16-ibld.c: Regenerate.
1841
1842 2016-02-02  Andrew Burgess  <andrew.burgess@embecosm.com>
1843
1844         * epiphany-dis.c: Regenerated from latest cpu files.
1845
1846 2016-02-01  Michael McConville  <mmcco@mykolab.com>
1847
1848         * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1849         test bit.
1850
1851 2016-01-25  Renlin Li  <renlin.li@arm.com>
1852
1853         * arm-dis.c (mapping_symbol_for_insn): New function.
1854         (find_ifthen_state): Call mapping_symbol_for_insn().
1855
1856 2016-01-20  Matthew Wahab  <matthew.wahab@arm.com>
1857
1858         * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1859         of MSR UAO immediate operand.
1860
1861 2016-01-18  Maciej W. Rozycki  <macro@imgtec.com>
1862
1863         * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1864         instruction support.
1865
1866 2016-01-17  Alan Modra  <amodra@gmail.com>
1867
1868         * configure: Regenerate.
1869
1870 2016-01-14  Nick Clifton  <nickc@redhat.com>
1871
1872         * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1873         instructions that can support stack pointer operations.
1874         * rl78-decode.c: Regenerate.
1875         * rl78-dis.c: Fix display of stack pointer in MOVW based
1876         instructions.
1877
1878 2016-01-14  Matthew Wahab  <matthew.wahab@arm.com>
1879
1880         * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1881         testing for RAS support.  Add checks for erxfr_el1, erxctlr_el1,
1882         erxtatus_el1 and erxaddr_el1.
1883
1884 2016-01-12  Matthew Wahab  <matthew.wahab@arm.com>
1885
1886         * arm-dis.c (arm_opcodes): Add "esb".
1887         (thumb_opcodes): Likewise.
1888
1889 2016-01-11  Peter Bergner <bergner@vnet.ibm.com>
1890
1891         * ppc-opc.c <xscmpnedp>: Delete.
1892         <xvcmpnedp>: Likewise.
1893         <xvcmpnedp.>: Likewise.
1894         <xvcmpnesp>: Likewise.
1895         <xvcmpnesp.>: Likewise.
1896
1897 2016-01-08  Andreas Schwab  <schwab@linux-m68k.org>
1898
1899         PR gas/13050
1900         * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1901         addition to ISA_A.
1902
1903 2016-01-01  Alan Modra  <amodra@gmail.com>
1904
1905         Update year range in copyright notice of all files.
1906
1907 For older changes see ChangeLog-2015
1908 \f
1909 Copyright (C) 2016 Free Software Foundation, Inc.
1910
1911 Copying and distribution of this file, with or without modification,
1912 are permitted in any medium without royalty provided the copyright
1913 notice and this notice are preserved.
1914
1915 Local Variables:
1916 mode: change-log
1917 left-margin: 8
1918 fill-column: 74
1919 version-control: never
1920 End: