opcodes/ChangeLog

   1 2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
   2             David Faust <david.faust@oracle.com>
   3
   4         * bpf-desc.c: Regenerate.
   5         * bpf-opc.h: Likewise.
   6         * bpf-opc.c: Likewise.
   7         * bpf-dis.c: Likewise.
   8
   9 2020-05-28  Alan Modra  <amodra@gmail.com>
  10
  11         * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
  12         values.
  13
  14 2020-05-28  Alan Modra  <amodra@gmail.com>
  15
  16         * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
  17         immediates.
  18         (print_insn_ns32k): Revert last change.
  19
  20 2020-05-28  Nick Clifton  <nickc@redhat.com>
  21
  22         * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
  23         static.
  24
  25 2020-05-26  Sandra Loosemore  <sandra@codesourcery.com>
  26
  27         Fix extraction of signed constants in nios2 disassembler (again).
  28
  29         * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
  30         extractions of signed fields.
  31
  32 2020-05-26  Stefan Schulze Frielinghaus  <stefansf@linux.ibm.com>
  33
  34         * s390-opc.txt: Relocate vector load/store instructions with
  35         additional alignment parameter and change architecture level
  36         constraint from z14 to z13.
  37
  38 2020-05-21  Alan Modra  <amodra@gmail.com>
  39
  40         * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
  41         * sparc-dis.c: Likewise.
  42         * tic4x-dis.c: Likewise.
  43         * xtensa-dis.c: Likewise.
  44         * bpf-desc.c: Regenerate.
  45         * epiphany-desc.c: Regenerate.
  46         * fr30-desc.c: Regenerate.
  47         * frv-desc.c: Regenerate.
  48         * ip2k-desc.c: Regenerate.
  49         * iq2000-desc.c: Regenerate.
  50         * lm32-desc.c: Regenerate.
  51         * m32c-desc.c: Regenerate.
  52         * m32r-desc.c: Regenerate.
  53         * mep-asm.c: Regenerate.
  54         * mep-desc.c: Regenerate.
  55         * mt-desc.c: Regenerate.
  56         * or1k-desc.c: Regenerate.
  57         * xc16x-desc.c: Regenerate.
  58         * xstormy16-desc.c: Regenerate.
  59
  60 2020-05-20  Nelson Chu  <nelson.chu@sifive.com>
  61
  62         * riscv-opc.c (riscv_ext_version_table): The table used to store
  63         all information about the supported spec and the corresponding ISA
  64         versions.  Currently, only Zicsr is supported to verify the
  65         correctness of Z sub extension settings.  Others will be supported
  66         in the future patches.
  67         (struct isa_spec_t, isa_specs): List for all supported ISA spec
  68         classes and the corresponding strings.
  69         (riscv_get_isa_spec_class): New function.  Get the corresponding ISA
  70         spec class by giving a ISA spec string.
  71         * riscv-opc.c (struct priv_spec_t): New structure.
  72         (struct priv_spec_t priv_specs): List for all supported privilege spec
  73         classes and the corresponding strings.
  74         (riscv_get_priv_spec_class): New function.  Get the corresponding
  75         privilege spec class by giving a spec string.
  76         (riscv_get_priv_spec_name): New function.  Get the corresponding
  77         privilege spec string by giving a CSR version class.
  78         * riscv-dis.c: Updated since DECLARE_CSR is changed.
  79         * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
  80         according to the chosen version.  Build a hash table riscv_csr_hash to
  81         store the valid CSR for the chosen pirv verison.  Dump the direct
  82         CSR address rather than it's name if it is invalid.
  83         (parse_riscv_dis_option_without_args): New function.  Parse the options
  84         without arguments.
  85         (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
  86         parse the options without arguments first, and then handle the options
  87         with arguments.  Add the new option -Mpriv-spec, which has argument.
  88         * riscv-dis.c (print_riscv_disassembler_options): Add description
  89         about the new OBJDUMP option.
  90
  91 2020-05-19  Peter Bergner  <bergner@linux.ibm.com>
  92
  93         * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
  94         WC values on POWER10 sync, dcbf  and wait instructions.
  95         (insert_pl, extract_pl): New functions.
  96         (L2OPT, LS, WC): Use insert_ls and extract_ls.
  97         (LS3): New , 3-bit L for sync.
  98         (LS3, L3OPT): New, 3-bit L for sync and dcbf.
  99         (SC2, PL): New, 2-bit SC and PL for sync and wait.
 100         (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
 101         (XOPL3, XWCPL, XSYNCLS): New opcode macros.
 102         (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
 103         plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
 104         <wait>: Enable PL operand on POWER10.
 105         <dcbf>: Enable L3OPT operand on POWER10.
 106         <sync>: Enable SC2 operand on POWER10.
 107
 108 2020-05-19  Stafford Horne  <shorne@gmail.com>
 109
 110         PR 25184
 111         * or1k-asm.c: Regenerate.
 112         * or1k-desc.c: Regenerate.
 113         * or1k-desc.h: Regenerate.
 114         * or1k-dis.c: Regenerate.
 115         * or1k-ibld.c: Regenerate.
 116         * or1k-opc.c: Regenerate.
 117         * or1k-opc.h: Regenerate.
 118         * or1k-opinst.c: Regenerate.
 119
 120 2020-05-11  Alan Modra  <amodra@gmail.com>
 121
 122         * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
 123         xsmaxcqp, xsmincqp.
 124
 125 2020-05-11  Alan Modra  <amodra@gmail.com>
 126
 127         * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
 128         stxvrbx, stxvrhx, stxvrwx, stxvrdx.
 129
 130 2020-05-11  Alan Modra  <amodra@gmail.com>
 131
 132         * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
 133
 134 2020-05-11  Alan Modra  <amodra@gmail.com>
 135
 136         * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
 137         vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
 138
 139 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 140
 141         * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
 142         mnemonics.
 143
 144 2020-05-11  Alan Modra  <amodra@gmail.com>
 145
 146         * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
 147         (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
 148         vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
 149         (prefix_opcodes): Add xxeval.
 150
 151 2020-05-11  Alan Modra  <amodra@gmail.com>
 152
 153         * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
 154         xxgenpcvwm, xxgenpcvdm.
 155
 156 2020-05-11  Alan Modra  <amodra@gmail.com>
 157
 158         * ppc-opc.c (MP, VXVAM_MASK): Define.
 159         (VXVAPS_MASK): Use VXVA_MASK.
 160         (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
 161         vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
 162         vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
 163         vcntmbb, vcntmbh, vcntmbw, vcntmbd.
 164
 165 2020-05-11  Alan Modra  <amodra@gmail.com>
 166             Peter Bergner  <bergner@linux.ibm.com>
 167
 168         * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
 169         New functions.
 170         (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
 171         YMSK2, XA6a, XA6ap, XB6a entries.
 172         (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
 173         (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
 174         (PPCVSX4): Define.
 175         (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
 176         xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
 177         xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
 178         xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
 179         xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
 180         xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
 181         xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
 182         (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
 183         pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
 184         pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
 185         pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
 186         pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
 187         pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
 188         pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
 189
 190 2020-05-11  Alan Modra  <amodra@gmail.com>
 191
 192         * ppc-opc.c (insert_imm32, extract_imm32): New functions.
 193         (insert_xts, extract_xts): New functions.
 194         (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
 195         (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
 196         (VXRC_MASK, VXSH_MASK): Define.
 197         (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
 198         vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
 199         vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
 200         vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
 201         vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
 202         (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
 203         xxblendvh, xxblendvw, xxblendvd, xxpermx.
 204
 205 2020-05-11  Alan Modra  <amodra@gmail.com>
 206
 207         * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
 208         vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
 209         vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
 210         vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
 211         xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
 212
 213 2020-05-11  Alan Modra  <amodra@gmail.com>
 214
 215         * ppc-opc.c (insert_xtp, extract_xtp): New functions.
 216         (XTP, DQXP, DQXP_MASK): Define.
 217         (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
 218         (prefix_opcodes): Add plxvp and pstxvp.
 219
 220 2020-05-11  Alan Modra  <amodra@gmail.com>
 221
 222         * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
 223         vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
 224         vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
 225
 226 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 227
 228         * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
 229
 230 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 231
 232         * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
 233         (L1OPT): Define.
 234         (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
 235
 236 2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
 237
 238         * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
 239
 240 2020-05-11  Alan Modra  <amodra@gmail.com>
 241
 242         * ppc-dis.c (powerpc_init_dialect): Default to "power10".
 243
 244 2020-05-11  Alan Modra  <amodra@gmail.com>
 245
 246         * ppc-dis.c (ppc_opts): Add "power10" entry.
 247         (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
 248         * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
 249
 250 2020-05-11  Nick Clifton  <nickc@redhat.com>
 251
 252         * po/fr.po: Updated French translation.
 253
 254 2020-04-30  Alex Coplan  <alex.coplan@arm.com>
 255
 256         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
 257         * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
 258         (operand_general_constraint_met_p): validate
 259         AARCH64_OPND_UNDEFINED.
 260         * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
 261         for FLD_imm16_2.
 262         * aarch64-asm-2.c: Regenerated.
 263         * aarch64-dis-2.c: Regenerated.
 264         * aarch64-opc-2.c: Regenerated.
 265
 266 2020-04-29  Nick Clifton  <nickc@redhat.com>
 267
 268         PR 22699
 269         * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
 270         and SETRC insns.
 271
 272 2020-04-29  Nick Clifton  <nickc@redhat.com>
 273
 274         * po/sv.po: Updated Swedish translation.
 275
 276 2020-04-29  Nick Clifton  <nickc@redhat.com>
 277
 278         PR 22699
 279         * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
 280         IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
 281         * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
 282         IMM0_8U case.
 283
 284 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 285
 286         PR 25848
 287         * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
 288         cmpi only on m68020up and cpu32.
 289
 290 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 291
 292         * aarch64-asm.c (aarch64_ins_none): New.
 293         * aarch64-asm.h (ins_none): New declaration.
 294         * aarch64-dis.c (aarch64_ext_none): New.
 295         * aarch64-dis.h (ext_none): New declaration.
 296         * aarch64-opc.c (aarch64_print_operand): Update case for
 297         AARCH64_OPND_BARRIER_PSB.
 298         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
 299         (AARCH64_OPERANDS): Update inserter/extracter for
 300         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
 301         * aarch64-asm-2.c: Regenerated.
 302         * aarch64-dis-2.c: Regenerated.
 303         * aarch64-opc-2.c: Regenerated.
 304
 305 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
 306
 307         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
 308         (aarch64_feature_ras, RAS): Likewise.
 309         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
 310         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
 311         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
 312         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
 313         * aarch64-asm-2.c: Regenerated.
 314         * aarch64-dis-2.c: Regenerated.
 315         * aarch64-opc-2.c: Regenerated.
 316
 317 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
 318
 319         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
 320         (print_insn_neon): Support disassembly of conditional
 321         instructions.
 322
 323 2020-02-16  David Faust  <david.faust@oracle.com>
 324
 325         * bpf-desc.c: Regenerate.
 326         * bpf-desc.h: Likewise.
 327         * bpf-opc.c: Regenerate.
 328         * bpf-opc.h: Likewise.
 329
 330 2020-04-07  Lili Cui  <lili.cui@intel.com>
 331
 332         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
 333         (prefix_table): New instructions (see prefixes above).
 334         (rm_table): Likewise
 335         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
 336         CPU_ANY_TSXLDTRK_FLAGS.
 337         (cpu_flags): Add CpuTSXLDTRK.
 338         * i386-opc.h (enum): Add CpuTSXLDTRK.
 339         (i386_cpu_flags): Add cputsxldtrk.
 340         * i386-opc.tbl: Add XSUSPLDTRK insns.
 341         * i386-init.h: Regenerate.
 342         * i386-tbl.h: Likewise.
 343
 344 2020-04-02  Lili Cui  <lili.cui@intel.com>
 345
 346         * i386-dis.c (prefix_table): New instructions serialize.
 347         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
 348         CPU_ANY_SERIALIZE_FLAGS.
 349         (cpu_flags): Add CpuSERIALIZE.
 350         * i386-opc.h (enum): Add CpuSERIALIZE.
 351         (i386_cpu_flags): Add cpuserialize.
 352         * i386-opc.tbl: Add SERIALIZE insns.
 353         * i386-init.h: Regenerate.
 354         * i386-tbl.h: Likewise.
 355
 356 2020-03-26  Alan Modra  <amodra@gmail.com>
 357
 358         * disassemble.h (opcodes_assert): Declare.
 359         (OPCODES_ASSERT): Define.
 360         * disassemble.c: Don't include assert.h.  Include opintl.h.
 361         (opcodes_assert): New function.
 362         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
 363         (bfd_h8_disassemble): Reduce size of data array.  Correctly
 364         calculate maxlen.  Omit insn decoding when insn length exceeds
 365         maxlen.  Exit from nibble loop when looking for E, before
 366         accessing next data byte.  Move processing of E outside loop.
 367         Replace tests of maxlen in loop with assertions.
 368
 369 2020-03-26  Alan Modra  <amodra@gmail.com>
 370
 371         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
 372
 373 2020-03-25  Alan Modra  <amodra@gmail.com>
 374
 375         * z80-dis.c (suffix): Init mybuf.
 376
 377 2020-03-22  Alan Modra  <amodra@gmail.com>
 378
 379         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
 380         successflly read from section.
 381
 382 2020-03-22  Alan Modra  <amodra@gmail.com>
 383
 384         * arc-dis.c (find_format): Use ISO C string concatenation rather
 385         than line continuation within a string.  Don't access needs_limm
 386         before testing opcode != NULL.
 387
 388 2020-03-22  Alan Modra  <amodra@gmail.com>
 389
 390         * ns32k-dis.c (print_insn_arg): Update comment.
 391         (print_insn_ns32k): Reduce size of index_offset array, and
 392         initialize, passing -1 to print_insn_arg for args that are not
 393         an index.  Don't exit arg loop early.  Abort on bad arg number.
 394
 395 2020-03-22  Alan Modra  <amodra@gmail.com>
 396
 397         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 398         * s12z-opc.c: Formatting.
 399         (operands_f): Return an int.
 400         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 401         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 402         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 403         (exg_sex_discrim): Likewise.
 404         (create_immediate_operand, create_bitfield_operand),
 405         (create_register_operand_with_size, create_register_all_operand),
 406         (create_register_all16_operand, create_simple_memory_operand),
 407         (create_memory_operand, create_memory_auto_operand): Don't
 408         segfault on malloc failure.
 409         (z_ext24_decode): Return an int status, negative on fail, zero
 410         on success.
 411         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 412         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 413         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 414         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 415         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 416         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 417         (loop_primitive_decode, shift_decode, psh_pul_decode),
 418         (bit_field_decode): Similarly.
 419         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 420         to return value, update callers.
 421         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 422         Don't segfault on NULL operand.
 423         (decode_operation): Return OP_INVALID on first fail.
 424         (decode_s12z): Check all reads, returning -1 on fail.
 425
 426 2020-03-20  Alan Modra  <amodra@gmail.com>
 427
 428         * metag-dis.c (print_insn_metag): Don't ignore status from
 429         read_memory_func.
 430
 431 2020-03-20  Alan Modra  <amodra@gmail.com>
 432
 433         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 434         Initialize parts of buffer not written when handling a possible
 435         2-byte insn at end of section.  Don't attempt decoding of such
 436         an insn by the 4-byte machinery.
 437
 438 2020-03-20  Alan Modra  <amodra@gmail.com>
 439
 440         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 441         partially filled buffer.  Prevent lookup of 4-byte insns when
 442         only VLE 2-byte insns are possible due to section size.  Print
 443         ".word" rather than ".long" for 2-byte leftovers.
 444
 445 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 446
 447         PR 25641
 448         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 449
 450 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 451
 452         * i386-dis.c (X86_64_0D): Rename to ...
 453         (X86_64_0E): ... this.
 454
 455 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 456
 457         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 458         * Makefile.in: Regenerated.
 459
 460 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 461
 462         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 463         3-operand pseudos.
 464         * i386-tbl.h: Re-generate.
 465
 466 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 467
 468         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 469         vprot*, vpsha*, and vpshl*.
 470         * i386-tbl.h: Re-generate.
 471
 472 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 473
 474         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 475         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 476         * i386-tbl.h: Re-generate.
 477
 478 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 479
 480         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 481         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 482         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 483         * i386-tbl.h: Re-generate.
 484
 485 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 486
 487         * i386-gen.c (struct template_arg, struct template_instance,
 488         struct template_param, struct template, templates,
 489         parse_template, expand_templates): New.
 490         (process_i386_opcodes): Various local variables moved to
 491         expand_templates. Call parse_template and expand_templates.
 492         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 493         * i386-tbl.h: Re-generate.
 494
 495 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 496
 497         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 498         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 499         register and memory source templates. Replace VexW= by VexW*
 500         where applicable.
 501         * i386-tbl.h: Re-generate.
 502
 503 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 504
 505         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 506         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 507         * i386-tbl.h: Re-generate.
 508
 509 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 510
 511         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 512         * i386-tbl.h: Re-generate.
 513
 514 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 515
 516         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 517         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 518         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 519         VexW0 on SSE2AVX variants.
 520         (vmovq): Drop NoRex64 from XMM/XMM variants.
 521         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 522         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 523         applicable use VexW0.
 524         * i386-tbl.h: Re-generate.
 525
 526 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 527
 528         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 529         * i386-opc.h (Rex64): Delete.
 530         (struct i386_opcode_modifier): Remove rex64 field.
 531         * i386-opc.tbl (crc32): Drop Rex64.
 532         Replace Rex64 with Size64 everywhere else.
 533         * i386-tbl.h: Re-generate.
 534
 535 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 536
 537         * i386-dis.c (OP_E_memory): Exclude recording of used address
 538         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 539         addressed memory operands for MPX insns.
 540
 541 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 542
 543         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 544         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 545         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 546         (ptwrite): Split into non-64-bit and 64-bit forms.
 547         * i386-tbl.h: Re-generate.
 548
 549 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 550
 551         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 552         template.
 553         * i386-tbl.h: Re-generate.
 554
 555 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 556
 557         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 558         (prefix_table): Move vmmcall here. Add vmgexit.
 559         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 560         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 561         (cpu_flags): Add CpuSEV_ES entry.
 562         * i386-opc.h (CpuSEV_ES): New.
 563         (union i386_cpu_flags): Add cpusev_es field.
 564         * i386-opc.tbl (vmgexit): New.
 565         * i386-init.h, i386-tbl.h: Re-generate.
 566
 567 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 568
 569         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 570         with MnemonicSize.
 571         * i386-opc.h (IGNORESIZE): New.
 572         (DEFAULTSIZE): Likewise.
 573         (IgnoreSize): Removed.
 574         (DefaultSize): Likewise.
 575         (MnemonicSize): New.
 576         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 577         mnemonicsize.
 578         * i386-opc.tbl (IgnoreSize): New.
 579         (DefaultSize): Likewise.
 580         * i386-tbl.h: Regenerated.
 581
 582 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 583
 584         PR 25627
 585         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 586         instructions.
 587
 588 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 589
 590         PR gas/25622
 591         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 592         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 593         * i386-tbl.h: Regenerated.
 594
 595 2020-02-26  Alan Modra  <amodra@gmail.com>
 596
 597         * aarch64-asm.c: Indent labels correctly.
 598         * aarch64-dis.c: Likewise.
 599         * aarch64-gen.c: Likewise.
 600         * aarch64-opc.c: Likewise.
 601         * alpha-dis.c: Likewise.
 602         * i386-dis.c: Likewise.
 603         * nds32-asm.c: Likewise.
 604         * nfp-dis.c: Likewise.
 605         * visium-dis.c: Likewise.
 606
 607 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 608
 609         * arc-regs.h (int_vector_base): Make it available for all ARC
 610         CPUs.
 611
 612 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 613
 614         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 615         changed.
 616
 617 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 618
 619         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 620         c.mv/c.li if rs1 is zero.
 621
 622 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 623
 624         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 625         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 626         CPU_POPCNT_FLAGS.
 627         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 628         * i386-opc.h (CpuABM): Removed.
 629         (CpuPOPCNT): New.
 630         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 631         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 632         popcnt.  Remove CpuABM from lzcnt.
 633         * i386-init.h: Regenerated.
 634         * i386-tbl.h: Likewise.
 635
 636 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 637
 638         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 639         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 640         VexW1 instead of open-coding them.
 641         * i386-tbl.h: Re-generate.
 642
 643 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 644
 645         * i386-opc.tbl (AddrPrefixOpReg): Define.
 646         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 647         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 648         templates. Drop NoRex64.
 649         * i386-tbl.h: Re-generate.
 650
 651 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 652
 653         PR gas/6518
 654         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 655         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 656         into Intel syntax instance (with Unpsecified) and AT&T one
 657         (without).
 658         (vcvtneps2bf16): Likewise, along with folding the two so far
 659         separate ones.
 660         * i386-tbl.h: Re-generate.
 661
 662 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 663
 664         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 665         CPU_ANY_SSE4A_FLAGS.
 666
 667 2020-02-17  Alan Modra  <amodra@gmail.com>
 668
 669         * i386-gen.c (cpu_flag_init): Correct last change.
 670
 671 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 672
 673         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 674         CPU_ANY_SSE4_FLAGS.
 675
 676 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 677
 678         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 679         (movzx): Likewise.
 680
 681 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 682
 683         PR gas/25438
 684         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 685         destination for Cpu64-only variant.
 686         (movzx): Fold patterns.
 687         * i386-tbl.h: Re-generate.
 688
 689 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 690
 691         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 692         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 693         CPU_ANY_SSE4_FLAGS entry.
 694         * i386-init.h: Re-generate.
 695
 696 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 697
 698         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 699         with Unspecified, making the present one AT&T syntax only.
 700         * i386-tbl.h: Re-generate.
 701
 702 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 703
 704         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 705         * i386-tbl.h: Re-generate.
 706
 707 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 708
 709         PR gas/24546
 710         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 711         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 712         Amd64 and Intel64 templates.
 713         (call, jmp): Likewise for far indirect variants. Dro
 714         Unspecified.
 715         * i386-tbl.h: Re-generate.
 716
 717 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 718
 719         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 720         * i386-opc.h (ShortForm): Delete.
 721         (struct i386_opcode_modifier): Remove shortform field.
 722         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 723         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 724         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 725         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 726         Drop ShortForm.
 727         * i386-tbl.h: Re-generate.
 728
 729 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 730
 731         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 732         fucompi): Drop ShortForm from operand-less templates.
 733         * i386-tbl.h: Re-generate.
 734
 735 2020-02-11  Alan Modra  <amodra@gmail.com>
 736
 737         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 738         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 739         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 740         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 741         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 742
 743 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 744
 745         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 746         (cde_opcodes): Add VCX* instructions.
 747
 748 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 749             Matthew Malcomson  <matthew.malcomson@arm.com>
 750
 751         * arm-dis.c (struct cdeopcode32): New.
 752         (CDE_OPCODE): New macro.
 753         (cde_opcodes): New disassembly table.
 754         (regnames): New option to table.
 755         (cde_coprocs): New global variable.
 756         (print_insn_cde): New
 757         (print_insn_thumb32): Use print_insn_cde.
 758         (parse_arm_disassembler_options): Parse coprocN args.
 759
 760 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 761
 762         PR gas/25516
 763         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 764         with ISA64.
 765         * i386-opc.h (AMD64): Removed.
 766         (Intel64): Likewose.
 767         (AMD64): New.
 768         (INTEL64): Likewise.
 769         (INTEL64ONLY): Likewise.
 770         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 771         * i386-opc.tbl (Amd64): New.
 772         (Intel64): Likewise.
 773         (Intel64Only): Likewise.
 774         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 775         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 776         * i386-tbl.h: Regenerated.
 777
 778 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 779
 780         PR 25469
 781         * z80-dis.c: Add support for GBZ80 opcodes.
 782
 783 2020-02-04  Alan Modra  <amodra@gmail.com>
 784
 785         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 786
 787 2020-02-03  Alan Modra  <amodra@gmail.com>
 788
 789         * m32c-ibld.c: Regenerate.
 790
 791 2020-02-01  Alan Modra  <amodra@gmail.com>
 792
 793         * frv-ibld.c: Regenerate.
 794
 795 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 796
 797         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 798         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 799         (OP_E_memory): Replace xmm_mdq_mode case label by
 800         vex_scalar_w_dq_mode one.
 801         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 802
 803 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 804
 805         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 806         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 807         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 808         (intel_operand_size): Drop vex_w_dq_mode case label.
 809
 810 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 811
 812         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 813         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 814
 815 2020-01-30  Alan Modra  <amodra@gmail.com>
 816
 817         * m32c-ibld.c: Regenerate.
 818
 819 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 820
 821         * bpf-opc.c: Regenerate.
 822
 823 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 824
 825         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 826         (dis386): Use them to replace C2/C3 table entries.
 827         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 828         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 829         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 830         * i386-tbl.h: Re-generate.
 831
 832 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 833
 834         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 835         forms.
 836         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 837         DefaultSize.
 838         * i386-tbl.h: Re-generate.
 839
 840 2020-01-30  Alan Modra  <amodra@gmail.com>
 841
 842         * tic4x-dis.c (tic4x_dp): Make unsigned.
 843
 844 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 845             Jan Beulich  <jbeulich@suse.com>
 846
 847         PR binutils/25445
 848         * i386-dis.c (MOVSXD_Fixup): New function.
 849         (movsxd_mode): New enum.
 850         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 851         (intel_operand_size): Handle movsxd_mode.
 852         (OP_E_register): Likewise.
 853         (OP_G): Likewise.
 854         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 855         register on movsxd.  Add movsxd with 16-bit destination register
 856         for AMD64 and Intel64 ISAs.
 857         * i386-tbl.h: Regenerated.
 858
 859 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 860
 861         PR 25403
 862         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 863         * aarch64-asm-2.c: Regenerate
 864         * aarch64-dis-2.c: Likewise.
 865         * aarch64-opc-2.c: Likewise.
 866
 867 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 868
 869         * i386-opc.tbl (sysret): Drop DefaultSize.
 870         * i386-tbl.h: Re-generate.
 871
 872 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 873
 874         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 875         Dword.
 876         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 877         * i386-tbl.h: Re-generate.
 878
 879 2020-01-20  Nick Clifton  <nickc@redhat.com>
 880
 881         * po/de.po: Updated German translation.
 882         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 883         * po/uk.po: Updated Ukranian translation.
 884
 885 2020-01-20  Alan Modra  <amodra@gmail.com>
 886
 887         * hppa-dis.c (fput_const): Remove useless cast.
 888
 889 2020-01-20  Alan Modra  <amodra@gmail.com>
 890
 891         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 892
 893 2020-01-18  Nick Clifton  <nickc@redhat.com>
 894
 895         * configure: Regenerate.
 896         * po/opcodes.pot: Regenerate.
 897
 898 2020-01-18  Nick Clifton  <nickc@redhat.com>
 899
 900         Binutils 2.34 branch created.
 901
 902 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 903
 904         * opintl.h: Fix spelling error (seperate).
 905
 906 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 907
 908         * i386-opc.tbl: Add {vex} pseudo prefix.
 909         * i386-tbl.h: Regenerated.
 910
 911 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 912
 913         PR 25376
 914         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 915         (neon_opcodes): Likewise.
 916         (select_arm_features): Make sure we enable MVE bits when selecting
 917         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 918         any architecture.
 919
 920 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 921
 922         * i386-opc.tbl: Drop stale comment from XOP section.
 923
 924 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 925
 926         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 927         (extractps): Add VexWIG to SSE2AVX forms.
 928         * i386-tbl.h: Re-generate.
 929
 930 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 931
 932         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 933         Size64 from and use VexW1 on SSE2AVX forms.
 934         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 935         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 936         * i386-tbl.h: Re-generate.
 937
 938 2020-01-15  Alan Modra  <amodra@gmail.com>
 939
 940         * tic4x-dis.c (tic4x_version): Make unsigned long.
 941         (optab, optab_special, registernames): New file scope vars.
 942         (tic4x_print_register): Set up registernames rather than
 943         malloc'd registertable.
 944         (tic4x_disassemble): Delete optable and optable_special.  Use
 945         optab and optab_special instead.  Throw away old optab,
 946         optab_special and registernames when info->mach changes.
 947
 948 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 949
 950         PR 25377
 951         * z80-dis.c (suffix): Use .db instruction to generate double
 952         prefix.
 953
 954 2020-01-14  Alan Modra  <amodra@gmail.com>
 955
 956         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 957         values to unsigned before shifting.
 958
 959 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 960
 961         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 962         flow instructions.
 963         (print_insn_thumb16, print_insn_thumb32): Likewise.
 964         (print_insn): Initialize the insn info.
 965         * i386-dis.c (print_insn): Initialize the insn info fields, and
 966         detect jumps.
 967
 968 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 969
 970         * arc-opc.c (C_NE): Make it required.
 971
 972 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 973
 974         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 975         reserved register name.
 976
 977 2020-01-13  Alan Modra  <amodra@gmail.com>
 978
 979         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 980         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 981
 982 2020-01-13  Alan Modra  <amodra@gmail.com>
 983
 984         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 985         result of wasm_read_leb128 in a uint64_t and check that bits
 986         are not lost when copying to other locals.  Use uint32_t for
 987         most locals.  Use PRId64 when printing int64_t.
 988
 989 2020-01-13  Alan Modra  <amodra@gmail.com>
 990
 991         * score-dis.c: Formatting.
 992         * score7-dis.c: Formatting.
 993
 994 2020-01-13  Alan Modra  <amodra@gmail.com>
 995
 996         * score-dis.c (print_insn_score48): Use unsigned variables for
 997         unsigned values.  Don't left shift negative values.
 998         (print_insn_score32): Likewise.
 999         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1000
1001 2020-01-13  Alan Modra  <amodra@gmail.com>
1002
1003         * tic4x-dis.c (tic4x_print_register): Remove dead code.
1004
1005 2020-01-13  Alan Modra  <amodra@gmail.com>
1006
1007         * fr30-ibld.c: Regenerate.
1008
1009 2020-01-13  Alan Modra  <amodra@gmail.com>
1010
1011         * xgate-dis.c (print_insn): Don't left shift signed value.
1012         (ripBits): Formatting, use 1u.
1013
1014 2020-01-10  Alan Modra  <amodra@gmail.com>
1015
1016         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1017         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
1018
1019 2020-01-10  Alan Modra  <amodra@gmail.com>
1020
1021         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1022         and XRREG value earlier to avoid a shift with negative exponent.
1023         * m10200-dis.c (disassemble): Similarly.
1024
1025 2020-01-09  Nick Clifton  <nickc@redhat.com>
1026
1027         PR 25224
1028         * z80-dis.c (ld_ii_ii): Use correct cast.
1029
1030 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
1031
1032         PR 25224
1033         * z80-dis.c (ld_ii_ii): Use character constant when checking
1034         opcode byte value.
1035
1036 2020-01-09  Jan Beulich  <jbeulich@suse.com>
1037
1038         * i386-dis.c (SEP_Fixup): New.
1039         (SEP): Define.
1040         (dis386_twobyte): Use it for sysenter/sysexit.
1041         (enum x86_64_isa): Change amd64 enumerator to value 1.
1042         (OP_J): Compare isa64 against intel64 instead of amd64.
1043         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1044         forms.
1045         * i386-tbl.h: Re-generate.
1046
1047 2020-01-08  Alan Modra  <amodra@gmail.com>
1048
1049         * z8k-dis.c: Include libiberty.h
1050         (instr_data_s): Make max_fetched unsigned.
1051         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1052         Don't exceed byte_info bounds.
1053         (output_instr): Make num_bytes unsigned.
1054         (unpack_instr): Likewise for nibl_count and loop.
1055         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1056         idx unsigned.
1057         * z8k-opc.h: Regenerate.
1058
1059 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
1060
1061         * arc-tbl.h (llock): Use 'LLOCK' as class.
1062         (llockd): Likewise.
1063         (scond): Use 'SCOND' as class.
1064         (scondd): Likewise.
1065         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1066         (scondd): Likewise.
1067
1068 2020-01-06  Alan Modra  <amodra@gmail.com>
1069
1070         * m32c-ibld.c: Regenerate.
1071
1072 2020-01-06  Alan Modra  <amodra@gmail.com>
1073
1074         PR 25344
1075         * z80-dis.c (suffix): Don't use a local struct buffer copy.
1076         Peek at next byte to prevent recursion on repeated prefix bytes.
1077         Ensure uninitialised "mybuf" is not accessed.
1078         (print_insn_z80): Don't zero n_fetch and n_used here,..
1079         (print_insn_z80_buf): ..do it here instead.
1080
1081 2020-01-04  Alan Modra  <amodra@gmail.com>
1082
1083         * m32r-ibld.c: Regenerate.
1084
1085 2020-01-04  Alan Modra  <amodra@gmail.com>
1086
1087         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1088
1089 2020-01-04  Alan Modra  <amodra@gmail.com>
1090
1091         * crx-dis.c (match_opcode): Avoid shift left of signed value.
1092
1093 2020-01-04  Alan Modra  <amodra@gmail.com>
1094
1095         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1096
1097 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1098
1099         * aarch64-tbl.h (aarch64_opcode_table): Use
1100         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1101
1102 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1103
1104         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
1105         forms of SUDOT and USDOT.
1106
1107 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1108
1109         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
1110         uzip{1,2}.
1111         * opcodes/aarch64-dis-2.c: Re-generate.
1112
1113 2020-01-03  Jan Beulich  <jbeulich@suse.com>
1114
1115         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
1116         FMMLA encoding.
1117         * opcodes/aarch64-dis-2.c: Re-generate.
1118
1119 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
1120
1121         * z80-dis.c: Add support for eZ80 and Z80 instructions.
1122
1123 2020-01-01  Alan Modra  <amodra@gmail.com>
1124
1125         Update year range in copyright notice of all files.
1126
1127 For older changes see ChangeLog-2019
1128 \f
1129 Copyright (C) 2020 Free Software Foundation, Inc.
1130
1131 Copying and distribution of this file, with or without modification,
1132 are permitted in any medium without royalty provided the copyright
1133 notice and this notice are preserved.
1134
1135 Local Variables:
1136 mode: change-log
1137 left-margin: 8
1138 fill-column: 74
1139 version-control: never
1140 End: