opcodes/ChangeLog

   1 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
   2
   3         * aarch64-asm.c (aarch64_ins_none): New.
   4         * aarch64-asm.h (ins_none): New declaration.
   5         * aarch64-dis.c (aarch64_ext_none): New.
   6         * aarch64-dis.h (ext_none): New declaration.
   7         * aarch64-opc.c (aarch64_print_operand): Update case for
   8         AARCH64_OPND_BARRIER_PSB.
   9         * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
  10         (AARCH64_OPERANDS): Update inserter/extracter for
  11         AARCH64_OPND_BARRIER_PSB to use new dummy functions.
  12         * aarch64-asm-2.c: Regenerated.
  13         * aarch64-dis-2.c: Regenerated.
  14         * aarch64-opc-2.c: Regenerated.
  15
  16 2020-04-20  Sudakshina Das  <sudi.das@arm.com>
  17
  18         * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
  19         (aarch64_feature_ras, RAS): Likewise.
  20         (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
  21         (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
  22         autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
  23         autiaz, autiasp, autibz, autibsp to be CORE_INSN.
  24         * aarch64-asm-2.c: Regenerated.
  25         * aarch64-dis-2.c: Regenerated.
  26         * aarch64-opc-2.c: Regenerated.
  27
  28 2020-04-17  Fredrik Strupe  <fredrik@strupe.net>
  29
  30         * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
  31         (print_insn_neon): Support disassembly of conditional
  32         instructions.
  33
  34 2020-02-16  David Faust  <david.faust@oracle.com>
  35
  36         * bpf-desc.c: Regenerate.
  37         * bpf-desc.h: Likewise.
  38         * bpf-opc.c: Regenerate.
  39         * bpf-opc.h: Likewise.
  40
  41 2020-04-07  Lili Cui  <lili.cui@intel.com>
  42
  43         * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
  44         (prefix_table): New instructions (see prefixes above).
  45         (rm_table): Likewise
  46         * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
  47         CPU_ANY_TSXLDTRK_FLAGS.
  48         (cpu_flags): Add CpuTSXLDTRK.
  49         * i386-opc.h (enum): Add CpuTSXLDTRK.
  50         (i386_cpu_flags): Add cputsxldtrk.
  51         * i386-opc.tbl: Add XSUSPLDTRK insns.
  52         * i386-init.h: Regenerate.
  53         * i386-tbl.h: Likewise.
  54
  55 2020-04-02  Lili Cui  <lili.cui@intel.com>
  56
  57         * i386-dis.c (prefix_table): New instructions serialize.
  58         * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
  59         CPU_ANY_SERIALIZE_FLAGS.
  60         (cpu_flags): Add CpuSERIALIZE.
  61         * i386-opc.h (enum): Add CpuSERIALIZE.
  62         (i386_cpu_flags): Add cpuserialize.
  63         * i386-opc.tbl: Add SERIALIZE insns.
  64         * i386-init.h: Regenerate.
  65         * i386-tbl.h: Likewise.
  66
  67 2020-03-26  Alan Modra  <amodra@gmail.com>
  68
  69         * disassemble.h (opcodes_assert): Declare.
  70         (OPCODES_ASSERT): Define.
  71         * disassemble.c: Don't include assert.h.  Include opintl.h.
  72         (opcodes_assert): New function.
  73         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
  74         (bfd_h8_disassemble): Reduce size of data array.  Correctly
  75         calculate maxlen.  Omit insn decoding when insn length exceeds
  76         maxlen.  Exit from nibble loop when looking for E, before
  77         accessing next data byte.  Move processing of E outside loop.
  78         Replace tests of maxlen in loop with assertions.
  79
  80 2020-03-26  Alan Modra  <amodra@gmail.com>
  81
  82         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
  83
  84 2020-03-25  Alan Modra  <amodra@gmail.com>
  85
  86         * z80-dis.c (suffix): Init mybuf.
  87
  88 2020-03-22  Alan Modra  <amodra@gmail.com>
  89
  90         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
  91         successflly read from section.
  92
  93 2020-03-22  Alan Modra  <amodra@gmail.com>
  94
  95         * arc-dis.c (find_format): Use ISO C string concatenation rather
  96         than line continuation within a string.  Don't access needs_limm
  97         before testing opcode != NULL.
  98
  99 2020-03-22  Alan Modra  <amodra@gmail.com>
 100
 101         * ns32k-dis.c (print_insn_arg): Update comment.
 102         (print_insn_ns32k): Reduce size of index_offset array, and
 103         initialize, passing -1 to print_insn_arg for args that are not
 104         an index.  Don't exit arg loop early.  Abort on bad arg number.
 105
 106 2020-03-22  Alan Modra  <amodra@gmail.com>
 107
 108         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
 109         * s12z-opc.c: Formatting.
 110         (operands_f): Return an int.
 111         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
 112         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
 113         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
 114         (exg_sex_discrim): Likewise.
 115         (create_immediate_operand, create_bitfield_operand),
 116         (create_register_operand_with_size, create_register_all_operand),
 117         (create_register_all16_operand, create_simple_memory_operand),
 118         (create_memory_operand, create_memory_auto_operand): Don't
 119         segfault on malloc failure.
 120         (z_ext24_decode): Return an int status, negative on fail, zero
 121         on success.
 122         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
 123         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
 124         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
 125         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
 126         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
 127         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
 128         (loop_primitive_decode, shift_decode, psh_pul_decode),
 129         (bit_field_decode): Similarly.
 130         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
 131         to return value, update callers.
 132         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
 133         Don't segfault on NULL operand.
 134         (decode_operation): Return OP_INVALID on first fail.
 135         (decode_s12z): Check all reads, returning -1 on fail.
 136
 137 2020-03-20  Alan Modra  <amodra@gmail.com>
 138
 139         * metag-dis.c (print_insn_metag): Don't ignore status from
 140         read_memory_func.
 141
 142 2020-03-20  Alan Modra  <amodra@gmail.com>
 143
 144         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
 145         Initialize parts of buffer not written when handling a possible
 146         2-byte insn at end of section.  Don't attempt decoding of such
 147         an insn by the 4-byte machinery.
 148
 149 2020-03-20  Alan Modra  <amodra@gmail.com>
 150
 151         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
 152         partially filled buffer.  Prevent lookup of 4-byte insns when
 153         only VLE 2-byte insns are possible due to section size.  Print
 154         ".word" rather than ".long" for 2-byte leftovers.
 155
 156 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
 157
 158         PR 25641
 159         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
 160
 161 2020-03-13  Jan Beulich  <jbeulich@suse.com>
 162
 163         * i386-dis.c (X86_64_0D): Rename to ...
 164         (X86_64_0E): ... this.
 165
 166 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 167
 168         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 169         * Makefile.in: Regenerated.
 170
 171 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 172
 173         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 174         3-operand pseudos.
 175         * i386-tbl.h: Re-generate.
 176
 177 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 178
 179         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 180         vprot*, vpsha*, and vpshl*.
 181         * i386-tbl.h: Re-generate.
 182
 183 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 184
 185         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 186         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 187         * i386-tbl.h: Re-generate.
 188
 189 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 190
 191         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 192         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 193         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 194         * i386-tbl.h: Re-generate.
 195
 196 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 197
 198         * i386-gen.c (struct template_arg, struct template_instance,
 199         struct template_param, struct template, templates,
 200         parse_template, expand_templates): New.
 201         (process_i386_opcodes): Various local variables moved to
 202         expand_templates. Call parse_template and expand_templates.
 203         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 204         * i386-tbl.h: Re-generate.
 205
 206 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 207
 208         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 209         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 210         register and memory source templates. Replace VexW= by VexW*
 211         where applicable.
 212         * i386-tbl.h: Re-generate.
 213
 214 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 215
 216         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 217         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 218         * i386-tbl.h: Re-generate.
 219
 220 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 221
 222         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 223         * i386-tbl.h: Re-generate.
 224
 225 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 226
 227         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 228         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 229         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 230         VexW0 on SSE2AVX variants.
 231         (vmovq): Drop NoRex64 from XMM/XMM variants.
 232         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 233         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 234         applicable use VexW0.
 235         * i386-tbl.h: Re-generate.
 236
 237 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 238
 239         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 240         * i386-opc.h (Rex64): Delete.
 241         (struct i386_opcode_modifier): Remove rex64 field.
 242         * i386-opc.tbl (crc32): Drop Rex64.
 243         Replace Rex64 with Size64 everywhere else.
 244         * i386-tbl.h: Re-generate.
 245
 246 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 247
 248         * i386-dis.c (OP_E_memory): Exclude recording of used address
 249         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 250         addressed memory operands for MPX insns.
 251
 252 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 253
 254         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 255         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 256         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 257         (ptwrite): Split into non-64-bit and 64-bit forms.
 258         * i386-tbl.h: Re-generate.
 259
 260 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 261
 262         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 263         template.
 264         * i386-tbl.h: Re-generate.
 265
 266 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 267
 268         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 269         (prefix_table): Move vmmcall here. Add vmgexit.
 270         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 271         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 272         (cpu_flags): Add CpuSEV_ES entry.
 273         * i386-opc.h (CpuSEV_ES): New.
 274         (union i386_cpu_flags): Add cpusev_es field.
 275         * i386-opc.tbl (vmgexit): New.
 276         * i386-init.h, i386-tbl.h: Re-generate.
 277
 278 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 279
 280         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 281         with MnemonicSize.
 282         * i386-opc.h (IGNORESIZE): New.
 283         (DEFAULTSIZE): Likewise.
 284         (IgnoreSize): Removed.
 285         (DefaultSize): Likewise.
 286         (MnemonicSize): New.
 287         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 288         mnemonicsize.
 289         * i386-opc.tbl (IgnoreSize): New.
 290         (DefaultSize): Likewise.
 291         * i386-tbl.h: Regenerated.
 292
 293 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 294
 295         PR 25627
 296         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 297         instructions.
 298
 299 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 300
 301         PR gas/25622
 302         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 303         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 304         * i386-tbl.h: Regenerated.
 305
 306 2020-02-26  Alan Modra  <amodra@gmail.com>
 307
 308         * aarch64-asm.c: Indent labels correctly.
 309         * aarch64-dis.c: Likewise.
 310         * aarch64-gen.c: Likewise.
 311         * aarch64-opc.c: Likewise.
 312         * alpha-dis.c: Likewise.
 313         * i386-dis.c: Likewise.
 314         * nds32-asm.c: Likewise.
 315         * nfp-dis.c: Likewise.
 316         * visium-dis.c: Likewise.
 317
 318 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 319
 320         * arc-regs.h (int_vector_base): Make it available for all ARC
 321         CPUs.
 322
 323 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 324
 325         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 326         changed.
 327
 328 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 329
 330         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 331         c.mv/c.li if rs1 is zero.
 332
 333 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 334
 335         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 336         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 337         CPU_POPCNT_FLAGS.
 338         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 339         * i386-opc.h (CpuABM): Removed.
 340         (CpuPOPCNT): New.
 341         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 342         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 343         popcnt.  Remove CpuABM from lzcnt.
 344         * i386-init.h: Regenerated.
 345         * i386-tbl.h: Likewise.
 346
 347 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 348
 349         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 350         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 351         VexW1 instead of open-coding them.
 352         * i386-tbl.h: Re-generate.
 353
 354 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 355
 356         * i386-opc.tbl (AddrPrefixOpReg): Define.
 357         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 358         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 359         templates. Drop NoRex64.
 360         * i386-tbl.h: Re-generate.
 361
 362 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 363
 364         PR gas/6518
 365         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 366         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 367         into Intel syntax instance (with Unpsecified) and AT&T one
 368         (without).
 369         (vcvtneps2bf16): Likewise, along with folding the two so far
 370         separate ones.
 371         * i386-tbl.h: Re-generate.
 372
 373 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 374
 375         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 376         CPU_ANY_SSE4A_FLAGS.
 377
 378 2020-02-17  Alan Modra  <amodra@gmail.com>
 379
 380         * i386-gen.c (cpu_flag_init): Correct last change.
 381
 382 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 383
 384         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 385         CPU_ANY_SSE4_FLAGS.
 386
 387 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 388
 389         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 390         (movzx): Likewise.
 391
 392 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 393
 394         PR gas/25438
 395         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 396         destination for Cpu64-only variant.
 397         (movzx): Fold patterns.
 398         * i386-tbl.h: Re-generate.
 399
 400 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 401
 402         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 403         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 404         CPU_ANY_SSE4_FLAGS entry.
 405         * i386-init.h: Re-generate.
 406
 407 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 408
 409         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 410         with Unspecified, making the present one AT&T syntax only.
 411         * i386-tbl.h: Re-generate.
 412
 413 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 414
 415         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 416         * i386-tbl.h: Re-generate.
 417
 418 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 419
 420         PR gas/24546
 421         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 422         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 423         Amd64 and Intel64 templates.
 424         (call, jmp): Likewise for far indirect variants. Dro
 425         Unspecified.
 426         * i386-tbl.h: Re-generate.
 427
 428 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 429
 430         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 431         * i386-opc.h (ShortForm): Delete.
 432         (struct i386_opcode_modifier): Remove shortform field.
 433         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 434         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 435         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 436         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 437         Drop ShortForm.
 438         * i386-tbl.h: Re-generate.
 439
 440 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 441
 442         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 443         fucompi): Drop ShortForm from operand-less templates.
 444         * i386-tbl.h: Re-generate.
 445
 446 2020-02-11  Alan Modra  <amodra@gmail.com>
 447
 448         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 449         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 450         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 451         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 452         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 453
 454 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 455
 456         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 457         (cde_opcodes): Add VCX* instructions.
 458
 459 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 460             Matthew Malcomson  <matthew.malcomson@arm.com>
 461
 462         * arm-dis.c (struct cdeopcode32): New.
 463         (CDE_OPCODE): New macro.
 464         (cde_opcodes): New disassembly table.
 465         (regnames): New option to table.
 466         (cde_coprocs): New global variable.
 467         (print_insn_cde): New
 468         (print_insn_thumb32): Use print_insn_cde.
 469         (parse_arm_disassembler_options): Parse coprocN args.
 470
 471 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 472
 473         PR gas/25516
 474         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 475         with ISA64.
 476         * i386-opc.h (AMD64): Removed.
 477         (Intel64): Likewose.
 478         (AMD64): New.
 479         (INTEL64): Likewise.
 480         (INTEL64ONLY): Likewise.
 481         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 482         * i386-opc.tbl (Amd64): New.
 483         (Intel64): Likewise.
 484         (Intel64Only): Likewise.
 485         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 486         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 487         * i386-tbl.h: Regenerated.
 488
 489 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 490
 491         PR 25469
 492         * z80-dis.c: Add support for GBZ80 opcodes.
 493
 494 2020-02-04  Alan Modra  <amodra@gmail.com>
 495
 496         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 497
 498 2020-02-03  Alan Modra  <amodra@gmail.com>
 499
 500         * m32c-ibld.c: Regenerate.
 501
 502 2020-02-01  Alan Modra  <amodra@gmail.com>
 503
 504         * frv-ibld.c: Regenerate.
 505
 506 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 507
 508         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 509         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 510         (OP_E_memory): Replace xmm_mdq_mode case label by
 511         vex_scalar_w_dq_mode one.
 512         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 513
 514 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 515
 516         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 517         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 518         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 519         (intel_operand_size): Drop vex_w_dq_mode case label.
 520
 521 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 522
 523         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 524         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 525
 526 2020-01-30  Alan Modra  <amodra@gmail.com>
 527
 528         * m32c-ibld.c: Regenerate.
 529
 530 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 531
 532         * bpf-opc.c: Regenerate.
 533
 534 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 535
 536         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 537         (dis386): Use them to replace C2/C3 table entries.
 538         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 539         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 540         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 541         * i386-tbl.h: Re-generate.
 542
 543 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 544
 545         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 546         forms.
 547         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 548         DefaultSize.
 549         * i386-tbl.h: Re-generate.
 550
 551 2020-01-30  Alan Modra  <amodra@gmail.com>
 552
 553         * tic4x-dis.c (tic4x_dp): Make unsigned.
 554
 555 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 556             Jan Beulich  <jbeulich@suse.com>
 557
 558         PR binutils/25445
 559         * i386-dis.c (MOVSXD_Fixup): New function.
 560         (movsxd_mode): New enum.
 561         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 562         (intel_operand_size): Handle movsxd_mode.
 563         (OP_E_register): Likewise.
 564         (OP_G): Likewise.
 565         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 566         register on movsxd.  Add movsxd with 16-bit destination register
 567         for AMD64 and Intel64 ISAs.
 568         * i386-tbl.h: Regenerated.
 569
 570 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 571
 572         PR 25403
 573         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 574         * aarch64-asm-2.c: Regenerate
 575         * aarch64-dis-2.c: Likewise.
 576         * aarch64-opc-2.c: Likewise.
 577
 578 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 579
 580         * i386-opc.tbl (sysret): Drop DefaultSize.
 581         * i386-tbl.h: Re-generate.
 582
 583 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 584
 585         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 586         Dword.
 587         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 588         * i386-tbl.h: Re-generate.
 589
 590 2020-01-20  Nick Clifton  <nickc@redhat.com>
 591
 592         * po/de.po: Updated German translation.
 593         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 594         * po/uk.po: Updated Ukranian translation.
 595
 596 2020-01-20  Alan Modra  <amodra@gmail.com>
 597
 598         * hppa-dis.c (fput_const): Remove useless cast.
 599
 600 2020-01-20  Alan Modra  <amodra@gmail.com>
 601
 602         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 603
 604 2020-01-18  Nick Clifton  <nickc@redhat.com>
 605
 606         * configure: Regenerate.
 607         * po/opcodes.pot: Regenerate.
 608
 609 2020-01-18  Nick Clifton  <nickc@redhat.com>
 610
 611         Binutils 2.34 branch created.
 612
 613 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 614
 615         * opintl.h: Fix spelling error (seperate).
 616
 617 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 618
 619         * i386-opc.tbl: Add {vex} pseudo prefix.
 620         * i386-tbl.h: Regenerated.
 621
 622 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 623
 624         PR 25376
 625         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 626         (neon_opcodes): Likewise.
 627         (select_arm_features): Make sure we enable MVE bits when selecting
 628         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 629         any architecture.
 630
 631 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 632
 633         * i386-opc.tbl: Drop stale comment from XOP section.
 634
 635 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 636
 637         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 638         (extractps): Add VexWIG to SSE2AVX forms.
 639         * i386-tbl.h: Re-generate.
 640
 641 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 642
 643         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 644         Size64 from and use VexW1 on SSE2AVX forms.
 645         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 646         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 647         * i386-tbl.h: Re-generate.
 648
 649 2020-01-15  Alan Modra  <amodra@gmail.com>
 650
 651         * tic4x-dis.c (tic4x_version): Make unsigned long.
 652         (optab, optab_special, registernames): New file scope vars.
 653         (tic4x_print_register): Set up registernames rather than
 654         malloc'd registertable.
 655         (tic4x_disassemble): Delete optable and optable_special.  Use
 656         optab and optab_special instead.  Throw away old optab,
 657         optab_special and registernames when info->mach changes.
 658
 659 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 660
 661         PR 25377
 662         * z80-dis.c (suffix): Use .db instruction to generate double
 663         prefix.
 664
 665 2020-01-14  Alan Modra  <amodra@gmail.com>
 666
 667         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 668         values to unsigned before shifting.
 669
 670 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 671
 672         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 673         flow instructions.
 674         (print_insn_thumb16, print_insn_thumb32): Likewise.
 675         (print_insn): Initialize the insn info.
 676         * i386-dis.c (print_insn): Initialize the insn info fields, and
 677         detect jumps.
 678
 679 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 680
 681         * arc-opc.c (C_NE): Make it required.
 682
 683 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 684
 685         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 686         reserved register name.
 687
 688 2020-01-13  Alan Modra  <amodra@gmail.com>
 689
 690         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 691         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 692
 693 2020-01-13  Alan Modra  <amodra@gmail.com>
 694
 695         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 696         result of wasm_read_leb128 in a uint64_t and check that bits
 697         are not lost when copying to other locals.  Use uint32_t for
 698         most locals.  Use PRId64 when printing int64_t.
 699
 700 2020-01-13  Alan Modra  <amodra@gmail.com>
 701
 702         * score-dis.c: Formatting.
 703         * score7-dis.c: Formatting.
 704
 705 2020-01-13  Alan Modra  <amodra@gmail.com>
 706
 707         * score-dis.c (print_insn_score48): Use unsigned variables for
 708         unsigned values.  Don't left shift negative values.
 709         (print_insn_score32): Likewise.
 710         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 711
 712 2020-01-13  Alan Modra  <amodra@gmail.com>
 713
 714         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 715
 716 2020-01-13  Alan Modra  <amodra@gmail.com>
 717
 718         * fr30-ibld.c: Regenerate.
 719
 720 2020-01-13  Alan Modra  <amodra@gmail.com>
 721
 722         * xgate-dis.c (print_insn): Don't left shift signed value.
 723         (ripBits): Formatting, use 1u.
 724
 725 2020-01-10  Alan Modra  <amodra@gmail.com>
 726
 727         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 728         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 729
 730 2020-01-10  Alan Modra  <amodra@gmail.com>
 731
 732         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 733         and XRREG value earlier to avoid a shift with negative exponent.
 734         * m10200-dis.c (disassemble): Similarly.
 735
 736 2020-01-09  Nick Clifton  <nickc@redhat.com>
 737
 738         PR 25224
 739         * z80-dis.c (ld_ii_ii): Use correct cast.
 740
 741 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 742
 743         PR 25224
 744         * z80-dis.c (ld_ii_ii): Use character constant when checking
 745         opcode byte value.
 746
 747 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 748
 749         * i386-dis.c (SEP_Fixup): New.
 750         (SEP): Define.
 751         (dis386_twobyte): Use it for sysenter/sysexit.
 752         (enum x86_64_isa): Change amd64 enumerator to value 1.
 753         (OP_J): Compare isa64 against intel64 instead of amd64.
 754         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 755         forms.
 756         * i386-tbl.h: Re-generate.
 757
 758 2020-01-08  Alan Modra  <amodra@gmail.com>
 759
 760         * z8k-dis.c: Include libiberty.h
 761         (instr_data_s): Make max_fetched unsigned.
 762         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 763         Don't exceed byte_info bounds.
 764         (output_instr): Make num_bytes unsigned.
 765         (unpack_instr): Likewise for nibl_count and loop.
 766         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 767         idx unsigned.
 768         * z8k-opc.h: Regenerate.
 769
 770 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 771
 772         * arc-tbl.h (llock): Use 'LLOCK' as class.
 773         (llockd): Likewise.
 774         (scond): Use 'SCOND' as class.
 775         (scondd): Likewise.
 776         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 777         (scondd): Likewise.
 778
 779 2020-01-06  Alan Modra  <amodra@gmail.com>
 780
 781         * m32c-ibld.c: Regenerate.
 782
 783 2020-01-06  Alan Modra  <amodra@gmail.com>
 784
 785         PR 25344
 786         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 787         Peek at next byte to prevent recursion on repeated prefix bytes.
 788         Ensure uninitialised "mybuf" is not accessed.
 789         (print_insn_z80): Don't zero n_fetch and n_used here,..
 790         (print_insn_z80_buf): ..do it here instead.
 791
 792 2020-01-04  Alan Modra  <amodra@gmail.com>
 793
 794         * m32r-ibld.c: Regenerate.
 795
 796 2020-01-04  Alan Modra  <amodra@gmail.com>
 797
 798         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 799
 800 2020-01-04  Alan Modra  <amodra@gmail.com>
 801
 802         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 803
 804 2020-01-04  Alan Modra  <amodra@gmail.com>
 805
 806         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 807
 808 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 809
 810         * aarch64-tbl.h (aarch64_opcode_table): Use
 811         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 812
 813 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 814
 815         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 816         forms of SUDOT and USDOT.
 817
 818 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 819
 820         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 821         uzip{1,2}.
 822         * opcodes/aarch64-dis-2.c: Re-generate.
 823
 824 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 825
 826         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 827         FMMLA encoding.
 828         * opcodes/aarch64-dis-2.c: Re-generate.
 829
 830 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 831
 832         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 833
 834 2020-01-01  Alan Modra  <amodra@gmail.com>
 835
 836         Update year range in copyright notice of all files.
 837
 838 For older changes see ChangeLog-2019
 839 \f
 840 Copyright (C) 2020 Free Software Foundation, Inc.
 841
 842 Copying and distribution of this file, with or without modification,
 843 are permitted in any medium without royalty provided the copyright
 844 notice and this notice are preserved.
 845
 846 Local Variables:
 847 mode: change-log
 848 left-margin: 8
 849 fill-column: 74
 850 version-control: never
 851 End: