opcodes/ChangeLog

   1 2019-12-04  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
   4
   5 2019-12-04  Jan Beulich  <jbeulich@suse.com>
   6
   7         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
   8         forms.
   9         (xbegin): Drop DefaultSize.
  10         * i386-tbl.h: Re-generate.
  11
  12 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
  13
  14         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
  15         Change the coproc CRC conditions to use the extension
  16         feature set, second word, base on ARM_EXT2_CRC.
  17
  18 2019-11-14  Jan Beulich  <jbeulich@suse.com>
  19
  20         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
  21         * i386-tbl.h: Re-generate.
  22
  23 2019-11-14  Jan Beulich  <jbeulich@suse.com>
  24
  25         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
  26         JumpInterSegment, and JumpAbsolute entries.
  27         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
  28         JUMP_ABSOLUTE): Define.
  29         (struct i386_opcode_modifier): Extend jump field to 3 bits.
  30         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
  31         fields.
  32         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
  33         JumpInterSegment): Define.
  34         * i386-tbl.h: Re-generate.
  35
  36 2019-11-14  Jan Beulich  <jbeulich@suse.com>
  37
  38         * i386-gen.c (operand_type_init): Remove
  39         OPERAND_TYPE_JUMPABSOLUTE entry.
  40         (opcode_modifiers): Add JumpAbsolute entry.
  41         (operand_types): Remove JumpAbsolute entry.
  42         * i386-opc.h (JumpAbsolute): Move between enums.
  43         (struct i386_opcode_modifier): Add jumpabsolute field.
  44         (union i386_operand_type): Remove jumpabsolute field.
  45         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
  46         * i386-init.h, i386-tbl.h: Re-generate.
  47
  48 2019-11-14  Jan Beulich  <jbeulich@suse.com>
  49
  50         * i386-gen.c (opcode_modifiers): Add AnySize entry.
  51         (operand_types): Remove AnySize entry.
  52         * i386-opc.h (AnySize): Move between enums.
  53         (struct i386_opcode_modifier): Add anysize field.
  54         (OTUnused): Un-comment.
  55         (union i386_operand_type): Remove anysize field.
  56         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
  57         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
  58         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
  59         AnySize.
  60         * i386-tbl.h: Re-generate.
  61
  62 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
  63
  64         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
  65         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
  66         use the floating point register (FPR).
  67
  68 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
  69
  70         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
  71         cmode 1101.
  72         (is_mve_encoding_conflict): Update cmode conflict checks for
  73         MVE_VMVN_IMM.
  74
  75 2019-11-12  Jan Beulich  <jbeulich@suse.com>
  76
  77         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
  78         entry.
  79         (operand_types): Remove EsSeg entry.
  80         (main): Replace stale use of OTMax.
  81         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
  82         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
  83         (EsSeg): Delete.
  84         (OTUnused): Comment out.
  85         (union i386_operand_type): Remove esseg field.
  86         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
  87         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
  88         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
  89         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
  90         * i386-init.h, i386-tbl.h: Re-generate.
  91
  92 2019-11-12  Jan Beulich  <jbeulich@suse.com>
  93
  94         * i386-gen.c (operand_instances): Add RegB entry.
  95         * i386-opc.h (enum operand_instance): Add RegB.
  96         * i386-opc.tbl (RegC, RegD, RegB): Define.
  97         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
  98         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
  99         monitorx, mwaitx): Drop ImmExt and convert encodings
 100         accordingly.
 101         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
 102         (edx, rdx): Add Instance=RegD.
 103         (ebx, rbx): Add Instance=RegB.
 104         * i386-tbl.h: Re-generate.
 105
 106 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 107
 108         * i386-gen.c (operand_type_init): Adjust
 109         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 110         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 111         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 112         (operand_instances): New.
 113         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 114         (output_operand_type): New parameter "instance". Process it.
 115         (process_i386_operand_type): New local variable "instance".
 116         (main): Adjust static assertions.
 117         * i386-opc.h (INSTANCE_WIDTH): Define.
 118         (enum operand_instance): New.
 119         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 120         (union i386_operand_type): Replace acc, inoutportreg, and
 121         shiftcount by instance.
 122         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 123         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 124         Add Instance=.
 125         * i386-init.h, i386-tbl.h: Re-generate.
 126
 127 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 128
 129         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 130         smaxp/sminp entries' "tied_operand" field to 2.
 131
 132 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 133
 134         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 135         "index" local variable by that of the already existing "num".
 136
 137 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 138
 139         PR gas/25167
 140         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 141         * i386-tbl.h: Regenerated.
 142
 143 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 144
 145         * i386-gen.c (operand_type_init): Add Class= to
 146         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 147         OPERAND_TYPE_REGBND entry.
 148         (operand_classes): Add RegMask and RegBND entries.
 149         (operand_types): Drop RegMask and RegBND entry.
 150         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 151         (RegMask, RegBND): Delete.
 152         (union i386_operand_type): Remove regmask and regbnd fields.
 153         * i386-opc.tbl (RegMask, RegBND): Define.
 154         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 155         Class=RegBND.
 156         * i386-init.h, i386-tbl.h: Re-generate.
 157
 158 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 159
 160         * i386-gen.c (operand_type_init): Add Class= to
 161         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 162         OPERAND_TYPE_REGZMM entries.
 163         (operand_classes): Add RegMMX and RegSIMD entries.
 164         (operand_types): Drop RegMMX and RegSIMD entries.
 165         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 166         (RegMMX, RegSIMD): Delete.
 167         (union i386_operand_type): Remove regmmx and regsimd fields.
 168         * i386-opc.tbl (RegMMX): Define.
 169         (RegXMM, RegYMM, RegZMM): Add Class=.
 170         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 171         Class=RegSIMD.
 172         * i386-init.h, i386-tbl.h: Re-generate.
 173
 174 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 175
 176         * i386-gen.c (operand_type_init): Add Class= to
 177         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 178         entries.
 179         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 180         (operand_types): Drop Control, Debug, and Test entries.
 181         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 182         (Control, Debug, Test): Delete.
 183         (union i386_operand_type): Remove control, debug, and test
 184         fields.
 185         * i386-opc.tbl (Control, Debug, Test): Define.
 186         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 187         Class=RegDR, and Test by Class=RegTR.
 188         * i386-init.h, i386-tbl.h: Re-generate.
 189
 190 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 191
 192         * i386-gen.c (operand_type_init): Add Class= to
 193         OPERAND_TYPE_SREG entry.
 194         (operand_classes): Add SReg entry.
 195         (operand_types): Drop SReg entry.
 196         * i386-opc.h (enum operand_class): Add SReg.
 197         (SReg): Delete.
 198         (union i386_operand_type): Remove sreg field.
 199         * i386-opc.tbl (SReg): Define.
 200         * i386-reg.tbl: Replace SReg by Class=SReg.
 201         * i386-init.h, i386-tbl.h: Re-generate.
 202
 203 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 204
 205         * i386-gen.c (operand_type_init): Add Class=. New
 206         OPERAND_TYPE_ANYIMM entry.
 207         (operand_classes): New.
 208         (operand_types): Drop Reg entry.
 209         (output_operand_type): New parameter "class". Process it.
 210         (process_i386_operand_type): New local variable "class".
 211         (main): Adjust static assertions.
 212         * i386-opc.h (CLASS_WIDTH): Define.
 213         (enum operand_class): New.
 214         (Reg): Replace by Class. Adjust comment.
 215         (union i386_operand_type): Replace reg by class.
 216         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 217         Class=.
 218         * i386-reg.tbl: Replace Reg by Class=Reg.
 219         * i386-init.h: Re-generate.
 220
 221 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 222
 223         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 224         (aarch64_opcode_table): Add data gathering hint mnemonic.
 225         * opcodes/aarch64-dis-2.c: Account for new instruction.
 226
 227 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 228
 229         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 230
 231
 232 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 233
 234         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 235         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 236         aarch64_feature_f64mm): New feature sets.
 237         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 238         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 239         instructions.
 240         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 241         macros.
 242         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 243         (OP_SVE_QQQ): New qualifier.
 244         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 245         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 246         the movprfx constraint.
 247         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 248         (aarch64_opcode_table): Define new instructions smmla,
 249         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 250         uzip{1/2}, trn{1/2}.
 251         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 252         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 253         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 254         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 255         Account for new instructions.
 256         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 257         S4x32 operand.
 258         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 259
 260 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 261 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 262
 263         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 264         Armv8.6-A.
 265         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 266         (neon_opcodes): Add bfloat SIMD instructions.
 267         (print_insn_coprocessor): Add new control character %b to print
 268         condition code without checking cp_num.
 269         (print_insn_neon): Account for BFloat16 instructions that have no
 270         special top-byte handling.
 271
 272 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 273 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 274
 275         * arm-dis.c (print_insn_coprocessor,
 276         print_insn_generic_coprocessor): Create wrapper functions around
 277         the implementation of the print_insn_coprocessor control codes.
 278         (print_insn_coprocessor_1): Original print_insn_coprocessor
 279         function that now takes which array to look at as an argument.
 280         (print_insn_arm): Use both print_insn_coprocessor and
 281         print_insn_generic_coprocessor.
 282         (print_insn_thumb32): As above.
 283
 284 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 285 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 286
 287         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 288         in reglane special case.
 289         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 290         aarch64_find_next_opcode): Account for new instructions.
 291         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 292         in reglane special case.
 293         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 294         new AARCH64_OPND_QLF_S_2H qualifier.
 295         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 296         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 297         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 298         sets.
 299         (BFLOAT_SVE, BFLOAT): New feature set macros.
 300         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 301         instructions.
 302         (aarch64_opcode_table): Define new instructions bfdot,
 303         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 304         bfcvtn2, bfcvt.
 305
 306 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 307 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 308
 309         * aarch64-tbl.h (ARMV8_6): New macro.
 310
 311 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 312
 313         * i386-dis.c (prefix_table): Add mcommit.
 314         (rm_table): Add rdpru.
 315         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 316         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 317         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 318         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 319         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 320         * i386-opc.tbl (mcommit, rdpru): New.
 321         * i386-init.h, i386-tbl.h: Re-generate.
 322
 323 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 324
 325         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 326         "names32" instead.
 327         (OP_Monitor): Drop local variable "op1_names", re-purpose
 328         "names" for it instead, and replace former "names" uses by
 329         "names32" ones.
 330
 331 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 332
 333         PR/gas 25167
 334         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 335         operand-less forms.
 336         * opcodes/i386-tbl.h: Re-generate.
 337
 338 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 339
 340         * i386-dis.c (OP_Mwaitx): Delete.
 341         (prefix_table): Use OP_Mwait for mwaitx entry.
 342         (OP_Mwait): Also handle mwaitx.
 343
 344 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 345
 346         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 347         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 348         (prefix_table): Add respective entries.
 349         (rm_table): Link to those entries.
 350
 351 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 352
 353         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 354         (REG_0F1C_P_0_MOD_0): ... this.
 355         (REG_0F1E_MOD_3): Rename to ...
 356         (REG_0F1E_P_1_MOD_3): ... this.
 357         (RM_0F01_REG_5): Rename to ...
 358         (RM_0F01_REG_5_MOD_3): ... this.
 359         (RM_0F01_REG_7): Rename to ...
 360         (RM_0F01_REG_7_MOD_3): ... this.
 361         (RM_0F1E_MOD_3_REG_7): Rename to ...
 362         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 363         (RM_0FAE_REG_6): Rename to ...
 364         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 365         (RM_0FAE_REG_7): Rename to ...
 366         (RM_0FAE_REG_7_MOD_3): ... this.
 367         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 368         (PREFIX_0F01_REG_5_MOD_0): ... this.
 369         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 370         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 371         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 372         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 373         (PREFIX_0FAE_REG_0): Rename to ...
 374         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 375         (PREFIX_0FAE_REG_1): Rename to ...
 376         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 377         (PREFIX_0FAE_REG_2): Rename to ...
 378         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 379         (PREFIX_0FAE_REG_3): Rename to ...
 380         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 381         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 382         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 383         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 384         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 385         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 386         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 387         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 388         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 389         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 390         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 391         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 392         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 393         (PREFIX_0FAE_REG_7): Rename to ...
 394         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 395         (PREFIX_MOD_0_0FC3): Rename to ...
 396         (PREFIX_0FC3_MOD_0): ... this.
 397         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 398         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 399         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 400         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 401         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 402         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 403         (reg_table, prefix_table, mod_table, rm_table): Adjust
 404         accordingly.
 405
 406 2019-11-04  Nick Clifton  <nickc@redhat.com>
 407
 408         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 409         of a v850 system register.  Move the v850_sreg_names array into
 410         this function.
 411         (get_v850_reg_name): Likewise for ordinary register names.
 412         (get_v850_vreg_name): Likewise for vector register names.
 413         (get_v850_cc_name): Likewise for condition codes.
 414         * get_v850_float_cc_name): Likewise for floating point condition
 415         codes.
 416         (get_v850_cacheop_name): Likewise for cache-ops.
 417         (get_v850_prefop_name): Likewise for pref-ops.
 418         (disassemble): Use the new accessor functions.
 419
 420 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 421
 422         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 423         immediate for the writeback form of ldraa/ldrab if it is 0.
 424         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 425         * aarch64-opc-2.c: Regenerated.
 426
 427 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 428
 429         * i386-gen.c (operand_type_shorthands): Delete.
 430         (operand_type_init): Expand previous shorthands.
 431         (set_bitfield_from_shorthand): Rename back to ...
 432         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 433         of operand_type_init[].
 434         (set_bitfield): Adjust call to the above function.
 435         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 436         RegXMM, RegYMM, RegZMM): Define.
 437         * i386-reg.tbl: Expand prior shorthands.
 438
 439 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 440
 441         * i386-gen.c (output_i386_opcode): Change order of fields
 442         emitted to output.
 443         * i386-opc.h (struct insn_template): Move operands field.
 444         Convert extension_opcode field to unsigned short.
 445         * i386-tbl.h: Re-generate.
 446
 447 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 448
 449         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 450         of W.
 451         * i386-opc.h (W): Extend comment.
 452         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 453         general purpose variants not allowing for byte operands.
 454         * i386-tbl.h: Re-generate.
 455
 456 2019-10-29  Nick Clifton  <nickc@redhat.com>
 457
 458         * tic30-dis.c (print_branch): Correct size of operand array.
 459
 460 2019-10-29  Nick Clifton  <nickc@redhat.com>
 461
 462         * d30v-dis.c (print_insn): Check that operand index is valid
 463         before attempting to access the operands array.
 464
 465 2019-10-29  Nick Clifton  <nickc@redhat.com>
 466
 467         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 468         locating the bit to be tested.
 469
 470 2019-10-29  Nick Clifton  <nickc@redhat.com>
 471
 472         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 473         values.
 474         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 475         (print_insn_s12z):  Check for illegal size values.
 476
 477 2019-10-28  Nick Clifton  <nickc@redhat.com>
 478
 479         * csky-dis.c (csky_chars_to_number): Check for a negative
 480         count. Use an unsigned integer to construct the return value.
 481
 482 2019-10-28  Nick Clifton  <nickc@redhat.com>
 483
 484         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 485         operand buffer.  Set value to 15 not 13.
 486         (get_register_operand): Use OPERAND_BUFFER_LEN.
 487         (get_indirect_operand): Likewise.
 488         (print_two_operand): Likewise.
 489         (print_three_operand): Likewise.
 490         (print_oar_insn): Likewise.
 491
 492 2019-10-28  Nick Clifton  <nickc@redhat.com>
 493
 494         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 495         (bit_extract_simple): Likewise.
 496         (bit_copy): Likewise.
 497         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 498         index_offset array are not accessed.
 499
 500 2019-10-28  Nick Clifton  <nickc@redhat.com>
 501
 502         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 503         operand.
 504
 505 2019-10-25  Nick Clifton  <nickc@redhat.com>
 506
 507         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 508         access to opcodes.op array element.
 509
 510 2019-10-23  Nick Clifton  <nickc@redhat.com>
 511
 512         * rx-dis.c (get_register_name): Fix spelling typo in error
 513         message.
 514         (get_condition_name, get_flag_name, get_double_register_name)
 515         (get_double_register_high_name, get_double_register_low_name)
 516         (get_double_control_register_name, get_double_condition_name)
 517         (get_opsize_name, get_size_name): Likewise.
 518
 519 2019-10-22  Nick Clifton  <nickc@redhat.com>
 520
 521         * rx-dis.c (get_size_name): New function.  Provides safe
 522         access to name array.
 523         (get_opsize_name): Likewise.
 524         (print_insn_rx): Use the accessor functions.
 525
 526 2019-10-16  Nick Clifton  <nickc@redhat.com>
 527
 528         * rx-dis.c (get_register_name): New function.  Provides safe
 529         access to name array.
 530         (get_condition_name, get_flag_name, get_double_register_name)
 531         (get_double_register_high_name, get_double_register_low_name)
 532         (get_double_control_register_name, get_double_condition_name):
 533         Likewise.
 534         (print_insn_rx): Use the accessor functions.
 535
 536 2019-10-09  Nick Clifton  <nickc@redhat.com>
 537
 538         PR 25041
 539         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 540         instructions.
 541
 542 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 543
 544         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 545         (cmpsd): Likewise. Move EsSeg to other operand.
 546         * opcodes/i386-tbl.h: Re-generate.
 547
 548 2019-09-23  Alan Modra  <amodra@gmail.com>
 549
 550         * m68k-dis.c: Include cpu-m68k.h
 551
 552 2019-09-23  Alan Modra  <amodra@gmail.com>
 553
 554         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 555         "elf/mips.h" earlier.
 556
 557 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 558
 559         PR gas/25012
 560         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 561         with SReg operand.
 562         * i386-tbl.h: Re-generate.
 563
 564 2019-09-18  Alan Modra  <amodra@gmail.com>
 565
 566         * arc-ext.c: Update throughout for bfd section macro changes.
 567
 568 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 569
 570         * Makefile.in: Re-generate.
 571         * configure: Re-generate.
 572
 573 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 574
 575         * riscv-opc.c (riscv_opcodes): Change subset field
 576         to insn_class field for all instructions.
 577         (riscv_insn_types): Likewise.
 578
 579 2019-09-16  Phil Blundell  <pb@pbcl.net>
 580
 581         * configure: Regenerated.
 582
 583 2019-09-10  Miod Vallat  <miod@online.fr>
 584
 585         PR 24982
 586         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 587
 588 2019-09-09  Phil Blundell  <pb@pbcl.net>
 589
 590         binutils 2.33 branch created.
 591
 592 2019-09-03  Nick Clifton  <nickc@redhat.com>
 593
 594         PR 24961
 595         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 596         greater than zero before indexing via (bufcnt -1).
 597
 598 2019-09-03  Nick Clifton  <nickc@redhat.com>
 599
 600         PR 24958
 601         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 602         (MAX_SPEC_REG_NAME_LEN): Define.
 603         (struct mmix_dis_info): Use defined constants for array lengths.
 604         (get_reg_name): New function.
 605         (get_sprec_reg_name): New function.
 606         (print_insn_mmix): Use new functions.
 607
 608 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 609
 610         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 611         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 612         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 613
 614 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 615
 616         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 617         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 618         (aarch64_sys_reg_supported_p): Update checks for the above.
 619
 620 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 621
 622         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 623         cases MVE_SQRSHRL and MVE_UQRSHLL.
 624         (print_insn_mve): Add case for specifier 'k' to check
 625         specific bit of the instruction.
 626
 627 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 628
 629         PR 24854
 630         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 631         encountering an unknown machine type.
 632         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 633         cases return -1 rather than calling abort.
 634
 635 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 636
 637         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 638         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 639         IgnoreSize.
 640         * i386-tbl.h: Re-generate.
 641
 642 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 643
 644         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 645         instructions.
 646
 647 2019-07-30  Mel Chen <mel.chen@sifive.com>
 648
 649         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 650         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 651
 652         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 653         fscsr.
 654
 655 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 656
 657         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 658         and MPY class instructions.
 659         (parse_option): Add nps400 option.
 660         (print_arc_disassembler_options): Add nps400 info.
 661
 662 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 663
 664         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 665         (bspop): Likewise.
 666         (modapp): Likewise.
 667         * arc-opc.c (RAD_CHK): Add.
 668         * arc-tbl.h: Regenerate.
 669
 670 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 671
 672         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 673         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 674
 675 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 676
 677         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 678         instructions as UNPREDICTABLE.
 679
 680 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 681
 682         * bpf-desc.c: Regenerated.
 683
 684 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 685
 686         * i386-gen.c (static_assert): Define.
 687         (main): Use it.
 688         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 689         (Opcode_Modifier_Num): ... this.
 690         (Mem): Delete.
 691
 692 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 693
 694         * i386-gen.c (operand_types): Move RegMem ...
 695         (opcode_modifiers): ... here.
 696         * i386-opc.h (RegMem): Move to opcode modifer enum.
 697         (union i386_operand_type): Move regmem field ...
 698         (struct i386_opcode_modifier): ... here.
 699         * i386-opc.tbl (RegMem): Define.
 700         (mov, movq): Move RegMem on segment, control, debug, and test
 701         register flavors.
 702         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 703         to non-SSE2AVX flavor.
 704         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 705         Move RegMem on register only flavors. Drop IgnoreSize from
 706         legacy encoding flavors.
 707         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 708         flavors.
 709         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 710         register only flavors.
 711         (vmovd): Move RegMem and drop IgnoreSize on register only
 712         flavor. Change opcode and operand order to store form.
 713         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 714
 715 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 716
 717         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 718         entries.
 719         * i386-opc.h (SReg2, SReg3): Replace by ...
 720         (SReg): ... this.
 721         (union i386_operand_type): Replace sreg fields.
 722         * i386-opc.tbl (mov, ): Use SReg.
 723         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 724         register flavors.
 725         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 726         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 727
 728 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 729
 730         * bpf-desc.c: Regenerate.
 731         * bpf-opc.c: Likewise.
 732         * bpf-opc.h: Likewise.
 733
 734 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 735
 736         * bpf-desc.c: Regenerate.
 737         * bpf-opc.c: Likewise.
 738
 739 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 740
 741         * arm-dis.c (print_insn_coprocessor): Rename index to
 742         index_operand.
 743
 744 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 745
 746         * riscv-opc.c (riscv_insn_types): Add r4 type.
 747
 748         * riscv-opc.c (riscv_insn_types): Add b and j type.
 749
 750         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 751         format for sb type and correct s type.
 752
 753 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 754
 755         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 756         SVE FMOV alias of FCPY.
 757
 758 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 759
 760         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 761         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 762
 763 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 764
 765         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 766         registers in an instruction prefixed by MOVPRFX.
 767
 768 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 769
 770         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 771         sve_size_13 icode to account for variant behaviour of
 772         pmull{t,b}.
 773         * aarch64-dis-2.c: Regenerate.
 774         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 775         sve_size_13 icode to account for variant behaviour of
 776         pmull{t,b}.
 777         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 778         (OP_SVE_VVV_Q_D): Add new qualifier.
 779         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 780         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 781         AES and those not.
 782
 783 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 784
 785         * opcodes/i386-gen.c (operand_type_init): Remove
 786         OPERAND_TYPE_VEC_IMM4 entry.
 787         (operand_types): Remove Vec_Imm4.
 788         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 789         (union i386_operand_type): Remove vec_imm4.
 790         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 791         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 792
 793 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 794
 795         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 796         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 797         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 798         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 799         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 800         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 801         * i386-tbl.h: Re-generate.
 802
 803 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 804
 805         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 806         register operands.
 807         * i386-tbl.h: Re-generate.
 808
 809 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 810
 811         * i386-opc.tbl (C): New.
 812         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 813         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 814         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 815         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 816         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 817         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 818         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 819         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 820         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 821         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 822         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 823         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 824         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 825         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 826         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 827         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 828         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 829         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 830         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 831         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 832         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 833         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 834         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 835         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 836         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 837         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 838         flavors.
 839         * i386-tbl.h: Re-generate.
 840
 841 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 842
 843         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 844         register operands.
 845         * i386-tbl.h: Re-generate.
 846
 847 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 848
 849         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 850         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 851         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 852         * i386-tbl.h: Re-generate.
 853
 854 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 855
 856         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 857         Disp8MemShift from register only templates.
 858         * i386-tbl.h: Re-generate.
 859
 860 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 861
 862         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 863         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 864         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 865         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 866         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 867         EVEX_W_0F11_P_3_M_1): Delete.
 868         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 869         EVEX_W_0F11_P_3): New.
 870         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 871         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 872         MOD_EVEX_0F11_PREFIX_3 table entries.
 873         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 874         PREFIX_EVEX_0F11 table entries.
 875         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 876         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 877         EVEX_W_0F11_P_3_M_{0,1} table entries.
 878
 879 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 880
 881         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 882         Delete.
 883
 884 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 885
 886         PR binutils/24719
 887         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 888         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 889         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 890         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 891         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 892         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 893         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 894         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 895         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 896         PREFIX_EVEX_0F38C6_REG_6 entries.
 897         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 898         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 899         EVEX_W_0F38C7_R_6_P_2 entries.
 900         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 901         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 902         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 903         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 904         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 905         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 906         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 907
 908 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 909
 910         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 911         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 912         VEX_LEN_0F2D_P_3): Delete.
 913         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 914         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 915         (prefix_table): ... here.
 916
 917 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 918
 919         * i386-dis.c (Iq): Delete.
 920         (Id): New.
 921         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 922         TBM insns.
 923         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 924         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 925         (OP_E_memory): Also honor needindex when deciding whether an
 926         address size prefix needs printing.
 927         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 928
 929 2019-06-26  Jim Wilson  <jimw@sifive.com>
 930
 931         PR binutils/24739
 932         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 933         Set info->display_endian to info->endian_code.
 934
 935 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 936
 937         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 938         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 939         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 940         OPERAND_TYPE_ACC64 entries.
 941         * i386-init.h: Re-generate.
 942
 943 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 944
 945         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 946         Delete.
 947         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 948         of dqa_mode.
 949         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 950         entries here.
 951         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 952         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 953
 954 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 955
 956         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 957         variables.
 958
 959 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 960
 961         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 962         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 963         movnti.
 964         * i386-opc.tbl (movnti): Add IgnoreSize.
 965         * i386-tbl.h: Re-generate.
 966
 967 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 968
 969         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 970         * i386-tbl.h: Re-generate.
 971
 972 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 973
 974         * i386-dis-evex.h: Break into ...
 975         * i386-dis-evex-len.h: New file.
 976         * i386-dis-evex-mod.h: Likewise.
 977         * i386-dis-evex-prefix.h: Likewise.
 978         * i386-dis-evex-reg.h: Likewise.
 979         * i386-dis-evex-w.h: Likewise.
 980         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 981         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 982         i386-dis-evex-mod.h.
 983
 984 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 985
 986         PR binutils/24700
 987         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 988         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 989         EVEX_W_0F385B_P_2.
 990         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 991         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 992         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 993         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 994         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 995         EVEX_LEN_0F385B_P_2_W_1.
 996         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 997         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 998         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 999         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1000         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1001         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1002         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1003         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1004         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1005         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1006
1007 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1008
1009         PR binutils/24691
1010         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1011         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1012         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1013         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1014         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1015         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1016         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1017         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1018         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1019         EVEX_LEN_0F3A43_P_2_W_1.
1020         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1021         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1022         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1023         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1024         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1025         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1026         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1027         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1028         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1029         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1030         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1031         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1032
1033 2019-06-14  Nick Clifton  <nickc@redhat.com>
1034
1035         * po/fr.po; Updated French translation.
1036
1037 2019-06-13  Stafford Horne  <shorne@gmail.com>
1038
1039         * or1k-asm.c: Regenerated.
1040         * or1k-desc.c: Regenerated.
1041         * or1k-desc.h: Regenerated.
1042         * or1k-dis.c: Regenerated.
1043         * or1k-ibld.c: Regenerated.
1044         * or1k-opc.c: Regenerated.
1045         * or1k-opc.h: Regenerated.
1046         * or1k-opinst.c: Regenerated.
1047
1048 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1049
1050         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1051
1052 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1053
1054         PR binutils/24633
1055         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1056         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1057         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1058         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1059         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1060         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1061         EVEX_LEN_0F3A1B_P_2_W_1.
1062         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1063         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1064         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1065         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1066         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1067         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1068         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1069         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1070
1071 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1072
1073         PR binutils/24626
1074         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1075         EVEX.vvvv when disassembling VEX and EVEX instructions.
1076         (OP_VEX): Set vex.register_specifier to 0 after readding
1077         vex.register_specifier.
1078         (OP_Vex_2src_1): Likewise.
1079         (OP_Vex_2src_2): Likewise.
1080         (OP_LWP_E): Likewise.
1081         (OP_EX_Vex): Don't check vex.register_specifier.
1082         (OP_XMM_Vex): Likewise.
1083
1084 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1085             Lili Cui  <lili.cui@intel.com>
1086
1087         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1088         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1089         instructions.
1090         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1091         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1092         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1093         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1094         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1095         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1096         * i386-init.h: Regenerated.
1097         * i386-tbl.h: Likewise.
1098
1099 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1100             Lili Cui  <lili.cui@intel.com>
1101
1102         * doc/c-i386.texi: Document enqcmd.
1103         * testsuite/gas/i386/enqcmd-intel.d: New file.
1104         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1105         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1106         * testsuite/gas/i386/enqcmd.d: Likewise.
1107         * testsuite/gas/i386/enqcmd.s: Likewise.
1108         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1109         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1110         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1111         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1112         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1113         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1114         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1115         and x86-64-enqcmd.
1116
1117 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1118
1119         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1120
1121 2019-06-03  Alan Modra  <amodra@gmail.com>
1122
1123         * ppc-dis.c (prefix_opcd_indices): Correct size.
1124
1125 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1126
1127         PR gas/24625
1128         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1129         Disp8ShiftVL.
1130         * i386-tbl.h: Regenerated.
1131
1132 2019-05-24  Alan Modra  <amodra@gmail.com>
1133
1134         * po/POTFILES.in: Regenerate.
1135
1136 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1137             Alan Modra  <amodra@gmail.com>
1138
1139         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1140         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1141         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1142         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1143         XTOP>): Define and add entries.
1144         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1145         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1146         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1147         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1148
1149 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1150             Alan Modra  <amodra@gmail.com>
1151
1152         * ppc-dis.c (ppc_opts): Add "future" entry.
1153         (PREFIX_OPCD_SEGS): Define.
1154         (prefix_opcd_indices): New array.
1155         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1156         (lookup_prefix): New function.
1157         (print_insn_powerpc): Handle 64-bit prefix instructions.
1158         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1159         (PMRR, POWERXX): Define.
1160         (prefix_opcodes): New instruction table.
1161         (prefix_num_opcodes): New constant.
1162
1163 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1164
1165         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1166         * configure: Regenerated.
1167         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1168         and cpu/bpf.opc.
1169         (HFILES): Add bpf-desc.h and bpf-opc.h.
1170         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1171         bpf-ibld.c and bpf-opc.c.
1172         (BPF_DEPS): Define.
1173         * Makefile.in: Regenerated.
1174         * disassemble.c (ARCH_bpf): Define.
1175         (disassembler): Add case for bfd_arch_bpf.
1176         (disassemble_init_for_target): Likewise.
1177         (enum epbf_isa_attr): Define.
1178         * disassemble.h: extern print_insn_bpf.
1179         * bpf-asm.c: Generated.
1180         * bpf-opc.h: Likewise.
1181         * bpf-opc.c: Likewise.
1182         * bpf-ibld.c: Likewise.
1183         * bpf-dis.c: Likewise.
1184         * bpf-desc.h: Likewise.
1185         * bpf-desc.c: Likewise.
1186
1187 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1188
1189         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1190         and VMSR with the new operands.
1191
1192 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1193
1194         * arm-dis.c (enum mve_instructions): New enum
1195         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1196         and cneg.
1197         (mve_opcodes): New instructions as above.
1198         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1199         csneg and csel.
1200         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1201
1202 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1203
1204         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1205         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1206         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1207         uqshl, urshrl and urshr.
1208         (is_mve_okay_in_it): Add new instructions to TRUE list.
1209         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1210         (print_insn_mve): Updated to accept new %j,
1211         %<bitfield>m and %<bitfield>n patterns.
1212
1213 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1214
1215         * mips-opc.c (mips_builtin_opcodes): Change source register
1216         constraint for DAUI.
1217
1218 2019-05-20  Nick Clifton  <nickc@redhat.com>
1219
1220         * po/fr.po: Updated French translation.
1221
1222 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1223             Michael Collison <michael.collison@arm.com>
1224
1225         * arm-dis.c (thumb32_opcodes): Add new instructions.
1226         (enum mve_instructions): Likewise.
1227         (enum mve_undefined): Add new reasons.
1228         (is_mve_encoding_conflict): Handle new instructions.
1229         (is_mve_undefined): Likewise.
1230         (is_mve_unpredictable): Likewise.
1231         (print_mve_undefined): Likewise.
1232         (print_mve_size): Likewise.
1233
1234 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1235             Michael Collison <michael.collison@arm.com>
1236
1237         * arm-dis.c (thumb32_opcodes): Add new instructions.
1238         (enum mve_instructions): Likewise.
1239         (is_mve_encoding_conflict): Handle new instructions.
1240         (is_mve_undefined): Likewise.
1241         (is_mve_unpredictable): Likewise.
1242         (print_mve_size): Likewise.
1243
1244 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1245             Michael Collison <michael.collison@arm.com>
1246
1247         * arm-dis.c (thumb32_opcodes): Add new instructions.
1248         (enum mve_instructions): Likewise.
1249         (is_mve_encoding_conflict): Likewise.
1250         (is_mve_unpredictable): Likewise.
1251         (print_mve_size): Likewise.
1252
1253 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1254             Michael Collison <michael.collison@arm.com>
1255
1256         * arm-dis.c (thumb32_opcodes): Add new instructions.
1257         (enum mve_instructions): Likewise.
1258         (is_mve_encoding_conflict): Handle new instructions.
1259         (is_mve_undefined): Likewise.
1260         (is_mve_unpredictable): Likewise.
1261         (print_mve_size): Likewise.
1262
1263 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1264             Michael Collison <michael.collison@arm.com>
1265
1266         * arm-dis.c (thumb32_opcodes): Add new instructions.
1267         (enum mve_instructions): Likewise.
1268         (is_mve_encoding_conflict): Handle new instructions.
1269         (is_mve_undefined): Likewise.
1270         (is_mve_unpredictable): Likewise.
1271         (print_mve_size): Likewise.
1272         (print_insn_mve): Likewise.
1273
1274 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1275             Michael Collison <michael.collison@arm.com>
1276
1277         * arm-dis.c (thumb32_opcodes): Add new instructions.
1278         (print_insn_thumb32): Handle new instructions.
1279
1280 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1281             Michael Collison <michael.collison@arm.com>
1282
1283         * arm-dis.c (enum mve_instructions): Add new instructions.
1284         (enum mve_undefined): Add new reasons.
1285         (is_mve_encoding_conflict): Handle new instructions.
1286         (is_mve_undefined): Likewise.
1287         (is_mve_unpredictable): Likewise.
1288         (print_mve_undefined): Likewise.
1289         (print_mve_size): Likewise.
1290         (print_mve_shift_n): Likewise.
1291         (print_insn_mve): Likewise.
1292
1293 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1294             Michael Collison <michael.collison@arm.com>
1295
1296         * arm-dis.c (enum mve_instructions): Add new instructions.
1297         (is_mve_encoding_conflict): Handle new instructions.
1298         (is_mve_unpredictable): Likewise.
1299         (print_mve_rotate): Likewise.
1300         (print_mve_size): Likewise.
1301         (print_insn_mve): Likewise.
1302
1303 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1304             Michael Collison <michael.collison@arm.com>
1305
1306         * arm-dis.c (enum mve_instructions): Add new instructions.
1307         (is_mve_encoding_conflict): Handle new instructions.
1308         (is_mve_unpredictable): Likewise.
1309         (print_mve_size): Likewise.
1310         (print_insn_mve): Likewise.
1311
1312 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1313             Michael Collison <michael.collison@arm.com>
1314
1315         * arm-dis.c (enum mve_instructions): Add new instructions.
1316         (enum mve_undefined): Add new reasons.
1317         (is_mve_encoding_conflict): Handle new instructions.
1318         (is_mve_undefined): Likewise.
1319         (is_mve_unpredictable): Likewise.
1320         (print_mve_undefined): Likewise.
1321         (print_mve_size): Likewise.
1322         (print_insn_mve): Likewise.
1323
1324 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1325             Michael Collison <michael.collison@arm.com>
1326
1327         * arm-dis.c (enum mve_instructions): Add new instructions.
1328         (is_mve_encoding_conflict): Handle new instructions.
1329         (is_mve_undefined): Likewise.
1330         (is_mve_unpredictable): Likewise.
1331         (print_mve_size): Likewise.
1332         (print_insn_mve): Likewise.
1333
1334 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1335             Michael Collison <michael.collison@arm.com>
1336
1337         * arm-dis.c (enum mve_instructions): Add new instructions.
1338         (enum mve_unpredictable): Add new reasons.
1339         (enum mve_undefined): Likewise.
1340         (is_mve_okay_in_it): Handle new isntructions.
1341         (is_mve_encoding_conflict): Likewise.
1342         (is_mve_undefined): Likewise.
1343         (is_mve_unpredictable): Likewise.
1344         (print_mve_vmov_index): Likewise.
1345         (print_simd_imm8): Likewise.
1346         (print_mve_undefined): Likewise.
1347         (print_mve_unpredictable): Likewise.
1348         (print_mve_size): Likewise.
1349         (print_insn_mve): Likewise.
1350
1351 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1352             Michael Collison <michael.collison@arm.com>
1353
1354         * arm-dis.c (enum mve_instructions): Add new instructions.
1355         (enum mve_unpredictable): Add new reasons.
1356         (enum mve_undefined): Likewise.
1357         (is_mve_encoding_conflict): Handle new instructions.
1358         (is_mve_undefined): Likewise.
1359         (is_mve_unpredictable): Likewise.
1360         (print_mve_undefined): Likewise.
1361         (print_mve_unpredictable): Likewise.
1362         (print_mve_rounding_mode): Likewise.
1363         (print_mve_vcvt_size): Likewise.
1364         (print_mve_size): Likewise.
1365         (print_insn_mve): Likewise.
1366
1367 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1368             Michael Collison <michael.collison@arm.com>
1369
1370         * arm-dis.c (enum mve_instructions): Add new instructions.
1371         (enum mve_unpredictable): Add new reasons.
1372         (enum mve_undefined): Likewise.
1373         (is_mve_undefined): Handle new instructions.
1374         (is_mve_unpredictable): Likewise.
1375         (print_mve_undefined): Likewise.
1376         (print_mve_unpredictable): Likewise.
1377         (print_mve_size): Likewise.
1378         (print_insn_mve): Likewise.
1379
1380 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1381             Michael Collison <michael.collison@arm.com>
1382
1383         * arm-dis.c (enum mve_instructions): Add new instructions.
1384         (enum mve_undefined): Add new reasons.
1385         (insns): Add new instructions.
1386         (is_mve_encoding_conflict):
1387         (print_mve_vld_str_addr): New print function.
1388         (is_mve_undefined): Handle new instructions.
1389         (is_mve_unpredictable): Likewise.
1390         (print_mve_undefined): Likewise.
1391         (print_mve_size): Likewise.
1392         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1393         (print_insn_mve):  Handle new operands.
1394
1395 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1396             Michael Collison <michael.collison@arm.com>
1397
1398         * arm-dis.c (enum mve_instructions): Add new instructions.
1399         (enum mve_unpredictable): Add new reasons.
1400         (is_mve_encoding_conflict): Handle new instructions.
1401         (is_mve_unpredictable): Likewise.
1402         (mve_opcodes): Add new instructions.
1403         (print_mve_unpredictable): Handle new reasons.
1404         (print_mve_register_blocks): New print function.
1405         (print_mve_size): Handle new instructions.
1406         (print_insn_mve): Likewise.
1407
1408 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1409             Michael Collison <michael.collison@arm.com>
1410
1411         * arm-dis.c (enum mve_instructions): Add new instructions.
1412         (enum mve_unpredictable): Add new reasons.
1413         (enum mve_undefined): Likewise.
1414         (is_mve_encoding_conflict): Handle new instructions.
1415         (is_mve_undefined): Likewise.
1416         (is_mve_unpredictable): Likewise.
1417         (coprocessor_opcodes): Move NEON VDUP from here...
1418         (neon_opcodes): ... to here.
1419         (mve_opcodes): Add new instructions.
1420         (print_mve_undefined):  Handle new reasons.
1421         (print_mve_unpredictable): Likewise.
1422         (print_mve_size): Handle new instructions.
1423         (print_insn_neon): Handle vdup.
1424         (print_insn_mve): Handle new operands.
1425
1426 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1427             Michael Collison <michael.collison@arm.com>
1428
1429         * arm-dis.c (enum mve_instructions): Add new instructions.
1430         (enum mve_unpredictable): Add new values.
1431         (mve_opcodes): Add new instructions.
1432         (vec_condnames): New array with vector conditions.
1433         (mve_predicatenames): New array with predicate suffixes.
1434         (mve_vec_sizename): New array with vector sizes.
1435         (enum vpt_pred_state): New enum with vector predication states.
1436         (struct vpt_block): New struct type for vpt blocks.
1437         (vpt_block_state): Global struct to keep track of state.
1438         (mve_extract_pred_mask): New helper function.
1439         (num_instructions_vpt_block): Likewise.
1440         (mark_outside_vpt_block): Likewise.
1441         (mark_inside_vpt_block): Likewise.
1442         (invert_next_predicate_state): Likewise.
1443         (update_next_predicate_state): Likewise.
1444         (update_vpt_block_state): Likewise.
1445         (is_vpt_instruction): Likewise.
1446         (is_mve_encoding_conflict): Add entries for new instructions.
1447         (is_mve_unpredictable): Likewise.
1448         (print_mve_unpredictable): Handle new cases.
1449         (print_instruction_predicate): Likewise.
1450         (print_mve_size): New function.
1451         (print_vec_condition): New function.
1452         (print_insn_mve): Handle vpt blocks and new print operands.
1453
1454 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1455
1456         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1457         8, 14 and 15 for Armv8.1-M Mainline.
1458
1459 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1460             Michael Collison <michael.collison@arm.com>
1461
1462         * arm-dis.c (enum mve_instructions): New enum.
1463         (enum mve_unpredictable): Likewise.
1464         (enum mve_undefined): Likewise.
1465         (struct mopcode32): New struct.
1466         (is_mve_okay_in_it): New function.
1467         (is_mve_architecture): Likewise.
1468         (arm_decode_field): Likewise.
1469         (arm_decode_field_multiple): Likewise.
1470         (is_mve_encoding_conflict): Likewise.
1471         (is_mve_undefined): Likewise.
1472         (is_mve_unpredictable): Likewise.
1473         (print_mve_undefined): Likewise.
1474         (print_mve_unpredictable): Likewise.
1475         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1476         (print_insn_mve): New function.
1477         (print_insn_thumb32): Handle MVE architecture.
1478         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1479
1480 2019-05-10  Nick Clifton  <nickc@redhat.com>
1481
1482         PR 24538
1483         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1484         end of the table prematurely.
1485
1486 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1487
1488         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1489         macros for R6.
1490
1491 2019-05-11  Alan Modra  <amodra@gmail.com>
1492
1493         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1494         when -Mraw is in effect.
1495
1496 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1497
1498         * aarch64-dis-2.c: Regenerate.
1499         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1500         (OP_SVE_BBB): New variant set.
1501         (OP_SVE_DDDD): New variant set.
1502         (OP_SVE_HHH): New variant set.
1503         (OP_SVE_HHHU): New variant set.
1504         (OP_SVE_SSS): New variant set.
1505         (OP_SVE_SSSU): New variant set.
1506         (OP_SVE_SHH): New variant set.
1507         (OP_SVE_SBBU): New variant set.
1508         (OP_SVE_DSS): New variant set.
1509         (OP_SVE_DHHU): New variant set.
1510         (OP_SVE_VMV_HSD_BHS): New variant set.
1511         (OP_SVE_VVU_HSD_BHS): New variant set.
1512         (OP_SVE_VVVU_SD_BH): New variant set.
1513         (OP_SVE_VVVU_BHSD): New variant set.
1514         (OP_SVE_VVV_QHD_DBS): New variant set.
1515         (OP_SVE_VVV_HSD_BHS): New variant set.
1516         (OP_SVE_VVV_HSD_BHS2): New variant set.
1517         (OP_SVE_VVV_BHS_HSD): New variant set.
1518         (OP_SVE_VV_BHS_HSD): New variant set.
1519         (OP_SVE_VVV_SD): New variant set.
1520         (OP_SVE_VVU_BHS_HSD): New variant set.
1521         (OP_SVE_VZVV_SD): New variant set.
1522         (OP_SVE_VZVV_BH): New variant set.
1523         (OP_SVE_VZV_SD): New variant set.
1524         (aarch64_opcode_table): Add sve2 instructions.
1525
1526 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1527
1528         * aarch64-asm-2.c: Regenerated.
1529         * aarch64-dis-2.c: Regenerated.
1530         * aarch64-opc-2.c: Regenerated.
1531         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1532         for SVE_SHLIMM_UNPRED_22.
1533         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1534         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1535         operand.
1536
1537 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1538
1539         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1540         sve_size_tsz_bhs iclass encode.
1541         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1542         sve_size_tsz_bhs iclass decode.
1543
1544 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1545
1546         * aarch64-asm-2.c: Regenerated.
1547         * aarch64-dis-2.c: Regenerated.
1548         * aarch64-opc-2.c: Regenerated.
1549         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1550         for SVE_Zm4_11_INDEX.
1551         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1552         (fields): Handle SVE_i2h field.
1553         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1554         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1555
1556 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1557
1558         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1559         sve_shift_tsz_bhsd iclass encode.
1560         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1561         sve_shift_tsz_bhsd iclass decode.
1562
1563 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1564
1565         * aarch64-asm-2.c: Regenerated.
1566         * aarch64-dis-2.c: Regenerated.
1567         * aarch64-opc-2.c: Regenerated.
1568         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1569         (aarch64_encode_variant_using_iclass): Handle
1570         sve_shift_tsz_hsd iclass encode.
1571         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1572         sve_shift_tsz_hsd iclass decode.
1573         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1574         for SVE_SHRIMM_UNPRED_22.
1575         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1576         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1577         operand.
1578
1579 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1580
1581         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1582         sve_size_013 iclass encode.
1583         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1584         sve_size_013 iclass decode.
1585
1586 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1587
1588         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1589         sve_size_bh iclass encode.
1590         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1591         sve_size_bh iclass decode.
1592
1593 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1594
1595         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1596         sve_size_sd2 iclass encode.
1597         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1598         sve_size_sd2 iclass decode.
1599         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1600         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1601
1602 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1603
1604         * aarch64-asm-2.c: Regenerated.
1605         * aarch64-dis-2.c: Regenerated.
1606         * aarch64-opc-2.c: Regenerated.
1607         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1608         for SVE_ADDR_ZX.
1609         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1610         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1611
1612 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1613
1614         * aarch64-asm-2.c: Regenerated.
1615         * aarch64-dis-2.c: Regenerated.
1616         * aarch64-opc-2.c: Regenerated.
1617         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1618         for SVE_Zm3_11_INDEX.
1619         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1620         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1621         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1622         fields.
1623         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1624
1625 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1626
1627         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1628         sve_size_hsd2 iclass encode.
1629         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1630         sve_size_hsd2 iclass decode.
1631         * aarch64-opc.c (fields): Handle SVE_size field.
1632         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1633
1634 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1635
1636         * aarch64-asm-2.c: Regenerated.
1637         * aarch64-dis-2.c: Regenerated.
1638         * aarch64-opc-2.c: Regenerated.
1639         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1640         for SVE_IMM_ROT3.
1641         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1642         (fields): Handle SVE_rot3 field.
1643         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1644         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1645
1646 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1647
1648         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1649         instructions.
1650
1651 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1652
1653         * aarch64-tbl.h
1654         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1655         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1656         aarch64_feature_sve2bitperm): New feature sets.
1657         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1658         for feature set addresses.
1659         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1660         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1661
1662 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1663             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1664
1665         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1666         argument and set ASE_EVA_R6 appropriately.
1667         (set_default_mips_dis_options): Pass ISA to above.
1668         (parse_mips_dis_option): Likewise.
1669         * mips-opc.c (EVAR6): New macro.
1670         (mips_builtin_opcodes): Add llwpe, scwpe.
1671
1672 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1673
1674         * aarch64-asm-2.c: Regenerated.
1675         * aarch64-dis-2.c: Regenerated.
1676         * aarch64-opc-2.c: Regenerated.
1677         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1678         AARCH64_OPND_TME_UIMM16.
1679         (aarch64_print_operand): Likewise.
1680         * aarch64-tbl.h (QL_IMM_NIL): New.
1681         (TME): New.
1682         (_TME_INSN): New.
1683         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1684
1685 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1686
1687         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1688
1689 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1690             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1691
1692         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1693
1694 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1695
1696         * s12z-opc.h: Add extern "C" bracketing to help
1697         users who wish to use this interface in c++ code.
1698
1699 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1700
1701         * s12z-opc.c (bm_decode): Handle bit map operations with the
1702         "reserved0" mode.
1703
1704 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1705
1706         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1707         specifier.  Add entries for VLDR and VSTR of system registers.
1708         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1709         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1710         of %J and %K format specifier.
1711
1712 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1713
1714         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1715         Add new entries for VSCCLRM instruction.
1716         (print_insn_coprocessor): Handle new %C format control code.
1717
1718 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1719
1720         * arm-dis.c (enum isa): New enum.
1721         (struct sopcode32): New structure.
1722         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1723         set isa field of all current entries to ANY.
1724         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1725         Only match an entry if its isa field allows the current mode.
1726
1727 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1728
1729         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1730         CLRM.
1731         (print_insn_thumb32): Add logic to print %n CLRM register list.
1732
1733 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1734
1735         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1736         and %Q patterns.
1737
1738 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1739
1740         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1741         (print_insn_thumb32): Edit the switch case for %Z.
1742
1743 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1744
1745         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1746
1747 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1748
1749         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1750
1751 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1752
1753         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1754
1755 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1756
1757         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1758         Arm register with r13 and r15 unpredictable.
1759         (thumb32_opcodes): New instructions for bfx and bflx.
1760
1761 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1762
1763         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1764
1765 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1766
1767         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1768
1769 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1770
1771         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1772
1773 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1774
1775         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1776
1777 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1778
1779         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1780         "optr". ("operator" is a reserved word in c++).
1781
1782 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1783
1784         * aarch64-opc.c (aarch64_print_operand): Add case for
1785         AARCH64_OPND_Rt_SP.
1786         (verify_constraints): Likewise.
1787         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1788         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1789         to accept Rt|SP as first operand.
1790         (AARCH64_OPERANDS): Add new Rt_SP.
1791         * aarch64-asm-2.c: Regenerated.
1792         * aarch64-dis-2.c: Regenerated.
1793         * aarch64-opc-2.c: Regenerated.
1794
1795 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1796
1797         * aarch64-asm-2.c: Regenerated.
1798         * aarch64-dis-2.c: Likewise.
1799         * aarch64-opc-2.c: Likewise.
1800         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1801
1802 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1803
1804         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1805
1806 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1807
1808         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1809         * i386-init.h: Regenerated.
1810
1811 2019-04-07  Alan Modra  <amodra@gmail.com>
1812
1813         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1814         op_separator to control printing of spaces, comma and parens
1815         rather than need_comma, need_paren and spaces vars.
1816
1817 2019-04-07  Alan Modra  <amodra@gmail.com>
1818
1819         PR 24421
1820         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1821         (print_insn_neon, print_insn_arm): Likewise.
1822
1823 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1824
1825         * i386-dis-evex.h (evex_table): Updated to support BF16
1826         instructions.
1827         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1828         and EVEX_W_0F3872_P_3.
1829         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1830         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1831         * i386-opc.h (enum): Add CpuAVX512_BF16.
1832         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1833         * i386-opc.tbl: Add AVX512 BF16 instructions.
1834         * i386-init.h: Regenerated.
1835         * i386-tbl.h: Likewise.
1836
1837 2019-04-05  Alan Modra  <amodra@gmail.com>
1838
1839         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1840         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1841         to favour printing of "-" branch hint when using the "y" bit.
1842         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1843
1844 2019-04-05  Alan Modra  <amodra@gmail.com>
1845
1846         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1847         opcode until first operand is output.
1848
1849 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1850
1851         PR gas/24349
1852         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1853         (valid_bo_post_v2): Add support for 'at' branch hints.
1854         (insert_bo): Only error on branch on ctr.
1855         (get_bo_hint_mask): New function.
1856         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1857         for inserting 'at' branch hints.
1858         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1859         for extracting 'at' branch hints.
1860         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1861         (BOE): Delete operand.
1862         (BOM, BOP): New operands.
1863         (RM): Update value.
1864         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1865         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1866         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1867         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1868         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1869         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1870         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1871         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1872         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1873         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1874         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1875         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1876         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1877         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1878         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1879         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1880         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1881         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1882         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1883         bttarl+>: New extended mnemonics.
1884
1885 2019-03-28  Alan Modra  <amodra@gmail.com>
1886
1887         PR 24390
1888         * ppc-opc.c (BTF): Define.
1889         (powerpc_opcodes): Use for mtfsb*.
1890         * ppc-dis.c (print_insn_powerpc): Print fields with both
1891         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1892
1893 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1894
1895         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1896         (mapping_symbol_for_insn): Implement new algorithm.
1897         (print_insn): Remove duplicate code.
1898
1899 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1900
1901         * aarch64-dis.c (print_insn_aarch64):
1902         Implement override.
1903
1904 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1905
1906         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1907         order.
1908
1909 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1910
1911         * aarch64-dis.c (last_stop_offset): New.
1912         (print_insn_aarch64): Use stop_offset.
1913
1914 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1915
1916         PR gas/24359
1917         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1918         CPU_ANY_AVX2_FLAGS.
1919         * i386-init.h: Regenerated.
1920
1921 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1922
1923         PR gas/24348
1924         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1925         vmovdqu16, vmovdqu32 and vmovdqu64.
1926         * i386-tbl.h: Regenerated.
1927
1928 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1929
1930         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1931         from vstrszb, vstrszh, and vstrszf.
1932
1933 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1934
1935         * s390-opc.txt: Add instruction descriptions.
1936
1937 2019-02-08  Jim Wilson  <jimw@sifive.com>
1938
1939         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1940         <bne>: Likewise.
1941
1942 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1943
1944         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1945
1946 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1947
1948         PR binutils/23212
1949         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1950         * aarch64-opc.c (verify_elem_sd): New.
1951         (fields): Add FLD_sz entr.
1952         * aarch64-tbl.h (_SIMD_INSN): New.
1953         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1954         fmulx scalar and vector by element isns.
1955
1956 2019-02-07  Nick Clifton  <nickc@redhat.com>
1957
1958         * po/sv.po: Updated Swedish translation.
1959
1960 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1961
1962         * s390-mkopc.c (main): Accept arch13 as cpu string.
1963         * s390-opc.c: Add new instruction formats and instruction opcode
1964         masks.
1965         * s390-opc.txt: Add new arch13 instructions.
1966
1967 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1968
1969         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1970         (aarch64_opcode): Change encoding for stg, stzg
1971         st2g and st2zg.
1972         * aarch64-asm-2.c: Regenerated.
1973         * aarch64-dis-2.c: Regenerated.
1974         * aarch64-opc-2.c: Regenerated.
1975
1976 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1977
1978         * aarch64-asm-2.c: Regenerated.
1979         * aarch64-dis-2.c: Likewise.
1980         * aarch64-opc-2.c: Likewise.
1981         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1982
1983 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1984             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1985
1986         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1987         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1988         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1989         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1990         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1991         case for ldstgv_indexed.
1992         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1993         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1994         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1995         * aarch64-asm-2.c: Regenerated.
1996         * aarch64-dis-2.c: Regenerated.
1997         * aarch64-opc-2.c: Regenerated.
1998
1999 2019-01-23  Nick Clifton  <nickc@redhat.com>
2000
2001         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2002
2003 2019-01-21  Nick Clifton  <nickc@redhat.com>
2004
2005         * po/de.po: Updated German translation.
2006         * po/uk.po: Updated Ukranian translation.
2007
2008 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2009         * mips-dis.c (mips_arch_choices): Fix typo in
2010         gs464, gs464e and gs264e descriptors.
2011
2012 2019-01-19  Nick Clifton  <nickc@redhat.com>
2013
2014         * configure: Regenerate.
2015         * po/opcodes.pot: Regenerate.
2016
2017 2018-06-24  Nick Clifton  <nickc@redhat.com>
2018
2019         2.32 branch created.
2020
2021 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2022
2023         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2024         if it is null.
2025         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2026         zero.
2027
2028 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2029
2030         * configure: Regenerate.
2031
2032 2019-01-07  Alan Modra  <amodra@gmail.com>
2033
2034         * configure: Regenerate.
2035         * po/POTFILES.in: Regenerate.
2036
2037 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2038
2039         * s12z-opc.c: New file.
2040         * s12z-opc.h: New file.
2041         * s12z-dis.c: Removed all code not directly related to display
2042         of instructions.  Used the interface provided by the new files
2043         instead.
2044         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2045         * Makefile.in: Regenerate.
2046         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2047         * configure: Regenerate.
2048
2049 2019-01-01  Alan Modra  <amodra@gmail.com>
2050
2051         Update year range in copyright notice of all files.
2052
2053 For older changes see ChangeLog-2018
2054 \f
2055 Copyright (C) 2019 Free Software Foundation, Inc.
2056
2057 Copying and distribution of this file, with or without modification,
2058 are permitted in any medium without royalty provided the copyright
2059 notice and this notice are preserved.
2060
2061 Local Variables:
2062 mode: change-log
2063 left-margin: 8
2064 fill-column: 74
2065 version-control: never
2066 End: