opcodes/ChangeLog

   1 2020-03-26  Alan Modra  <amodra@gmail.com>
   2
   3         * disassemble.h (opcodes_assert): Declare.
   4         (OPCODES_ASSERT): Define.
   5         * disassemble.c: Don't include assert.h.  Include opintl.h.
   6         (opcodes_assert): New function.
   7         * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
   8         (bfd_h8_disassemble): Reduce size of data array.  Correctly
   9         calculate maxlen.  Omit insn decoding when insn length exceeds
  10         maxlen.  Exit from nibble loop when looking for E, before
  11         accessing next data byte.  Move processing of E outside loop.
  12         Replace tests of maxlen in loop with assertions.
  13
  14 2020-03-26  Alan Modra  <amodra@gmail.com>
  15
  16         * arc-dis.c (find_format): Init needs_limm.  Simplify use of limm.
  17
  18 2020-03-25  Alan Modra  <amodra@gmail.com>
  19
  20         * z80-dis.c (suffix): Init mybuf.
  21
  22 2020-03-22  Alan Modra  <amodra@gmail.com>
  23
  24         * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
  25         successflly read from section.
  26
  27 2020-03-22  Alan Modra  <amodra@gmail.com>
  28
  29         * arc-dis.c (find_format): Use ISO C string concatenation rather
  30         than line continuation within a string.  Don't access needs_limm
  31         before testing opcode != NULL.
  32
  33 2020-03-22  Alan Modra  <amodra@gmail.com>
  34
  35         * ns32k-dis.c (print_insn_arg): Update comment.
  36         (print_insn_ns32k): Reduce size of index_offset array, and
  37         initialize, passing -1 to print_insn_arg for args that are not
  38         an index.  Don't exit arg loop early.  Abort on bad arg number.
  39
  40 2020-03-22  Alan Modra  <amodra@gmail.com>
  41
  42         * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
  43         * s12z-opc.c: Formatting.
  44         (operands_f): Return an int.
  45         (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
  46         (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
  47         (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
  48         (exg_sex_discrim): Likewise.
  49         (create_immediate_operand, create_bitfield_operand),
  50         (create_register_operand_with_size, create_register_all_operand),
  51         (create_register_all16_operand, create_simple_memory_operand),
  52         (create_memory_operand, create_memory_auto_operand): Don't
  53         segfault on malloc failure.
  54         (z_ext24_decode): Return an int status, negative on fail, zero
  55         on success.
  56         (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
  57         (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
  58         (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
  59         (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
  60         (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
  61         (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
  62         (loop_primitive_decode, shift_decode, psh_pul_decode),
  63         (bit_field_decode): Similarly.
  64         (z_decode_signed_value, decode_signed_value): Similarly.  Add arg
  65         to return value, update callers.
  66         (x_opr_decode_with_size): Check all reads, returning NULL on fail.
  67         Don't segfault on NULL operand.
  68         (decode_operation): Return OP_INVALID on first fail.
  69         (decode_s12z): Check all reads, returning -1 on fail.
  70
  71 2020-03-20  Alan Modra  <amodra@gmail.com>
  72
  73         * metag-dis.c (print_insn_metag): Don't ignore status from
  74         read_memory_func.
  75
  76 2020-03-20  Alan Modra  <amodra@gmail.com>
  77
  78         * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
  79         Initialize parts of buffer not written when handling a possible
  80         2-byte insn at end of section.  Don't attempt decoding of such
  81         an insn by the 4-byte machinery.
  82
  83 2020-03-20  Alan Modra  <amodra@gmail.com>
  84
  85         * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
  86         partially filled buffer.  Prevent lookup of 4-byte insns when
  87         only VLE 2-byte insns are possible due to section size.  Print
  88         ".word" rather than ".long" for 2-byte leftovers.
  89
  90 2020-03-17  Sergey Belyashov  <sergey.belyashov@gmail.com>
  91
  92         PR 25641
  93         * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
  94
  95 2020-03-13  Jan Beulich  <jbeulich@suse.com>
  96
  97         * i386-dis.c (X86_64_0D): Rename to ...
  98         (X86_64_0E): ... this.
  99
 100 2020-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 101
 102         * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
 103         * Makefile.in: Regenerated.
 104
 105 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 106
 107         * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
 108         3-operand pseudos.
 109         * i386-tbl.h: Re-generate.
 110
 111 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 112
 113         * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
 114         vprot*, vpsha*, and vpshl*.
 115         * i386-tbl.h: Re-generate.
 116
 117 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 118
 119         * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
 120         vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
 121         * i386-tbl.h: Re-generate.
 122
 123 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 124
 125         * i386-gen.c (set_bitfield): Ignore zero-length field names.
 126         * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
 127         cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
 128         * i386-tbl.h: Re-generate.
 129
 130 2020-03-09  Jan Beulich  <jbeulich@suse.com>
 131
 132         * i386-gen.c (struct template_arg, struct template_instance,
 133         struct template_param, struct template, templates,
 134         parse_template, expand_templates): New.
 135         (process_i386_opcodes): Various local variables moved to
 136         expand_templates. Call parse_template and expand_templates.
 137         * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
 138         * i386-tbl.h: Re-generate.
 139
 140 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 141
 142         * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
 143         vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
 144         register and memory source templates. Replace VexW= by VexW*
 145         where applicable.
 146         * i386-tbl.h: Re-generate.
 147
 148 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 149
 150         * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
 151         VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
 152         * i386-tbl.h: Re-generate.
 153
 154 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 155
 156         * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
 157         * i386-tbl.h: Re-generate.
 158
 159 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 160
 161         * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
 162         (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
 163         pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
 164         VexW0 on SSE2AVX variants.
 165         (vmovq): Drop NoRex64 from XMM/XMM variants.
 166         (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
 167         vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
 168         applicable use VexW0.
 169         * i386-tbl.h: Re-generate.
 170
 171 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 172
 173         * i386-gen.c (opcode_modifiers): Remove Rex64 field.
 174         * i386-opc.h (Rex64): Delete.
 175         (struct i386_opcode_modifier): Remove rex64 field.
 176         * i386-opc.tbl (crc32): Drop Rex64.
 177         Replace Rex64 with Size64 everywhere else.
 178         * i386-tbl.h: Re-generate.
 179
 180 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 181
 182         * i386-dis.c (OP_E_memory): Exclude recording of used address
 183         prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
 184         addressed memory operands for MPX insns.
 185
 186 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 187
 188         * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
 189         invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
 190         adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
 191         (ptwrite): Split into non-64-bit and 64-bit forms.
 192         * i386-tbl.h: Re-generate.
 193
 194 2020-03-06  Jan Beulich  <jbeulich@suse.com>
 195
 196         * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
 197         template.
 198         * i386-tbl.h: Re-generate.
 199
 200 2020-03-04  Jan Beulich  <jbeulich@suse.com>
 201
 202         * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
 203         (prefix_table): Move vmmcall here. Add vmgexit.
 204         (rm_table): Replace vmmcall entry by prefix_table[] escape.
 205         * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
 206         (cpu_flags): Add CpuSEV_ES entry.
 207         * i386-opc.h (CpuSEV_ES): New.
 208         (union i386_cpu_flags): Add cpusev_es field.
 209         * i386-opc.tbl (vmgexit): New.
 210         * i386-init.h, i386-tbl.h: Re-generate.
 211
 212 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 213
 214         * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
 215         with MnemonicSize.
 216         * i386-opc.h (IGNORESIZE): New.
 217         (DEFAULTSIZE): Likewise.
 218         (IgnoreSize): Removed.
 219         (DefaultSize): Likewise.
 220         (MnemonicSize): New.
 221         (i386_opcode_modifier): Replace ignoresize/defaultsize with
 222         mnemonicsize.
 223         * i386-opc.tbl (IgnoreSize): New.
 224         (DefaultSize): Likewise.
 225         * i386-tbl.h: Regenerated.
 226
 227 2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 228
 229         PR 25627
 230         * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
 231         instructions.
 232
 233 2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
 234
 235         PR gas/25622
 236         * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
 237         vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
 238         * i386-tbl.h: Regenerated.
 239
 240 2020-02-26  Alan Modra  <amodra@gmail.com>
 241
 242         * aarch64-asm.c: Indent labels correctly.
 243         * aarch64-dis.c: Likewise.
 244         * aarch64-gen.c: Likewise.
 245         * aarch64-opc.c: Likewise.
 246         * alpha-dis.c: Likewise.
 247         * i386-dis.c: Likewise.
 248         * nds32-asm.c: Likewise.
 249         * nfp-dis.c: Likewise.
 250         * visium-dis.c: Likewise.
 251
 252 2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
 253
 254         * arc-regs.h (int_vector_base): Make it available for all ARC
 255         CPUs.
 256
 257 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 258
 259         * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
 260         changed.
 261
 262 2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
 263
 264         * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
 265         c.mv/c.li if rs1 is zero.
 266
 267 2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
 268
 269         * i386-gen.c (cpu_flag_init): Replace CpuABM with
 270         CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
 271         CPU_POPCNT_FLAGS.
 272         (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
 273         * i386-opc.h (CpuABM): Removed.
 274         (CpuPOPCNT): New.
 275         (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
 276         * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
 277         popcnt.  Remove CpuABM from lzcnt.
 278         * i386-init.h: Regenerated.
 279         * i386-tbl.h: Likewise.
 280
 281 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 282
 283         * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
 284         Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
 285         VexW1 instead of open-coding them.
 286         * i386-tbl.h: Re-generate.
 287
 288 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 289
 290         * i386-opc.tbl (AddrPrefixOpReg): Define.
 291         (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
 292         umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
 293         templates. Drop NoRex64.
 294         * i386-tbl.h: Re-generate.
 295
 296 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 297
 298         PR gas/6518
 299         * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
 300         vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
 301         into Intel syntax instance (with Unpsecified) and AT&T one
 302         (without).
 303         (vcvtneps2bf16): Likewise, along with folding the two so far
 304         separate ones.
 305         * i386-tbl.h: Re-generate.
 306
 307 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 308
 309         * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
 310         CPU_ANY_SSE4A_FLAGS.
 311
 312 2020-02-17  Alan Modra  <amodra@gmail.com>
 313
 314         * i386-gen.c (cpu_flag_init): Correct last change.
 315
 316 2020-02-16  H.J. Lu  <hongjiu.lu@intel.com>
 317
 318         * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS.  Remove
 319         CPU_ANY_SSE4_FLAGS.
 320
 321 2020-02-14  H.J. Lu  <hongjiu.lu@intel.com>
 322
 323         * i386-opc.tbl (movsx): Remove Intel syntax comments.
 324         (movzx): Likewise.
 325
 326 2020-02-14  Jan Beulich  <jbeulich@suse.com>
 327
 328         PR gas/25438
 329         * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
 330         destination for Cpu64-only variant.
 331         (movzx): Fold patterns.
 332         * i386-tbl.h: Re-generate.
 333
 334 2020-02-13  Jan Beulich  <jbeulich@suse.com>
 335
 336         * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
 337         CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
 338         CPU_ANY_SSE4_FLAGS entry.
 339         * i386-init.h: Re-generate.
 340
 341 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 342
 343         * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
 344         with Unspecified, making the present one AT&T syntax only.
 345         * i386-tbl.h: Re-generate.
 346
 347 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 348
 349         * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
 350         * i386-tbl.h: Re-generate.
 351
 352 2020-02-12  Jan Beulich  <jbeulich@suse.com>
 353
 354         PR gas/24546
 355         * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
 356         * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
 357         Amd64 and Intel64 templates.
 358         (call, jmp): Likewise for far indirect variants. Dro
 359         Unspecified.
 360         * i386-tbl.h: Re-generate.
 361
 362 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 363
 364         * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
 365         * i386-opc.h (ShortForm): Delete.
 366         (struct i386_opcode_modifier): Remove shortform field.
 367         * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
 368         fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
 369         fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
 370         ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
 371         Drop ShortForm.
 372         * i386-tbl.h: Re-generate.
 373
 374 2020-02-11  Jan Beulich  <jbeulich@suse.com>
 375
 376         * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
 377         fucompi): Drop ShortForm from operand-less templates.
 378         * i386-tbl.h: Re-generate.
 379
 380 2020-02-11  Alan Modra  <amodra@gmail.com>
 381
 382         * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
 383         * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
 384         * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
 385         * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
 386         * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
 387
 388 2020-02-10  Matthew Malcomson  <matthew.malcomson@arm.com>
 389
 390         * arm-dis.c (print_insn_cde): Define 'V' parse character.
 391         (cde_opcodes): Add VCX* instructions.
 392
 393 2020-02-10  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
 394             Matthew Malcomson  <matthew.malcomson@arm.com>
 395
 396         * arm-dis.c (struct cdeopcode32): New.
 397         (CDE_OPCODE): New macro.
 398         (cde_opcodes): New disassembly table.
 399         (regnames): New option to table.
 400         (cde_coprocs): New global variable.
 401         (print_insn_cde): New
 402         (print_insn_thumb32): Use print_insn_cde.
 403         (parse_arm_disassembler_options): Parse coprocN args.
 404
 405 2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>
 406
 407         PR gas/25516
 408         * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
 409         with ISA64.
 410         * i386-opc.h (AMD64): Removed.
 411         (Intel64): Likewose.
 412         (AMD64): New.
 413         (INTEL64): Likewise.
 414         (INTEL64ONLY): Likewise.
 415         (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
 416         * i386-opc.tbl (Amd64): New.
 417         (Intel64): Likewise.
 418         (Intel64Only): Likewise.
 419         Replace AMD64 with Amd64.  Update sysenter/sysenter with
 420         Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
 421         * i386-tbl.h: Regenerated.
 422
 423 2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>
 424
 425         PR 25469
 426         * z80-dis.c: Add support for GBZ80 opcodes.
 427
 428 2020-02-04  Alan Modra  <amodra@gmail.com>
 429
 430         * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
 431
 432 2020-02-03  Alan Modra  <amodra@gmail.com>
 433
 434         * m32c-ibld.c: Regenerate.
 435
 436 2020-02-01  Alan Modra  <amodra@gmail.com>
 437
 438         * frv-ibld.c: Regenerate.
 439
 440 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 441
 442         * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
 443         (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
 444         (OP_E_memory): Replace xmm_mdq_mode case label by
 445         vex_scalar_w_dq_mode one.
 446         * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
 447
 448 2020-01-31  Jan Beulich  <jbeulich@suse.com>
 449
 450         * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
 451         (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
 452         vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
 453         (intel_operand_size): Drop vex_w_dq_mode case label.
 454
 455 2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>
 456
 457         * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
 458         Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
 459
 460 2020-01-30  Alan Modra  <amodra@gmail.com>
 461
 462         * m32c-ibld.c: Regenerate.
 463
 464 2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>
 465
 466         * bpf-opc.c: Regenerate.
 467
 468 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 469
 470         * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
 471         (dis386): Use them to replace C2/C3 table entries.
 472         (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
 473         * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
 474         ones. Use Size64 instead of DefaultSize on Intel64 ones.
 475         * i386-tbl.h: Re-generate.
 476
 477 2020-01-30  Jan Beulich  <jbeulich@suse.com>
 478
 479         * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
 480         forms.
 481         (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
 482         DefaultSize.
 483         * i386-tbl.h: Re-generate.
 484
 485 2020-01-30  Alan Modra  <amodra@gmail.com>
 486
 487         * tic4x-dis.c (tic4x_dp): Make unsigned.
 488
 489 2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
 490             Jan Beulich  <jbeulich@suse.com>
 491
 492         PR binutils/25445
 493         * i386-dis.c (MOVSXD_Fixup): New function.
 494         (movsxd_mode): New enum.
 495         (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
 496         (intel_operand_size): Handle movsxd_mode.
 497         (OP_E_register): Likewise.
 498         (OP_G): Likewise.
 499         * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
 500         register on movsxd.  Add movsxd with 16-bit destination register
 501         for AMD64 and Intel64 ISAs.
 502         * i386-tbl.h: Regenerated.
 503
 504 2020-01-27  Tamar Christina  <tamar.christina@arm.com>
 505
 506         PR 25403
 507         * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
 508         * aarch64-asm-2.c: Regenerate
 509         * aarch64-dis-2.c: Likewise.
 510         * aarch64-opc-2.c: Likewise.
 511
 512 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 513
 514         * i386-opc.tbl (sysret): Drop DefaultSize.
 515         * i386-tbl.h: Re-generate.
 516
 517 2020-01-21  Jan Beulich  <jbeulich@suse.com>
 518
 519         * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
 520         Dword.
 521         (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
 522         * i386-tbl.h: Re-generate.
 523
 524 2020-01-20  Nick Clifton  <nickc@redhat.com>
 525
 526         * po/de.po: Updated German translation.
 527         * po/pt_BR.po: Updated Brazilian Portuguese translation.
 528         * po/uk.po: Updated Ukranian translation.
 529
 530 2020-01-20  Alan Modra  <amodra@gmail.com>
 531
 532         * hppa-dis.c (fput_const): Remove useless cast.
 533
 534 2020-01-20  Alan Modra  <amodra@gmail.com>
 535
 536         * arm-dis.c (print_insn_arm): Wrap 'T' value.
 537
 538 2020-01-18  Nick Clifton  <nickc@redhat.com>
 539
 540         * configure: Regenerate.
 541         * po/opcodes.pot: Regenerate.
 542
 543 2020-01-18  Nick Clifton  <nickc@redhat.com>
 544
 545         Binutils 2.34 branch created.
 546
 547 2020-01-17  Christian Biesinger  <cbiesinger@google.com>
 548
 549         * opintl.h: Fix spelling error (seperate).
 550
 551 2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>
 552
 553         * i386-opc.tbl: Add {vex} pseudo prefix.
 554         * i386-tbl.h: Regenerated.
 555
 556 2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 557
 558         PR 25376
 559         * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
 560         (neon_opcodes): Likewise.
 561         (select_arm_features): Make sure we enable MVE bits when selecting
 562         armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
 563         any architecture.
 564
 565 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 566
 567         * i386-opc.tbl: Drop stale comment from XOP section.
 568
 569 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 570
 571         * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
 572         (extractps): Add VexWIG to SSE2AVX forms.
 573         * i386-tbl.h: Re-generate.
 574
 575 2020-01-16  Jan Beulich  <jbeulich@suse.com>
 576
 577         * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
 578         Size64 from and use VexW1 on SSE2AVX forms.
 579         (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
 580         VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
 581         * i386-tbl.h: Re-generate.
 582
 583 2020-01-15  Alan Modra  <amodra@gmail.com>
 584
 585         * tic4x-dis.c (tic4x_version): Make unsigned long.
 586         (optab, optab_special, registernames): New file scope vars.
 587         (tic4x_print_register): Set up registernames rather than
 588         malloc'd registertable.
 589         (tic4x_disassemble): Delete optable and optable_special.  Use
 590         optab and optab_special instead.  Throw away old optab,
 591         optab_special and registernames when info->mach changes.
 592
 593 2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>
 594
 595         PR 25377
 596         * z80-dis.c (suffix): Use .db instruction to generate double
 597         prefix.
 598
 599 2020-01-14  Alan Modra  <amodra@gmail.com>
 600
 601         * z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
 602         values to unsigned before shifting.
 603
 604 2020-01-13  Thomas Troeger  <tstroege@gmx.de>
 605
 606         * arm-dis.c (print_insn_arm): Fill in insn info fields for control
 607         flow instructions.
 608         (print_insn_thumb16, print_insn_thumb32): Likewise.
 609         (print_insn): Initialize the insn info.
 610         * i386-dis.c (print_insn): Initialize the insn info fields, and
 611         detect jumps.
 612
 613 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 614
 615         * arc-opc.c (C_NE): Make it required.
 616
 617 2012-01-13  Claudiu Zissulescu <claziss@gmail.com>
 618
 619         * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
 620         reserved register name.
 621
 622 2020-01-13  Alan Modra  <amodra@gmail.com>
 623
 624         * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
 625         (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
 626
 627 2020-01-13  Alan Modra  <amodra@gmail.com>
 628
 629         * wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
 630         result of wasm_read_leb128 in a uint64_t and check that bits
 631         are not lost when copying to other locals.  Use uint32_t for
 632         most locals.  Use PRId64 when printing int64_t.
 633
 634 2020-01-13  Alan Modra  <amodra@gmail.com>
 635
 636         * score-dis.c: Formatting.
 637         * score7-dis.c: Formatting.
 638
 639 2020-01-13  Alan Modra  <amodra@gmail.com>
 640
 641         * score-dis.c (print_insn_score48): Use unsigned variables for
 642         unsigned values.  Don't left shift negative values.
 643         (print_insn_score32): Likewise.
 644         * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
 645
 646 2020-01-13  Alan Modra  <amodra@gmail.com>
 647
 648         * tic4x-dis.c (tic4x_print_register): Remove dead code.
 649
 650 2020-01-13  Alan Modra  <amodra@gmail.com>
 651
 652         * fr30-ibld.c: Regenerate.
 653
 654 2020-01-13  Alan Modra  <amodra@gmail.com>
 655
 656         * xgate-dis.c (print_insn): Don't left shift signed value.
 657         (ripBits): Formatting, use 1u.
 658
 659 2020-01-10  Alan Modra  <amodra@gmail.com>
 660
 661         * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
 662         * tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.
 663
 664 2020-01-10  Alan Modra  <amodra@gmail.com>
 665
 666         * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
 667         and XRREG value earlier to avoid a shift with negative exponent.
 668         * m10200-dis.c (disassemble): Similarly.
 669
 670 2020-01-09  Nick Clifton  <nickc@redhat.com>
 671
 672         PR 25224
 673         * z80-dis.c (ld_ii_ii): Use correct cast.
 674
 675 2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
 676
 677         PR 25224
 678         * z80-dis.c (ld_ii_ii): Use character constant when checking
 679         opcode byte value.
 680
 681 2020-01-09  Jan Beulich  <jbeulich@suse.com>
 682
 683         * i386-dis.c (SEP_Fixup): New.
 684         (SEP): Define.
 685         (dis386_twobyte): Use it for sysenter/sysexit.
 686         (enum x86_64_isa): Change amd64 enumerator to value 1.
 687         (OP_J): Compare isa64 against intel64 instead of amd64.
 688         * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
 689         forms.
 690         * i386-tbl.h: Re-generate.
 691
 692 2020-01-08  Alan Modra  <amodra@gmail.com>
 693
 694         * z8k-dis.c: Include libiberty.h
 695         (instr_data_s): Make max_fetched unsigned.
 696         (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
 697         Don't exceed byte_info bounds.
 698         (output_instr): Make num_bytes unsigned.
 699         (unpack_instr): Likewise for nibl_count and loop.
 700         * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
 701         idx unsigned.
 702         * z8k-opc.h: Regenerate.
 703
 704 2020-01-07  Shahab Vahedi  <shahab@synopsys.com>
 705
 706         * arc-tbl.h (llock): Use 'LLOCK' as class.
 707         (llockd): Likewise.
 708         (scond): Use 'SCOND' as class.
 709         (scondd): Likewise.
 710         (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
 711         (scondd): Likewise.
 712
 713 2020-01-06  Alan Modra  <amodra@gmail.com>
 714
 715         * m32c-ibld.c: Regenerate.
 716
 717 2020-01-06  Alan Modra  <amodra@gmail.com>
 718
 719         PR 25344
 720         * z80-dis.c (suffix): Don't use a local struct buffer copy.
 721         Peek at next byte to prevent recursion on repeated prefix bytes.
 722         Ensure uninitialised "mybuf" is not accessed.
 723         (print_insn_z80): Don't zero n_fetch and n_used here,..
 724         (print_insn_z80_buf): ..do it here instead.
 725
 726 2020-01-04  Alan Modra  <amodra@gmail.com>
 727
 728         * m32r-ibld.c: Regenerate.
 729
 730 2020-01-04  Alan Modra  <amodra@gmail.com>
 731
 732         * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
 733
 734 2020-01-04  Alan Modra  <amodra@gmail.com>
 735
 736         * crx-dis.c (match_opcode): Avoid shift left of signed value.
 737
 738 2020-01-04  Alan Modra  <amodra@gmail.com>
 739
 740         * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
 741
 742 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 743
 744         * aarch64-tbl.h (aarch64_opcode_table): Use
 745         SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
 746
 747 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 748
 749         * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
 750         forms of SUDOT and USDOT.
 751
 752 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 753
 754         * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
 755         uzip{1,2}.
 756         * opcodes/aarch64-dis-2.c: Re-generate.
 757
 758 2020-01-03  Jan Beulich  <jbeulich@suse.com>
 759
 760         * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
 761         FMMLA encoding.
 762         * opcodes/aarch64-dis-2.c: Re-generate.
 763
 764 2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>
 765
 766         * z80-dis.c: Add support for eZ80 and Z80 instructions.
 767
 768 2020-01-01  Alan Modra  <amodra@gmail.com>
 769
 770         Update year range in copyright notice of all files.
 771
 772 For older changes see ChangeLog-2019
 773 \f
 774 Copyright (C) 2020 Free Software Foundation, Inc.
 775
 776 Copying and distribution of this file, with or without modification,
 777 are permitted in any medium without royalty provided the copyright
 778 notice and this notice are preserved.
 779
 780 Local Variables:
 781 mode: change-log
 782 left-margin: 8
 783 fill-column: 74
 784 version-control: never
 785 End: