opcodes/ChangeLog

   1 2019-12-23  Alan Modra  <amodra@gmail.com>
   2
   3         * d30v-dis.c (extract_value): Make num param a uint64_t, constify
   4         oper.  Use unsigned vars.
   5         (print_insn): Make num var uint64_t.  Constify oper and remove now
   6         unnecessary casts on extract_value calls.
   7         (print_insn_d30v): Use unsigned vars.  Adjust printf formats.
   8
   9 2019-12-23  Alan Modra  <amodra@gmail.com>
  10
  11         * wasm32-dis.c (wasm_read_leb128): Don't allow oversize shifts.
  12         Catch value overflow.  Sign extend only on terminating byte.
  13
  14 2019-12-20  Alan Modra  <amodra@gmail.com>
  15
  16         PR 25281
  17         * sh-dis.c (print_insn_ddt): Properly check validity of MOVX_NOPY
  18         and MOVY_NOPX insns.  For invalid cases include 0xf000 in the word
  19         printed.  Print .word in more cases.
  20
  21 2019-12-20  Alan Modra  <amodra@gmail.com>
  22
  23         * or1k-ibld.c: Regenerate.
  24
  25 2019-12-20  Alan Modra  <amodra@gmail.com>
  26
  27         * hppa-dis.c (extract_16, extract_21, print_insn_hppa): Use
  28         unsigned variables.
  29
  30 2019-12-20  Alan Modra  <amodra@gmail.com>
  31
  32         * m68hc11-dis.c (read_memory): Delete forward decls.
  33         (print_indexed_operand, print_insn): Likewise.
  34         (print_indexed_operand): Formatting.  Don't rely on short being
  35         exactly 16 bits, make sign extension explicit.
  36         (print_insn): Likewise.  Avoid signed overflow.
  37
  38 2019-12-19  Alan Modra  <amodra@gmail.com>
  39
  40         * vax-dis.c (print_insn_mode): Stop index mode recursion.
  41
  42 2019-12-19  Dr N.W. Filardo  <nwf20@cam.ac.uk>
  43
  44         PR 25277
  45         * microblaze-opcm.h (enum microblaze_instr): Prefix fadd, fmul and
  46         fdiv with "mbi_".
  47         * microblaze-opc.h (opcodes): Adjust to suit.
  48
  49 2019-12-18  Alan Modra  <amodra@gmail.com>
  50
  51         * alpha-opc.c (OP): Avoid signed overflow.
  52         * arm-dis.c (print_insn): Likewise.
  53         * mcore-dis.c (print_insn_mcore): Likewise.
  54         * pj-dis.c (get_int): Likewise.
  55         * ppc-opc.c (EBD15, EBD15BI): Likewise.
  56         * score7-dis.c (s7_print_insn): Likewise.
  57         * tic30-dis.c (print_insn_tic30): Likewise.
  58         * v850-opc.c (insert_SELID): Likewise.
  59         * vax-dis.c (print_insn_vax): Likewise.
  60         * arc-ext.c (create_map): Likewise.
  61         (struct ExtAuxRegister): Make "address" field unsigned int.
  62         (arcExtMap_auxRegName): Pass unsigned address.
  63         (dump_ARC_extmap): Adjust.
  64         * arc-ext.h (arcExtMap_auxRegName): Update prototype.
  65
  66 2019-12-17  Alan Modra  <amodra@gmail.com>
  67
  68         * visium-dis.c (print_insn_visium): Avoid signed overflow.
  69
  70 2019-12-17  Alan Modra  <amodra@gmail.com>
  71
  72         * aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow.
  73         (value_fit_unsigned_field_p): Likewise.
  74         (aarch64_wide_constant_p): Likewise.
  75         (operand_general_constraint_met_p): Likewise.
  76         * aarch64-opc.h (aarch64_wide_constant_p): Update prototype.
  77
  78 2019-12-17  Alan Modra  <amodra@gmail.com>
  79
  80         * nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
  81         (print_insn_nds32): Use uint64_t for "given" and "given1".
  82
  83 2019-12-17  Alan Modra  <amodra@gmail.com>
  84
  85         * tic80-dis.c: Delete file.
  86         * tic80-opc.c: Delete file.
  87         * disassemble.c: Remove tic80 support.
  88         * disassemble.h: Likewise.
  89         * Makefile.am: Likewise.
  90         * configure.ac: Likewise.
  91         * Makefile.in: Regenerate.
  92         * configure: Regenerate.
  93         * po/POTFILES.in: Regenerate.
  94
  95 2019-12-17  Alan Modra  <amodra@gmail.com>
  96
  97         * bpf-ibld.c: Regenerate.
  98
  99 2019-12-16  Alan Modra  <amodra@gmail.com>
 100
 101         * aarch64-dis.c (sign_extend): Return uint64_t.  Rewrite without
 102         conditional.
 103         (aarch64_ext_imm): Avoid signed overflow.
 104
 105 2019-12-16  Alan Modra  <amodra@gmail.com>
 106
 107         * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
 108
 109 2019-12-16  Alan Modra  <amodra@gmail.com>
 110
 111         * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
 112
 113 2019-12-16  Alan Modra  <amodra@gmail.com>
 114
 115         * xstormy16-ibld.c: Regenerate.
 116
 117 2019-12-16  Alan Modra  <amodra@gmail.com>
 118
 119         * score-dis.c (print_insn_score16): Move rpush/rpop imm field
 120         value adjustment so that it doesn't affect reg field too.
 121
 122 2019-12-16  Alan Modra  <amodra@gmail.com>
 123
 124         * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
 125         (get_number_of_operands, getargtype, getbits, getregname),
 126         (getcopregname, getprocregname, gettrapstring, getcinvstring),
 127         (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
 128         (powerof2, match_opcode, make_instruction, print_arguments),
 129         (print_arg): Delete forward declarations, moving static to..
 130         (getregname, getcopregname, getregliststring): ..these definitions.
 131         (build_mask): Return unsigned int mask.
 132         (match_opcode): Use unsigned int vars.
 133
 134 2019-12-16  Alan Modra  <amodra@gmail.com>
 135
 136         * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
 137
 138 2019-12-16  Alan Modra  <amodra@gmail.com>
 139
 140         * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
 141         (struct objdump_disasm_info): Delete.
 142         (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
 143         N32_IMMS to unsigned before shifting left.
 144
 145 2019-12-16  Alan Modra  <amodra@gmail.com>
 146
 147         * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
 148         (print_insn_moxie): Remove unnecessary cast.
 149
 150 2019-12-12  Alan Modra  <amodra@gmail.com>
 151
 152         * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
 153         mask.
 154
 155 2019-12-11  Alan Modra  <amodra@gmail.com>
 156
 157         * arc-dis.c (BITS): Don't truncate high bits with shifts.
 158         * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
 159         * tic54x-dis.c (print_instruction): Likewise.
 160         * tilegx-opc.c (parse_insn_tilegx): Likewise.
 161         * tilepro-opc.c (parse_insn_tilepro): Likewise.
 162         * visium-dis.c (disassem_class0): Likewise.
 163         * pdp11-dis.c (sign_extend): Likewise.
 164         (SIGN_BITS): Delete.
 165         * epiphany-ibld.c: Regenerate.
 166         * lm32-ibld.c: Regenerate.
 167         * m32c-ibld.c: Regenerate.
 168
 169 2019-12-11  Alan Modra  <amodra@gmail.com>
 170
 171         * ns32k-dis.c (sign_extend): Correct last patch.
 172
 173 2019-12-11  Alan Modra  <amodra@gmail.com>
 174
 175         * vax-dis.c (NEXTLONG): Avoid signed overflow.
 176
 177 2019-12-11  Alan Modra  <amodra@gmail.com>
 178
 179         * v850-dis.c (get_operand_value): Use unsigned arithmetic.  Don't
 180         sign extend using shifts.
 181
 182 2019-12-11  Alan Modra  <amodra@gmail.com>
 183
 184         * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
 185
 186 2019-12-11  Alan Modra  <amodra@gmail.com>
 187
 188         * tic4x-dis.c (tic4x_print_register): Formatting.  Don't segfault
 189         on NULL registertable entry.
 190         (tic4x_hash_opcode): Use unsigned arithmetic.
 191
 192 2019-12-11  Alan Modra  <amodra@gmail.com>
 193
 194         * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
 195
 196 2019-12-11  Alan Modra  <amodra@gmail.com>
 197
 198         * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
 199         (bit_extract_simple, sign_extend): Likewise.
 200
 201 2019-12-11  Alan Modra  <amodra@gmail.com>
 202
 203         * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
 204
 205 2019-12-11  Alan Modra  <amodra@gmail.com>
 206
 207         * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
 208
 209 2019-12-11  Alan Modra  <amodra@gmail.com>
 210
 211         * m68k-dis.c (COERCE32): Cast value first.
 212         (NEXTLONG, NEXTULONG): Avoid signed overflow.
 213
 214 2019-12-11  Alan Modra  <amodra@gmail.com>
 215
 216         * h8300-dis.c (extract_immediate): Avoid signed overflow.
 217         (bfd_h8_disassemble): Likewise.
 218
 219 2019-12-11  Alan Modra  <amodra@gmail.com>
 220
 221         * d30v-dis.c (print_insn): Make opind unsigned.  Don't access
 222         past end of operands array.
 223
 224 2019-12-11  Alan Modra  <amodra@gmail.com>
 225
 226         * csky-dis.c (csky_chars_to_number): Rewrite.  Avoid signed
 227         overflow when collecting bytes of a number.
 228
 229 2019-12-11  Alan Modra  <amodra@gmail.com>
 230
 231         * cris-dis.c (print_with_operands): Avoid signed integer
 232         overflow when collecting bytes of a 32-bit integer.
 233
 234 2019-12-11  Alan Modra  <amodra@gmail.com>
 235
 236         * cr16-dis.c (EXTRACT, SBM): Rewrite.
 237         (cr16_match_opcode): Delete duplicate bcond test.
 238
 239 2019-12-11  Alan Modra  <amodra@gmail.com>
 240
 241         * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
 242         (SIGNBIT): New.
 243         (MASKBITS, SIGNEXTEND): Rewrite.
 244         (fmtconst): Don't use ? expression now that SIGNEXTEND uses
 245         unsigned arithmetic, instead assign result of SIGNEXTEND back
 246         to x.
 247         (fmtconst_val): Use 1u in shift expression.
 248
 249 2019-12-11  Alan Modra  <amodra@gmail.com>
 250
 251         * arc-dis.c (find_format_from_table): Use ull constant when
 252         shifting by up to 32.
 253
 254 2019-12-11  Alan Modra  <amodra@gmail.com>
 255
 256         PR 25270
 257         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
 258         false when field is zero for sve_size_tsz_bhs.
 259
 260 2019-12-11  Alan Modra  <amodra@gmail.com>
 261
 262         * epiphany-ibld.c: Regenerate.
 263
 264 2019-12-10  Alan Modra  <amodra@gmail.com>
 265
 266         PR 24960
 267         * disassemble.c (disassemble_free_target): New function.
 268
 269 2019-12-10  Alan Modra  <amodra@gmail.com>
 270
 271         * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
 272         * disassemble.c (disassemble_init_for_target): Likewise.
 273         * bpf-dis.c: Regenerate.
 274         * epiphany-dis.c: Regenerate.
 275         * fr30-dis.c: Regenerate.
 276         * frv-dis.c: Regenerate.
 277         * ip2k-dis.c: Regenerate.
 278         * iq2000-dis.c: Regenerate.
 279         * lm32-dis.c: Regenerate.
 280         * m32c-dis.c: Regenerate.
 281         * m32r-dis.c: Regenerate.
 282         * mep-dis.c: Regenerate.
 283         * mt-dis.c: Regenerate.
 284         * or1k-dis.c: Regenerate.
 285         * xc16x-dis.c: Regenerate.
 286         * xstormy16-dis.c: Regenerate.
 287
 288 2019-12-10  Alan Modra  <amodra@gmail.com>
 289
 290         * ppc-dis.c (private): Delete variable.
 291         (get_powerpc_dialect): Don't segfault on NULL info->private_data.
 292         (powerpc_init_dialect): Don't use global private.
 293
 294 2019-12-10  Alan Modra  <amodra@gmail.com>
 295
 296         * s12z-opc.c: Formatting.
 297
 298 2019-12-08  Alan Modra  <amodra@gmail.com>
 299
 300         * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
 301         registers.
 302
 303 2019-12-05  Jan Beulich  <jbeulich@suse.com>
 304
 305         * aarch64-tbl.h (aarch64_feature_crypto,
 306         aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
 307         CRYPTO_V8_2_INSN): Delete.
 308
 309 2019-12-05  Alan Modra  <amodra@gmail.com>
 310
 311         PR 25249
 312         * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
 313         (struct string_buf): New.
 314         (strbuf): New function.
 315         (get_field): Use strbuf rather than strdup of local temp.
 316         (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
 317         (get_field_rfsl, get_field_imm15): Likewise.
 318         (get_field_rd, get_field_r1, get_field_r2): Update macros.
 319         (get_field_special): Likewise.  Don't strcpy spr.  Formatting.
 320         (print_insn_microblaze): Formatting.  Init and pass string_buf to
 321         get_field functions.
 322
 323 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 324
 325         * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
 326         * i386-tbl.h: Re-generate.
 327
 328 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 329
 330         * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
 331
 332 2019-12-04  Jan Beulich  <jbeulich@suse.com>
 333
 334         * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
 335         forms.
 336         (xbegin): Drop DefaultSize.
 337         * i386-tbl.h: Re-generate.
 338
 339 2019-11-22  Mihail Ionescu  <mihail.ionescu@arm.com>
 340
 341         * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
 342         Change the coproc CRC conditions to use the extension
 343         feature set, second word, base on ARM_EXT2_CRC.
 344
 345 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 346
 347         * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
 348         * i386-tbl.h: Re-generate.
 349
 350 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 351
 352         * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
 353         JumpInterSegment, and JumpAbsolute entries.
 354         * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
 355         JUMP_ABSOLUTE): Define.
 356         (struct i386_opcode_modifier): Extend jump field to 3 bits.
 357         Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
 358         fields.
 359         * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
 360         JumpInterSegment): Define.
 361         * i386-tbl.h: Re-generate.
 362
 363 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 364
 365         * i386-gen.c (operand_type_init): Remove
 366         OPERAND_TYPE_JUMPABSOLUTE entry.
 367         (opcode_modifiers): Add JumpAbsolute entry.
 368         (operand_types): Remove JumpAbsolute entry.
 369         * i386-opc.h (JumpAbsolute): Move between enums.
 370         (struct i386_opcode_modifier): Add jumpabsolute field.
 371         (union i386_operand_type): Remove jumpabsolute field.
 372         * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
 373         * i386-init.h, i386-tbl.h: Re-generate.
 374
 375 2019-11-14  Jan Beulich  <jbeulich@suse.com>
 376
 377         * i386-gen.c (opcode_modifiers): Add AnySize entry.
 378         (operand_types): Remove AnySize entry.
 379         * i386-opc.h (AnySize): Move between enums.
 380         (struct i386_opcode_modifier): Add anysize field.
 381         (OTUnused): Un-comment.
 382         (union i386_operand_type): Remove anysize field.
 383         * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
 384         prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
 385         bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
 386         AnySize.
 387         * i386-tbl.h: Re-generate.
 388
 389 2019-11-12  Nelson Chu  <nelson.chu@sifive.com>
 390
 391         * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
 392         INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
 393         use the floating point register (FPR).
 394
 395 2019-11-12  Mihail Ionescu  <mihail.ionescu@arm.com>
 396
 397         * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
 398         cmode 1101.
 399         (is_mve_encoding_conflict): Update cmode conflict checks for
 400         MVE_VMVN_IMM.
 401
 402 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 403
 404         * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
 405         entry.
 406         (operand_types): Remove EsSeg entry.
 407         (main): Replace stale use of OTMax.
 408         * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
 409         (struct i386_opcode_modifier): Expand isstring field to 2 bits.
 410         (EsSeg): Delete.
 411         (OTUnused): Comment out.
 412         (union i386_operand_type): Remove esseg field.
 413         * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
 414         (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
 415         (ins, movs, smov, movsd): Add IsStringEsOpOp1.
 416         (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
 417         * i386-init.h, i386-tbl.h: Re-generate.
 418
 419 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 420
 421         * i386-gen.c (operand_instances): Add RegB entry.
 422         * i386-opc.h (enum operand_instance): Add RegB.
 423         * i386-opc.tbl (RegC, RegD, RegB): Define.
 424         (Acc, ShiftCount, InOutPortReg): Adjust definitions.
 425         (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
 426         monitorx, mwaitx): Drop ImmExt and convert encodings
 427         accordingly.
 428         * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
 429         (edx, rdx): Add Instance=RegD.
 430         (ebx, rbx): Add Instance=RegB.
 431         * i386-tbl.h: Re-generate.
 432
 433 2019-11-12  Jan Beulich  <jbeulich@suse.com>
 434
 435         * i386-gen.c (operand_type_init): Adjust
 436         OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
 437         OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
 438         OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
 439         (operand_instances): New.
 440         (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
 441         (output_operand_type): New parameter "instance". Process it.
 442         (process_i386_operand_type): New local variable "instance".
 443         (main): Adjust static assertions.
 444         * i386-opc.h (INSTANCE_WIDTH): Define.
 445         (enum operand_instance): New.
 446         (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
 447         (union i386_operand_type): Replace acc, inoutportreg, and
 448         shiftcount by instance.
 449         * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
 450         * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
 451         Add Instance=.
 452         * i386-init.h, i386-tbl.h: Re-generate.
 453
 454 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 455
 456         * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
 457         smaxp/sminp entries' "tied_operand" field to 2.
 458
 459 2019-11-11  Jan Beulich  <jbeulich@suse.com>
 460
 461         * aarch64-opc.c (operand_general_constraint_met_p): Replace
 462         "index" local variable by that of the already existing "num".
 463
 464 2019-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 465
 466         PR gas/25167
 467         * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
 468         * i386-tbl.h: Regenerated.
 469
 470 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 471
 472         * i386-gen.c (operand_type_init): Add Class= to
 473         OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
 474         OPERAND_TYPE_REGBND entry.
 475         (operand_classes): Add RegMask and RegBND entries.
 476         (operand_types): Drop RegMask and RegBND entry.
 477         * i386-opc.h (enum operand_class): Add RegMask and RegBND.
 478         (RegMask, RegBND): Delete.
 479         (union i386_operand_type): Remove regmask and regbnd fields.
 480         * i386-opc.tbl (RegMask, RegBND): Define.
 481         * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
 482         Class=RegBND.
 483         * i386-init.h, i386-tbl.h: Re-generate.
 484
 485 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 486
 487         * i386-gen.c (operand_type_init): Add Class= to
 488         OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
 489         OPERAND_TYPE_REGZMM entries.
 490         (operand_classes): Add RegMMX and RegSIMD entries.
 491         (operand_types): Drop RegMMX and RegSIMD entries.
 492         * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
 493         (RegMMX, RegSIMD): Delete.
 494         (union i386_operand_type): Remove regmmx and regsimd fields.
 495         * i386-opc.tbl (RegMMX): Define.
 496         (RegXMM, RegYMM, RegZMM): Add Class=.
 497         * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
 498         Class=RegSIMD.
 499         * i386-init.h, i386-tbl.h: Re-generate.
 500
 501 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 502
 503         * i386-gen.c (operand_type_init): Add Class= to
 504         OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
 505         entries.
 506         (operand_classes): Add RegCR, RegDR, and RegTR entries.
 507         (operand_types): Drop Control, Debug, and Test entries.
 508         * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
 509         (Control, Debug, Test): Delete.
 510         (union i386_operand_type): Remove control, debug, and test
 511         fields.
 512         * i386-opc.tbl (Control, Debug, Test): Define.
 513         * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
 514         Class=RegDR, and Test by Class=RegTR.
 515         * i386-init.h, i386-tbl.h: Re-generate.
 516
 517 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 518
 519         * i386-gen.c (operand_type_init): Add Class= to
 520         OPERAND_TYPE_SREG entry.
 521         (operand_classes): Add SReg entry.
 522         (operand_types): Drop SReg entry.
 523         * i386-opc.h (enum operand_class): Add SReg.
 524         (SReg): Delete.
 525         (union i386_operand_type): Remove sreg field.
 526         * i386-opc.tbl (SReg): Define.
 527         * i386-reg.tbl: Replace SReg by Class=SReg.
 528         * i386-init.h, i386-tbl.h: Re-generate.
 529
 530 2019-11-08  Jan Beulich  <jbeulich@suse.com>
 531
 532         * i386-gen.c (operand_type_init): Add Class=. New
 533         OPERAND_TYPE_ANYIMM entry.
 534         (operand_classes): New.
 535         (operand_types): Drop Reg entry.
 536         (output_operand_type): New parameter "class". Process it.
 537         (process_i386_operand_type): New local variable "class".
 538         (main): Adjust static assertions.
 539         * i386-opc.h (CLASS_WIDTH): Define.
 540         (enum operand_class): New.
 541         (Reg): Replace by Class. Adjust comment.
 542         (union i386_operand_type): Replace reg by class.
 543         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
 544         Class=.
 545         * i386-reg.tbl: Replace Reg by Class=Reg.
 546         * i386-init.h: Re-generate.
 547
 548 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 549
 550         * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
 551         (aarch64_opcode_table): Add data gathering hint mnemonic.
 552         * opcodes/aarch64-dis-2.c: Account for new instruction.
 553
 554 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 555
 556         * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
 557
 558
 559 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 560
 561         * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
 562         aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
 563         aarch64_feature_f64mm): New feature sets.
 564         (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
 565         F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
 566         instructions.
 567         (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
 568         macros.
 569         (QL_MMLA64, OP_SVE_SBB): New qualifiers.
 570         (OP_SVE_QQQ): New qualifier.
 571         (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
 572         F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
 573         the movprfx constraint.
 574         (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
 575         (aarch64_opcode_table): Define new instructions smmla,
 576         ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
 577         uzip{1/2}, trn{1/2}.
 578         * aarch64-opc.c (operand_general_constraint_met_p): Handle
 579         AARCH64_OPND_SVE_ADDR_RI_S4x32.
 580         (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
 581         * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
 582         Account for new instructions.
 583         * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
 584         S4x32 operand.
 585         * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
 586
 587 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 588 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 589
 590         * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
 591         Armv8.6-A.
 592         (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
 593         (neon_opcodes): Add bfloat SIMD instructions.
 594         (print_insn_coprocessor): Add new control character %b to print
 595         condition code without checking cp_num.
 596         (print_insn_neon): Account for BFloat16 instructions that have no
 597         special top-byte handling.
 598
 599 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 600 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 601
 602         * arm-dis.c (print_insn_coprocessor,
 603         print_insn_generic_coprocessor): Create wrapper functions around
 604         the implementation of the print_insn_coprocessor control codes.
 605         (print_insn_coprocessor_1): Original print_insn_coprocessor
 606         function that now takes which array to look at as an argument.
 607         (print_insn_arm): Use both print_insn_coprocessor and
 608         print_insn_generic_coprocessor.
 609         (print_insn_thumb32): As above.
 610
 611 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 612 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 613
 614         * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
 615         in reglane special case.
 616         * aarch64-dis-2.c (aarch64_opcode_lookup_1,
 617         aarch64_find_next_opcode): Account for new instructions.
 618         * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
 619         in reglane special case.
 620         * aarch64-opc.c (struct operand_qualifier_data): Add data for
 621         new AARCH64_OPND_QLF_S_2H qualifier.
 622         * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
 623         QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
 624         (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
 625         sets.
 626         (BFLOAT_SVE, BFLOAT): New feature set macros.
 627         (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
 628         instructions.
 629         (aarch64_opcode_table): Define new instructions bfdot,
 630         bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
 631         bfcvtn2, bfcvt.
 632
 633 2019-11-07  Mihail Ionescu  <mihail.ionescu@arm.com>
 634 2019-11-07  Matthew Malcomson  <matthew.malcomson@arm.com>
 635
 636         * aarch64-tbl.h (ARMV8_6): New macro.
 637
 638 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 639
 640         * i386-dis.c (prefix_table): Add mcommit.
 641         (rm_table): Add rdpru.
 642         * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
 643         CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
 644         (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
 645         * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
 646         (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
 647         * i386-opc.tbl (mcommit, rdpru): New.
 648         * i386-init.h, i386-tbl.h: Re-generate.
 649
 650 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 651
 652         * i386-dis.c (OP_Mwait): Drop local variable "names", use
 653         "names32" instead.
 654         (OP_Monitor): Drop local variable "op1_names", re-purpose
 655         "names" for it instead, and replace former "names" uses by
 656         "names32" ones.
 657
 658 2019-11-07  Jan Beulich  <jbeulich@suse.com>
 659
 660         PR/gas 25167
 661         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
 662         operand-less forms.
 663         * opcodes/i386-tbl.h: Re-generate.
 664
 665 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 666
 667         * i386-dis.c (OP_Mwaitx): Delete.
 668         (prefix_table): Use OP_Mwait for mwaitx entry.
 669         (OP_Mwait): Also handle mwaitx.
 670
 671 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 672
 673         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
 674         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
 675         (prefix_table): Add respective entries.
 676         (rm_table): Link to those entries.
 677
 678 2019-11-05  Jan Beulich  <jbeulich@suse.com>
 679
 680         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
 681         (REG_0F1C_P_0_MOD_0): ... this.
 682         (REG_0F1E_MOD_3): Rename to ...
 683         (REG_0F1E_P_1_MOD_3): ... this.
 684         (RM_0F01_REG_5): Rename to ...
 685         (RM_0F01_REG_5_MOD_3): ... this.
 686         (RM_0F01_REG_7): Rename to ...
 687         (RM_0F01_REG_7_MOD_3): ... this.
 688         (RM_0F1E_MOD_3_REG_7): Rename to ...
 689         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
 690         (RM_0FAE_REG_6): Rename to ...
 691         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
 692         (RM_0FAE_REG_7): Rename to ...
 693         (RM_0FAE_REG_7_MOD_3): ... this.
 694         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
 695         (PREFIX_0F01_REG_5_MOD_0): ... this.
 696         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
 697         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
 698         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
 699         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
 700         (PREFIX_0FAE_REG_0): Rename to ...
 701         (PREFIX_0FAE_REG_0_MOD_3): ... this.
 702         (PREFIX_0FAE_REG_1): Rename to ...
 703         (PREFIX_0FAE_REG_1_MOD_3): ... this.
 704         (PREFIX_0FAE_REG_2): Rename to ...
 705         (PREFIX_0FAE_REG_2_MOD_3): ... this.
 706         (PREFIX_0FAE_REG_3): Rename to ...
 707         (PREFIX_0FAE_REG_3_MOD_3): ... this.
 708         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
 709         (PREFIX_0FAE_REG_4_MOD_0): ... this.
 710         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
 711         (PREFIX_0FAE_REG_4_MOD_3): ... this.
 712         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
 713         (PREFIX_0FAE_REG_5_MOD_0): ... this.
 714         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
 715         (PREFIX_0FAE_REG_5_MOD_3): ... this.
 716         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
 717         (PREFIX_0FAE_REG_6_MOD_0): ... this.
 718         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
 719         (PREFIX_0FAE_REG_6_MOD_3): ... this.
 720         (PREFIX_0FAE_REG_7): Rename to ...
 721         (PREFIX_0FAE_REG_7_MOD_0): ... this.
 722         (PREFIX_MOD_0_0FC3): Rename to ...
 723         (PREFIX_0FC3_MOD_0): ... this.
 724         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
 725         (PREFIX_0FC7_REG_6_MOD_0): ... this.
 726         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
 727         (PREFIX_0FC7_REG_6_MOD_3): ... this.
 728         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
 729         (PREFIX_0FC7_REG_7_MOD_3): ... this.
 730         (reg_table, prefix_table, mod_table, rm_table): Adjust
 731         accordingly.
 732
 733 2019-11-04  Nick Clifton  <nickc@redhat.com>
 734
 735         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
 736         of a v850 system register.  Move the v850_sreg_names array into
 737         this function.
 738         (get_v850_reg_name): Likewise for ordinary register names.
 739         (get_v850_vreg_name): Likewise for vector register names.
 740         (get_v850_cc_name): Likewise for condition codes.
 741         * get_v850_float_cc_name): Likewise for floating point condition
 742         codes.
 743         (get_v850_cacheop_name): Likewise for cache-ops.
 744         (get_v850_prefop_name): Likewise for pref-ops.
 745         (disassemble): Use the new accessor functions.
 746
 747 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
 748
 749         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 750         immediate for the writeback form of ldraa/ldrab if it is 0.
 751         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 752         * aarch64-opc-2.c: Regenerated.
 753
 754 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 755
 756         * i386-gen.c (operand_type_shorthands): Delete.
 757         (operand_type_init): Expand previous shorthands.
 758         (set_bitfield_from_shorthand): Rename back to ...
 759         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 760         of operand_type_init[].
 761         (set_bitfield): Adjust call to the above function.
 762         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 763         RegXMM, RegYMM, RegZMM): Define.
 764         * i386-reg.tbl: Expand prior shorthands.
 765
 766 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 767
 768         * i386-gen.c (output_i386_opcode): Change order of fields
 769         emitted to output.
 770         * i386-opc.h (struct insn_template): Move operands field.
 771         Convert extension_opcode field to unsigned short.
 772         * i386-tbl.h: Re-generate.
 773
 774 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 775
 776         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 777         of W.
 778         * i386-opc.h (W): Extend comment.
 779         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 780         general purpose variants not allowing for byte operands.
 781         * i386-tbl.h: Re-generate.
 782
 783 2019-10-29  Nick Clifton  <nickc@redhat.com>
 784
 785         * tic30-dis.c (print_branch): Correct size of operand array.
 786
 787 2019-10-29  Nick Clifton  <nickc@redhat.com>
 788
 789         * d30v-dis.c (print_insn): Check that operand index is valid
 790         before attempting to access the operands array.
 791
 792 2019-10-29  Nick Clifton  <nickc@redhat.com>
 793
 794         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 795         locating the bit to be tested.
 796
 797 2019-10-29  Nick Clifton  <nickc@redhat.com>
 798
 799         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 800         values.
 801         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 802         (print_insn_s12z):  Check for illegal size values.
 803
 804 2019-10-28  Nick Clifton  <nickc@redhat.com>
 805
 806         * csky-dis.c (csky_chars_to_number): Check for a negative
 807         count. Use an unsigned integer to construct the return value.
 808
 809 2019-10-28  Nick Clifton  <nickc@redhat.com>
 810
 811         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 812         operand buffer.  Set value to 15 not 13.
 813         (get_register_operand): Use OPERAND_BUFFER_LEN.
 814         (get_indirect_operand): Likewise.
 815         (print_two_operand): Likewise.
 816         (print_three_operand): Likewise.
 817         (print_oar_insn): Likewise.
 818
 819 2019-10-28  Nick Clifton  <nickc@redhat.com>
 820
 821         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 822         (bit_extract_simple): Likewise.
 823         (bit_copy): Likewise.
 824         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 825         index_offset array are not accessed.
 826
 827 2019-10-28  Nick Clifton  <nickc@redhat.com>
 828
 829         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 830         operand.
 831
 832 2019-10-25  Nick Clifton  <nickc@redhat.com>
 833
 834         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 835         access to opcodes.op array element.
 836
 837 2019-10-23  Nick Clifton  <nickc@redhat.com>
 838
 839         * rx-dis.c (get_register_name): Fix spelling typo in error
 840         message.
 841         (get_condition_name, get_flag_name, get_double_register_name)
 842         (get_double_register_high_name, get_double_register_low_name)
 843         (get_double_control_register_name, get_double_condition_name)
 844         (get_opsize_name, get_size_name): Likewise.
 845
 846 2019-10-22  Nick Clifton  <nickc@redhat.com>
 847
 848         * rx-dis.c (get_size_name): New function.  Provides safe
 849         access to name array.
 850         (get_opsize_name): Likewise.
 851         (print_insn_rx): Use the accessor functions.
 852
 853 2019-10-16  Nick Clifton  <nickc@redhat.com>
 854
 855         * rx-dis.c (get_register_name): New function.  Provides safe
 856         access to name array.
 857         (get_condition_name, get_flag_name, get_double_register_name)
 858         (get_double_register_high_name, get_double_register_low_name)
 859         (get_double_control_register_name, get_double_condition_name):
 860         Likewise.
 861         (print_insn_rx): Use the accessor functions.
 862
 863 2019-10-09  Nick Clifton  <nickc@redhat.com>
 864
 865         PR 25041
 866         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 867         instructions.
 868
 869 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 870
 871         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 872         (cmpsd): Likewise. Move EsSeg to other operand.
 873         * opcodes/i386-tbl.h: Re-generate.
 874
 875 2019-09-23  Alan Modra  <amodra@gmail.com>
 876
 877         * m68k-dis.c: Include cpu-m68k.h
 878
 879 2019-09-23  Alan Modra  <amodra@gmail.com>
 880
 881         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 882         "elf/mips.h" earlier.
 883
 884 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 885
 886         PR gas/25012
 887         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 888         with SReg operand.
 889         * i386-tbl.h: Re-generate.
 890
 891 2019-09-18  Alan Modra  <amodra@gmail.com>
 892
 893         * arc-ext.c: Update throughout for bfd section macro changes.
 894
 895 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 896
 897         * Makefile.in: Re-generate.
 898         * configure: Re-generate.
 899
 900 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 901
 902         * riscv-opc.c (riscv_opcodes): Change subset field
 903         to insn_class field for all instructions.
 904         (riscv_insn_types): Likewise.
 905
 906 2019-09-16  Phil Blundell  <pb@pbcl.net>
 907
 908         * configure: Regenerated.
 909
 910 2019-09-10  Miod Vallat  <miod@online.fr>
 911
 912         PR 24982
 913         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 914
 915 2019-09-09  Phil Blundell  <pb@pbcl.net>
 916
 917         binutils 2.33 branch created.
 918
 919 2019-09-03  Nick Clifton  <nickc@redhat.com>
 920
 921         PR 24961
 922         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 923         greater than zero before indexing via (bufcnt -1).
 924
 925 2019-09-03  Nick Clifton  <nickc@redhat.com>
 926
 927         PR 24958
 928         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 929         (MAX_SPEC_REG_NAME_LEN): Define.
 930         (struct mmix_dis_info): Use defined constants for array lengths.
 931         (get_reg_name): New function.
 932         (get_sprec_reg_name): New function.
 933         (print_insn_mmix): Use new functions.
 934
 935 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 936
 937         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 938         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 939         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 940
 941 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 942
 943         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 944         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 945         (aarch64_sys_reg_supported_p): Update checks for the above.
 946
 947 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 948
 949         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 950         cases MVE_SQRSHRL and MVE_UQRSHLL.
 951         (print_insn_mve): Add case for specifier 'k' to check
 952         specific bit of the instruction.
 953
 954 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 955
 956         PR 24854
 957         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 958         encountering an unknown machine type.
 959         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 960         cases return -1 rather than calling abort.
 961
 962 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 963
 964         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 965         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 966         IgnoreSize.
 967         * i386-tbl.h: Re-generate.
 968
 969 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 970
 971         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 972         instructions.
 973
 974 2019-07-30  Mel Chen <mel.chen@sifive.com>
 975
 976         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 977         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 978
 979         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 980         fscsr.
 981
 982 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 983
 984         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 985         and MPY class instructions.
 986         (parse_option): Add nps400 option.
 987         (print_arc_disassembler_options): Add nps400 info.
 988
 989 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 990
 991         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 992         (bspop): Likewise.
 993         (modapp): Likewise.
 994         * arc-opc.c (RAD_CHK): Add.
 995         * arc-tbl.h: Regenerate.
 996
 997 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 998
 999         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
1000         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
1001
1002 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
1003
1004         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
1005         instructions as UNPREDICTABLE.
1006
1007 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
1008
1009         * bpf-desc.c: Regenerated.
1010
1011 2019-07-17  Jan Beulich  <jbeulich@suse.com>
1012
1013         * i386-gen.c (static_assert): Define.
1014         (main): Use it.
1015         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
1016         (Opcode_Modifier_Num): ... this.
1017         (Mem): Delete.
1018
1019 2019-07-16  Jan Beulich  <jbeulich@suse.com>
1020
1021         * i386-gen.c (operand_types): Move RegMem ...
1022         (opcode_modifiers): ... here.
1023         * i386-opc.h (RegMem): Move to opcode modifer enum.
1024         (union i386_operand_type): Move regmem field ...
1025         (struct i386_opcode_modifier): ... here.
1026         * i386-opc.tbl (RegMem): Define.
1027         (mov, movq): Move RegMem on segment, control, debug, and test
1028         register flavors.
1029         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
1030         to non-SSE2AVX flavor.
1031         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
1032         Move RegMem on register only flavors. Drop IgnoreSize from
1033         legacy encoding flavors.
1034         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
1035         flavors.
1036         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
1037         register only flavors.
1038         (vmovd): Move RegMem and drop IgnoreSize on register only
1039         flavor. Change opcode and operand order to store form.
1040         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1041
1042 2019-07-16  Jan Beulich  <jbeulich@suse.com>
1043
1044         * i386-gen.c (operand_type_init, operand_types): Replace SReg
1045         entries.
1046         * i386-opc.h (SReg2, SReg3): Replace by ...
1047         (SReg): ... this.
1048         (union i386_operand_type): Replace sreg fields.
1049         * i386-opc.tbl (mov, ): Use SReg.
1050         (push, pop): Likewies. Drop i386 and x86-64 specific segment
1051         register flavors.
1052         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
1053         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1054
1055 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
1056
1057         * bpf-desc.c: Regenerate.
1058         * bpf-opc.c: Likewise.
1059         * bpf-opc.h: Likewise.
1060
1061 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
1062
1063         * bpf-desc.c: Regenerate.
1064         * bpf-opc.c: Likewise.
1065
1066 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
1067
1068         * arm-dis.c (print_insn_coprocessor): Rename index to
1069         index_operand.
1070
1071 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
1072
1073         * riscv-opc.c (riscv_insn_types): Add r4 type.
1074
1075         * riscv-opc.c (riscv_insn_types): Add b and j type.
1076
1077         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
1078         format for sb type and correct s type.
1079
1080 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
1081
1082         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
1083         SVE FMOV alias of FCPY.
1084
1085 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
1086
1087         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
1088         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
1089
1090 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
1091
1092         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
1093         registers in an instruction prefixed by MOVPRFX.
1094
1095 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
1096
1097         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1098         sve_size_13 icode to account for variant behaviour of
1099         pmull{t,b}.
1100         * aarch64-dis-2.c: Regenerate.
1101         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1102         sve_size_13 icode to account for variant behaviour of
1103         pmull{t,b}.
1104         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1105         (OP_SVE_VVV_Q_D): Add new qualifier.
1106         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1107         (struct aarch64_opcode): Split pmull{t,b} into those requiring
1108         AES and those not.
1109
1110 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1111
1112         * opcodes/i386-gen.c (operand_type_init): Remove
1113         OPERAND_TYPE_VEC_IMM4 entry.
1114         (operand_types): Remove Vec_Imm4.
1115         * opcodes/i386-opc.h (Vec_Imm4): Delete.
1116         (union i386_operand_type): Remove vec_imm4.
1117         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1118         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1119
1120 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1121
1122         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1123         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1124         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1125         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1126         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1127         monitorx, mwaitx): Drop ImmExt from operand-less forms.
1128         * i386-tbl.h: Re-generate.
1129
1130 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1131
1132         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1133         register operands.
1134         * i386-tbl.h: Re-generate.
1135
1136 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1137
1138         * i386-opc.tbl (C): New.
1139         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1140         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1141         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1142         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1143         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1144         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1145         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1146         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1147         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1148         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1149         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1150         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1151         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1152         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1153         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1154         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1155         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1156         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1157         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1158         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1159         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1160         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1161         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1162         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1163         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1164         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1165         flavors.
1166         * i386-tbl.h: Re-generate.
1167
1168 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1169
1170         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1171         register operands.
1172         * i386-tbl.h: Re-generate.
1173
1174 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1175
1176         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1177         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1178         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1179         * i386-tbl.h: Re-generate.
1180
1181 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1182
1183         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1184         Disp8MemShift from register only templates.
1185         * i386-tbl.h: Re-generate.
1186
1187 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1188
1189         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1190         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1191         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1192         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1193         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1194         EVEX_W_0F11_P_3_M_1): Delete.
1195         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1196         EVEX_W_0F11_P_3): New.
1197         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1198         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1199         MOD_EVEX_0F11_PREFIX_3 table entries.
1200         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1201         PREFIX_EVEX_0F11 table entries.
1202         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1203         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1204         EVEX_W_0F11_P_3_M_{0,1} table entries.
1205
1206 2019-07-01  Jan Beulich  <jbeulich@suse.com>
1207
1208         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1209         Delete.
1210
1211 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
1212
1213         PR binutils/24719
1214         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1215         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1216         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1217         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1218         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1219         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1220         EVEX_LEN_0F38C7_R_6_P_2_W_1.
1221         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1222         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1223         PREFIX_EVEX_0F38C6_REG_6 entries.
1224         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1225         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1226         EVEX_W_0F38C7_R_6_P_2 entries.
1227         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1228         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1229         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1230         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1231         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1232         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1233         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1234
1235 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1236
1237         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1238         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1239         VEX_LEN_0F2D_P_3): Delete.
1240         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1241         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1242         (prefix_table): ... here.
1243
1244 2019-06-27  Jan Beulich  <jbeulich@suse.com>
1245
1246         * i386-dis.c (Iq): Delete.
1247         (Id): New.
1248         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1249         TBM insns.
1250         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1251         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1252         (OP_E_memory): Also honor needindex when deciding whether an
1253         address size prefix needs printing.
1254         (OP_I): Remove handling of q_mode. Add handling of d_mode.
1255
1256 2019-06-26  Jim Wilson  <jimw@sifive.com>
1257
1258         PR binutils/24739
1259         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1260         Set info->display_endian to info->endian_code.
1261
1262 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1263
1264         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1265         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1266         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1267         OPERAND_TYPE_ACC64 entries.
1268         * i386-init.h: Re-generate.
1269
1270 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1271
1272         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1273         Delete.
1274         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1275         of dqa_mode.
1276         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1277         entries here.
1278         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1279         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1280
1281 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1282
1283         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1284         variables.
1285
1286 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1287
1288         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1289         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1290         movnti.
1291         * i386-opc.tbl (movnti): Add IgnoreSize.
1292         * i386-tbl.h: Re-generate.
1293
1294 2019-06-25  Jan Beulich  <jbeulich@suse.com>
1295
1296         * i386-opc.tbl (and): Mark Imm8S form for optimization.
1297         * i386-tbl.h: Re-generate.
1298
1299 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
1300
1301         * i386-dis-evex.h: Break into ...
1302         * i386-dis-evex-len.h: New file.
1303         * i386-dis-evex-mod.h: Likewise.
1304         * i386-dis-evex-prefix.h: Likewise.
1305         * i386-dis-evex-reg.h: Likewise.
1306         * i386-dis-evex-w.h: Likewise.
1307         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1308         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1309         i386-dis-evex-mod.h.
1310
1311 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
1312
1313         PR binutils/24700
1314         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1315         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1316         EVEX_W_0F385B_P_2.
1317         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1318         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1319         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1320         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1321         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1322         EVEX_LEN_0F385B_P_2_W_1.
1323         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1324         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1325         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1326         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1327         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1328         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1329         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1330         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1331         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1332         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1333
1334 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
1335
1336         PR binutils/24691
1337         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1338         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1339         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1340         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1341         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1342         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1343         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1344         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1345         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1346         EVEX_LEN_0F3A43_P_2_W_1.
1347         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1348         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1349         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1350         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1351         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1352         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1353         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1354         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1355         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1356         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1357         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1358         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1359
1360 2019-06-14  Nick Clifton  <nickc@redhat.com>
1361
1362         * po/fr.po; Updated French translation.
1363
1364 2019-06-13  Stafford Horne  <shorne@gmail.com>
1365
1366         * or1k-asm.c: Regenerated.
1367         * or1k-desc.c: Regenerated.
1368         * or1k-desc.h: Regenerated.
1369         * or1k-dis.c: Regenerated.
1370         * or1k-ibld.c: Regenerated.
1371         * or1k-opc.c: Regenerated.
1372         * or1k-opc.h: Regenerated.
1373         * or1k-opinst.c: Regenerated.
1374
1375 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
1376
1377         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1378
1379 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
1380
1381         PR binutils/24633
1382         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1383         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1384         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1385         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1386         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1387         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1388         EVEX_LEN_0F3A1B_P_2_W_1.
1389         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1390         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1391         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1392         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1393         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1394         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1395         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1396         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1397
1398 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
1399
1400         PR binutils/24626
1401         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1402         EVEX.vvvv when disassembling VEX and EVEX instructions.
1403         (OP_VEX): Set vex.register_specifier to 0 after readding
1404         vex.register_specifier.
1405         (OP_Vex_2src_1): Likewise.
1406         (OP_Vex_2src_2): Likewise.
1407         (OP_LWP_E): Likewise.
1408         (OP_EX_Vex): Don't check vex.register_specifier.
1409         (OP_XMM_Vex): Likewise.
1410
1411 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
1412             Lili Cui  <lili.cui@intel.com>
1413
1414         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1415         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1416         instructions.
1417         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1418         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1419         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1420         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1421         (i386_cpu_flags): Add cpuavx512_vp2intersect.
1422         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1423         * i386-init.h: Regenerated.
1424         * i386-tbl.h: Likewise.
1425
1426 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
1427             Lili Cui  <lili.cui@intel.com>
1428
1429         * doc/c-i386.texi: Document enqcmd.
1430         * testsuite/gas/i386/enqcmd-intel.d: New file.
1431         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1432         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1433         * testsuite/gas/i386/enqcmd.d: Likewise.
1434         * testsuite/gas/i386/enqcmd.s: Likewise.
1435         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1436         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1437         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1438         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1439         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1440         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1441         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1442         and x86-64-enqcmd.
1443
1444 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
1445
1446         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1447
1448 2019-06-03  Alan Modra  <amodra@gmail.com>
1449
1450         * ppc-dis.c (prefix_opcd_indices): Correct size.
1451
1452 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
1453
1454         PR gas/24625
1455         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1456         Disp8ShiftVL.
1457         * i386-tbl.h: Regenerated.
1458
1459 2019-05-24  Alan Modra  <amodra@gmail.com>
1460
1461         * po/POTFILES.in: Regenerate.
1462
1463 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1464             Alan Modra  <amodra@gmail.com>
1465
1466         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1467         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1468         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1469         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1470         XTOP>): Define and add entries.
1471         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1472         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1473         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1474         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1475
1476 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
1477             Alan Modra  <amodra@gmail.com>
1478
1479         * ppc-dis.c (ppc_opts): Add "future" entry.
1480         (PREFIX_OPCD_SEGS): Define.
1481         (prefix_opcd_indices): New array.
1482         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1483         (lookup_prefix): New function.
1484         (print_insn_powerpc): Handle 64-bit prefix instructions.
1485         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1486         (PMRR, POWERXX): Define.
1487         (prefix_opcodes): New instruction table.
1488         (prefix_num_opcodes): New constant.
1489
1490 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
1491
1492         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1493         * configure: Regenerated.
1494         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1495         and cpu/bpf.opc.
1496         (HFILES): Add bpf-desc.h and bpf-opc.h.
1497         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1498         bpf-ibld.c and bpf-opc.c.
1499         (BPF_DEPS): Define.
1500         * Makefile.in: Regenerated.
1501         * disassemble.c (ARCH_bpf): Define.
1502         (disassembler): Add case for bfd_arch_bpf.
1503         (disassemble_init_for_target): Likewise.
1504         (enum epbf_isa_attr): Define.
1505         * disassemble.h: extern print_insn_bpf.
1506         * bpf-asm.c: Generated.
1507         * bpf-opc.h: Likewise.
1508         * bpf-opc.c: Likewise.
1509         * bpf-ibld.c: Likewise.
1510         * bpf-dis.c: Likewise.
1511         * bpf-desc.h: Likewise.
1512         * bpf-desc.c: Likewise.
1513
1514 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1515
1516         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1517         and VMSR with the new operands.
1518
1519 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1520
1521         * arm-dis.c (enum mve_instructions): New enum
1522         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1523         and cneg.
1524         (mve_opcodes): New instructions as above.
1525         (is_mve_encoding_conflict): Add cases for csinc, csinv,
1526         csneg and csel.
1527         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1528
1529 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
1530
1531         * arm-dis.c (emun mve_instructions): Updated for new instructions.
1532         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1533         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1534         uqshl, urshrl and urshr.
1535         (is_mve_okay_in_it): Add new instructions to TRUE list.
1536         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1537         (print_insn_mve): Updated to accept new %j,
1538         %<bitfield>m and %<bitfield>n patterns.
1539
1540 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1541
1542         * mips-opc.c (mips_builtin_opcodes): Change source register
1543         constraint for DAUI.
1544
1545 2019-05-20  Nick Clifton  <nickc@redhat.com>
1546
1547         * po/fr.po: Updated French translation.
1548
1549 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1550             Michael Collison <michael.collison@arm.com>
1551
1552         * arm-dis.c (thumb32_opcodes): Add new instructions.
1553         (enum mve_instructions): Likewise.
1554         (enum mve_undefined): Add new reasons.
1555         (is_mve_encoding_conflict): Handle new instructions.
1556         (is_mve_undefined): Likewise.
1557         (is_mve_unpredictable): Likewise.
1558         (print_mve_undefined): Likewise.
1559         (print_mve_size): Likewise.
1560
1561 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1562             Michael Collison <michael.collison@arm.com>
1563
1564         * arm-dis.c (thumb32_opcodes): Add new instructions.
1565         (enum mve_instructions): Likewise.
1566         (is_mve_encoding_conflict): Handle new instructions.
1567         (is_mve_undefined): Likewise.
1568         (is_mve_unpredictable): Likewise.
1569         (print_mve_size): Likewise.
1570
1571 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1572             Michael Collison <michael.collison@arm.com>
1573
1574         * arm-dis.c (thumb32_opcodes): Add new instructions.
1575         (enum mve_instructions): Likewise.
1576         (is_mve_encoding_conflict): Likewise.
1577         (is_mve_unpredictable): Likewise.
1578         (print_mve_size): Likewise.
1579
1580 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1581             Michael Collison <michael.collison@arm.com>
1582
1583         * arm-dis.c (thumb32_opcodes): Add new instructions.
1584         (enum mve_instructions): Likewise.
1585         (is_mve_encoding_conflict): Handle new instructions.
1586         (is_mve_undefined): Likewise.
1587         (is_mve_unpredictable): Likewise.
1588         (print_mve_size): Likewise.
1589
1590 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1591             Michael Collison <michael.collison@arm.com>
1592
1593         * arm-dis.c (thumb32_opcodes): Add new instructions.
1594         (enum mve_instructions): Likewise.
1595         (is_mve_encoding_conflict): Handle new instructions.
1596         (is_mve_undefined): Likewise.
1597         (is_mve_unpredictable): Likewise.
1598         (print_mve_size): Likewise.
1599         (print_insn_mve): Likewise.
1600
1601 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1602             Michael Collison <michael.collison@arm.com>
1603
1604         * arm-dis.c (thumb32_opcodes): Add new instructions.
1605         (print_insn_thumb32): Handle new instructions.
1606
1607 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1608             Michael Collison <michael.collison@arm.com>
1609
1610         * arm-dis.c (enum mve_instructions): Add new instructions.
1611         (enum mve_undefined): Add new reasons.
1612         (is_mve_encoding_conflict): Handle new instructions.
1613         (is_mve_undefined): Likewise.
1614         (is_mve_unpredictable): Likewise.
1615         (print_mve_undefined): Likewise.
1616         (print_mve_size): Likewise.
1617         (print_mve_shift_n): Likewise.
1618         (print_insn_mve): Likewise.
1619
1620 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1621             Michael Collison <michael.collison@arm.com>
1622
1623         * arm-dis.c (enum mve_instructions): Add new instructions.
1624         (is_mve_encoding_conflict): Handle new instructions.
1625         (is_mve_unpredictable): Likewise.
1626         (print_mve_rotate): Likewise.
1627         (print_mve_size): Likewise.
1628         (print_insn_mve): Likewise.
1629
1630 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1631             Michael Collison <michael.collison@arm.com>
1632
1633         * arm-dis.c (enum mve_instructions): Add new instructions.
1634         (is_mve_encoding_conflict): Handle new instructions.
1635         (is_mve_unpredictable): Likewise.
1636         (print_mve_size): Likewise.
1637         (print_insn_mve): Likewise.
1638
1639 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1640             Michael Collison <michael.collison@arm.com>
1641
1642         * arm-dis.c (enum mve_instructions): Add new instructions.
1643         (enum mve_undefined): Add new reasons.
1644         (is_mve_encoding_conflict): Handle new instructions.
1645         (is_mve_undefined): Likewise.
1646         (is_mve_unpredictable): Likewise.
1647         (print_mve_undefined): Likewise.
1648         (print_mve_size): Likewise.
1649         (print_insn_mve): Likewise.
1650
1651 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1652             Michael Collison <michael.collison@arm.com>
1653
1654         * arm-dis.c (enum mve_instructions): Add new instructions.
1655         (is_mve_encoding_conflict): Handle new instructions.
1656         (is_mve_undefined): Likewise.
1657         (is_mve_unpredictable): Likewise.
1658         (print_mve_size): Likewise.
1659         (print_insn_mve): Likewise.
1660
1661 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1662             Michael Collison <michael.collison@arm.com>
1663
1664         * arm-dis.c (enum mve_instructions): Add new instructions.
1665         (enum mve_unpredictable): Add new reasons.
1666         (enum mve_undefined): Likewise.
1667         (is_mve_okay_in_it): Handle new isntructions.
1668         (is_mve_encoding_conflict): Likewise.
1669         (is_mve_undefined): Likewise.
1670         (is_mve_unpredictable): Likewise.
1671         (print_mve_vmov_index): Likewise.
1672         (print_simd_imm8): Likewise.
1673         (print_mve_undefined): Likewise.
1674         (print_mve_unpredictable): Likewise.
1675         (print_mve_size): Likewise.
1676         (print_insn_mve): Likewise.
1677
1678 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1679             Michael Collison <michael.collison@arm.com>
1680
1681         * arm-dis.c (enum mve_instructions): Add new instructions.
1682         (enum mve_unpredictable): Add new reasons.
1683         (enum mve_undefined): Likewise.
1684         (is_mve_encoding_conflict): Handle new instructions.
1685         (is_mve_undefined): Likewise.
1686         (is_mve_unpredictable): Likewise.
1687         (print_mve_undefined): Likewise.
1688         (print_mve_unpredictable): Likewise.
1689         (print_mve_rounding_mode): Likewise.
1690         (print_mve_vcvt_size): Likewise.
1691         (print_mve_size): Likewise.
1692         (print_insn_mve): Likewise.
1693
1694 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1695             Michael Collison <michael.collison@arm.com>
1696
1697         * arm-dis.c (enum mve_instructions): Add new instructions.
1698         (enum mve_unpredictable): Add new reasons.
1699         (enum mve_undefined): Likewise.
1700         (is_mve_undefined): Handle new instructions.
1701         (is_mve_unpredictable): Likewise.
1702         (print_mve_undefined): Likewise.
1703         (print_mve_unpredictable): Likewise.
1704         (print_mve_size): Likewise.
1705         (print_insn_mve): Likewise.
1706
1707 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1708             Michael Collison <michael.collison@arm.com>
1709
1710         * arm-dis.c (enum mve_instructions): Add new instructions.
1711         (enum mve_undefined): Add new reasons.
1712         (insns): Add new instructions.
1713         (is_mve_encoding_conflict):
1714         (print_mve_vld_str_addr): New print function.
1715         (is_mve_undefined): Handle new instructions.
1716         (is_mve_unpredictable): Likewise.
1717         (print_mve_undefined): Likewise.
1718         (print_mve_size): Likewise.
1719         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1720         (print_insn_mve):  Handle new operands.
1721
1722 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1723             Michael Collison <michael.collison@arm.com>
1724
1725         * arm-dis.c (enum mve_instructions): Add new instructions.
1726         (enum mve_unpredictable): Add new reasons.
1727         (is_mve_encoding_conflict): Handle new instructions.
1728         (is_mve_unpredictable): Likewise.
1729         (mve_opcodes): Add new instructions.
1730         (print_mve_unpredictable): Handle new reasons.
1731         (print_mve_register_blocks): New print function.
1732         (print_mve_size): Handle new instructions.
1733         (print_insn_mve): Likewise.
1734
1735 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1736             Michael Collison <michael.collison@arm.com>
1737
1738         * arm-dis.c (enum mve_instructions): Add new instructions.
1739         (enum mve_unpredictable): Add new reasons.
1740         (enum mve_undefined): Likewise.
1741         (is_mve_encoding_conflict): Handle new instructions.
1742         (is_mve_undefined): Likewise.
1743         (is_mve_unpredictable): Likewise.
1744         (coprocessor_opcodes): Move NEON VDUP from here...
1745         (neon_opcodes): ... to here.
1746         (mve_opcodes): Add new instructions.
1747         (print_mve_undefined):  Handle new reasons.
1748         (print_mve_unpredictable): Likewise.
1749         (print_mve_size): Handle new instructions.
1750         (print_insn_neon): Handle vdup.
1751         (print_insn_mve): Handle new operands.
1752
1753 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1754             Michael Collison <michael.collison@arm.com>
1755
1756         * arm-dis.c (enum mve_instructions): Add new instructions.
1757         (enum mve_unpredictable): Add new values.
1758         (mve_opcodes): Add new instructions.
1759         (vec_condnames): New array with vector conditions.
1760         (mve_predicatenames): New array with predicate suffixes.
1761         (mve_vec_sizename): New array with vector sizes.
1762         (enum vpt_pred_state): New enum with vector predication states.
1763         (struct vpt_block): New struct type for vpt blocks.
1764         (vpt_block_state): Global struct to keep track of state.
1765         (mve_extract_pred_mask): New helper function.
1766         (num_instructions_vpt_block): Likewise.
1767         (mark_outside_vpt_block): Likewise.
1768         (mark_inside_vpt_block): Likewise.
1769         (invert_next_predicate_state): Likewise.
1770         (update_next_predicate_state): Likewise.
1771         (update_vpt_block_state): Likewise.
1772         (is_vpt_instruction): Likewise.
1773         (is_mve_encoding_conflict): Add entries for new instructions.
1774         (is_mve_unpredictable): Likewise.
1775         (print_mve_unpredictable): Handle new cases.
1776         (print_instruction_predicate): Likewise.
1777         (print_mve_size): New function.
1778         (print_vec_condition): New function.
1779         (print_insn_mve): Handle vpt blocks and new print operands.
1780
1781 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1782
1783         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1784         8, 14 and 15 for Armv8.1-M Mainline.
1785
1786 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1787             Michael Collison <michael.collison@arm.com>
1788
1789         * arm-dis.c (enum mve_instructions): New enum.
1790         (enum mve_unpredictable): Likewise.
1791         (enum mve_undefined): Likewise.
1792         (struct mopcode32): New struct.
1793         (is_mve_okay_in_it): New function.
1794         (is_mve_architecture): Likewise.
1795         (arm_decode_field): Likewise.
1796         (arm_decode_field_multiple): Likewise.
1797         (is_mve_encoding_conflict): Likewise.
1798         (is_mve_undefined): Likewise.
1799         (is_mve_unpredictable): Likewise.
1800         (print_mve_undefined): Likewise.
1801         (print_mve_unpredictable): Likewise.
1802         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1803         (print_insn_mve): New function.
1804         (print_insn_thumb32): Handle MVE architecture.
1805         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1806
1807 2019-05-10  Nick Clifton  <nickc@redhat.com>
1808
1809         PR 24538
1810         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1811         end of the table prematurely.
1812
1813 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1814
1815         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1816         macros for R6.
1817
1818 2019-05-11  Alan Modra  <amodra@gmail.com>
1819
1820         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1821         when -Mraw is in effect.
1822
1823 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1824
1825         * aarch64-dis-2.c: Regenerate.
1826         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1827         (OP_SVE_BBB): New variant set.
1828         (OP_SVE_DDDD): New variant set.
1829         (OP_SVE_HHH): New variant set.
1830         (OP_SVE_HHHU): New variant set.
1831         (OP_SVE_SSS): New variant set.
1832         (OP_SVE_SSSU): New variant set.
1833         (OP_SVE_SHH): New variant set.
1834         (OP_SVE_SBBU): New variant set.
1835         (OP_SVE_DSS): New variant set.
1836         (OP_SVE_DHHU): New variant set.
1837         (OP_SVE_VMV_HSD_BHS): New variant set.
1838         (OP_SVE_VVU_HSD_BHS): New variant set.
1839         (OP_SVE_VVVU_SD_BH): New variant set.
1840         (OP_SVE_VVVU_BHSD): New variant set.
1841         (OP_SVE_VVV_QHD_DBS): New variant set.
1842         (OP_SVE_VVV_HSD_BHS): New variant set.
1843         (OP_SVE_VVV_HSD_BHS2): New variant set.
1844         (OP_SVE_VVV_BHS_HSD): New variant set.
1845         (OP_SVE_VV_BHS_HSD): New variant set.
1846         (OP_SVE_VVV_SD): New variant set.
1847         (OP_SVE_VVU_BHS_HSD): New variant set.
1848         (OP_SVE_VZVV_SD): New variant set.
1849         (OP_SVE_VZVV_BH): New variant set.
1850         (OP_SVE_VZV_SD): New variant set.
1851         (aarch64_opcode_table): Add sve2 instructions.
1852
1853 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1854
1855         * aarch64-asm-2.c: Regenerated.
1856         * aarch64-dis-2.c: Regenerated.
1857         * aarch64-opc-2.c: Regenerated.
1858         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1859         for SVE_SHLIMM_UNPRED_22.
1860         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1861         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1862         operand.
1863
1864 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1865
1866         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1867         sve_size_tsz_bhs iclass encode.
1868         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1869         sve_size_tsz_bhs iclass decode.
1870
1871 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1872
1873         * aarch64-asm-2.c: Regenerated.
1874         * aarch64-dis-2.c: Regenerated.
1875         * aarch64-opc-2.c: Regenerated.
1876         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1877         for SVE_Zm4_11_INDEX.
1878         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1879         (fields): Handle SVE_i2h field.
1880         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1881         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1882
1883 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1884
1885         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1886         sve_shift_tsz_bhsd iclass encode.
1887         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1888         sve_shift_tsz_bhsd iclass decode.
1889
1890 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1891
1892         * aarch64-asm-2.c: Regenerated.
1893         * aarch64-dis-2.c: Regenerated.
1894         * aarch64-opc-2.c: Regenerated.
1895         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1896         (aarch64_encode_variant_using_iclass): Handle
1897         sve_shift_tsz_hsd iclass encode.
1898         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1899         sve_shift_tsz_hsd iclass decode.
1900         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1901         for SVE_SHRIMM_UNPRED_22.
1902         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1903         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1904         operand.
1905
1906 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1907
1908         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1909         sve_size_013 iclass encode.
1910         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1911         sve_size_013 iclass decode.
1912
1913 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1914
1915         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1916         sve_size_bh iclass encode.
1917         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1918         sve_size_bh iclass decode.
1919
1920 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1921
1922         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1923         sve_size_sd2 iclass encode.
1924         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1925         sve_size_sd2 iclass decode.
1926         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1927         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1928
1929 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1930
1931         * aarch64-asm-2.c: Regenerated.
1932         * aarch64-dis-2.c: Regenerated.
1933         * aarch64-opc-2.c: Regenerated.
1934         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1935         for SVE_ADDR_ZX.
1936         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1937         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1938
1939 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1940
1941         * aarch64-asm-2.c: Regenerated.
1942         * aarch64-dis-2.c: Regenerated.
1943         * aarch64-opc-2.c: Regenerated.
1944         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1945         for SVE_Zm3_11_INDEX.
1946         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1947         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1948         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1949         fields.
1950         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1951
1952 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1953
1954         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1955         sve_size_hsd2 iclass encode.
1956         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1957         sve_size_hsd2 iclass decode.
1958         * aarch64-opc.c (fields): Handle SVE_size field.
1959         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1960
1961 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1962
1963         * aarch64-asm-2.c: Regenerated.
1964         * aarch64-dis-2.c: Regenerated.
1965         * aarch64-opc-2.c: Regenerated.
1966         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1967         for SVE_IMM_ROT3.
1968         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1969         (fields): Handle SVE_rot3 field.
1970         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1971         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1972
1973 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1974
1975         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1976         instructions.
1977
1978 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1979
1980         * aarch64-tbl.h
1981         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1982         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1983         aarch64_feature_sve2bitperm): New feature sets.
1984         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1985         for feature set addresses.
1986         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1987         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1988
1989 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1990             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1991
1992         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1993         argument and set ASE_EVA_R6 appropriately.
1994         (set_default_mips_dis_options): Pass ISA to above.
1995         (parse_mips_dis_option): Likewise.
1996         * mips-opc.c (EVAR6): New macro.
1997         (mips_builtin_opcodes): Add llwpe, scwpe.
1998
1999 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
2000
2001         * aarch64-asm-2.c: Regenerated.
2002         * aarch64-dis-2.c: Regenerated.
2003         * aarch64-opc-2.c: Regenerated.
2004         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
2005         AARCH64_OPND_TME_UIMM16.
2006         (aarch64_print_operand): Likewise.
2007         * aarch64-tbl.h (QL_IMM_NIL): New.
2008         (TME): New.
2009         (_TME_INSN): New.
2010         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
2011
2012 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
2013
2014         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
2015
2016 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
2017             Faraz Shahbazker  <fshahbazker@wavecomp.com>
2018
2019         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
2020
2021 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
2022
2023         * s12z-opc.h: Add extern "C" bracketing to help
2024         users who wish to use this interface in c++ code.
2025
2026 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
2027
2028         * s12z-opc.c (bm_decode): Handle bit map operations with the
2029         "reserved0" mode.
2030
2031 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2032
2033         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
2034         specifier.  Add entries for VLDR and VSTR of system registers.
2035         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
2036         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
2037         of %J and %K format specifier.
2038
2039 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2040
2041         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
2042         Add new entries for VSCCLRM instruction.
2043         (print_insn_coprocessor): Handle new %C format control code.
2044
2045 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2046
2047         * arm-dis.c (enum isa): New enum.
2048         (struct sopcode32): New structure.
2049         (coprocessor_opcodes): change type of entries to struct sopcode32 and
2050         set isa field of all current entries to ANY.
2051         (print_insn_coprocessor): Change type of insn to struct sopcode32.
2052         Only match an entry if its isa field allows the current mode.
2053
2054 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2055
2056         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
2057         CLRM.
2058         (print_insn_thumb32): Add logic to print %n CLRM register list.
2059
2060 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2061
2062         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
2063         and %Q patterns.
2064
2065 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2066
2067         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
2068         (print_insn_thumb32): Edit the switch case for %Z.
2069
2070 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2071
2072         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2073
2074 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2075
2076         * arm-dis.c (thumb32_opcodes): New instruction bfl.
2077
2078 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2079
2080         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2081
2082 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2083
2084         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
2085         Arm register with r13 and r15 unpredictable.
2086         (thumb32_opcodes): New instructions for bfx and bflx.
2087
2088 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2089
2090         * arm-dis.c (thumb32_opcodes): New instructions for bf.
2091
2092 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2093
2094         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2095
2096 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
2097
2098         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2099
2100 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
2101
2102         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2103
2104 2019-04-12  John Darrington <john@darrington.wattle.id.au>
2105
2106         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2107         "optr". ("operator" is a reserved word in c++).
2108
2109 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
2110
2111         * aarch64-opc.c (aarch64_print_operand): Add case for
2112         AARCH64_OPND_Rt_SP.
2113         (verify_constraints): Likewise.
2114         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2115         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2116         to accept Rt|SP as first operand.
2117         (AARCH64_OPERANDS): Add new Rt_SP.
2118         * aarch64-asm-2.c: Regenerated.
2119         * aarch64-dis-2.c: Regenerated.
2120         * aarch64-opc-2.c: Regenerated.
2121
2122 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
2123
2124         * aarch64-asm-2.c: Regenerated.
2125         * aarch64-dis-2.c: Likewise.
2126         * aarch64-opc-2.c: Likewise.
2127         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2128
2129 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
2130
2131         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2132
2133 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
2134
2135         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2136         * i386-init.h: Regenerated.
2137
2138 2019-04-07  Alan Modra  <amodra@gmail.com>
2139
2140         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2141         op_separator to control printing of spaces, comma and parens
2142         rather than need_comma, need_paren and spaces vars.
2143
2144 2019-04-07  Alan Modra  <amodra@gmail.com>
2145
2146         PR 24421
2147         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2148         (print_insn_neon, print_insn_arm): Likewise.
2149
2150 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
2151
2152         * i386-dis-evex.h (evex_table): Updated to support BF16
2153         instructions.
2154         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2155         and EVEX_W_0F3872_P_3.
2156         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2157         (cpu_flags): Add bitfield for CpuAVX512_BF16.
2158         * i386-opc.h (enum): Add CpuAVX512_BF16.
2159         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2160         * i386-opc.tbl: Add AVX512 BF16 instructions.
2161         * i386-init.h: Regenerated.
2162         * i386-tbl.h: Likewise.
2163
2164 2019-04-05  Alan Modra  <amodra@gmail.com>
2165
2166         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2167         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2168         to favour printing of "-" branch hint when using the "y" bit.
2169         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2170
2171 2019-04-05  Alan Modra  <amodra@gmail.com>
2172
2173         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2174         opcode until first operand is output.
2175
2176 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
2177
2178         PR gas/24349
2179         * ppc-opc.c (valid_bo_pre_v2): Add comments.
2180         (valid_bo_post_v2): Add support for 'at' branch hints.
2181         (insert_bo): Only error on branch on ctr.
2182         (get_bo_hint_mask): New function.
2183         (insert_boe): Add new 'branch_taken' formal argument.  Add support
2184         for inserting 'at' branch hints.
2185         (extract_boe): Add new 'branch_taken' formal argument.  Add support
2186         for extracting 'at' branch hints.
2187         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2188         (BOE): Delete operand.
2189         (BOM, BOP): New operands.
2190         (RM): Update value.
2191         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2192         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2193         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2194         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2195         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2196         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2197         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2198         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2199         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2200         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2201         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2202         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2203         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2204         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2205         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2206         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2207         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2208         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2209         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2210         bttarl+>: New extended mnemonics.
2211
2212 2019-03-28  Alan Modra  <amodra@gmail.com>
2213
2214         PR 24390
2215         * ppc-opc.c (BTF): Define.
2216         (powerpc_opcodes): Use for mtfsb*.
2217         * ppc-dis.c (print_insn_powerpc): Print fields with both
2218         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2219
2220 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2221
2222         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2223         (mapping_symbol_for_insn): Implement new algorithm.
2224         (print_insn): Remove duplicate code.
2225
2226 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2227
2228         * aarch64-dis.c (print_insn_aarch64):
2229         Implement override.
2230
2231 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2232
2233         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2234         order.
2235
2236 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
2237
2238         * aarch64-dis.c (last_stop_offset): New.
2239         (print_insn_aarch64): Use stop_offset.
2240
2241 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
2242
2243         PR gas/24359
2244         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2245         CPU_ANY_AVX2_FLAGS.
2246         * i386-init.h: Regenerated.
2247
2248 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
2249
2250         PR gas/24348
2251         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2252         vmovdqu16, vmovdqu32 and vmovdqu64.
2253         * i386-tbl.h: Regenerated.
2254
2255 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2256
2257         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
2258         from vstrszb, vstrszh, and vstrszf.
2259
2260 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
2261
2262         * s390-opc.txt: Add instruction descriptions.
2263
2264 2019-02-08  Jim Wilson  <jimw@sifive.com>
2265
2266         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2267         <bne>: Likewise.
2268
2269 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2270
2271         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2272
2273 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
2274
2275         PR binutils/23212
2276         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2277         * aarch64-opc.c (verify_elem_sd): New.
2278         (fields): Add FLD_sz entr.
2279         * aarch64-tbl.h (_SIMD_INSN): New.
2280         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2281         fmulx scalar and vector by element isns.
2282
2283 2019-02-07  Nick Clifton  <nickc@redhat.com>
2284
2285         * po/sv.po: Updated Swedish translation.
2286
2287 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
2288
2289         * s390-mkopc.c (main): Accept arch13 as cpu string.
2290         * s390-opc.c: Add new instruction formats and instruction opcode
2291         masks.
2292         * s390-opc.txt: Add new arch13 instructions.
2293
2294 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2295
2296         * aarch64-tbl.h (QL_LDST_AT): Update macro.
2297         (aarch64_opcode): Change encoding for stg, stzg
2298         st2g and st2zg.
2299         * aarch64-asm-2.c: Regenerated.
2300         * aarch64-dis-2.c: Regenerated.
2301         * aarch64-opc-2.c: Regenerated.
2302
2303 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2304
2305         * aarch64-asm-2.c: Regenerated.
2306         * aarch64-dis-2.c: Likewise.
2307         * aarch64-opc-2.c: Likewise.
2308         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2309
2310 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
2311             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
2312
2313         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2314         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2315         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2316         * aarch64-dis.h (ext_addr_simple_2): Likewise.
2317         * aarch64-opc.c (operand_general_constraint_met_p): Remove
2318         case for ldstgv_indexed.
2319         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2320         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2321         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2322         * aarch64-asm-2.c: Regenerated.
2323         * aarch64-dis-2.c: Regenerated.
2324         * aarch64-opc-2.c: Regenerated.
2325
2326 2019-01-23  Nick Clifton  <nickc@redhat.com>
2327
2328         * po/pt_BR.po: Updated Brazilian Portuguese translation.
2329
2330 2019-01-21  Nick Clifton  <nickc@redhat.com>
2331
2332         * po/de.po: Updated German translation.
2333         * po/uk.po: Updated Ukranian translation.
2334
2335 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
2336         * mips-dis.c (mips_arch_choices): Fix typo in
2337         gs464, gs464e and gs264e descriptors.
2338
2339 2019-01-19  Nick Clifton  <nickc@redhat.com>
2340
2341         * configure: Regenerate.
2342         * po/opcodes.pot: Regenerate.
2343
2344 2018-06-24  Nick Clifton  <nickc@redhat.com>
2345
2346         2.32 branch created.
2347
2348 2019-01-09  John Darrington <john@darrington.wattle.id.au>
2349
2350         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
2351         if it is null.
2352         -dis.c (opr_emit_disassembly): Do not omit an index if it is
2353         zero.
2354
2355 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
2356
2357         * configure: Regenerate.
2358
2359 2019-01-07  Alan Modra  <amodra@gmail.com>
2360
2361         * configure: Regenerate.
2362         * po/POTFILES.in: Regenerate.
2363
2364 2019-01-03  John Darrington <john@darrington.wattle.id.au>
2365
2366         * s12z-opc.c: New file.
2367         * s12z-opc.h: New file.
2368         * s12z-dis.c: Removed all code not directly related to display
2369         of instructions.  Used the interface provided by the new files
2370         instead.
2371         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
2372         * Makefile.in: Regenerate.
2373         * configure.ac (bfd_s12z_arch): Correct the dependencies.
2374         * configure: Regenerate.
2375
2376 2019-01-01  Alan Modra  <amodra@gmail.com>
2377
2378         Update year range in copyright notice of all files.
2379
2380 For older changes see ChangeLog-2018
2381 \f
2382 Copyright (C) 2019 Free Software Foundation, Inc.
2383
2384 Copying and distribution of this file, with or without modification,
2385 are permitted in any medium without royalty provided the copyright
2386 notice and this notice are preserved.
2387
2388 Local Variables:
2389 mode: change-log
2390 left-margin: 8
2391 fill-column: 74
2392 version-control: never
2393 End: