opcodes/ChangeLog

   1 2017-04-21  Nick Clifton  <nickc@redhat.com>
   2
   3         PR binutils/21380
   4         * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
   5         LD3R and LD4R.
   6
   7 2017-04-13  Alan Modra  <amodra@gmail.com>
   8
   9         * epiphany-desc.c: Regenerate.
  10         * fr30-desc.c: Regenerate.
  11         * frv-desc.c: Regenerate.
  12         * ip2k-desc.c: Regenerate.
  13         * iq2000-desc.c: Regenerate.
  14         * lm32-desc.c: Regenerate.
  15         * m32c-desc.c: Regenerate.
  16         * m32r-desc.c: Regenerate.
  17         * mep-desc.c: Regenerate.
  18         * mt-desc.c: Regenerate.
  19         * or1k-desc.c: Regenerate.
  20         * xc16x-desc.c: Regenerate.
  21         * xstormy16-desc.c: Regenerate.
  22
  23 2017-04-11  Alan Modra  <amodra@gmail.com>
  24
  25         * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
  26         PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".  Formatting.  Set
  27         PPC_OPCODE_TMR for e6500.
  28         * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
  29         (PPCVEC3): Define as PPC_OPCODE_POWER9.
  30         (PPCVSX2): Define as PPC_OPCODE_POWER8.
  31         (PPCVSX3): Define as PPC_OPCODE_POWER9.
  32         (PPCHTM): Define as PPC_OPCODE_POWER8.
  33         (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
  34
  35 2017-04-10  Alan Modra  <amodra@gmail.com>
  36
  37         * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
  38         * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
  39         (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
  40         removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
  41
  42 2017-04-09  Pip Cet  <pipcet@gmail.com>
  43
  44         * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
  45         appropriate floating-point precision directly.
  46
  47 2017-04-07  Alan Modra  <amodra@gmail.com>
  48
  49         * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
  50         lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
  51         lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
  52         lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
  53         vector instructions with E6500 not PPCVEC2.
  54
  55 2017-04-06  Pip Cet  <pipcet@gmail.com>
  56
  57         * Makefile.am: Add wasm32-dis.c.
  58         * configure.ac: Add wasm32-dis.c to wasm32 target.
  59         * disassemble.c: Add wasm32 disassembler code.
  60         * wasm32-dis.c: New file.
  61         * Makefile.in: Regenerate.
  62         * configure: Regenerate.
  63         * po/POTFILES.in: Regenerate.
  64         * po/opcodes.pot: Regenerate.
  65
  66 2017-04-05  Pedro Alves  <palves@redhat.com>
  67
  68         * arc-dis.c (parse_option, parse_disassembler_options): Constify.
  69         * arm-dis.c (parse_arm_disassembler_options): Constify.
  70         * ppc-dis.c (powerpc_init_dialect): Constify local.
  71         * vax-dis.c (parse_disassembler_options): Constify.
  72
  73 2017-04-03  Palmer Dabbelt  <palmer@dabbelt.com>
  74
  75         * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
  76         RISCV_GP_SYMBOL.
  77
  78 2017-03-30  Pip Cet  <pipcet@gmail.com>
  79
  80         * configure.ac: Add (empty) bfd_wasm32_arch target.
  81         * configure: Regenerate
  82         * po/opcodes.pot: Regenerate.
  83
  84 2017-03-29  Sheldon Lobo  <sheldon.lobo@oracle.com>
  85
  86         Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
  87         OSA2015.
  88         * opcodes/sparc-opc.c (asi_table): New ASIs.
  89
  90 2017-03-29  Alan Modra  <amodra@gmail.com>
  91
  92         * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
  93         "raw" option.
  94         (lookup_powerpc): Don't special case -1 dialect.  Handle
  95         PPC_OPCODE_RAW.
  96         (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
  97         lookup_powerpc call, pass it on second.
  98
  99 2017-03-27  Alan Modra  <amodra@gmail.com>
 100
 101         PR 21303
 102         * ppc-dis.c (struct ppc_mopt): Comment.
 103         (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
 104
 105 2017-03-27  Rinat Zelig  <rinat@mellanox.com>
 106
 107         * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
 108         * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
 109         F_NPS_M, F_NPS_CORE, F_NPS_ALL.
 110         (insert_nps_misc_imm_offset): New function.
 111         (extract_nps_misc imm_offset): New function.
 112         (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
 113         (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
 114
 115 2017-03-21  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>
 116
 117         * s390-mkopc.c (main): Remove vx2 check.
 118         * s390-opc.txt: Remove vx2 instruction flags.
 119
 120 2017-03-21  Rinat Zelig  <rinat@mellanox.com>
 121
 122         * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
 123         * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
 124         (insert_nps_imm_offset): New function.
 125         (extract_nps_imm_offset): New function.
 126         (insert_nps_imm_entry): New function.
 127         (extract_nps_imm_entry): New function.
 128
 129 2017-03-17  Alan Modra  <amodra@gmail.com>
 130
 131         PR 21248
 132         * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
 133         mtivor32, and mtivor33 for e6500.  Move mfibatl and mfibatu after
 134         those spr mnemonics they alias.  Similarly for mtibatl, mtibatu.
 135
 136 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 137
 138         * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
 139         <c.andi>: Likewise.
 140         <c.addiw> Likewise.
 141
 142 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
 143
 144         * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
 145
 146 2017-03-13  Andrew Waterman  <andrew@sifive.com>
 147
 148         * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
 149         <srl> Likewise.
 150         <srai> Likewise.
 151         <sra> Likewise.
 152
 153 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 154
 155         * i386-gen.c (opcode_modifiers): Replace S with Load.
 156         * i386-opc.h (S): Removed.
 157         (Load): New.
 158         (i386_opcode_modifier): Replace s with load.
 159         * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
 160         and {evex}.  Replace S with Load.
 161         * i386-tbl.h: Regenerated.
 162
 163 2017-03-09  H.J. Lu  <hongjiu.lu@intel.com>
 164
 165         * i386-opc.tbl: Use CpuCET on rdsspq.
 166         * i386-tbl.h: Regenerated.
 167
 168 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 169
 170         * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
 171         <vsx>: Do not use PPC_OPCODE_VSX3;
 172
 173 2017-03-08  Peter Bergner  <bergner@vnet.ibm.com>
 174
 175         * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
 176
 177 2017-03-06  H.J. Lu  <hongjiu.lu@intel.com>
 178
 179         * i386-dis.c (REG_0F1E_MOD_3): New enum.
 180         (MOD_0F1E_PREFIX_1): Likewise.
 181         (MOD_0F38F5_PREFIX_2): Likewise.
 182         (MOD_0F38F6_PREFIX_0): Likewise.
 183         (RM_0F1E_MOD_3_REG_7): Likewise.
 184         (PREFIX_MOD_0_0F01_REG_5): Likewise.
 185         (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
 186         (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
 187         (PREFIX_0F1E): Likewise.
 188         (PREFIX_MOD_0_0FAE_REG_5): Likewise.
 189         (PREFIX_0F38F5): Likewise.
 190         (dis386_twobyte): Use PREFIX_0F1E.
 191         (reg_table): Add REG_0F1E_MOD_3.
 192         (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
 193         PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
 194         PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5.  Update
 195         PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
 196         (three_byte_table): Use PREFIX_0F38F5.
 197         (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
 198         Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
 199         (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
 200         RM_0F1E_MOD_3_REG_7.  Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
 201         PREFIX_MOD_3_0F01_REG_5_RM_2.
 202         * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
 203         (cpu_flags): Add CpuCET.
 204         * i386-opc.h (CpuCET): New enum.
 205         (CpuUnused): Commented out.
 206         (i386_cpu_flags): Add cpucet.
 207         * i386-opc.tbl: Add Intel CET instructions.
 208         * i386-init.h: Regenerated.
 209         * i386-tbl.h: Likewise.
 210
 211 2017-03-06  Alan Modra  <amodra@gmail.com>
 212
 213         PR 21124
 214         * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
 215         (extract_raq, extract_ras, extract_rbx): New functions.
 216         (powerpc_operands): Use opposite corresponding insert function.
 217         (Q_MASK): Define.
 218         (powerpc_opcodes): Apply Q_MASK to all quad insns with even
 219         register restriction.
 220
 221 2017-02-28  Peter Bergner  <bergner@vnet.ibm.com>
 222
 223         * disassemble.c Include "safe-ctype.h".
 224         (disassemble_init_for_target): Handle s390 init.
 225         (remove_whitespace_and_extra_commas): New function.
 226         (disassembler_options_cmp): Likewise.
 227         * arm-dis.c: Include "libiberty.h".
 228         (NUM_ELEM): Delete.
 229         (regnames): Use long disassembler style names.
 230         Add force-thumb and no-force-thumb options.
 231         (NUM_ARM_REGNAMES): Rename from this...
 232         (NUM_ARM_OPTIONS): ...to this.  Use ARRAY_SIZE.
 233         (get_arm_regname_num_options): Delete.
 234         (set_arm_regname_option): Likewise.
 235         (get_arm_regnames): Likewise.
 236         (parse_disassembler_options): Likewise.
 237         (parse_arm_disassembler_option): Rename from this...
 238         (parse_arm_disassembler_options): ...to this.  Make static.
 239         Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
 240         (print_insn): Use parse_arm_disassembler_options.
 241         (disassembler_options_arm): New function.
 242         (print_arm_disassembler_options): Handle updated regnames.
 243         * ppc-dis.c: Include "libiberty.h".
 244         (ppc_opts): Add "32" and "64" entries.
 245         (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
 246         (powerpc_init_dialect): Add break to switch statement.
 247         Use new FOR_EACH_DISASSEMBLER_OPTION macro.
 248         (disassembler_options_powerpc): New function.
 249         (print_ppc_disassembler_options): Use ARRAY_SIZE.
 250         Remove printing of "32" and "64".
 251         * s390-dis.c: Include "libiberty.h".
 252         (init_flag): Remove unneeded variable.
 253         (struct s390_options_t): New structure type.
 254         (options): New structure.
 255         (init_disasm): Rename from this...
 256         (disassemble_init_s390): ...to this.  Add initializations for
 257         current_arch_mask and option_use_insn_len_bits_p.  Remove init_flag.
 258         (print_insn_s390): Delete call to init_disasm.
 259         (disassembler_options_s390): New function.
 260         (print_s390_disassembler_options): Print using information from
 261         struct 'options'.
 262         * po/opcodes.pot: Regenerate.
 263
 264 2017-02-28  Jan Beulich  <jbeulich@suse.com>
 265
 266         * i386-dis.c (PCMPESTR_Fixup): New.
 267         (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
 268         (prefix_table): Use PCMPESTR_Fixup.
 269         (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
 270         PCMPESTR_Fixup.
 271         (vex_w_table): Delete VPCMPESTR{I,M} entries.
 272         * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
 273         Split 64-bit and non-64-bit variants.
 274         * opcodes/i386-tbl.h: Re-generate.
 275
 276 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 277
 278         * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
 279         (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
 280         (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
 281         (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
 282         (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
 283         (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
 284         (OP_SVE_V_HSD): New macros.
 285         (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
 286         (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
 287         (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
 288         (aarch64_opcode_table): Add new SVE instructions.
 289         (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
 290         for rotation operands.  Add new SVE operands.
 291         * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
 292         (ins_sve_quad_index): Likewise.
 293         (ins_imm_rotate): Split into...
 294         (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
 295         * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
 296         (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
 297         functions.
 298         (aarch64_ins_sve_addr_ri_s4): New function.
 299         (aarch64_ins_sve_quad_index): Likewise.
 300         (do_misc_encoding): Handle "MOV Zn.Q, Qm".
 301         * aarch64-asm-2.c: Regenerate.
 302         * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
 303         (ext_sve_quad_index): Likewise.
 304         (ext_imm_rotate): Split into...
 305         (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
 306         * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
 307         (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
 308         functions.
 309         (aarch64_ext_sve_addr_ri_s4): New function.
 310         (aarch64_ext_sve_quad_index): Likewise.
 311         (aarch64_ext_sve_index): Allow quad indices.
 312         (do_misc_decoding): Likewise.
 313         * aarch64-dis-2.c: Regenerate.
 314         * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
 315         aarch64_field_kinds.
 316         (OPD_F_OD_MASK): Widen by one bit.
 317         (OPD_F_NO_ZR): Bump accordingly.
 318         (get_operand_field_width): New function.
 319         * aarch64-opc.c (fields): Add new SVE fields.
 320         (operand_general_constraint_met_p): Handle new SVE operands.
 321         (aarch64_print_operand): Likewise.
 322         * aarch64-opc-2.c: Regenerate.
 323
 324 2017-02-24  Richard Sandiford  <richard.sandiford@arm.com>
 325
 326         * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
 327         (aarch64_feature_compnum): ...this.
 328         (SIMD_V8_3): Replace with...
 329         (COMPNUM): ...this.
 330         (CNUM_INSN): New macro.
 331         (aarch64_opcode_table): Use it for the complex number instructions.
 332
 333 2017-02-24  Jan Beulich  <jbeulich@suse.com>
 334
 335         * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
 336
 337 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 338
 339         Add support for associating SPARC ASIs with an architecture level.
 340         * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
 341         * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
 342         decoding of SPARC ASIs.
 343
 344 2017-02-23  Jan Beulich  <jbeulich@suse.com>
 345
 346         * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
 347         82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
 348
 349 2017-02-21  Jan Beulich  <jbeulich@suse.com>
 350
 351         * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
 352         1 (instead of to itself). Correct typo.
 353
 354 2017-02-14  Andrew Waterman  <andrew@sifive.com>
 355
 356         * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
 357         pseudoinstructions.
 358
 359 2017-02-15  Richard Sandiford  <richard.sandiford@arm.com>
 360
 361         * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
 362         (aarch64_sys_reg_supported_p): Handle them.
 363
 364 2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
 365
 366         * arc-opc.c (UIMM6_20R): Define.
 367         (SIMM12_20): Use above.
 368         (SIMM12_20R): Define.
 369         (SIMM3_5_S): Use above.
 370         (UIMM7_A32_11R_S): Define.
 371         (UIMM7_9_S): Use above.
 372         (UIMM3_13R_S): Define.
 373         (SIMM11_A32_7_S): Use above.
 374         (SIMM9_8R): Define.
 375         (UIMM10_A32_8_S): Use above.
 376         (UIMM8_8R_S): Define.
 377         (W6): Use above.
 378         (arc_relax_opcodes): Use all above defines.
 379
 380 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 381
 382         * arc-regs.h: Distinguish some of the registers different on
 383         ARC700 and HS38 cpus.
 384
 385 2017-02-14  Alan Modra  <amodra@gmail.com>
 386
 387         PR 21118
 388         * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
 389         with PPC_OPERAND_SPR.  Flag PSQ and PSQM with PPC_OPERAND_GQR.
 390
 391 2017-02-11  Stafford Horne  <shorne@gmail.com>
 392             Alan Modra  <amodra@gmail.com>
 393
 394         * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
 395         Use insn_bytes_value and insn_int_value directly instead.  Don't
 396         free allocated memory until function exit.
 397
 398 2017-02-10  Nicholas Piggin  <npiggin@gmail.com>
 399
 400         * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
 401
 402 2017-02-03  Nick Clifton  <nickc@redhat.com>
 403
 404         PR 21096
 405         * aarch64-opc.c (print_register_list): Ensure that the register
 406         list index will fir into the tb buffer.
 407         (print_register_offset_address): Likewise.
 408         * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
 409
 410 2017-01-27  Alexis Deruell  <alexis.deruelle@gmail.com>
 411
 412         PR 21056
 413         * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
 414         instructions when the previous fetch packet ends with a 32-bit
 415         instruction.
 416
 417 2017-01-24  Dimitar Dimitrov  <dimitar@dinux.eu>
 418
 419         * pru-opc.c: Remove vague reference to a future GDB port.
 420
 421 2017-01-20  Nick Clifton  <nickc@redhat.com>
 422
 423         * po/ga.po: Updated Irish translation.
 424
 425 2017-01-18  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 426
 427         * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
 428
 429 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 430
 431         * m68k-dis.c (match_insn_m68k): Extend comments.  Return -1
 432         if FETCH_DATA returns 0.
 433         (m68k_scan_mask): Likewise.
 434         (print_insn_m68k): Update code to handle -1 return value.
 435
 436 2017-01-13  Yao Qi  <yao.qi@linaro.org>
 437
 438         * m68k-dis.c (enum print_insn_arg_error): New.
 439         (NEXTBYTE): Replace -3 with
 440         PRINT_INSN_ARG_MEMORY_ERROR.
 441         (NEXTULONG): Likewise.
 442         (NEXTSINGLE): Likewise.
 443         (NEXTDOUBLE): Likewise.
 444         (NEXTDOUBLE): Likewise.
 445         (NEXTPACKED): Likewise.
 446         (FETCH_ARG): Likewise.
 447         (FETCH_DATA): Update comments.
 448         (print_insn_arg): Update comments. Replace magic numbers with
 449         enum.
 450         (match_insn_m68k): Likewise.
 451
 452 2017-01-12  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 453
 454         * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
 455         * i386-dis-evex.h (evex_table): Updated.
 456         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
 457         CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
 458         (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
 459         * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
 460         (i386_cpu_flags): Add cpuavx512_vpopcntdq.
 461         * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
 462         * i386-init.h: Regenerate.
 463         * i386-tbl.h: Ditto.
 464
 465 2017-01-12  Yao Qi  <yao.qi@linaro.org>
 466
 467         * msp430-dis.c (msp430_singleoperand): Return -1 if
 468         msp430dis_opcode_signed returns false.
 469         (msp430_doubleoperand): Likewise.
 470         (msp430_branchinstr): Return -1 if
 471         msp430dis_opcode_unsigned returns false.
 472         (msp430x_calla_instr): Likewise.
 473         (print_insn_msp430): Likewise.
 474
 475 2017-01-05  Nick Clifton  <nickc@redhat.com>
 476
 477         PR 20946
 478         * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
 479         could not be matched.
 480         (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
 481         NULL.
 482
 483 2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
 484
 485         * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
 486         (aarch64_opcode_table): Use RCPC_INSN.
 487
 488 2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
 489
 490         * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
 491         extension.
 492         * riscv-opcodes/all-opcodes: Likewise.
 493
 494 2017-01-03  Dilyan Palauzov  <dilyan.palauzov@aegee.org>
 495
 496         * riscv-dis.c (print_insn_args): Add fall through comment.
 497
 498 2017-01-03  Nick Clifton  <nickc@redhat.com>
 499
 500         * po/sr.po: New Serbian translation.
 501         * configure.ac (ALL_LINGUAS): Add sr.
 502         * configure: Regenerate.
 503
 504 2017-01-02  Alan Modra  <amodra@gmail.com>
 505
 506         * epiphany-desc.h: Regenerate.
 507         * epiphany-opc.h: Regenerate.
 508         * fr30-desc.h: Regenerate.
 509         * fr30-opc.h: Regenerate.
 510         * frv-desc.h: Regenerate.
 511         * frv-opc.h: Regenerate.
 512         * ip2k-desc.h: Regenerate.
 513         * ip2k-opc.h: Regenerate.
 514         * iq2000-desc.h: Regenerate.
 515         * iq2000-opc.h: Regenerate.
 516         * lm32-desc.h: Regenerate.
 517         * lm32-opc.h: Regenerate.
 518         * m32c-desc.h: Regenerate.
 519         * m32c-opc.h: Regenerate.
 520         * m32r-desc.h: Regenerate.
 521         * m32r-opc.h: Regenerate.
 522         * mep-desc.h: Regenerate.
 523         * mep-opc.h: Regenerate.
 524         * mt-desc.h: Regenerate.
 525         * mt-opc.h: Regenerate.
 526         * or1k-desc.h: Regenerate.
 527         * or1k-opc.h: Regenerate.
 528         * xc16x-desc.h: Regenerate.
 529         * xc16x-opc.h: Regenerate.
 530         * xstormy16-desc.h: Regenerate.
 531         * xstormy16-opc.h: Regenerate.
 532
 533 2017-01-02  Alan Modra  <amodra@gmail.com>
 534
 535         Update year range in copyright notice of all files.
 536
 537 For older changes see ChangeLog-2016
 538 \f
 539 Copyright (C) 2017 Free Software Foundation, Inc.
 540
 541 Copying and distribution of this file, with or without modification,
 542 are permitted in any medium without royalty provided the copyright
 543 notice and this notice are preserved.
 544
 545 Local Variables:
 546 mode: change-log
 547 left-margin: 8
 548 fill-column: 74
 549 version-control: never
 550 End: