opcodes/ChangeLog

   1 2019-11-07  Jan Beulich  <jbeulich@suse.com>
   2
   3         * i386-dis.c (OP_Mwait): Drop local variable "names", use
   4         "names32" instead.
   5         (OP_Monitor): Drop local variable "op1_names", re-purpose
   6         "names" for it instead, and replace former "names" uses by
   7         "names32" ones.
   8
   9 2019-11-07  Jan Beulich  <jbeulich@suse.com>
  10
  11         PR/gas 25167
  12         * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
  13         operand-less forms.
  14         * opcodes/i386-tbl.h: Re-generate.
  15
  16 2019-11-05  Jan Beulich  <jbeulich@suse.com>
  17
  18         * i386-dis.c (OP_Mwaitx): Delete.
  19         (prefix_table): Use OP_Mwait for mwaitx entry.
  20         (OP_Mwait): Also handle mwaitx.
  21
  22 2019-11-05  Jan Beulich  <jbeulich@suse.com>
  23
  24         * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
  25         PREFIX_0F01_REG_7_MOD_3_RM_3): New.
  26         (prefix_table): Add respective entries.
  27         (rm_table): Link to those entries.
  28
  29 2019-11-05  Jan Beulich  <jbeulich@suse.com>
  30
  31         * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
  32         (REG_0F1C_P_0_MOD_0): ... this.
  33         (REG_0F1E_MOD_3): Rename to ...
  34         (REG_0F1E_P_1_MOD_3): ... this.
  35         (RM_0F01_REG_5): Rename to ...
  36         (RM_0F01_REG_5_MOD_3): ... this.
  37         (RM_0F01_REG_7): Rename to ...
  38         (RM_0F01_REG_7_MOD_3): ... this.
  39         (RM_0F1E_MOD_3_REG_7): Rename to ...
  40         (RM_0F1E_P_1_MOD_3_REG_7): ... this.
  41         (RM_0FAE_REG_6): Rename to ...
  42         (RM_0FAE_REG_6_MOD_3_P_0): ... this.
  43         (RM_0FAE_REG_7): Rename to ...
  44         (RM_0FAE_REG_7_MOD_3): ... this.
  45         (PREFIX_MOD_0_0F01_REG_5): Rename to ...
  46         (PREFIX_0F01_REG_5_MOD_0): ... this.
  47         (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
  48         (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
  49         (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
  50         (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
  51         (PREFIX_0FAE_REG_0): Rename to ...
  52         (PREFIX_0FAE_REG_0_MOD_3): ... this.
  53         (PREFIX_0FAE_REG_1): Rename to ...
  54         (PREFIX_0FAE_REG_1_MOD_3): ... this.
  55         (PREFIX_0FAE_REG_2): Rename to ...
  56         (PREFIX_0FAE_REG_2_MOD_3): ... this.
  57         (PREFIX_0FAE_REG_3): Rename to ...
  58         (PREFIX_0FAE_REG_3_MOD_3): ... this.
  59         (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
  60         (PREFIX_0FAE_REG_4_MOD_0): ... this.
  61         (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
  62         (PREFIX_0FAE_REG_4_MOD_3): ... this.
  63         (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
  64         (PREFIX_0FAE_REG_5_MOD_0): ... this.
  65         (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
  66         (PREFIX_0FAE_REG_5_MOD_3): ... this.
  67         (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
  68         (PREFIX_0FAE_REG_6_MOD_0): ... this.
  69         (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
  70         (PREFIX_0FAE_REG_6_MOD_3): ... this.
  71         (PREFIX_0FAE_REG_7): Rename to ...
  72         (PREFIX_0FAE_REG_7_MOD_0): ... this.
  73         (PREFIX_MOD_0_0FC3): Rename to ...
  74         (PREFIX_0FC3_MOD_0): ... this.
  75         (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
  76         (PREFIX_0FC7_REG_6_MOD_0): ... this.
  77         (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
  78         (PREFIX_0FC7_REG_6_MOD_3): ... this.
  79         (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
  80         (PREFIX_0FC7_REG_7_MOD_3): ... this.
  81         (reg_table, prefix_table, mod_table, rm_table): Adjust
  82         accordingly.
  83
  84 2019-11-04  Nick Clifton  <nickc@redhat.com>
  85
  86         * v850-dis.c (get_v850_sreg_name): New function.  Returns the name
  87         of a v850 system register.  Move the v850_sreg_names array into
  88         this function.
  89         (get_v850_reg_name): Likewise for ordinary register names.
  90         (get_v850_vreg_name): Likewise for vector register names.
  91         (get_v850_cc_name): Likewise for condition codes.
  92         * get_v850_float_cc_name): Likewise for floating point condition
  93         codes.
  94         (get_v850_cacheop_name): Likewise for cache-ops.
  95         (get_v850_prefop_name): Likewise for pref-ops.
  96         (disassemble): Use the new accessor functions.
  97
  98 2019-10-30  Delia Burduv   <delia.burduv@arm.com>
  99
 100         * aarch64-opc.c (print_immediate_offset_address): Don't print the
 101         immediate for the writeback form of ldraa/ldrab if it is 0.
 102         * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
 103         * aarch64-opc-2.c: Regenerated.
 104
 105 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 106
 107         * i386-gen.c (operand_type_shorthands): Delete.
 108         (operand_type_init): Expand previous shorthands.
 109         (set_bitfield_from_shorthand): Rename back to ...
 110         (set_bitfield_from_cpu_flag_init): ... this.  Drop processing
 111         of operand_type_init[].
 112         (set_bitfield): Adjust call to the above function.
 113         * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
 114         RegXMM, RegYMM, RegZMM): Define.
 115         * i386-reg.tbl: Expand prior shorthands.
 116
 117 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 118
 119         * i386-gen.c (output_i386_opcode): Change order of fields
 120         emitted to output.
 121         * i386-opc.h (struct insn_template): Move operands field.
 122         Convert extension_opcode field to unsigned short.
 123         * i386-tbl.h: Re-generate.
 124
 125 2019-10-30  Jan Beulich  <jbeulich@suse.com>
 126
 127         * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
 128         of W.
 129         * i386-opc.h (W): Extend comment.
 130         * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
 131         general purpose variants not allowing for byte operands.
 132         * i386-tbl.h: Re-generate.
 133
 134 2019-10-29  Nick Clifton  <nickc@redhat.com>
 135
 136         * tic30-dis.c (print_branch): Correct size of operand array.
 137
 138 2019-10-29  Nick Clifton  <nickc@redhat.com>
 139
 140         * d30v-dis.c (print_insn): Check that operand index is valid
 141         before attempting to access the operands array.
 142
 143 2019-10-29  Nick Clifton  <nickc@redhat.com>
 144
 145         * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
 146         locating the bit to be tested.
 147
 148 2019-10-29  Nick Clifton  <nickc@redhat.com>
 149
 150         * s12z-dis.c (opr_emit_disassembly): Check for illegal register
 151         values.
 152         (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
 153         (print_insn_s12z):  Check for illegal size values.
 154
 155 2019-10-28  Nick Clifton  <nickc@redhat.com>
 156
 157         * csky-dis.c (csky_chars_to_number): Check for a negative
 158         count. Use an unsigned integer to construct the return value.
 159
 160 2019-10-28  Nick Clifton  <nickc@redhat.com>
 161
 162         * tic30-dis.c (OPERAND_BUFFER_LEN): Define.  Use as length of
 163         operand buffer.  Set value to 15 not 13.
 164         (get_register_operand): Use OPERAND_BUFFER_LEN.
 165         (get_indirect_operand): Likewise.
 166         (print_two_operand): Likewise.
 167         (print_three_operand): Likewise.
 168         (print_oar_insn): Likewise.
 169
 170 2019-10-28  Nick Clifton  <nickc@redhat.com>
 171
 172         * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
 173         (bit_extract_simple): Likewise.
 174         (bit_copy): Likewise.
 175         (pirnt_insn_ns32k): Ensure that uninitialised elements in the
 176         index_offset array are not accessed.
 177
 178 2019-10-28  Nick Clifton  <nickc@redhat.com>
 179
 180         * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
 181         operand.
 182
 183 2019-10-25  Nick Clifton  <nickc@redhat.com>
 184
 185         * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
 186         access to opcodes.op array element.
 187
 188 2019-10-23  Nick Clifton  <nickc@redhat.com>
 189
 190         * rx-dis.c (get_register_name): Fix spelling typo in error
 191         message.
 192         (get_condition_name, get_flag_name, get_double_register_name)
 193         (get_double_register_high_name, get_double_register_low_name)
 194         (get_double_control_register_name, get_double_condition_name)
 195         (get_opsize_name, get_size_name): Likewise.
 196
 197 2019-10-22  Nick Clifton  <nickc@redhat.com>
 198
 199         * rx-dis.c (get_size_name): New function.  Provides safe
 200         access to name array.
 201         (get_opsize_name): Likewise.
 202         (print_insn_rx): Use the accessor functions.
 203
 204 2019-10-16  Nick Clifton  <nickc@redhat.com>
 205
 206         * rx-dis.c (get_register_name): New function.  Provides safe
 207         access to name array.
 208         (get_condition_name, get_flag_name, get_double_register_name)
 209         (get_double_register_high_name, get_double_register_low_name)
 210         (get_double_control_register_name, get_double_condition_name):
 211         Likewise.
 212         (print_insn_rx): Use the accessor functions.
 213
 214 2019-10-09  Nick Clifton  <nickc@redhat.com>
 215
 216         PR 25041
 217         * avr-dis.c (avr_operand): Fix construction of address for lds/sts
 218         instructions.
 219
 220 2019-10-07  Jan Beulich  <jbeulich@suse.com>
 221
 222         * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
 223         (cmpsd): Likewise. Move EsSeg to other operand.
 224         * opcodes/i386-tbl.h: Re-generate.
 225
 226 2019-09-23  Alan Modra  <amodra@gmail.com>
 227
 228         * m68k-dis.c: Include cpu-m68k.h
 229
 230 2019-09-23  Alan Modra  <amodra@gmail.com>
 231
 232         * mips-dis.c: Include elfxx-mips.h.  Move "elf-bfd.h" and
 233         "elf/mips.h" earlier.
 234
 235 2018-09-20  Jan Beulich  <jbeulich@suse.com>
 236
 237         PR gas/25012
 238         * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
 239         with SReg operand.
 240         * i386-tbl.h: Re-generate.
 241
 242 2019-09-18  Alan Modra  <amodra@gmail.com>
 243
 244         * arc-ext.c: Update throughout for bfd section macro changes.
 245
 246 2019-09-18  Simon Marchi  <simon.marchi@polymtl.ca>
 247
 248         * Makefile.in: Re-generate.
 249         * configure: Re-generate.
 250
 251 2019-09-17  Maxim Blinov  <maxim.blinov@embecosm.com>
 252
 253         * riscv-opc.c (riscv_opcodes): Change subset field
 254         to insn_class field for all instructions.
 255         (riscv_insn_types): Likewise.
 256
 257 2019-09-16  Phil Blundell  <pb@pbcl.net>
 258
 259         * configure: Regenerated.
 260
 261 2019-09-10  Miod Vallat  <miod@online.fr>
 262
 263         PR 24982
 264         * m68k-opc.c: Correct aliases for tdivsl and tdivul.
 265
 266 2019-09-09  Phil Blundell  <pb@pbcl.net>
 267
 268         binutils 2.33 branch created.
 269
 270 2019-09-03  Nick Clifton  <nickc@redhat.com>
 271
 272         PR 24961
 273         * tic30-dis.c (get_indirect_operand): Check for bufcnt being
 274         greater than zero before indexing via (bufcnt -1).
 275
 276 2019-09-03  Nick Clifton  <nickc@redhat.com>
 277
 278         PR 24958
 279         * mmix-dis.c (MAX_REG_NAME_LEN): Define.
 280         (MAX_SPEC_REG_NAME_LEN): Define.
 281         (struct mmix_dis_info): Use defined constants for array lengths.
 282         (get_reg_name): New function.
 283         (get_sprec_reg_name): New function.
 284         (print_insn_mmix): Use new functions.
 285
 286 2019-08-27  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 287
 288         * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
 289         (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
 290         (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
 291
 292 2019-08-22  Kyrylo Tkachov <kyrylo.tkachov@arm.com>
 293
 294         * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
 295         tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
 296         (aarch64_sys_reg_supported_p): Update checks for the above.
 297
 298 2019-08-12  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>
 299
 300         * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
 301         cases MVE_SQRSHRL and MVE_UQRSHLL.
 302         (print_insn_mve): Add case for specifier 'k' to check
 303         specific bit of the instruction.
 304
 305 2019-08-07  Phillipe Antoine  <p.antoine@catenacyber.fr>
 306
 307         PR 24854
 308         * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
 309         encountering an unknown machine type.
 310         (print_insn_arc): Handle arc_insn_length returning 0.  In error
 311         cases return -1 rather than calling abort.
 312
 313 2019-08-07  Jan Beulich  <jbeulich@suse.com>
 314
 315         * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
 316         (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
 317         IgnoreSize.
 318         * i386-tbl.h: Re-generate.
 319
 320 2019-08-05  Barnaby Wilks  <barnaby.wilks@arm.com>
 321
 322         * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
 323         instructions.
 324
 325 2019-07-30  Mel Chen <mel.chen@sifive.com>
 326
 327         * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
 328         fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
 329
 330         * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
 331         fscsr.
 332
 333 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 334
 335         * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
 336         and MPY class instructions.
 337         (parse_option): Add nps400 option.
 338         (print_arc_disassembler_options): Add nps400 info.
 339
 340 2019-07-24  Claudiu Zissulescu  <claziss@synopsys.com>
 341
 342         * arc-ext-tbl.h (bspeek): Remove it, added to main table.
 343         (bspop): Likewise.
 344         (modapp): Likewise.
 345         * arc-opc.c (RAD_CHK): Add.
 346         * arc-tbl.h: Regenerate.
 347
 348 2019-07-23  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 349
 350         * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
 351         (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
 352
 353 2019-07-22  Barnaby Wilks  <barnaby.wilks@arm.com>
 354
 355         * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
 356         instructions as UNPREDICTABLE.
 357
 358 2019-07-19  Jose E. Marchesi  <jose.marchesi@oracle.com>
 359
 360         * bpf-desc.c: Regenerated.
 361
 362 2019-07-17  Jan Beulich  <jbeulich@suse.com>
 363
 364         * i386-gen.c (static_assert): Define.
 365         (main): Use it.
 366         * i386-opc.h (Opcode_Modifier_Max): Rename to ...
 367         (Opcode_Modifier_Num): ... this.
 368         (Mem): Delete.
 369
 370 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 371
 372         * i386-gen.c (operand_types): Move RegMem ...
 373         (opcode_modifiers): ... here.
 374         * i386-opc.h (RegMem): Move to opcode modifer enum.
 375         (union i386_operand_type): Move regmem field ...
 376         (struct i386_opcode_modifier): ... here.
 377         * i386-opc.tbl (RegMem): Define.
 378         (mov, movq): Move RegMem on segment, control, debug, and test
 379         register flavors.
 380         (pextrb): Move RegMem on register only flavors. Add IgnoreSize
 381         to non-SSE2AVX flavor.
 382         (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
 383         Move RegMem on register only flavors. Drop IgnoreSize from
 384         legacy encoding flavors.
 385         (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
 386         flavors.
 387         (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
 388         register only flavors.
 389         (vmovd): Move RegMem and drop IgnoreSize on register only
 390         flavor. Change opcode and operand order to store form.
 391         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 392
 393 2019-07-16  Jan Beulich  <jbeulich@suse.com>
 394
 395         * i386-gen.c (operand_type_init, operand_types): Replace SReg
 396         entries.
 397         * i386-opc.h (SReg2, SReg3): Replace by ...
 398         (SReg): ... this.
 399         (union i386_operand_type): Replace sreg fields.
 400         * i386-opc.tbl (mov, ): Use SReg.
 401         (push, pop): Likewies. Drop i386 and x86-64 specific segment
 402         register flavors.
 403         * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
 404         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 405
 406 2019-07-15  Jose E. Marchesi  <jose.marchesi@oracle.com>
 407
 408         * bpf-desc.c: Regenerate.
 409         * bpf-opc.c: Likewise.
 410         * bpf-opc.h: Likewise.
 411
 412 2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
 413
 414         * bpf-desc.c: Regenerate.
 415         * bpf-opc.c: Likewise.
 416
 417 2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
 418
 419         * arm-dis.c (print_insn_coprocessor): Rename index to
 420         index_operand.
 421
 422 2019-07-05  Kito Cheng <kito.cheng@sifive.com>
 423
 424         * riscv-opc.c (riscv_insn_types): Add r4 type.
 425
 426         * riscv-opc.c (riscv_insn_types): Add b and j type.
 427
 428         * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
 429         format for sb type and correct s type.
 430
 431 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 432
 433         * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
 434         SVE FMOV alias of FCPY.
 435
 436 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 437
 438         * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
 439         to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
 440
 441 2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
 442
 443         * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
 444         registers in an instruction prefixed by MOVPRFX.
 445
 446 2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
 447
 448         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
 449         sve_size_13 icode to account for variant behaviour of
 450         pmull{t,b}.
 451         * aarch64-dis-2.c: Regenerate.
 452         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
 453         sve_size_13 icode to account for variant behaviour of
 454         pmull{t,b}.
 455         * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
 456         (OP_SVE_VVV_Q_D): Add new qualifier.
 457         (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
 458         (struct aarch64_opcode): Split pmull{t,b} into those requiring
 459         AES and those not.
 460
 461 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 462
 463         * opcodes/i386-gen.c (operand_type_init): Remove
 464         OPERAND_TYPE_VEC_IMM4 entry.
 465         (operand_types): Remove Vec_Imm4.
 466         * opcodes/i386-opc.h (Vec_Imm4): Delete.
 467         (union i386_operand_type): Remove vec_imm4.
 468         * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
 469         * opcodes/i386-init.h, i386-tbl.h: Re-generate.
 470
 471 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 472
 473         * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
 474         vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
 475         rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
 476         vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
 477         xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
 478         monitorx, mwaitx): Drop ImmExt from operand-less forms.
 479         * i386-tbl.h: Re-generate.
 480
 481 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 482
 483         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 484         register operands.
 485         * i386-tbl.h: Re-generate.
 486
 487 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 488
 489         * i386-opc.tbl (C): New.
 490         (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
 491         pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
 492         por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
 493         cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
 494         pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
 495         cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
 496         cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
 497         vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
 498         vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
 499         vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
 500         vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
 501         vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
 502         vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
 503         vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
 504         vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
 505         vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
 506         vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
 507         vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
 508         vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
 509         vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
 510         vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
 511         vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
 512         vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
 513         vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
 514         vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
 515         vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
 516         flavors.
 517         * i386-tbl.h: Re-generate.
 518
 519 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 520
 521         * i386-opc.tbl (and, or): Add Optimize to forms allowing two
 522         register operands.
 523         * i386-tbl.h: Re-generate.
 524
 525 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 526
 527         * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
 528         * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
 529         vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
 530         * i386-tbl.h: Re-generate.
 531
 532 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 533
 534         * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
 535         Disp8MemShift from register only templates.
 536         * i386-tbl.h: Re-generate.
 537
 538 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 539
 540         * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
 541         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
 542         MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
 543         EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
 544         EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
 545         EVEX_W_0F11_P_3_M_1): Delete.
 546         (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
 547         EVEX_W_0F11_P_3): New.
 548         * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
 549         MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
 550         MOD_EVEX_0F11_PREFIX_3 table entries.
 551         * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
 552         PREFIX_EVEX_0F11 table entries.
 553         * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
 554         EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
 555         EVEX_W_0F11_P_3_M_{0,1} table entries.
 556
 557 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 558
 559         * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
 560         Delete.
 561
 562 2019-06-27  H.J. Lu  <hongjiu.lu@intel.com>
 563
 564         PR binutils/24719
 565         * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 566         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 567         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 568         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 569         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 570         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 571         EVEX_LEN_0F38C7_R_6_P_2_W_1.
 572         * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
 573         PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
 574         PREFIX_EVEX_0F38C6_REG_6 entries.
 575         * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
 576         EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
 577         EVEX_W_0F38C7_R_6_P_2 entries.
 578         * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
 579         EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
 580         EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
 581         EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
 582         EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
 583         EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
 584         EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
 585
 586 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 587
 588         * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
 589         VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
 590         VEX_LEN_0F2D_P_3): Delete.
 591         (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
 592         vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
 593         (prefix_table): ... here.
 594
 595 2019-06-27  Jan Beulich  <jbeulich@suse.com>
 596
 597         * i386-dis.c (Iq): Delete.
 598         (Id): New.
 599         (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
 600         TBM insns.
 601         (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
 602         vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
 603         (OP_E_memory): Also honor needindex when deciding whether an
 604         address size prefix needs printing.
 605         (OP_I): Remove handling of q_mode. Add handling of d_mode.
 606
 607 2019-06-26  Jim Wilson  <jimw@sifive.com>
 608
 609         PR binutils/24739
 610         * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
 611         Set info->display_endian to info->endian_code.
 612
 613 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 614
 615         * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
 616         entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
 617         OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
 618         OPERAND_TYPE_ACC64 entries.
 619         * i386-init.h: Re-generate.
 620
 621 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 622
 623         * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
 624         Delete.
 625         (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
 626         of dqa_mode.
 627         * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
 628         entries here.
 629         * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
 630         entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
 631
 632 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 633
 634         * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
 635         variables.
 636
 637 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 638
 639         * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
 640         Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
 641         movnti.
 642         * i386-opc.tbl (movnti): Add IgnoreSize.
 643         * i386-tbl.h: Re-generate.
 644
 645 2019-06-25  Jan Beulich  <jbeulich@suse.com>
 646
 647         * i386-opc.tbl (and): Mark Imm8S form for optimization.
 648         * i386-tbl.h: Re-generate.
 649
 650 2019-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 651
 652         * i386-dis-evex.h: Break into ...
 653         * i386-dis-evex-len.h: New file.
 654         * i386-dis-evex-mod.h: Likewise.
 655         * i386-dis-evex-prefix.h: Likewise.
 656         * i386-dis-evex-reg.h: Likewise.
 657         * i386-dis-evex-w.h: Likewise.
 658         * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
 659         i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
 660         i386-dis-evex-mod.h.
 661
 662 2019-06-19  H.J. Lu  <hongjiu.lu@intel.com>
 663
 664         PR binutils/24700
 665         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
 666         EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
 667         EVEX_W_0F385B_P_2.
 668         (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
 669         EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
 670         EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
 671         EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
 672         EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
 673         EVEX_LEN_0F385B_P_2_W_1.
 674         * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
 675         (EVEX_LEN_0F3819_P_2_W_1): Likewise.
 676         (EVEX_LEN_0F381A_P_2_W_0): Likewise.
 677         (EVEX_LEN_0F381A_P_2_W_1): Likewise.
 678         (EVEX_LEN_0F381B_P_2_W_0): Likewise.
 679         (EVEX_LEN_0F381B_P_2_W_1): Likewise.
 680         (EVEX_LEN_0F385A_P_2_W_0): Likewise.
 681         (EVEX_LEN_0F385A_P_2_W_1): Likewise.
 682         (EVEX_LEN_0F385B_P_2_W_0): Likewise.
 683         (EVEX_LEN_0F385B_P_2_W_1): Likewise.
 684
 685 2019-06-17  H.J. Lu  <hongjiu.lu@intel.com>
 686
 687         PR binutils/24691
 688         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
 689         EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
 690         EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
 691         (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
 692         EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
 693         EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
 694         EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
 695         EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
 696         EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
 697         EVEX_LEN_0F3A43_P_2_W_1.
 698         * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
 699         (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
 700         (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
 701         (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
 702         (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
 703         (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
 704         (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
 705         (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
 706         (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
 707         (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
 708         (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
 709         (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
 710
 711 2019-06-14  Nick Clifton  <nickc@redhat.com>
 712
 713         * po/fr.po; Updated French translation.
 714
 715 2019-06-13  Stafford Horne  <shorne@gmail.com>
 716
 717         * or1k-asm.c: Regenerated.
 718         * or1k-desc.c: Regenerated.
 719         * or1k-desc.h: Regenerated.
 720         * or1k-dis.c: Regenerated.
 721         * or1k-ibld.c: Regenerated.
 722         * or1k-opc.c: Regenerated.
 723         * or1k-opc.h: Regenerated.
 724         * or1k-opinst.c: Regenerated.
 725
 726 2019-06-12  Peter Bergner  <bergner@linux.ibm.com>
 727
 728         * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
 729
 730 2019-06-05  H.J. Lu  <hongjiu.lu@intel.com>
 731
 732         PR binutils/24633
 733         * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
 734         EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
 735         (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
 736         EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
 737         EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
 738         EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
 739         EVEX_LEN_0F3A1B_P_2_W_1.
 740         * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
 741         (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
 742         (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
 743         (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
 744         (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
 745         (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
 746         (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
 747         (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
 748
 749 2019-06-04  H.J. Lu  <hongjiu.lu@intel.com>
 750
 751         PR binutils/24626
 752         * i386-dis.c (print_insn): Check for unused VEX.vvvv and
 753         EVEX.vvvv when disassembling VEX and EVEX instructions.
 754         (OP_VEX): Set vex.register_specifier to 0 after readding
 755         vex.register_specifier.
 756         (OP_Vex_2src_1): Likewise.
 757         (OP_Vex_2src_2): Likewise.
 758         (OP_LWP_E): Likewise.
 759         (OP_EX_Vex): Don't check vex.register_specifier.
 760         (OP_XMM_Vex): Likewise.
 761
 762 2019-06-04  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
 763             Lili Cui  <lili.cui@intel.com>
 764
 765         * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
 766         * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
 767         instructions.
 768         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
 769         CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
 770         (cpu_flags): Add CpuAVX512_VP2INTERSECT.
 771         * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
 772         (i386_cpu_flags): Add cpuavx512_vp2intersect.
 773         * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
 774         * i386-init.h: Regenerated.
 775         * i386-tbl.h: Likewise.
 776
 777 2019-06-04  Xuepeng Guo  <xuepeng.guo@intel.com>
 778             Lili Cui  <lili.cui@intel.com>
 779
 780         * doc/c-i386.texi: Document enqcmd.
 781         * testsuite/gas/i386/enqcmd-intel.d: New file.
 782         * testsuite/gas/i386/enqcmd-inval.l: Likewise.
 783         * testsuite/gas/i386/enqcmd-inval.s: Likewise.
 784         * testsuite/gas/i386/enqcmd.d: Likewise.
 785         * testsuite/gas/i386/enqcmd.s: Likewise.
 786         * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
 787         * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
 788         * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
 789         * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
 790         * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
 791         * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
 792         enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
 793         and x86-64-enqcmd.
 794
 795 2019-06-04  Alan Hayward  <alan.hayward@arm.com>
 796
 797         * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
 798
 799 2019-06-03  Alan Modra  <amodra@gmail.com>
 800
 801         * ppc-dis.c (prefix_opcd_indices): Correct size.
 802
 803 2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
 804
 805         PR gas/24625
 806         * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
 807         Disp8ShiftVL.
 808         * i386-tbl.h: Regenerated.
 809
 810 2019-05-24  Alan Modra  <amodra@gmail.com>
 811
 812         * po/POTFILES.in: Regenerate.
 813
 814 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 815             Alan Modra  <amodra@gmail.com>
 816
 817         * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
 818         (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
 819         (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
 820         (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
 821         XTOP>): Define and add entries.
 822         (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
 823         (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
 824         pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
 825         plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
 826
 827 2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
 828             Alan Modra  <amodra@gmail.com>
 829
 830         * ppc-dis.c (ppc_opts): Add "future" entry.
 831         (PREFIX_OPCD_SEGS): Define.
 832         (prefix_opcd_indices): New array.
 833         (disassemble_init_powerpc): Initialize prefix_opcd_indices.
 834         (lookup_prefix): New function.
 835         (print_insn_powerpc): Handle 64-bit prefix instructions.
 836         * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
 837         (PMRR, POWERXX): Define.
 838         (prefix_opcodes): New instruction table.
 839         (prefix_num_opcodes): New constant.
 840
 841 2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
 842
 843         * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
 844         * configure: Regenerated.
 845         * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
 846         and cpu/bpf.opc.
 847         (HFILES): Add bpf-desc.h and bpf-opc.h.
 848         (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
 849         bpf-ibld.c and bpf-opc.c.
 850         (BPF_DEPS): Define.
 851         * Makefile.in: Regenerated.
 852         * disassemble.c (ARCH_bpf): Define.
 853         (disassembler): Add case for bfd_arch_bpf.
 854         (disassemble_init_for_target): Likewise.
 855         (enum epbf_isa_attr): Define.
 856         * disassemble.h: extern print_insn_bpf.
 857         * bpf-asm.c: Generated.
 858         * bpf-opc.h: Likewise.
 859         * bpf-opc.c: Likewise.
 860         * bpf-ibld.c: Likewise.
 861         * bpf-dis.c: Likewise.
 862         * bpf-desc.h: Likewise.
 863         * bpf-desc.c: Likewise.
 864
 865 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 866
 867         * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
 868         and VMSR with the new operands.
 869
 870 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 871
 872         * arm-dis.c (enum mve_instructions): New enum
 873         for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
 874         and cneg.
 875         (mve_opcodes): New instructions as above.
 876         (is_mve_encoding_conflict): Add cases for csinc, csinv,
 877         csneg and csel.
 878         (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
 879
 880 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 881
 882         * arm-dis.c (emun mve_instructions): Updated for new instructions.
 883         (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
 884         sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
 885         uqshl, urshrl and urshr.
 886         (is_mve_okay_in_it): Add new instructions to TRUE list.
 887         (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
 888         (print_insn_mve): Updated to accept new %j,
 889         %<bitfield>m and %<bitfield>n patterns.
 890
 891 2019-05-21  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 892
 893         * mips-opc.c (mips_builtin_opcodes): Change source register
 894         constraint for DAUI.
 895
 896 2019-05-20  Nick Clifton  <nickc@redhat.com>
 897
 898         * po/fr.po: Updated French translation.
 899
 900 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 901             Michael Collison <michael.collison@arm.com>
 902
 903         * arm-dis.c (thumb32_opcodes): Add new instructions.
 904         (enum mve_instructions): Likewise.
 905         (enum mve_undefined): Add new reasons.
 906         (is_mve_encoding_conflict): Handle new instructions.
 907         (is_mve_undefined): Likewise.
 908         (is_mve_unpredictable): Likewise.
 909         (print_mve_undefined): Likewise.
 910         (print_mve_size): Likewise.
 911
 912 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 913             Michael Collison <michael.collison@arm.com>
 914
 915         * arm-dis.c (thumb32_opcodes): Add new instructions.
 916         (enum mve_instructions): Likewise.
 917         (is_mve_encoding_conflict): Handle new instructions.
 918         (is_mve_undefined): Likewise.
 919         (is_mve_unpredictable): Likewise.
 920         (print_mve_size): Likewise.
 921
 922 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 923             Michael Collison <michael.collison@arm.com>
 924
 925         * arm-dis.c (thumb32_opcodes): Add new instructions.
 926         (enum mve_instructions): Likewise.
 927         (is_mve_encoding_conflict): Likewise.
 928         (is_mve_unpredictable): Likewise.
 929         (print_mve_size): Likewise.
 930
 931 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 932             Michael Collison <michael.collison@arm.com>
 933
 934         * arm-dis.c (thumb32_opcodes): Add new instructions.
 935         (enum mve_instructions): Likewise.
 936         (is_mve_encoding_conflict): Handle new instructions.
 937         (is_mve_undefined): Likewise.
 938         (is_mve_unpredictable): Likewise.
 939         (print_mve_size): Likewise.
 940
 941 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 942             Michael Collison <michael.collison@arm.com>
 943
 944         * arm-dis.c (thumb32_opcodes): Add new instructions.
 945         (enum mve_instructions): Likewise.
 946         (is_mve_encoding_conflict): Handle new instructions.
 947         (is_mve_undefined): Likewise.
 948         (is_mve_unpredictable): Likewise.
 949         (print_mve_size): Likewise.
 950         (print_insn_mve): Likewise.
 951
 952 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 953             Michael Collison <michael.collison@arm.com>
 954
 955         * arm-dis.c (thumb32_opcodes): Add new instructions.
 956         (print_insn_thumb32): Handle new instructions.
 957
 958 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 959             Michael Collison <michael.collison@arm.com>
 960
 961         * arm-dis.c (enum mve_instructions): Add new instructions.
 962         (enum mve_undefined): Add new reasons.
 963         (is_mve_encoding_conflict): Handle new instructions.
 964         (is_mve_undefined): Likewise.
 965         (is_mve_unpredictable): Likewise.
 966         (print_mve_undefined): Likewise.
 967         (print_mve_size): Likewise.
 968         (print_mve_shift_n): Likewise.
 969         (print_insn_mve): Likewise.
 970
 971 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 972             Michael Collison <michael.collison@arm.com>
 973
 974         * arm-dis.c (enum mve_instructions): Add new instructions.
 975         (is_mve_encoding_conflict): Handle new instructions.
 976         (is_mve_unpredictable): Likewise.
 977         (print_mve_rotate): Likewise.
 978         (print_mve_size): Likewise.
 979         (print_insn_mve): Likewise.
 980
 981 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 982             Michael Collison <michael.collison@arm.com>
 983
 984         * arm-dis.c (enum mve_instructions): Add new instructions.
 985         (is_mve_encoding_conflict): Handle new instructions.
 986         (is_mve_unpredictable): Likewise.
 987         (print_mve_size): Likewise.
 988         (print_insn_mve): Likewise.
 989
 990 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 991             Michael Collison <michael.collison@arm.com>
 992
 993         * arm-dis.c (enum mve_instructions): Add new instructions.
 994         (enum mve_undefined): Add new reasons.
 995         (is_mve_encoding_conflict): Handle new instructions.
 996         (is_mve_undefined): Likewise.
 997         (is_mve_unpredictable): Likewise.
 998         (print_mve_undefined): Likewise.
 999         (print_mve_size): Likewise.
1000         (print_insn_mve): Likewise.
1001
1002 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1003             Michael Collison <michael.collison@arm.com>
1004
1005         * arm-dis.c (enum mve_instructions): Add new instructions.
1006         (is_mve_encoding_conflict): Handle new instructions.
1007         (is_mve_undefined): Likewise.
1008         (is_mve_unpredictable): Likewise.
1009         (print_mve_size): Likewise.
1010         (print_insn_mve): Likewise.
1011
1012 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1013             Michael Collison <michael.collison@arm.com>
1014
1015         * arm-dis.c (enum mve_instructions): Add new instructions.
1016         (enum mve_unpredictable): Add new reasons.
1017         (enum mve_undefined): Likewise.
1018         (is_mve_okay_in_it): Handle new isntructions.
1019         (is_mve_encoding_conflict): Likewise.
1020         (is_mve_undefined): Likewise.
1021         (is_mve_unpredictable): Likewise.
1022         (print_mve_vmov_index): Likewise.
1023         (print_simd_imm8): Likewise.
1024         (print_mve_undefined): Likewise.
1025         (print_mve_unpredictable): Likewise.
1026         (print_mve_size): Likewise.
1027         (print_insn_mve): Likewise.
1028
1029 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1030             Michael Collison <michael.collison@arm.com>
1031
1032         * arm-dis.c (enum mve_instructions): Add new instructions.
1033         (enum mve_unpredictable): Add new reasons.
1034         (enum mve_undefined): Likewise.
1035         (is_mve_encoding_conflict): Handle new instructions.
1036         (is_mve_undefined): Likewise.
1037         (is_mve_unpredictable): Likewise.
1038         (print_mve_undefined): Likewise.
1039         (print_mve_unpredictable): Likewise.
1040         (print_mve_rounding_mode): Likewise.
1041         (print_mve_vcvt_size): Likewise.
1042         (print_mve_size): Likewise.
1043         (print_insn_mve): Likewise.
1044
1045 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1046             Michael Collison <michael.collison@arm.com>
1047
1048         * arm-dis.c (enum mve_instructions): Add new instructions.
1049         (enum mve_unpredictable): Add new reasons.
1050         (enum mve_undefined): Likewise.
1051         (is_mve_undefined): Handle new instructions.
1052         (is_mve_unpredictable): Likewise.
1053         (print_mve_undefined): Likewise.
1054         (print_mve_unpredictable): Likewise.
1055         (print_mve_size): Likewise.
1056         (print_insn_mve): Likewise.
1057
1058 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1059             Michael Collison <michael.collison@arm.com>
1060
1061         * arm-dis.c (enum mve_instructions): Add new instructions.
1062         (enum mve_undefined): Add new reasons.
1063         (insns): Add new instructions.
1064         (is_mve_encoding_conflict):
1065         (print_mve_vld_str_addr): New print function.
1066         (is_mve_undefined): Handle new instructions.
1067         (is_mve_unpredictable): Likewise.
1068         (print_mve_undefined): Likewise.
1069         (print_mve_size): Likewise.
1070         (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1071         (print_insn_mve):  Handle new operands.
1072
1073 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1074             Michael Collison <michael.collison@arm.com>
1075
1076         * arm-dis.c (enum mve_instructions): Add new instructions.
1077         (enum mve_unpredictable): Add new reasons.
1078         (is_mve_encoding_conflict): Handle new instructions.
1079         (is_mve_unpredictable): Likewise.
1080         (mve_opcodes): Add new instructions.
1081         (print_mve_unpredictable): Handle new reasons.
1082         (print_mve_register_blocks): New print function.
1083         (print_mve_size): Handle new instructions.
1084         (print_insn_mve): Likewise.
1085
1086 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1087             Michael Collison <michael.collison@arm.com>
1088
1089         * arm-dis.c (enum mve_instructions): Add new instructions.
1090         (enum mve_unpredictable): Add new reasons.
1091         (enum mve_undefined): Likewise.
1092         (is_mve_encoding_conflict): Handle new instructions.
1093         (is_mve_undefined): Likewise.
1094         (is_mve_unpredictable): Likewise.
1095         (coprocessor_opcodes): Move NEON VDUP from here...
1096         (neon_opcodes): ... to here.
1097         (mve_opcodes): Add new instructions.
1098         (print_mve_undefined):  Handle new reasons.
1099         (print_mve_unpredictable): Likewise.
1100         (print_mve_size): Handle new instructions.
1101         (print_insn_neon): Handle vdup.
1102         (print_insn_mve): Handle new operands.
1103
1104 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1105             Michael Collison <michael.collison@arm.com>
1106
1107         * arm-dis.c (enum mve_instructions): Add new instructions.
1108         (enum mve_unpredictable): Add new values.
1109         (mve_opcodes): Add new instructions.
1110         (vec_condnames): New array with vector conditions.
1111         (mve_predicatenames): New array with predicate suffixes.
1112         (mve_vec_sizename): New array with vector sizes.
1113         (enum vpt_pred_state): New enum with vector predication states.
1114         (struct vpt_block): New struct type for vpt blocks.
1115         (vpt_block_state): Global struct to keep track of state.
1116         (mve_extract_pred_mask): New helper function.
1117         (num_instructions_vpt_block): Likewise.
1118         (mark_outside_vpt_block): Likewise.
1119         (mark_inside_vpt_block): Likewise.
1120         (invert_next_predicate_state): Likewise.
1121         (update_next_predicate_state): Likewise.
1122         (update_vpt_block_state): Likewise.
1123         (is_vpt_instruction): Likewise.
1124         (is_mve_encoding_conflict): Add entries for new instructions.
1125         (is_mve_unpredictable): Likewise.
1126         (print_mve_unpredictable): Handle new cases.
1127         (print_instruction_predicate): Likewise.
1128         (print_mve_size): New function.
1129         (print_vec_condition): New function.
1130         (print_insn_mve): Handle vpt blocks and new print operands.
1131
1132 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1133
1134         * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1135         8, 14 and 15 for Armv8.1-M Mainline.
1136
1137 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
1138             Michael Collison <michael.collison@arm.com>
1139
1140         * arm-dis.c (enum mve_instructions): New enum.
1141         (enum mve_unpredictable): Likewise.
1142         (enum mve_undefined): Likewise.
1143         (struct mopcode32): New struct.
1144         (is_mve_okay_in_it): New function.
1145         (is_mve_architecture): Likewise.
1146         (arm_decode_field): Likewise.
1147         (arm_decode_field_multiple): Likewise.
1148         (is_mve_encoding_conflict): Likewise.
1149         (is_mve_undefined): Likewise.
1150         (is_mve_unpredictable): Likewise.
1151         (print_mve_undefined): Likewise.
1152         (print_mve_unpredictable): Likewise.
1153         (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1154         (print_insn_mve): New function.
1155         (print_insn_thumb32): Handle MVE architecture.
1156         (select_arm_features): Force thumb for Armv8.1-m Mainline.
1157
1158 2019-05-10  Nick Clifton  <nickc@redhat.com>
1159
1160         PR 24538
1161         * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1162         end of the table prematurely.
1163
1164 2019-05-10  Faraz Shahbazker  <fshahbazker@wavecomp.com>
1165
1166         * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1167         macros for R6.
1168
1169 2019-05-11  Alan Modra  <amodra@gmail.com>
1170
1171         * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1172         when -Mraw is in effect.
1173
1174 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1175
1176         * aarch64-dis-2.c: Regenerate.
1177         * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1178         (OP_SVE_BBB): New variant set.
1179         (OP_SVE_DDDD): New variant set.
1180         (OP_SVE_HHH): New variant set.
1181         (OP_SVE_HHHU): New variant set.
1182         (OP_SVE_SSS): New variant set.
1183         (OP_SVE_SSSU): New variant set.
1184         (OP_SVE_SHH): New variant set.
1185         (OP_SVE_SBBU): New variant set.
1186         (OP_SVE_DSS): New variant set.
1187         (OP_SVE_DHHU): New variant set.
1188         (OP_SVE_VMV_HSD_BHS): New variant set.
1189         (OP_SVE_VVU_HSD_BHS): New variant set.
1190         (OP_SVE_VVVU_SD_BH): New variant set.
1191         (OP_SVE_VVVU_BHSD): New variant set.
1192         (OP_SVE_VVV_QHD_DBS): New variant set.
1193         (OP_SVE_VVV_HSD_BHS): New variant set.
1194         (OP_SVE_VVV_HSD_BHS2): New variant set.
1195         (OP_SVE_VVV_BHS_HSD): New variant set.
1196         (OP_SVE_VV_BHS_HSD): New variant set.
1197         (OP_SVE_VVV_SD): New variant set.
1198         (OP_SVE_VVU_BHS_HSD): New variant set.
1199         (OP_SVE_VZVV_SD): New variant set.
1200         (OP_SVE_VZVV_BH): New variant set.
1201         (OP_SVE_VZV_SD): New variant set.
1202         (aarch64_opcode_table): Add sve2 instructions.
1203
1204 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1205
1206         * aarch64-asm-2.c: Regenerated.
1207         * aarch64-dis-2.c: Regenerated.
1208         * aarch64-opc-2.c: Regenerated.
1209         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1210         for SVE_SHLIMM_UNPRED_22.
1211         (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1212         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1213         operand.
1214
1215 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1216
1217         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1218         sve_size_tsz_bhs iclass encode.
1219         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1220         sve_size_tsz_bhs iclass decode.
1221
1222 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1223
1224         * aarch64-asm-2.c: Regenerated.
1225         * aarch64-dis-2.c: Regenerated.
1226         * aarch64-opc-2.c: Regenerated.
1227         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1228         for SVE_Zm4_11_INDEX.
1229         (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1230         (fields): Handle SVE_i2h field.
1231         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1232         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1233
1234 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1235
1236         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1237         sve_shift_tsz_bhsd iclass encode.
1238         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1239         sve_shift_tsz_bhsd iclass decode.
1240
1241 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1242
1243         * aarch64-asm-2.c: Regenerated.
1244         * aarch64-dis-2.c: Regenerated.
1245         * aarch64-opc-2.c: Regenerated.
1246         * aarch64-asm.c (aarch64_ins_sve_shrimm):
1247         (aarch64_encode_variant_using_iclass): Handle
1248         sve_shift_tsz_hsd iclass encode.
1249         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1250         sve_shift_tsz_hsd iclass decode.
1251         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1252         for SVE_SHRIMM_UNPRED_22.
1253         (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1254         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1255         operand.
1256
1257 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1258
1259         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1260         sve_size_013 iclass encode.
1261         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1262         sve_size_013 iclass decode.
1263
1264 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1265
1266         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1267         sve_size_bh iclass encode.
1268         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1269         sve_size_bh iclass decode.
1270
1271 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1272
1273         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1274         sve_size_sd2 iclass encode.
1275         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1276         sve_size_sd2 iclass decode.
1277         * aarch64-opc.c (fields): Handle SVE_sz2 field.
1278         * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1279
1280 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1281
1282         * aarch64-asm-2.c: Regenerated.
1283         * aarch64-dis-2.c: Regenerated.
1284         * aarch64-opc-2.c: Regenerated.
1285         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1286         for SVE_ADDR_ZX.
1287         (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1288         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1289
1290 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1291
1292         * aarch64-asm-2.c: Regenerated.
1293         * aarch64-dis-2.c: Regenerated.
1294         * aarch64-opc-2.c: Regenerated.
1295         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1296         for SVE_Zm3_11_INDEX.
1297         (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1298         (fields): Handle SVE_i3l and SVE_i3h2 fields.
1299         * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1300         fields.
1301         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1302
1303 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1304
1305         * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1306         sve_size_hsd2 iclass encode.
1307         * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1308         sve_size_hsd2 iclass decode.
1309         * aarch64-opc.c (fields): Handle SVE_size field.
1310         * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1311
1312 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1313
1314         * aarch64-asm-2.c: Regenerated.
1315         * aarch64-dis-2.c: Regenerated.
1316         * aarch64-opc-2.c: Regenerated.
1317         * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1318         for SVE_IMM_ROT3.
1319         (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1320         (fields): Handle SVE_rot3 field.
1321         * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1322         * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1323
1324 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1325
1326         * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1327         instructions.
1328
1329 2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>
1330
1331         * aarch64-tbl.h
1332         (aarch64_feature_sve2, aarch64_feature_sve2aes,
1333         aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1334         aarch64_feature_sve2bitperm): New feature sets.
1335         (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1336         for feature set addresses.
1337         (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1338         SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1339
1340 2019-05-06  Andrew Bennett  <andrew.bennett@imgtec.com>
1341             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1342
1343         * mips-dis.c (mips_calculate_combination_ases): Add ISA
1344         argument and set ASE_EVA_R6 appropriately.
1345         (set_default_mips_dis_options): Pass ISA to above.
1346         (parse_mips_dis_option): Likewise.
1347         * mips-opc.c (EVAR6): New macro.
1348         (mips_builtin_opcodes): Add llwpe, scwpe.
1349
1350 2019-05-01  Sudakshina Das  <sudi.das@arm.com>
1351
1352         * aarch64-asm-2.c: Regenerated.
1353         * aarch64-dis-2.c: Regenerated.
1354         * aarch64-opc-2.c: Regenerated.
1355         * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1356         AARCH64_OPND_TME_UIMM16.
1357         (aarch64_print_operand): Likewise.
1358         * aarch64-tbl.h (QL_IMM_NIL): New.
1359         (TME): New.
1360         (_TME_INSN): New.
1361         (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1362
1363 2019-04-29  John Darrington  <john@darrington.wattle.id.au>
1364
1365         * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1366
1367 2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
1368             Faraz Shahbazker  <fshahbazker@wavecomp.com>
1369
1370         * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1371
1372 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1373
1374         * s12z-opc.h: Add extern "C" bracketing to help
1375         users who wish to use this interface in c++ code.
1376
1377 2019-04-24  John Darrington  <john@darrington.wattle.id.au>
1378
1379         * s12z-opc.c (bm_decode): Handle bit map operations with the
1380         "reserved0" mode.
1381
1382 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1383
1384         * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1385         specifier.  Add entries for VLDR and VSTR of system registers.
1386         (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1387         coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
1388         of %J and %K format specifier.
1389
1390 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1391
1392         * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1393         Add new entries for VSCCLRM instruction.
1394         (print_insn_coprocessor): Handle new %C format control code.
1395
1396 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1397
1398         * arm-dis.c (enum isa): New enum.
1399         (struct sopcode32): New structure.
1400         (coprocessor_opcodes): change type of entries to struct sopcode32 and
1401         set isa field of all current entries to ANY.
1402         (print_insn_coprocessor): Change type of insn to struct sopcode32.
1403         Only match an entry if its isa field allows the current mode.
1404
1405 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1406
1407         * arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
1408         CLRM.
1409         (print_insn_thumb32): Add logic to print %n CLRM register list.
1410
1411 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1412
1413         * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1414         and %Q patterns.
1415
1416 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1417
1418         * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1419         (print_insn_thumb32): Edit the switch case for %Z.
1420
1421 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1422
1423         * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1424
1425 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1426
1427         * arm-dis.c (thumb32_opcodes): New instruction bfl.
1428
1429 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1430
1431         * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1432
1433 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1434
1435         * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1436         Arm register with r13 and r15 unpredictable.
1437         (thumb32_opcodes): New instructions for bfx and bflx.
1438
1439 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1440
1441         * arm-dis.c (thumb32_opcodes): New instructions for bf.
1442
1443 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1444
1445         * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1446
1447 2019-04-15  Sudakshina Das  <sudi.das@arm.com>
1448
1449         * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1450
1451 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
1452
1453         * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1454
1455 2019-04-12  John Darrington <john@darrington.wattle.id.au>
1456
1457         s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1458         "optr". ("operator" is a reserved word in c++).
1459
1460 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1461
1462         * aarch64-opc.c (aarch64_print_operand): Add case for
1463         AARCH64_OPND_Rt_SP.
1464         (verify_constraints): Likewise.
1465         * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1466         (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1467         to accept Rt|SP as first operand.
1468         (AARCH64_OPERANDS): Add new Rt_SP.
1469         * aarch64-asm-2.c: Regenerated.
1470         * aarch64-dis-2.c: Regenerated.
1471         * aarch64-opc-2.c: Regenerated.
1472
1473 2019-04-11  Sudakshina Das  <sudi.das@arm.com>
1474
1475         * aarch64-asm-2.c: Regenerated.
1476         * aarch64-dis-2.c: Likewise.
1477         * aarch64-opc-2.c: Likewise.
1478         * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1479
1480 2019-04-09  Robert Suchanek  <robert.suchanek@mips.com>
1481
1482         * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1483
1484 2019-04-08  H.J. Lu  <hongjiu.lu@intel.com>
1485
1486         * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1487         * i386-init.h: Regenerated.
1488
1489 2019-04-07  Alan Modra  <amodra@gmail.com>
1490
1491         * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1492         op_separator to control printing of spaces, comma and parens
1493         rather than need_comma, need_paren and spaces vars.
1494
1495 2019-04-07  Alan Modra  <amodra@gmail.com>
1496
1497         PR 24421
1498         * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1499         (print_insn_neon, print_insn_arm): Likewise.
1500
1501 2019-04-05  Xuepeng Guo  <xuepeng.guo@intel.com>
1502
1503         * i386-dis-evex.h (evex_table): Updated to support BF16
1504         instructions.
1505         * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1506         and EVEX_W_0F3872_P_3.
1507         * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1508         (cpu_flags): Add bitfield for CpuAVX512_BF16.
1509         * i386-opc.h (enum): Add CpuAVX512_BF16.
1510         (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1511         * i386-opc.tbl: Add AVX512 BF16 instructions.
1512         * i386-init.h: Regenerated.
1513         * i386-tbl.h: Likewise.
1514
1515 2019-04-05  Alan Modra  <amodra@gmail.com>
1516
1517         * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1518         (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1519         to favour printing of "-" branch hint when using the "y" bit.
1520         Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1521
1522 2019-04-05  Alan Modra  <amodra@gmail.com>
1523
1524         * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1525         opcode until first operand is output.
1526
1527 2019-04-04  Peter Bergner  <bergner@linux.ibm.com>
1528
1529         PR gas/24349
1530         * ppc-opc.c (valid_bo_pre_v2): Add comments.
1531         (valid_bo_post_v2): Add support for 'at' branch hints.
1532         (insert_bo): Only error on branch on ctr.
1533         (get_bo_hint_mask): New function.
1534         (insert_boe): Add new 'branch_taken' formal argument.  Add support
1535         for inserting 'at' branch hints.
1536         (extract_boe): Add new 'branch_taken' formal argument.  Add support
1537         for extracting 'at' branch hints.
1538         (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1539         (BOE): Delete operand.
1540         (BOM, BOP): New operands.
1541         (RM): Update value.
1542         (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1543         (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1544         bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1545         (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1546         bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1547         <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1548         bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1549         bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1550         bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1551         bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1552         bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1553         bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1554         bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1555         beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1556         bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1557         buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1558         bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1559         bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1560         bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1561         bttarl+>: New extended mnemonics.
1562
1563 2019-03-28  Alan Modra  <amodra@gmail.com>
1564
1565         PR 24390
1566         * ppc-opc.c (BTF): Define.
1567         (powerpc_opcodes): Use for mtfsb*.
1568         * ppc-dis.c (print_insn_powerpc): Print fields with both
1569         PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1570
1571 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1572
1573         * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1574         (mapping_symbol_for_insn): Implement new algorithm.
1575         (print_insn): Remove duplicate code.
1576
1577 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1578
1579         * aarch64-dis.c (print_insn_aarch64):
1580         Implement override.
1581
1582 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1583
1584         * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1585         order.
1586
1587 2019-03-25  Tamar Christina  <tamar.christina@arm.com>
1588
1589         * aarch64-dis.c (last_stop_offset): New.
1590         (print_insn_aarch64): Use stop_offset.
1591
1592 2019-03-19  H.J. Lu  <hongjiu.lu@intel.com>
1593
1594         PR gas/24359
1595         * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1596         CPU_ANY_AVX2_FLAGS.
1597         * i386-init.h: Regenerated.
1598
1599 2019-03-18  H.J. Lu  <hongjiu.lu@intel.com>
1600
1601         PR gas/24348
1602         * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1603         vmovdqu16, vmovdqu32 and vmovdqu64.
1604         * i386-tbl.h: Regenerated.
1605
1606 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1607
1608         * s390-opc.txt: Rename selhhhr to selfhr.  Remove optional operand
1609         from vstrszb, vstrszh, and vstrszf.
1610
1611 2019-03-12  Andreas Krebbel  <krebbel@linux.ibm.com>
1612
1613         * s390-opc.txt: Add instruction descriptions.
1614
1615 2019-02-08  Jim Wilson  <jimw@sifive.com>
1616
1617         * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1618         <bne>: Likewise.
1619
1620 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1621
1622         * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1623
1624 2019-02-07  Tamar Christina  <tamar.christina@arm.com>
1625
1626         PR binutils/23212
1627         * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1628         * aarch64-opc.c (verify_elem_sd): New.
1629         (fields): Add FLD_sz entr.
1630         * aarch64-tbl.h (_SIMD_INSN): New.
1631         (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1632         fmulx scalar and vector by element isns.
1633
1634 2019-02-07  Nick Clifton  <nickc@redhat.com>
1635
1636         * po/sv.po: Updated Swedish translation.
1637
1638 2019-01-31  Andreas Krebbel  <krebbel@linux.ibm.com>
1639
1640         * s390-mkopc.c (main): Accept arch13 as cpu string.
1641         * s390-opc.c: Add new instruction formats and instruction opcode
1642         masks.
1643         * s390-opc.txt: Add new arch13 instructions.
1644
1645 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1646
1647         * aarch64-tbl.h (QL_LDST_AT): Update macro.
1648         (aarch64_opcode): Change encoding for stg, stzg
1649         st2g and st2zg.
1650         * aarch64-asm-2.c: Regenerated.
1651         * aarch64-dis-2.c: Regenerated.
1652         * aarch64-opc-2.c: Regenerated.
1653
1654 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1655
1656         * aarch64-asm-2.c: Regenerated.
1657         * aarch64-dis-2.c: Likewise.
1658         * aarch64-opc-2.c: Likewise.
1659         * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1660
1661 2019-01-25  Sudakshina Das  <sudi.das@arm.com>
1662             Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>
1663
1664         * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1665         * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1666         * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1667         * aarch64-dis.h (ext_addr_simple_2): Likewise.
1668         * aarch64-opc.c (operand_general_constraint_met_p): Remove
1669         case for ldstgv_indexed.
1670         (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1671         * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1672         (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1673         * aarch64-asm-2.c: Regenerated.
1674         * aarch64-dis-2.c: Regenerated.
1675         * aarch64-opc-2.c: Regenerated.
1676
1677 2019-01-23  Nick Clifton  <nickc@redhat.com>
1678
1679         * po/pt_BR.po: Updated Brazilian Portuguese translation.
1680
1681 2019-01-21  Nick Clifton  <nickc@redhat.com>
1682
1683         * po/de.po: Updated German translation.
1684         * po/uk.po: Updated Ukranian translation.
1685
1686 2019-01-20  Chenghua Xu  <paul.hua.gm@gmail.com>
1687         * mips-dis.c (mips_arch_choices): Fix typo in
1688         gs464, gs464e and gs264e descriptors.
1689
1690 2019-01-19  Nick Clifton  <nickc@redhat.com>
1691
1692         * configure: Regenerate.
1693         * po/opcodes.pot: Regenerate.
1694
1695 2018-06-24  Nick Clifton  <nickc@redhat.com>
1696
1697         2.32 branch created.
1698
1699 2019-01-09  John Darrington <john@darrington.wattle.id.au>
1700
1701         * s12z-dis.c (print_insn_s12z):  Do not dereference an operand
1702         if it is null.
1703         -dis.c (opr_emit_disassembly): Do not omit an index if it is
1704         zero.
1705
1706 2019-01-09  Andrew Paprocki  <andrew@ishiboo.com>
1707
1708         * configure: Regenerate.
1709
1710 2019-01-07  Alan Modra  <amodra@gmail.com>
1711
1712         * configure: Regenerate.
1713         * po/POTFILES.in: Regenerate.
1714
1715 2019-01-03  John Darrington <john@darrington.wattle.id.au>
1716
1717         * s12z-opc.c: New file.
1718         * s12z-opc.h: New file.
1719         * s12z-dis.c: Removed all code not directly related to display
1720         of instructions.  Used the interface provided by the new files
1721         instead.
1722         * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1723         * Makefile.in: Regenerate.
1724         * configure.ac (bfd_s12z_arch): Correct the dependencies.
1725         * configure: Regenerate.
1726
1727 2019-01-01  Alan Modra  <amodra@gmail.com>
1728
1729         Update year range in copyright notice of all files.
1730
1731 For older changes see ChangeLog-2018
1732 \f
1733 Copyright (C) 2019 Free Software Foundation, Inc.
1734
1735 Copying and distribution of this file, with or without modification,
1736 are permitted in any medium without royalty provided the copyright
1737 notice and this notice are preserved.
1738
1739 Local Variables:
1740 mode: change-log
1741 left-margin: 8
1742 fill-column: 74
1743 version-control: never
1744 End: